Method for forming semiconductor structure

Abstract

The present disclosure provides a method for forming a semiconductor structure, relating to the field of semiconductor technology. The method includes: forming an active layer; forming a mask material layer including a first mask layer, a second mask layer, and a third mask layer on one side of the active layer; the first mask layer includes a plurality of mask structures distributed at intervals; the second mask layer is located on a side of the first mask layer away from the active layer and fills the gaps between the mask structures; the third mask layer is located on the surface of the second mask layer; a plurality of first mask holes and a plurality of second masks are formed in the third mask layer; the second mask layer and the first mask layer are etched using the third mask layer having the first mask holes and the second mask holes as a mask to form a target mask pattern in the first mask layer. The present disclosure achieves better uniformity of local critical dimensions in the active area of ​​the device formed by this method, thereby improving the performance of the device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. The active area (AOA) is the main region on the substrate where devices are formed, providing the foundation for device formation.

[0003] Multiple active areas are isolated by isolation structures. Currently, due to process limitations, when forming multiple active areas, the structural integrity of the isolation structures formed in some areas is poor, resulting in poor uniformity of local key dimensions within the final active areas, affecting the formation quality and performance of subsequent devices.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] In view of this, a method for forming a semiconductor structure is provided, wherein a target mask pattern formed by the method has high structural integrity and thus improves the uniformity of local critical dimensions of the device active area.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] forming an active layer;

[0009] A mask material layer is formed on one side of the active layer, wherein the mask material layer includes a first mask layer, a second mask layer, and a third mask layer arranged in sequence, wherein the first mask layer includes a plurality of mask structures distributed at intervals; the second mask layer is located on a side of the first mask layer away from the active layer and fills the gaps between the mask structures; and the third mask layer is located on a surface of the second mask layer;

[0010] forming a plurality of first mask holes and a plurality of second mask holes in the third mask layer, wherein the orthographic projections of the first mask holes on the first mask layer and the orthographic projections of the second mask holes on the first mask layer are both located on the mask structure, and the first mask holes and the second mask holes whose orthographic projections are located on the same mask structure are alternately distributed in an extension direction of the mask structure;

[0011] The second mask layer and the first mask layer are etched using the third mask layer having the first mask hole and the second mask hole as a mask to form a target mask pattern in the first mask layer.

[0012] In some embodiments of the present disclosure, based on the aforementioned solution, before forming the first mask hole and the second mask hole, the forming method further includes:

[0013] forming a fourth mask layer on the surface of the third mask layer;

[0014] The forming of a plurality of first mask holes and a plurality of second mask holes in the third mask layer comprises:

[0015] forming a plurality of third mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the orthographic projections of the third mask holes on the first mask layer are located on the mask structure;

[0016] forming a first photoresist layer on the surface of the fourth mask layer having the third mask hole, wherein the first photoresist layer fills the third mask hole;

[0017] exposing and developing the first photoresist layer to form a plurality of first development areas, wherein orthographic projections of the first development areas on the first mask layer are located on the mask structure;

[0018] etching the fourth mask layer based on the first developing area to form a plurality of fourth mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the third mask holes and the fourth mask holes whose orthographic projections are located on the same mask structure are alternately distributed in an extension direction of the mask structure;

[0019] removing the first photoresist layer;

[0020] The third mask layer is etched using the fourth mask layer having the third mask hole and the fourth mask hole as a mask to form the first mask hole and the second mask hole.

[0021] In some embodiments of the present disclosure, based on the aforementioned solution, before forming the first mask hole and the second mask hole, the forming method further includes:

[0022] forming a fourth mask layer on the surface of the third mask layer;

[0023] The forming of a plurality of first mask holes and a plurality of second mask holes in the third mask layer comprises:

[0024] forming a plurality of fifth mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the orthographic projections of the fifth mask holes on the first mask layer are located on the mask structure;

[0025] forming a fifth mask layer on the surface of the fourth mask layer having the fifth mask hole, wherein the fifth mask layer fills the fifth mask hole;

[0026] forming a sixth mask layer on the surface of the fifth mask layer, forming a second photoresist layer on the surface of the sixth mask layer, exposing and developing the second photoresist layer to form a plurality of second development areas, wherein orthographic projections of the second development areas on the first mask layer are located on the mask structure;

[0027] etching the sixth mask layer, the fifth mask layer, and the fourth mask layer based on the second developing area to form a plurality of sixth mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the fifth mask holes and the sixth mask holes whose orthographic projections are located on the same mask structure are alternately distributed in an extension direction of the mask structure;

[0028] removing the second photoresist layer, the sixth mask layer, and the fifth mask layer;

[0029] The third mask layer is etched using the fourth mask layer having the fifth mask hole and the sixth mask hole as a mask to form the first mask hole and the second mask hole.

[0030] In some embodiments of the present disclosure, based on the aforementioned scheme, during the etching of the third mask layer, the etching rate of the third mask layer is greater than or equal to the etching rate of the fourth mask layer, and the thickness of the third mask layer is less than or equal to the thickness of the fourth mask layer.

[0031] In some embodiments of the present disclosure, based on the aforementioned solution, the material of the third mask layer includes silicon oxide, and the material of the fourth mask layer includes silicon oxynitride.

[0032] In some embodiments of the present disclosure, based on the aforementioned solution, the thickness of the fourth mask layer is 26-30 nm, and the thickness of the third mask layer is 20 nm-28 nm.

[0033] In some embodiments of the present disclosure, based on the aforementioned solution, the forming method further includes:

[0034] After forming the target mask pattern, the second mask layer is removed.

[0035] In some embodiments of the present disclosure, based on the aforementioned solution, the material of the first mask layer includes polysilicon, and the material of the second mask layer includes spin-on organic carbon.

[0036] In some embodiments of the present disclosure, based on the aforementioned solution, the forming method further includes:

[0037] The active layer is etched using the first mask layer having the target mask pattern as a mask to form a plurality of active regions.

[0038] In some embodiments of the present disclosure, based on the aforementioned solution, the target mask patterns are distributed at equal intervals.

[0039] The present disclosure provides a method for forming a semiconductor structure, which forms a mask material layer on an active layer, wherein the mask material layer includes a first mask layer, a second mask layer, and a third mask layer arranged in sequence, forms a plurality of first mask holes and a plurality of second mask holes in the third mask layer, and etches the first mask layer and the second mask layer using the third mask layer as a mask to form a target mask pattern in the first mask layer. The target mask pattern formed by this formation method has high structural integrity, eliminates structural defects caused by the etching process, improves the uniformity of local critical dimensions in the active area of ​​the device, and thereby improves the formation quality and performance of the device.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0042] Figure 1 FIG. 1 is a schematic diagram of the structure of an active region in the prior art in an exemplary embodiment of the present disclosure.

[0043] Figure 2 The present invention is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0044] Figure 3 Schematic diagram of the structure of an active area in an exemplary embodiment of the present disclosure.

[0045] Figure 4Flowchart showing the formation of the first mask hole and the second mask hole in the first embodiment of the present disclosure.

[0046] Figure 5 This is a structural diagram corresponding to step S310 in the first embodiment of the present disclosure.

[0047] Figure 6 This is a structural diagram corresponding to step S320 in the first embodiment of the present disclosure.

[0048] Figure 7 3 is a schematic structural diagram corresponding to step S330 and step S340 in the first embodiment of the present disclosure.

[0049] Figure 8 3 is a schematic structural diagram corresponding to step S350 and step S360 in the first embodiment of the present disclosure.

[0050] Figure 9 This is a structural diagram corresponding to step S370 in the first embodiment of the present disclosure.

[0051] Figure 10 Schematic diagram of the structure of the distribution of the first mask holes and the second mask holes in an exemplary embodiment of the present disclosure.

[0052] Figure 11 Schematic diagram of the structure of an active area in an exemplary embodiment of the present disclosure.

[0053] Figure 12 Flowchart showing the formation of the first mask hole and the second mask hole in the second embodiment of the present disclosure.

[0054] Figure 13 This is a structural diagram corresponding to step S301 in the second embodiment of the present disclosure.

[0055] Figure 14 This is a structural diagram corresponding to step S302 in the second embodiment of the present disclosure.

[0056] Figure 15 3 is a schematic structural diagram corresponding to step S303 and step S304 in the second embodiment of the present disclosure.

[0057] Figure 16 3 is a schematic structural diagram corresponding to step S305 and step S306 in the second embodiment of the present disclosure.

[0058] The description of the accompanying drawings is as follows:

[0059] 100, active layer; 110, substrate; 120, insulating layer; 200, active region; 201, first isolation structure; 202, second isolation structure; 310, first mask layer; 320, second mask layer; 330, third mask layer; 340, fourth mask layer; 350, fifth mask layer; 360, sixth mask layer; 311, mask structure; 401, first mask hole; 402, second mask hole; 403, third mask hole; 404, fourth mask hole; 405, fifth mask hole; 406, sixth mask hole; 510, first photoresist layer; 520, second photoresist layer; 530, intermediate photoresist layer; 511, first developing area; 521, second developing area; 531, intermediate developing area; 351, intermediate fifth mask layer; 361, intermediate sixth mask layer; 600, target mask pattern; X, first direction. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0061] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0062] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0063] In related technologies, the active area of ​​the device can provide the basis for the formation of the source and drain as well as the connecting circuit between the source and drain, especially the polysilicon film layer in the active area, which can serve as part of the substrate or a conductive layer, and doping and other processes are performed on it to form the source and drain of the device. Therefore, the patterning quality of the polysilicon film layer directly affects the formation quality of the device.

[0064] Currently, if Figure 1 As shown, within the active area 200, the isolation structure of the active area 200 may include a plurality of first isolation structures 201 and a plurality of second isolation structures 202. The plurality of first isolation structures 201 and the plurality of second isolation structures 202 are alternately distributed in a first direction X (the extension direction of the active area 200). The plurality of first isolation structures 201 and the plurality of second isolation structures 202 may be formed by etching, ashing, cleaning, and other processes. In the prior art, the first isolation structures 201 and the second isolation structures 202 are etched and formed in different steps, and ashing and cleaning processes are performed separately to remove the mask layers used for pattern transfer. Due to the different formation times of the first isolation structures 201, the ashing and cleaning processes of the second openings may damage the already formed first isolation structures 201, thereby destroying the structural integrity of the first isolation structures 201. That is, the local critical dimension uniformity (LCDU) of the polysilicon film layer openings in the active area 200 is poor, resulting in poor performance of subsequently formed devices.

[0065] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 2 As shown, the forming method includes steps: S100 to S400.

[0066] Wherein, step S100: forming an active layer;

[0067] Step S200: forming a mask material layer on one side of the active layer, the mask material layer comprising a first mask layer, a second mask layer, and a third mask layer arranged in sequence, the first mask layer comprising a plurality of mask structures spaced apart; the second mask layer being located on a side of the first mask layer away from the active layer and filling gaps between the mask structures; the third mask layer being located on a surface of the second mask layer;

[0068] Step S300: forming a plurality of first mask holes and a plurality of second mask holes in the third mask layer, wherein the orthographic projections of the first mask holes on the first mask layer and the orthographic projections of the second mask holes on the first mask layer are both located on the mask structure, and the first mask holes and the second mask holes whose orthographic projections are located on the same mask structure are alternately distributed in an extension direction of the mask structure;

[0069] Step S400 : etching the second mask layer and the first mask layer using the third mask layer having the first mask hole and the second mask hole as a mask to form a target mask pattern in the first mask layer.

[0070] The present disclosure provides a method for forming a semiconductor structure, which forms a mask material layer on an active layer, wherein the mask material layer includes a first mask layer, a second mask layer, and a third mask layer arranged in sequence, and a plurality of first mask holes and second mask holes are formed in the third mask layer, wherein the first mask holes and the second mask holes are alternately distributed in the extension direction of the mask structure, and the second mask layer and the first mask layer are etched using the third mask layer as a mask to form a target mask pattern in the first mask layer. The local critical dimension uniformity of the active area formed by this method is good, the structural defects caused by the etching process are eliminated, the formation quality and performance of the device are improved, and the yield of the device is thereby improved.

[0071] The following is a detailed description of the various steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure with reference to the accompanying drawings:

[0072] In the embodiments provided in the present disclosure, Figure 5-Figure 11 as well as Figure 13-16 The aa', bb', cc', and dd' shown in Figure 3 The cross-sectional views correspond to the directions indicated by the arrows, and the corresponding positional relationships described in each cross-sectional view will not be specifically stated below.

[0073] In the embodiments provided in the present disclosure, Figure 5 As shown, in step S100, an active layer 100 is formed. Forming the active layer 100 may include forming the active layer 100 on a substrate 110, and the substrate 110 may form a stacked structure, that is, the active layer 100 may include the substrate 110 and other layers formed on the substrate 110.

[0074] The substrate 110 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, an SOI (Silicon On Insulator), or a GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs). The substrate 110 may be selected based on the actual design requirements of the semiconductor structure and is not specifically limited in this disclosure.

[0075] The stacked structure may include an insulating layer 120 and an isolation layer alternately formed on the surface of the substrate 110, with the top film layer of the stacked structure being the insulating layer 120. For example, the stacked structure may be composed of one insulating layer 120, one isolation layer, and another insulating layer 120. Of course, the stacked structure may also include only the insulating layer 120.

[0076] Among them, the insulating layer 120 can be an oxide layer, for example, the material of the insulating layer 120 can be silicon dioxide (SiO2) or the like. The isolation layer can be a nitride layer, for example, the material of the isolation layer can be silicon nitride (SiN) silicon carbonitride (SiCN) or silicon oxynitride (SiON) or the like. The insulating layer 120 and the isolation layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vacuum evaporation (PVD) or magnetron sputtering. Of course, the number of layers, materials and formation methods of the stacked structure can be selected according to the actual structural requirements of the device, and this disclosure does not make specific limitations.

[0077] It should be noted that the following embodiments of the present disclosure take the stacked structure including only the insulating layer 120 as an example, but the present invention is not limited thereto.

[0078] In the embodiments provided in the present disclosure, Figure 5 As shown, in step S200, a mask material layer is formed on one side of the active layer 100, and the mask material layer includes a first mask layer 310, a second mask layer 320 and a third mask layer 330 arranged in sequence, the first mask layer 310 includes a plurality of spaced mask structures 311; the second mask layer 320 is located on the side of the first mask layer 310 away from the active layer 100, and fills the gaps between the mask structures 311; the third mask layer 330 is located on the surface of the second mask layer 320.

[0079] Among them, the first mask layer 310 includes a plurality of spaced mask structures 311, and forming a plurality of spaced mask structures 311 in the first mask layer 310 includes: forming an initial first mask layer 310 on the active layer 100; patterning the initial first mask layer 310 to form a plurality of spaced mask structures 311 in the initial first mask layer 310.

[0080] The material of the first mask layer 310 includes polysilicon (Poly). The first mask layer 310 can be formed using methods such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), direct chemical vapor deposition (DCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vacuum evaporation (PVD), or magnetron sputtering.

[0081] The second mask layer 320 is located on a side of the first mask layer 310 away from the active layer 100, and the second mask layer 320 fills the gaps between the mask structures 311 in the first mask layer 310. The material of the second mask layer 320 includes spin-on organic carbon (SOC) or spin-on hard mask (SOH). Since the spin-on hard mask has good fluidity before hardening, the second mask layer 320 can be formed on the first mask layer 310 by coating or other methods, and then hardening can be performed to increase the stability of the second mask layer 320. The above-mentioned formation process of the second mask layer 320 is only illustrative and does not limit the formation process of the second mask layer 320. Other methods for forming the second mask layer 320 in the art are applicable to the present disclosure.

[0082] Among them, the third mask layer 330 is formed on the side of the second mask layer 320 away from the active layer 100. The material of the third mask layer 330 may include oxides such as silicon oxide (SiO2), which can serve as the insulating layer 120 and also as an etching stop layer in the semiconductor process. Of course, the third mask layer 330 can also be made of other materials, for example, it can be made of other materials that can serve as an etching stop layer, such as silicon nitride (Si3N4), silicon boron nitride (BN), aluminum nitride (AlN), etc. According to the relationship between the etching rates of each film layer in the subsequent processing process, in the present disclosure, preferably, the third mask layer 330 can be made of silicon oxide (SiO2).

[0083] The thickness of the third mask layer 330 can be 20 nm to 28 nm, for example, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, or 28 nm. The third mask layer 330 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vacuum evaporation (PVD), or magnetron sputtering. Parameters such as the thickness, material, or formation method of the third mask layer 330 can be selected according to the actual formation requirements of the device and are not specifically limited in this disclosure.

[0084] In the embodiments provided in the present disclosure, Figure 8 As shown, in step S300, a plurality of first mask holes 401 and a plurality of second mask holes 402 are formed in the third mask layer 330, and the orthographic projections of the first mask holes 401 on the first mask layer 310 and the orthographic projections of the second mask holes 402 on the first mask layer 310 are both located on the mask structure 311, and the first mask holes 401 and the second mask holes 402 whose orthographic projections are located on the same mask structure 311 are alternately distributed in the extension direction of the mask structure 311.

[0085] In the first embodiment provided by the present disclosure, Figure 4 As shown, combined Figures 5 to 11 , forming a plurality of first mask holes 401 and a plurality of second mask holes 402 in the third mask layer 330 , including: steps S310 to S370 .

[0086] Wherein, step S310: forming a fourth mask layer 340 on the surface of the third mask layer 330;

[0087] Step S320 : forming a plurality of third mask holes 403 in the fourth mask layer 340 , each of which exposes the third mask layer 330 , wherein the orthographic projections of the third mask holes 403 on the first mask layer 310 are located on the mask structure 311 ;

[0088] Step S330 : forming a first photoresist layer 510 on the surface of the fourth mask layer 340 having the third mask hole 403 , wherein the first photoresist layer 510 fills the third mask hole 403 ;

[0089] Step S340 : exposing and developing the first photoresist layer 510 to form a plurality of first development areas 511 , wherein the orthographic projections of the first development areas 511 on the first mask layer 310 are located on the mask structure 311 ;

[0090] Step S350: etching the fourth mask layer 340 based on the first developing area 511 to form a plurality of fourth mask holes 404 in the fourth mask layer 340, each of which exposes the third mask layer 330. The third mask holes 403 and the fourth mask holes 404 whose orthographic projections are located on the same mask structure 311 are alternately distributed in the extension direction of the mask structure 311.

[0091] Step S360: removing the first photoresist layer 510;

[0092] Step S370 : etching the third mask layer 330 using the fourth mask layer 340 having the third mask hole 403 and the fourth mask hole 404 as a mask to form the first mask hole 401 and the second mask hole 402 .

[0093] In step S310, Figure 5 As shown, a fourth mask layer 340 is formed on the surface of the third mask layer 330. The material of the fourth mask layer 340 may include silicon oxynitride (SiON), and the fourth mask layer 340 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vacuum evaporation (PVD), or magnetron sputtering. The thickness of the fourth mask layer 340 may be 26 nm to 30 nm, for example, 26 nm, 27 nm, 28 nm, 29 nm, or 30 nm. The thickness of the third mask layer 330 must be less than or equal to the thickness of the fourth mask layer 340. For example, when the thickness of the fourth mask layer 340 is 26 nm, the thickness of the third mask layer 330 may be in the range of 20 nm to 26 nm. Preferably, the thickness of the fourth mask layer 340 is 28 nm, and the thickness of the third mask layer 330 is in the range of 20 nm to 28 nm.

[0094] In step S320, Figure 6As shown, a plurality of third mask holes 403 are formed in the fourth mask layer 340, each exposing the third mask layer 330. The orthographic projections of the third mask holes 403 on the first mask layer 310 are located on the mask structure 311. The formation of the plurality of third mask holes 403 in the fourth mask layer 340 includes: forming an intermediate photoresist layer 530 on the fourth mask layer 340; exposing and developing the intermediate photoresist layer 530 to form a plurality of intermediate developed regions 531 corresponding to each of the third mask holes 403; etching the fourth mask layer 340 based on the intermediate developed regions 531 to form a plurality of third mask holes 403 in the fourth mask layer 340, wherein the orthographic projections of the third mask holes 403 on the first mask layer 310 are located on the mask structure 311; and removing the intermediate photoresist layer 530.

[0095] In steps S330 to S350, if Figure 7 and Figure 8 As shown, a first photoresist layer 510 is formed on the surface of the fourth mask layer 340 having the third mask hole 403, and the first photoresist layer 510 fills the third mask hole 403. The first photoresist layer 510 is exposed and developed to form a plurality of first developed areas 511. The orthographic projections of the first developed areas 511 on the first mask layer 310 are located on the mask structure 311. The fourth mask layer 340 is etched based on the first developed areas 511 to form a plurality of fourth mask holes 404 in the fourth mask layer 340, each of which exposes the third mask layer 330. The third mask holes 403 and the fourth mask holes 404, whose orthographic projections are located on the same mask structure 311, are alternately distributed in the extension direction of the mask structure 311. When etching the fourth mask layer 340, the third mask layer 330 can be used as an etch stop layer to ensure uniform etching of the third mask holes 403 and the fourth mask holes 404.

[0096] In step S360, Figure 8 As shown, the first photoresist layer 510 is removed. The first photoresist layer 510 can be removed using methods such as wet chemical etching, plasma etching, and thermal stripping. Furthermore, for other photoresist layers in the present disclosure, an appropriate removal method can be selected based on the material and other properties of the photoresist layer, and the present disclosure does not specifically limit such removal methods.

[0097] In step S370, if Figure 9As shown, the third mask layer 330 is etched using the fourth mask layer 340 having the third mask hole 403 and the fourth mask hole 404 as a mask to form the first mask hole 401 and the second mask hole 402. During the etching process of the third mask layer 330, the etching rate of the third mask layer 330 must be greater than or equal to the etching rate of the fourth mask layer 340, and the thickness of the third mask layer 330 must be less than or equal to the thickness of the fourth mask layer 340. This ensures that the fourth mask layer 340 can protect the surface of the third mask layer 330 when etching the third mask layer 330, further ensuring the uniformity of the first mask hole 401 and the second mask hole 402.

[0098] In the second embodiment provided by the present disclosure, Figure 10 As shown, combined Figures 11 to 16 , forming a plurality of first mask holes 401 and a plurality of second mask holes 402 in the third mask layer 330 , including: steps S301 to S307 .

[0099] Wherein, step S301: forming a fourth mask layer 340 on the surface of the third mask layer 330;

[0100] Step S302 : forming a plurality of fifth mask holes 405 in the fourth mask layer 340 , each of which exposes the third mask layer 330 , wherein the orthographic projections of the fifth mask holes 405 on the first mask layer 310 are located on the mask structure 311 ;

[0101] Step S303: forming a fifth mask layer 350 on the surface of the fourth mask layer 340 having the fifth mask hole 405 , wherein the fifth mask layer 350 fills the fifth mask hole 405 ;

[0102] Step S304: forming a sixth mask layer 360 on the surface of the fifth mask layer 350, forming a second photoresist layer 520 on the surface of the sixth mask layer 360, exposing and developing the second photoresist layer 520 to form a plurality of second developed areas 521, wherein the orthographic projections of the second developed areas 521 on the first mask layer 310 are located on the mask structure 311;

[0103] Step S305: etching the sixth mask layer 360, the fifth mask layer 350, and the fourth mask layer 340 based on the second developing area 521 to form a plurality of sixth mask holes 406 in the fourth mask layer 340, each of which exposes the third mask layer 330. The fifth mask holes 405 and the sixth mask holes 406, whose orthographic projections are located on the same mask structure 311, are alternately distributed in the extending direction of the mask structure 311.

[0104] Step S306: removing the second photoresist layer 520, the sixth mask layer 360 and the fifth mask layer 350;

[0105] Step S307 : using the fourth mask layer 340 having the fifth mask hole 405 and the sixth mask hole 406 as a mask, etching the third mask layer 330 to form the first mask hole 401 and the second mask hole 402 .

[0106] Among them, in step S301 to step S302, if Figure 13 and Figure 14 As shown, a fourth mask layer 340 is formed on the surface of the third mask layer 330 ; a plurality of fifth mask holes 405 are formed in the fourth mask layer 340 to expose the third mask layer 330 respectively, and the orthographic projections of the fifth mask holes 405 on the first mask layer 310 are located on the mask structure 311 . Among them, multiple fifth mask holes 405 are formed in the fourth mask layer 340, including: stacking an intermediate fifth mask layer 351, an intermediate sixth mask layer 361 and an intermediate photoresist layer 530 in sequence on the fourth mask layer 340; exposing and developing the intermediate photoresist layer 530 to form multiple intermediate development areas 531 corresponding to each fifth mask hole 405; etching the fourth mask layer 340 based on the intermediate development areas 531 to form multiple fifth mask holes 405 in the fourth mask layer 340, and the orthographic projection of the fifth mask hole 405 on the first mask layer 310 is located on the mask structure 311; removing the intermediate photoresist layer 530, the intermediate sixth mask layer 361 and the intermediate fifth mask layer 351.

[0107] The intermediate fifth mask layer 351 can be made of the same material as the fifth mask layer 350, and the intermediate sixth mask layer 361 can be made of the same material as the sixth mask layer 360. When forming the fifth mask hole 405 on the fourth mask layer 340, the formation quality of the fifth mask hole 405 can be improved by forming the intermediate fifth mask layer 351 and the intermediate sixth mask layer 361 on the fourth mask layer 340.

[0108] In step S303, Figure 15As shown, a fifth mask layer 350 is formed on the surface of the fourth mask layer 340 having the fifth mask hole 405, and the fifth mask layer 350 fills the fifth mask hole 405. The fifth mask layer 350 can be made of the same material as the second mask layer 320. For example, the fifth mask layer 350 can include spin-on organic carbon (SOC) or spin-on hard mask (SOH). The method for forming the fifth mask layer 350 can be the same as or similar to the method for forming the second mask layer 320, and will not be described in detail here. In this embodiment, since the fifth mask layer 350 fills the fifth mask hole 405, when the fifth mask layer 350 is subsequently removed, the film layer residue in the fifth mask hole 405 can be reduced, thereby optimizing the process.

[0109] In step S304, Figure 15 As shown, a sixth mask layer 360 is formed on the surface of the fifth mask layer 350, and a second photoresist layer 520 is formed on the surface of the sixth mask layer 360. The second photoresist layer 520 is exposed and developed to form a plurality of second developed areas 521. The orthographic projections of the second developed areas 521 on the first mask layer 310 are located on the mask structure 311. The sixth mask layer 360 can be made of the same material as the fourth mask layer 340. For example, the sixth mask layer 360 can include silicon oxynitride (SiON). The method for forming the sixth mask layer 360 can be the same as or similar to the method for forming the fourth mask layer 340, and will not be repeated here.

[0110] In step S305, Figure 16 As shown, based on the second developing area 521, the sixth mask layer 360, the fifth mask layer 350, and the fourth mask layer 340 are etched to form a plurality of sixth mask holes 406 in the fourth mask layer 340, each of which exposes the third mask layer 330. The fifth mask holes 405 and the sixth mask holes 406, whose orthographic projections are located on the same mask structure 311, are alternately distributed in the extension direction of the mask structure 311. When etching the fourth mask layer 340, the third mask layer 330 can serve as an etch stop layer to ensure uniformity of the fifth mask holes 405 and the sixth mask layers 360 in the fourth mask layer 340.

[0111] In step S306, Figure 16As shown, the second photoresist layer 520, the sixth mask layer 360, and the fifth mask layer 350 are removed. The fifth mask layer 350 and the sixth mask layer 360 can be removed by methods such as chemical mechanical polishing (CMP), dry plasma etching, and thermal stripping. The fifth mask layer 350 and the sixth mask layer 360 can be removed separately or simultaneously. The specific removal method can be selected based on the actual process.

[0112] In step S307, Figure 9 As shown, the third mask layer 330 is etched using the fourth mask layer 340 having the fifth mask hole 405 and the sixth mask hole 406 as a mask to form the first mask hole 401 and the second mask hole 402. During the etching of the third mask layer 330, the etching rate of the third mask layer 330 must be greater than or equal to the etching rate of the fourth mask layer 340, and the thickness of the third mask layer 330 must be less than or equal to the thickness of the fourth mask layer 340. This ensures that the fourth mask layer 340 can protect the surface of the third mask layer 330 during the etching of the third mask layer 330, further ensuring the uniformity and structural integrity of the first mask hole 401 and the second mask hole 402.

[0113] In the embodiment provided by the present disclosure, in step S400, as Figure 10 As shown, the second mask layer 320 and the first mask layer 310 are etched using the third mask layer 330 having the first mask hole 401 and the second mask hole 402 as a mask to form a target mask pattern 600 in the first mask layer 310. In some embodiments, the target mask patterns 600 formed in the first mask layer 310 are distributed at equal intervals, and the spacing between two adjacent target mask patterns 600 can be selected according to the actual design requirements of the device. Of course, in other embodiments, the target mask patterns 600 formed in the first mask layer 310 can also be distributed at non-equal intervals. The distribution of the target mask patterns 600 can be regular or irregular, and can be selected according to actual design requirements, and is not specifically limited in this disclosure.

[0114] After forming the target mask pattern 600, the above-mentioned formation method further includes: removing the second mask layer 320. The second mask layer 320 can be removed by methods such as chemical wet etching, plasma etching, and thermal stripping to expose the first mask layer 310.

[0115] After removing the second mask layer 320, as shown in FIG. Figure 3and Figure 11 As shown, the above-mentioned formation method further includes: etching the active layer 100 using the first mask layer 310 having the target mask pattern 600 as a mask to form a plurality of active regions 200. Etching the active layer 100 may include etching the substrate 110 and the stacked structure within the active layer 100 to form the plurality of active regions 200 within the active layer 100. Of course, the specific composition of the active layer 100 can be selected according to the actual structural requirements of the device, that is, etching the active layer 100 may include etching the corresponding film layers within the active layer 100 used to form the device.

[0116] The present disclosure provides a method for forming a semiconductor structure, by forming a mask material layer on an active layer 100, the mask material layer including a first mask layer 310, a second mask layer 320 and a third mask layer 330 arranged in sequence, a plurality of first mask holes 401 and second mask holes 402 are formed in the third mask layer 330, each first mask hole 401 and each second mask hole 402 is alternately distributed in the extension direction of the mask structure 311, and the second mask layer 320 and the first mask layer 310 are etched using the third mask layer 330 as a mask to form a target mask pattern 600 in the first mask layer 310. The local critical dimension uniformity of the polysilicon layer openings in the active area 200 formed by this method is good, structural defects caused by the process are eliminated, the structural integrity of the active area 200 is ensured, the formation quality and performance of the device are improved, and the yield of the device is thereby improved.

[0117] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0118] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: forming an active layer; A mask material layer is formed on one side of the active layer, wherein the mask material layer includes a first mask layer, a second mask layer, and a third mask layer arranged in sequence, wherein the first mask layer includes a plurality of mask structures distributed at intervals; the second mask layer is located on a side of the first mask layer away from the active layer and fills the gaps between the mask structures; and the third mask layer is located on a surface of the second mask layer; forming a plurality of first mask holes and a plurality of second mask holes in the third mask layer, wherein the orthographic projections of the first mask holes on the first mask layer and the orthographic projections of the second mask holes on the first mask layer are both located on the mask structure, and the first mask holes and the second mask holes whose orthographic projections are located on the same mask structure are alternately distributed in an extension direction of the mask structure; The second mask layer and the first mask layer are etched using the third mask layer having the first mask hole and the second mask hole as a mask to form a target mask pattern in the first mask layer.

2. The forming method according to claim 1, wherein: Before forming the first mask hole and the second mask hole, the forming method further includes: forming a fourth mask layer on the surface of the third mask layer; The forming of a plurality of first mask holes and a plurality of second mask holes in the third mask layer comprises: forming a plurality of third mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the orthographic projections of the third mask holes on the first mask layer are located on the mask structure; forming a first photoresist layer on the surface of the fourth mask layer having the third mask hole, wherein the first photoresist layer fills the third mask hole; exposing and developing the first photoresist layer to form a plurality of first development areas, wherein orthographic projections of the first development areas on the first mask layer are located on the mask structure; etching the fourth mask layer based on the first developing area to form a plurality of fourth mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the third mask holes and the fourth mask holes whose orthographic projections are located on the same mask structure are alternately distributed in an extension direction of the mask structure; removing the first photoresist layer; The third mask layer is etched using the fourth mask layer having the third mask hole and the fourth mask hole as a mask to form the first mask hole and the second mask hole.

3. The forming method according to claim 1, wherein: Before forming the first mask hole and the second mask hole, the forming method further includes: forming a fourth mask layer on the surface of the third mask layer; The forming of a plurality of first mask holes and a plurality of second mask holes in the third mask layer comprises: forming a plurality of fifth mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the orthographic projections of the fifth mask holes on the first mask layer are located on the mask structure; forming a fifth mask layer on the surface of the fourth mask layer having the fifth mask hole, wherein the fifth mask layer fills the fifth mask hole; forming a sixth mask layer on the surface of the fifth mask layer, forming a second photoresist layer on the surface of the sixth mask layer, exposing and developing the second photoresist layer to form a plurality of second development areas, wherein orthographic projections of the second development areas on the first mask layer are located on the mask structure; etching the sixth mask layer, the fifth mask layer, and the fourth mask layer based on the second developing area to form a plurality of sixth mask holes in the fourth mask layer, each of which exposes the third mask layer, wherein the fifth mask holes and the sixth mask holes whose orthographic projections are located on the same mask structure are alternately distributed in an extension direction of the mask structure; removing the second photoresist layer, the sixth mask layer, and the fifth mask layer; The third mask layer is etched using the fourth mask layer having the fifth mask hole and the sixth mask hole as a mask to form the first mask hole and the second mask hole.

4. The forming method according to claim 2 or 3, characterized in that: During the etching of the third mask layer, an etching rate of the third mask layer is greater than or equal to an etching rate of the fourth mask layer, and a thickness of the third mask layer is less than or equal to a thickness of the fourth mask layer.

5. The forming method according to claim 4, wherein: The material of the third mask layer includes silicon oxide, and the material of the fourth mask layer includes silicon oxynitride.

6. The forming method according to claim 4, wherein: The thickness of the fourth mask layer is 26-30 nm, and the thickness of the third mask layer is 20-28 nm.

7. The forming method according to any one of claims 1 to 3, characterized in that: The forming method further comprises: After forming the target mask pattern, the second mask layer is removed.

8. The forming method according to claim 7, wherein: The material of the first mask layer includes polysilicon, and the material of the second mask layer includes spin-on organic carbon.

9. The forming method according to claim 7, wherein: The forming method further comprises: The active layer is etched using the first mask layer having the target mask pattern as a mask to form a plurality of active regions.

10. The forming method according to claim 9, wherein: The target mask patterns are distributed at equal intervals.

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