Memory cell, manufacturing method thereof and semiconductor structure

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a storage unit, a manufacturing method thereof and a semiconductor structure, and the storage unit comprises a first word line which extends along a first direction; the first bit line extends in the first direction, the first bit line and the first word line are arranged in the second direction, and the first bit line and the first word line are spaced; the first channel layer is positioned between the first bit line and the first word line, and is electrically connected with the first bit line and the first word line respectively; a second word line extending in a third direction; the second channel layer extends in the third direction, surrounds the second word line and controls the transmission path between the first word line and the first bit line to be switched on and switched off; and the second bit line is at least positioned on one side of the second word line along the second direction, is electrically connected with the second channel layer, and is separated from the first word line and the first bit line in the third direction, and a new storage unit structure can be provided.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a storage unit and a manufacturing method thereof, as well as a semiconductor structure. Background Art

[0002] Common dynamic random access memory (DRAM) is of the 1T1C (1Transistor-1Capacitor) type, that is, a transistor source or drain is electrically connected to a capacitor to form a storage unit structure. This structure uses capacitors to store data, but because the capacitor consumes power when reading, and the capacitor itself also leaks electricity, it is necessary to constantly refresh the charge in the capacitor, which makes DRAM power consumption high and the electrical performance unstable. At the same time, because the process of manufacturing capacitors occupies a large area, miniaturization has also become a problem.

[0003] In order to overcome the problem caused by capacitance, a 2T0C type memory cell structure is used, that is, a source or drain of a transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the invention

[0004] The embodiments of the present disclosure provide a storage unit, which can at least propose a new 2T0C structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a storage unit, comprising: a first word line extending along a first direction; a first bit line extending along the first direction, the first bit line and the first word line are arranged along a second direction, and the first bit line is spaced apart from the first word line; a first channel layer, the first channel layer is located between the first bit line and the first word line, and is electrically connected to the first bit line and the first word line respectively, a first transistor comprises: the first word line, the first bit line and the first channel layer; a second word line extending along a third direction; a second channel layer extending along the third direction, the second channel layer is arranged opposite to the second word line, the second channel layer controls the conduction and disconnection of a transmission path between the first word line and the first bit line; a second bit line, the second bit line is at least located on one side of the second word line along the second direction, and is electrically connected to the second channel layer, and is spaced apart from the first word line and the first bit line in the third direction, a second transistor comprises: the second word line, the second channel layer and the second bit line.

[0006] In some embodiments, the first transistor further includes: a first metal oxide layer, the first metal oxide layer is in contact with the second channel layer and is arranged opposite to the first channel layer; the second transistor further includes: a second metal oxide layer, the second metal oxide layer is in contact with the second channel layer and the second bit line, and the second metal oxide layer is spaced apart from the first metal oxide layer.

[0007] In some embodiments, the first metal oxide layer surrounds the second channel layer, and the first transistor further includes: a first dielectric layer, the first dielectric layer surrounds the first metal oxide layer, and the first channel layer surrounds the first dielectric layer.

[0008] In some embodiments, the second metal oxide layer surrounds the second channel layer, and the second bit line surrounds the second metal oxide layer.

[0009] In some embodiments, the second transistor further includes: a second dielectric layer, wherein the second dielectric layer is located between the second word line and the second channel layer.

[0010] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including a plurality of memory cells as described above, and the plurality of memory cells are arranged at intervals along the first direction and the third direction, and the first word lines of the plurality of memory cells are located on the same side of the second word line along the second direction.

[0011] In some embodiments, the method further includes: a first conductive column, the first conductive column is in contact with and connected to the first word line, and the first word lines of a plurality of the memory cells are in contact with and connected to the same first conductive column.

[0012] In some embodiments, it also includes: a second conductive column, the second conductive column is in contact with the first bit line; a third conductive column is in contact with the second bit line, the second conductive columns connected to different first bit lines are adjacent along the first direction, and the third conductive columns connected to different second bit lines are adjacent along the first direction.

[0013] In some embodiments, it also includes: a second conductive column, the second conductive column is connected to the first bit line; a third conductive column, the third conductive column is connected to the second bit line, and the second conductive column and the third conductive column are arranged alternately along the first direction.

[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a storage unit, comprising: forming a first transistor, the first transistor comprising: a first word line extending along a first direction, a first bit line extending along the first direction, the first bit line and the first word line are arranged along a second direction, and the first bit line is spaced apart from the first word line, a first channel layer, the first channel layer is located between the first bit line and the first word line, and is respectively in contact with and connected to the first bit line and the first word line; forming a second transistor, the second transistor comprising: a second word line extending along a third direction, a second channel layer extending along the third direction, the second channel layer is arranged opposite to the second word line, the second channel layer controls the conduction and disconnection of a transmission path between the first word line and the first bit line, and a second bit line, the second bit line is at least located on one side of the second word line along the second direction, and is electrically connected to the second channel layer, and is spaced apart from the first word line and the first bit line in the third direction.

[0015] In some embodiments, the method of forming the second transistor includes: providing a stacking structure, the stacking structure including a first sacrificial layer, a second sacrificial layer, a first insulating layer and a third sacrificial layer stacked in sequence; etching the stacking structure to form a first groove penetrating the stacking structure; forming a second channel layer, the second channel layer covering the inner wall of the first groove; forming a second word line, the second word line is located in the first groove and fills the first groove; removing the third sacrificial layer, and forming the second bit line, the second bit line is located on the top surface of the first insulating layer, and the second bit line is electrically connected to the second channel layer.

[0016] In some embodiments, the method of forming the first transistor includes: removing the second sacrificial layer to form a second groove; forming the first channel layer, the first channel layer is located in the second groove; forming the first word line and the first bit line, the first word line and the first bit line are located in the second groove, the first word line and the first bit line are arranged at intervals along the second direction, and the first word line and the first bit line are both in contact with the first channel layer.

[0017] In some embodiments, before forming the first word line and the first bit line, the method further includes: forming a second insulating layer, wherein the second insulating layer covers the sidewalls of the first channel layer arranged along the first direction.

[0018] In some embodiments, the method of forming the second insulating layer includes: forming a second initial insulating layer, wherein the second initial insulating layer fills the second groove; and etching the second initial insulating layer to expose the sidewall of the first channel layer arranged along the second direction.

[0019] In some embodiments, before forming the first channel layer, the process also includes: etching the exposed second sacrificial layer and the third sacrificial layer along the first groove to form a third groove, wherein the third groove exposes a portion of the top surface of the first insulating layer and the first sacrificial layer; forming a first metal oxide layer, wherein the first metal oxide layer is located in the third groove between the second sacrificial layer and the second channel layer; and forming a second metal oxide layer, wherein the second metal oxide layer is located in the third groove on the top surface of the first insulating layer.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the second transistor can be used as a write transistor, the first transistor can be used as a read transistor, wherein the second word line can be used as the gate of the second transistor, and when an electrical signal is input to the second word line, the second word line is turned on, and the signal on the second bit line can be transmitted to the second channel layer, so that the second channel layer can control the first channel layer of the first transistor to transmit the signal, so that the signal can be transmitted between the first bit line and the first word line, and when the signal can be read from between the first bit line and the first word line, it indicates that data information is stored in the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of the structure of a storage unit provided in one embodiment of the present disclosure;

[0023] Figure 2 A cross-sectional view of a storage unit provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the structure of a second storage unit provided in an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 5 A cross-sectional view of a semiconductor structure provided in accordance with an embodiment of the present disclosure;

[0027] Figure 6 to Figure 32A schematic structural diagram corresponding to each step of a method for manufacturing a storage unit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] From the background technology, it is known that it is necessary to propose a new 2T0C structure.

[0029] The present disclosure implements a storage unit, in which a second transistor can be used as a write transistor, and a first transistor can be used as a read transistor, wherein a second word line can be used as a gate of the second transistor. When an electrical signal is input to the second word line, the second word line is turned on, and the signal on the second bit line can be transmitted to the second channel layer, so that the second channel layer can control the first channel layer of the first transistor to transmit a signal, thereby transmitting a signal between the first bit line and the first word line. When a signal can be read from between the first bit line and the first word line, it indicates that data information is stored in the storage unit.

[0030] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0031] refer to Figures 1 to 3 , Figure 1 A schematic diagram of a storage unit according to an embodiment of the present disclosure is shown in FIG. Figure 2 An embodiment of the present disclosure provides Figure 1 Cross-section along BB direction; Figure 3 A cross-sectional view of a second storage unit provided in accordance with an embodiment of the present disclosure.

[0032] In some embodiments, the memory cell may include: a first word line 100 extending along a first direction X.

[0033] The memory cell may include a first bit line 110 extending along a first direction X, the first bit line 110 and the first word line 100 being arranged along a second direction Y, and the first bit line 110 and the first word line 100 being spaced apart.

[0034] The memory cell may include a first channel layer 120 located between the first bit line 110 and the first word line 100 and electrically connected to the first bit line 110 and the first word line 100 respectively. The first transistor 130 includes the first word line 100 , the first bit line 110 and the first channel layer 120 .

[0035] The memory cell may include a second word line 200 extending along a third direction Z.

[0036] The memory cell may include: a second channel layer 220 extending along a third direction Z, the second channel layer 220 being disposed opposite to the second word line 200 , and the second channel layer 220 controlling the conduction and disconnection of a transmission path between the first word line 100 and the first bit line 110 .

[0037] The memory cell may include: a second bit line 210, the second bit line 210 is located at least on one side of the second word line 200 along the second direction Y, and is electrically connected to the second channel layer 220, and is spaced apart from the first word line 100 and the first bit line 110 in the third direction Z, and the second transistor 230 includes: a second word line 200, a second channel layer 220 and a second bit line 210.

[0038] The second transistor 230 can be used as a write transistor, and the first transistor 130 can be used as a read transistor, wherein the second word line 200 can be used as the gate of the second transistor 230. When an electrical signal is input to the second word line 200, the second word line 200 is turned on, and the signal on the second bit line 210 can be transmitted to the second channel layer 220, so that the second channel layer 220 can control the first channel layer 120 of the first transistor 130 to transmit signals, so that signals can be transmitted between the first bit line 110 and the first word line 100. When the signal can be read from between the first bit line 110 and the first word line 100, it indicates that data information is stored in the storage unit.

[0039] In some embodiments, the second bit line 210 can be in direct contact with the second channel layer 220. In this way, when a high-level signal is received on the second word line 200, the second channel layer 220 can be turned on under the influence of the second word line 200, so that the signal on the second bit line 210 can be transmitted to the second channel layer 220. At this time, the second channel layer 220 can also serve as the gate of the first transistor 130, that is, it receives a high-level signal and controls the first channel layer 120 of the first transistor 130 to be turned on, and the first bit line 110 and the first word line 100 respectively connected to the first channel layer 120 can also transmit signals to each other, thereby forming a 2T0C structure.

[0040] In some embodiments, taking the second word line 200 as a rectangular parallelepiped as an example, the second channel layer 220 can be arranged opposite to only three of the three side surfaces of the rectangular parallelepiped, that is, signal transmission can be achieved. The second channel layer 220 can also surround the entire side surface of the second word line 200, and surrounding the entire side surface of the second word line 200 can relatively increase the length of the second channel layer 220 and reduce the short channel effect of the second transistor 230.

[0041] It should be noted that the above description is only based on a rectangular parallelepiped as an example, the second word line 200 may also be cylindrical, and the second channel layer 220 may only surround a portion of the sidewall of the cylinder, or may surround the entire sidewall of the cylinder.

[0042] In some embodiments, the material of the second word line 200 can be a metal material, such as tungsten or cobalt. By setting the material of the second word line 200 to a metal material, the data transmission rate on the second word line 200 can be increased and the resistance of the semiconductor structure can be reduced.

[0043] In some embodiments, the second bit line 210 may be located only on one side of the second word line 200 along the second direction Y, and only needs to be electrically connected to the second channel layer 220 to transmit the signal to the first transistor 130 through the second channel layer 220, thereby controlling the conduction of the transmission path between the first word line 100 and the first bit line 110 in the first transistor 130. In some embodiments, the second bit line 210 may also surround the second channel layer 220, thereby increasing the contact area between the second bit line 210 and the second channel layer 220 and reducing the contact resistance between the second bit line 210 and the second channel layer 220.

[0044] In some embodiments, the material of the second bit line 210 may be a metal material, such as tungsten or cobalt. By setting the material of the second bit line 210 to be a metal material, the data transmission rate on the second bit line 210 may be increased, and the resistance of the semiconductor structure may be reduced. In some embodiments, the material of the second bit line 210 may be the same as the material of the second word line 200.

[0045] In some embodiments, the second channel layer 220 surrounds the entire side of the second word line 200 , and the second bit line 210 may surround the entire side of the second channel layer 220 .

[0046] In some embodiments, the material of the second channel layer 220 may be a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide).

[0047] In some embodiments, the first channel layer 120 can surround part of the side wall of the second channel layer 220, and the first channel layer 120 only needs to ensure electrical connection with the first word line 100 and the first bit line 110 respectively to realize the transmission signal between the first word line 100 and the first bit line 110; in some embodiments, the first channel layer can also surround the entire side wall of the second channel layer 220, so as to increase the channel length of the first transistor 130, and then reduce the short channel effect in the first transistor 130.

[0048] In some embodiments, the material of the first channel layer 120 may also be a metal oxide material, such as IGZO (Indium Gallium Zinc Oxide).

[0049] In some embodiments, the material of the first word line 100 may be a metal material, such as tungsten or cobalt. By setting the material of the first word line 100 to be a metal material, the data transmission rate on the first word line 100 may be increased and the resistance of the storage unit may be reduced.

[0050] In some embodiments, the material of the first bit line 110 may be a metal material, such as tungsten or cobalt. By setting the material of the first bit line 110 to be a metal material, the data transmission rate on the first bit line 110 may be increased, and the resistance of the semiconductor structure may be reduced. In some embodiments, the material of the first bit line 110 may be the same as the material of the first word line 100.

[0051] In some embodiments, the material of the first bit line 110 may be different from the material of the second bit line 210, and the material of the first word line 100 may be different from the material of the second word line 200. By setting the material of the first bit line 110 to be different from the material of the second bit line 210 and the material of the first word line 100 to be different from the material of the second word line 200, the production of the storage unit can be facilitated.

[0052] In some embodiments, the first transistor 130 also includes: a first metal oxide layer 140, the first metal oxide layer 140 is in contact with the second channel layer 220 and is arranged opposite to the first channel layer 120; the second transistor 230 also includes: a second metal oxide layer 240, the second metal oxide layer 240 is in contact with the second channel layer 220 and the second bit line 210, and the second metal oxide layer 240 is spaced apart from the first metal oxide layer 140. By setting the first metal oxide layer 140, when the signal of the second bit line 210 is transmitted through the second channel layer 220, it is first transmitted to the first metal oxide layer 140. At this time, the first metal oxide layer 140 serves as the gate of the first transistor 130, and then controls the first channel layer 120 of the first transistor 130 to be turned on, thereby turning on the transmission path between the first bit line 110 and the first word line 100. By setting the second metal oxide layer 240, and the second metal oxide layer is connected to the second bit line 210 and the second channel layer 220 respectively, it is possible to avoid direct connection between the second bit line 210 and the second channel layer 220, avoid excessive difference in material properties between the second bit line 210 and the second channel layer 220, and avoid abnormal signal transmission.

[0053] In some embodiments, the material of the first metal oxide layer 140 may include metal oxides such as indium tin oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, or indium gallium zinc oxide. In some embodiments, the material of the second metal oxide layer 240 may include metal oxides such as indium tin oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, or indium gallium zinc oxide. In some embodiments, the material of the first metal oxide layer 140 may be the same as the material of the second metal oxide layer 240.

[0054] In some embodiments, the first metal oxide layer 140 surrounds the second channel layer 220, and the first transistor 130 further includes: a first dielectric layer 150, the first dielectric layer 150 surrounds the first metal oxide layer 140, and the first channel layer 120 surrounds the first dielectric layer 150. By providing the first metal oxide layer 140 to surround the second channel layer 220, the contact area between the first metal oxide layer 140 and the second channel layer 220 can be increased, and the contact resistance between the first metal oxide layer 140 and the second channel layer 220 can be reduced. By providing the first dielectric layer 150, the first metal oxide layer 140 can be prevented from directly contacting the first word line 100 and the first bit line 110, and the abnormal performance of the storage unit can be avoided. By providing the first channel layer 120 to surround the first dielectric layer 150, the relative channel length of the first channel layer 120 can be increased, and the short channel effect of the first transistor 130 can be reduced.

[0055] In some embodiments, the first metal oxide layer may be absent, and the first dielectric layer 150 is located between the first channel layer 120 and the second channel layer 220 , thereby avoiding carrier transmission between the first channel layer 120 and the second channel layer 220 and avoiding abnormal performance of the first transistor 130 .

[0056] In some embodiments, the material of the first dielectric layer 150 may be a material with a high dielectric constant such as hafnium oxide. By setting the material of the first dielectric layer 150 to be a material with a high dielectric constant such as hafnium oxide, the leakage current between the first metal oxide layer 140 and the first channel layer 120 can be reduced.

[0057] In some embodiments, the second metal oxide layer 240 surrounds the second channel layer 220, and the second bit line 210 surrounds the second metal oxide layer 240. By disposing the second metal oxide layer 240 to surround the second channel layer 220, the contact area between the second metal oxide layer 240 and the second channel layer 220 can be increased, and by the second bit line 210 surrounding the second metal oxide layer 240, the contact area between the second bit line 210 and the second metal oxide layer 240 can be increased, so that the contact resistance between the second metal oxide layer 240 and the second channel layer 220 can be reduced, and the contact resistance between the second bit line 210 and the second metal oxide layer 240 can be reduced, thereby improving the performance of the memory cell.

[0058] In some embodiments, the second transistor 230 further includes a second dielectric layer 250, and the second dielectric layer 250 is located between the second word line 200 and the second channel layer 220. The second dielectric layer 250 can avoid direct contact between the second word line 200 and the second channel layer 220, and prevent carriers on the second channel layer 220 from directly flowing to the second word line 200.

[0059] In some embodiments, the second dielectric layer 250 may be made of a material with a high dielectric constant such as hafnium oxide. By setting the second dielectric layer to be made of a material with a high dielectric constant such as hafnium oxide, the leakage current between the second word line 200 and the second channel layer 220 can be reduced.

[0060] It should be noted that the dielectric constant here refers to: relative dielectric constant, with the value of the absolute dielectric constant of free space or vacuum being considered as the standard. The relative dielectric constant refers to the ratio of the absolute dielectric constant of any material to the absolute dielectric constant of free space or vacuum.

[0061] In some embodiments, it may also include: a first insulating layer 160, the first insulating layer 160 is located between the second word line 200 and the first word line 100, and is used to isolate the second word line 200 from the first word line 100, and the first insulating layer 160 is also located between the second word line 200 and the first bit line 110, and is used to isolate the second word line 200 from the first bit line 110, and the first insulating layer 160 is also located between the first metal oxide layer 140 and the second metal oxide layer 240, and is used to isolate the first metal oxide layer 140 from the second metal oxide layer 240.

[0062] In some embodiments, the memory cell may further include: a second insulating layer 170, the second insulating layer 170 covers the side walls of the first channel layer 120 arranged along the first direction X, and the second insulating layer 170 is used to separate the first word line 100 from the first bit line 110, thereby avoiding electrical connection between the first word line 100 and the first bit line 110.

[0063] In some embodiments, the memory cell may further include: a third insulating layer 180, the third insulating layer 180 covers the bottom surface of the first word line 100, the first bit line 110 and the first channel layer 120 arranged along the third direction Z, and the first word line 100, the first bit line 110 and the first channel layer 120 can be supported by forming the third insulating layer 180.

[0064] In some embodiments, the memory cell further includes a first metal oxide layer 140 , and the third insulating layer 180 further covers the bottom surface of the first metal oxide layer 140 arranged along the third direction Z to support the first metal oxide layer 140 .

[0065] In some embodiments, the storage unit also includes: a first conductive column 190, the first conductive column 190 is in contact with the first word line 100; a second conductive column 260, the second conductive column 260 is in contact with the first bit line 110; a third conductive column 270, the third conductive column 270 is in contact with the second bit line 210, and data information is provided to the first word line 100, the first bit line 110 and the second bit line 210 through the first conductive column 190, the second conductive column 260 and the third conductive column 270, respectively, or the data information in the first word line 100, the first bit line 110 and the second bit line 210 is led out.

[0066] In some embodiments, the second conductive pillar 260 also penetrates the second bit line 210 and connects with the first bit line 110 , and a fourth insulating layer 280 is included between the second conductive pillar 260 and the second bit line 210 . The fourth insulating layer 280 can prevent the second conductive pillar 260 from being electrically connected to the second bit line 210 .

[0067] In the embodiment of the present disclosure, the second transistor 230 is used as a write transistor and the first transistor 130 is used as a read transistor, wherein the second word line 200 can be used as the gate of the second transistor 230. When an electrical signal is input to the second word line 200, the second word line 200 is turned on, and the signal on the second bit line 210 can be transmitted to the second channel layer 220, so that the second channel layer 220 can control the first channel layer 120 of the first transistor 130 to transmit signals, so that signals can be transmitted between the first bit line 110 and the first word line 100. When the signal can be read from between the first bit line 110 and the first word line 100, it indicates that data information is stored in the storage unit.

[0068] Another embodiment of the present disclosure further provides a semiconductor structure, which includes multiple storage units such as some or all of the above-mentioned embodiments. The semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the same or corresponding parts of the above-mentioned embodiments can refer to the corresponding description of the above-mentioned embodiments and will not be repeated below.

[0069] refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 Cross-section along CC direction.

[0070] In some embodiments, the semiconductor structure includes: multiple memory cells as described in some or all of the above embodiments, and the multiple memory cells are arranged at intervals along the first direction X and the third direction Z, and the first word lines 100 of the multiple memory cells are located on the same side of the second word lines 200 along the second direction Y.

[0071] By providing a plurality of memory cells, and the first word lines 100 of the plurality of memory cells are located on the same side of the second word line 200 along the second direction Y, the manufacturing process of the entire semiconductor structure can be facilitated and the morphology of the entire semiconductor structure can be improved.

[0072] In some embodiments, the semiconductor structure further includes: a first conductive pillar 190, the first conductive pillar 190 is in contact with the first word line 100, and the first word lines 100 of the plurality of memory cells are in contact with the same first conductive pillar 190. Taking the first word lines 100 of the plurality of memory cells arranged at intervals along the third direction Z as an example, the plurality of first word lines 100 arranged at intervals along the third direction Z are connected through one first conductive pillar 190. For example, if the first word line 100 needs to be fed with a ground signal, the ground signal can be fed into the first conductive pillar 190, so that the signals on the plurality of first word lines 100 can be controlled by one first conductive pillar 190.

[0073] In some embodiments, a plurality of memory cells are arranged at intervals along a first direction X, and the first word lines 100 of the memory cells arranged at intervals along the first direction are electrically connected to each other. In other words, an electrical signal is applied to one first word line 100, and in fact, an electrical signal is applied to all the memory cells arranged at intervals along the first direction. In some embodiments, a plurality of first word lines 100 arranged at intervals along a third direction Z are connected through a first conductive pillar 190, so that a first conductive pillar 190 is actually connected to the first word lines 100 of the memory cells arranged along the first direction X and the third direction Z.

[0074] In some embodiments, the first word lines 100 of the memory cells arranged at intervals along the first direction may be an integrated structure, and the first bit lines 110 of the memory cells arranged at intervals along the first direction may be an integrated structure.

[0075] In some embodiments, the device may further include: a second conductive pillar 260, a second conductive pillar 260 being in contact with and connected to a first bit line 110; and a third conductive pillar 270, a third conductive pillar 270 being in contact with and connected to a second bit line 210, the second conductive pillars 260 connecting different first bit lines 110 being adjacent to each other along the first direction X, and the third conductive pillars 270 connecting different second bit lines 210 being adjacent to each other along the first direction X. The second conductive pillars 260 are used to pass an electrical signal to the first bit line 110 or the electrical signal in the first bit line 110 is led out through the second conductive pillars 260, and the third conductive pillars 270 are used to pass an electrical signal to the second bit line 210 or the electrical signal in the second bit line 210 is led out through the second conductive pillars 260. By arranging the second conductive pillars 260 connecting different first bit lines 110 to be adjacent to each other along the first direction X, and the third conductive pillars 270 connecting different second bit lines 210 to be adjacent to each other along the first direction X, the process steps of the entire semiconductor structure can be facilitated.

[0076] In some embodiments, the second conductive pillars 260 connected to different memory cells are spaced apart from each other, and the third conductive pillars 270 connected to different memory cells are spaced apart from each other.

[0077] In some embodiments, the device may further include: a second conductive pillar 260, a second conductive pillar 260 is in contact with a first bit line 110; a third conductive pillar 270, a third conductive pillar 270 is in contact with a second bit line 210, and the second conductive pillar 260 and the third conductive pillar 270 are arranged alternately along the first direction X. An electrical signal is input to the first bit line 110 through the second conductive pillar 260 or the electrical signal in the first bit line 110 is led out through the second conductive pillar 260, an electrical signal is input to the second bit line 210 through the third conductive pillar 270 or the electrical signal in the second bit line 210 is led out through the second conductive pillar 260, and the second conductive pillar 260 and the third conductive pillar 270 are arranged alternately along the first direction X, so that the second conductive pillar 260 can be formed in units of one storage unit, and it is also convenient to check each storage unit.

[0078] In some embodiments, the first word lines 100 of the memory cells arranged at intervals along the first direction X are an integrated structure, the first bit lines 110 of the memory cells arranged at intervals along the first direction X are an integrated structure, part of the second conductive pillars 260 also penetrate the first bit lines 110 and the second bit lines 210 of part of other memory cells, and a fourth insulating layer 280 is provided between the part of the second conductive pillars 260 and the first bit lines 110 and the second bit lines 210 of the other memory cells, thereby avoiding electrical connection between the second conductive pillars 260 and the first bit lines 110 and the second bit lines 210 of the other memory cells; part of the third conductive pillars 270 also penetrate the first bit lines 110 and the second bit lines 210 of part of other memory cells, and a fourth insulating layer 280 is provided between the part of the third conductive pillars 270 and the first bit lines 110 and the second bit lines 210 of the other memory cells, thereby avoiding electrical connection between the third conductive pillars 270 and the first bit lines 110 and the second bit lines 210 of the other memory cells.

[0079] For example, the semiconductor structure includes two memory cells arranged along a third direction, namely a first memory cell and a second memory cell. The first memory cell is located above the second memory cell. Therefore, the second conductive column 260 connected to the second memory cell also passes through the first bit line 110 and the second bit line 210 of the first memory cell. Therefore, there is a fourth insulating layer 280 between the second conductive column 260 connected to the second memory cell and the first bit line 110 and the second bit line 210 of the first memory cell, thereby avoiding electrical connection between the first bit line 110 and the second bit line 210 of the first memory cell and the second memory cell.

[0080] In some embodiments, the second word lines 200 of the memory cells arranged along the third direction Z are connected to each other; in some embodiments, the second word lines 200 of the memory cells arranged along the third direction Z can be an integrated structure; in some embodiments, the second dielectric layer 250 of the memory cells arranged along the third direction Z can be an integrated structure.

[0081] Another embodiment of the present disclosure further provides a method for manufacturing a storage unit, which can be used to manufacture the above-mentioned storage unit. The method for manufacturing a storage unit provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the same or corresponding parts of the aforementioned embodiments can refer to the corresponding description of the aforementioned embodiments and will not be repeated below.

[0082] refer to Figure 6 to Figure 32 , Figure 6 to Figure 32 A schematic structural diagram corresponding to each step of a method for manufacturing a storage unit provided in one embodiment of the present disclosure.

[0083] In some embodiments, the manufacturing method of the memory cell may include: forming a first transistor 130, the first transistor 130 includes: a first word line 100 extending along a first direction X, a first bit line 110 extending along the first direction X, the first bit line 110 and the first word line 100 are arranged along a second direction Y, and the first bit line 110 is spaced from the first word line 100, and a first channel layer 120, the first channel layer 120 is located between the first bit line 110 and the first word line 100, and is respectively in contact with the first bit line 110 and the first word line 100; forming a second Transistor 230, the second transistor 230 includes: a second word line 200 extending along a third direction Z, a second channel layer 220 extending along the third direction Z, the second channel layer 220 and the second word line 200 are arranged opposite to each other, the second channel layer 220 controls the conduction and disconnection of the transmission path between the first word line 100 and the first bit line 110, and the second bit line 210, the second bit line 210 is at least located on one side of the second word line 200 along the second direction Y, and is electrically connected to the second channel layer 220, and is spaced apart from the first word line 100 and the first bit line 110 in the third direction Z.

[0084] By forming the first transistor 130, it can be used as a read transistor, and by forming the second transistor 230, it can be used as a write transistor, wherein the second word line 200 can be used as the gate of the second transistor 230. When an electrical signal is input to the second word line 200, the second word line 200 is turned on, and the signal on the second bit line 210 can be transmitted to the second channel layer 220, so that the second channel layer 220 can control the first channel layer 120 of the first transistor 130 to transmit the signal, so that the signal can be transmitted between the first bit line 110 and the first word line 100. When the signal can be read from between the first bit line 110 and the first word line 100, it indicates that data information is stored in the storage unit.

[0085] refer to Figures 6 to 16 In some embodiments, the method of forming the second transistor 230 may include: providing a stack structure 290, the stack structure 290 including a first sacrificial layer 291, a second sacrificial layer 292, a first insulating layer 160 and a third sacrificial layer 293 stacked in sequence; etching the stack structure 290 to form a first groove 300 penetrating the stack structure 290; forming a second channel layer 220, the second channel layer 220 covering the inner wall of the first groove 300; forming a second word line 200, the second word line 200 is located in the first groove 300 and fills the first groove 300; removing the third sacrificial layer 293, and forming a second bit line 210, the second bit line 210 is located on the top surface of the first insulating layer 160, and the second bit line 210 is electrically connected to the second channel layer 220. By first forming the stack structure, deformation of the film layer can be avoided when forming the second channel layer 220, the second word line 200 and the second bit line 210, thereby improving the quality of the formed second transistor 230.

[0086] refer to Figure 6 , providing a stacked structure 290. In some embodiments, the materials of the first sacrificial layer 291, the second sacrificial layer 292, the first insulating layer 160 and the third sacrificial layer 293 may be different from each other, so that they will not affect each other during the subsequent etching of each film layer, thereby improving the reliability of the formed semiconductor structure.

[0087] In some embodiments, the material of the first sacrificial layer 291 may include silicon oxyfluoride, the material of the second sacrificial layer 292 may include polysilicon, and the material of the third sacrificial layer 293 may include silicon nitride.

[0088] refer to Figures 7 to 10 ,in, Figure 8 for Figure 7 The cross-section along the DD direction, Fig.10 for Fig. 9The cross-sectional view along the DD direction. Before forming the first channel layer, the method further includes: etching the exposed second sacrificial layer 292 and the third sacrificial layer 293 along the first groove 300 to form a third groove 310, wherein the third groove 310 exposes a portion of the top surface of the first insulating layer 160 and the first sacrificial layer 291; forming a first metal oxide layer 140, wherein the first metal oxide layer 140 is located in the third groove 310 between the second sacrificial layer 292 and the second channel layer 220; and forming a second metal oxide layer 240, wherein the second metal oxide layer 240 is located in the third groove 310 on the top surface of the first insulating layer 160. The third groove 310 is formed to provide a process basis for forming the first metal oxide layer 140 and the second metal oxide layer 240. The first metal oxide layer 140 is formed so that when the signal of the second bit line 210 is transmitted through the second channel layer 220, it is first transmitted to the first metal oxide layer 140. At this time, the first metal oxide layer 140 serves as the gate of the first transistor 130, and then the first channel layer 120 of the first transistor 130 is controlled to be turned on, thereby turning on the transmission path between the first bit line 110 and the first word line 100. The second metal oxide layer 240 is formed, and the second metal oxide layer is connected to the second bit line 210 and the second channel layer 220 respectively, so that the second bit line 210 and the second channel layer 220 are avoided to be directly connected, and the material property difference between the second bit line 210 and the second channel layer 220 is avoided to be too large, and abnormal signal transmission is avoided.

[0089] In some embodiments, before forming the second channel layer 220, the process may also include: etching the first sacrificial layer 291 exposed along the first groove, so that when the second word line 200 is subsequently formed, the width of the second word line 200 on the same layer as the first sacrificial layer 291 is greater than the width of the second word line 200 on the same layer as the first insulating layer 160, thereby increasing the contact area of ​​the second word line of the storage unit arranged along the third direction.

[0090] refer to Fig.11 and Fig.12 , Fig.12 for Fig.11 A cross-sectional view along the DD direction; after forming the second channel layer 220 and before forming the second word line 200, it also includes: forming a second dielectric layer 250, by forming the second dielectric layer 250 can prevent the carriers in the second channel layer 220 from flowing directly to the second word line 200, avoiding the abnormality of the second transistor 230.

[0091] refer to Fig.13 and Fig.14 , Fig.14 for Fig.13 The third sacrificial layer 293 is removed, and the process basis for the subsequent formation of the second bit line 210 is provided by removing the third sacrificial layer 293 .

[0092] refer to Fig.15 and Fig.16 , Fig.16 for Fig.15 A cross-sectional view along the DD direction; a second bit line 210 is formed.

[0093] refer to Figures 17 to 26 The method for forming the first transistor 130 includes: removing the second sacrificial layer 292 to form a second groove 320; forming a first channel layer 120, wherein the first channel layer 120 is located in the second groove 320; forming a first word line 100 and a first bit line 110, wherein the first word line 100 and the first bit line 110 are located in the second groove 320, and the first word line 100 and the first bit line 110 are arranged at intervals along the second direction Y, and both the first word line 100 and the first bit line 110 are in contact with and connected to the first channel layer 120.

[0094] refer to Fig.17 and Fig.18 , Fig.18 for Fig.17 The cross-sectional view along the DD direction; the second sacrificial layer 292 is removed to form a second groove 320.

[0095] refer to Fig.19 and Fig. 20 , Fig. 20 for Fig.19 A cross-sectional view along the DD direction; in some embodiments, before forming the first channel layer 120 , the process further includes: forming a first dielectric layer 150 . By forming the first dielectric layer 150 , carriers of the first channel layer 120 can be prevented from flowing directly to the second channel layer.

[0096] In some embodiments, a first metal oxide layer 140 is further formed, and the first dielectric layer 150 further covers the sidewalls of the first metal oxide layer.

[0097] After forming the first dielectric layer 150 , the first channel layer 120 is formed.

[0098] refer to Figure 21 to Figure 24 ,in Fig. 22 for Fig. 20 The cross-section along the DD direction, Fig.24 for Fig.23 Cross-sectional view along the DD direction; in some embodiments, before forming the first word line 100 and the first bit line 110, the method further includes: forming a second insulating layer 170, the second insulating layer 170 covers the sidewalls of the first channel layer 120 arranged along the first direction X. By forming the second insulating layer 170, electrical contact between the first word line 100 and the first bit line 110 formed later can be avoided, thereby improving the reliability of the formed semiconductor structure.

[0099] In some embodiments, the method of forming the second insulating layer 170 includes: forming a second initial insulating layer 171, the second initial insulating layer 171 fills the second groove 320, and etching the second initial insulating layer 171 to expose the sidewalls of the first channel layer 120 arranged along the second direction Y. The reliability of the formed second insulating layer 170 can be improved by first forming the second initial insulating layer 171 that fills the second groove 320 and then etching.

[0100] refer to Fig.25 and Fig.26 ,in Fig.26 for Fig.25 A cross-sectional view along the DD direction; a first word line 100 and a first bit line 110 are formed.

[0101] refer to Figures 27 to 30 ,in Fig.28 for Fig. 27 The cross-section along the DD direction, Fig.30 for Fig.29 Cross-sectional view along the DD direction; in some embodiments, after forming the second transistor 230, the method may further include: forming a third insulating layer 180, the third insulating layer 180 covering the bottom surface of the first word line 100, the first bit line 110 and the first channel layer 120 arranged along the third direction Z. By forming the third insulating layer 180, different memory cells can be spaced apart when forming a plurality of memory cells.

[0102] refer to Fig.31 and Fig.32 ,in Fig.32 for Fig.31 Cross-sectional view along direction DD; in some embodiments, the second bit line 210 is also etched.

[0103] refer to Figure 1 and Figure 2 After etching the second bit line 210 , a fifth insulating layer 330 will be formed. The fifth insulating layer 330 can also support other second transistors 230 arranged along the third direction Z.

[0104] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage unit, characterized in that: include: a first word line extending along a first direction; a first bit line extending along the first direction, the first bit line and the first word line being arranged along the second direction, and the first bit line and the first word line being spaced apart; A first channel layer, wherein the first channel layer is located between the first bit line and the first word line and is electrically connected to the first bit line and the first word line respectively, and the first transistor comprises: the first word line, the first bit line and the first channel layer; a second word line extending along a third direction; a second channel layer extending along the third direction, the second channel layer being arranged opposite to the second word line, and the second channel layer controlling the conduction and disconnection of a transmission path between the first word line and the first bit line; A second bit line, the second bit line is at least located on one side of the second word line along the second direction and is electrically connected to the second channel layer, and is spaced from the first word line and the first bit line in the third direction. The second transistor includes: the second word line, the second channel layer and the second bit line.

2. The storage unit according to claim 1, characterized in that The first transistor also includes: a first metal oxide layer, the first metal oxide layer is in contact with the second channel layer and is arranged opposite to the first channel layer; the second transistor also includes: a second metal oxide layer, the second metal oxide layer is in contact with the second channel layer and the second bit line, and the second metal oxide layer is spaced apart from the first metal oxide layer.

3. The storage unit according to claim 2, characterized in that The first metal oxide layer surrounds the second channel layer. The first transistor further includes a first dielectric layer, the first dielectric layer surrounds the first metal oxide layer, and the first channel layer surrounds the first dielectric layer.

4. The storage unit according to claim 2, characterized in that The second metal oxide layer surrounds the second channel layer, and the second bit line surrounds the second metal oxide layer.

5. The storage unit according to claim 1, characterized in that The second transistor further includes: a second dielectric layer, wherein the second dielectric layer is located between the second word line and the second channel layer.

6. A semiconductor structure, characterized in that: It comprises a plurality of memory cells as claimed in any one of claims 1 to 5, wherein the plurality of memory cells are arranged at intervals along the first direction and the third direction, and the first word lines of the plurality of memory cells are located on the same side of the second word lines along the second direction.

7. The semiconductor structure according to claim 6, characterized in that: Also includes: A first conductive column is connected to the first word line, and the first word lines of a plurality of the memory cells are connected to the same first conductive column.

8. The semiconductor structure according to claim 6, characterized in that: Also includes: A second conductive column, wherein the second conductive column is contact-connected with the first bit line; A third conductive pillar, wherein the third conductive pillar is in contact with and connected to the second bit line, the second conductive pillars connected to different first bit lines are adjacent to each other along the first direction, and the third conductive pillars connected to different second bit lines are adjacent to each other along the first direction.

9. The semiconductor structure according to claim 6, characterized in that: Also includes: A second conductive column, wherein the second conductive column is contact-connected with the first bit line; A third conductive pillar is connected to the second bit line in contact with the third conductive pillar. The second conductive pillar and the third conductive pillar are arranged alternately along the first direction.

10. A method for manufacturing a storage unit, characterized in that: include: Forming a first transistor, the first transistor comprising: a first word line extending along a first direction, a first bit line extending along the first direction, the first bit line and the first word line are arranged along a second direction, and the first bit line is spaced apart from the first word line, and a first channel layer, the first channel layer is located between the first bit line and the first word line, and is in contact with and connected to the first bit line and the first word line respectively; A second transistor is formed, the second transistor comprising: a second word line extending along a third direction, a second channel layer extending along the third direction, the second channel layer being arranged opposite to the second word line, the second channel layer controlling the conduction and disconnection of a transmission path between the first word line and the first bit line, a second bit line, the second bit line being located at least on one side of the second word line along the second direction and being electrically connected to the second channel layer, and the first word line and the first bit line being spaced apart in the third direction.

11. The method for manufacturing a storage unit according to claim 10, characterized in that: The method of forming the second transistor includes: Providing a stacked structure, the stacked structure comprising a first sacrificial layer, a second sacrificial layer, a first insulating layer and a third sacrificial layer stacked in sequence; Etching the stack structure to form a first groove penetrating the stack structure; forming a second channel layer, wherein the second channel layer covers an inner wall of the first groove; forming a second word line, wherein the second word line is located in the first groove and completely fills the first groove; The third sacrificial layer is removed, and the second bit line is formed, wherein the second bit line is located on a top surface of the first insulating layer, and the second bit line is electrically connected to the second channel layer.

12. The method for manufacturing a storage unit according to claim 11, characterized in that: The method of forming the first transistor includes: removing the second sacrificial layer to form a second groove; forming the first channel layer, wherein the first channel layer is located in the second groove; The first word line and the first bit line are formed, the first word line and the first bit line are located in the second groove, the first word line and the first bit line are arranged at intervals along the second direction, and the first word line and the first bit line are both in contact with the first channel layer.

13. The method for manufacturing a storage unit according to claim 12, characterized in that: Before forming the first word line and the first bit line, the method further includes: A second insulating layer is formed, where the second insulating layer covers the sidewalls of the first channel layer arranged along the first direction.

14. The method for manufacturing a storage unit according to claim 13, characterized in that: The method of forming the second insulating layer includes: forming a second initial insulating layer, wherein the second initial insulating layer completely fills the second groove; The second initial insulating layer is etched to expose sidewalls of the first channel layer arranged along the second direction.

15. The method for manufacturing a storage unit according to claim 11, characterized in that: Before forming the first channel layer, the method further includes: etching the exposed second sacrificial layer and the third sacrificial layer along the first groove to form a third groove, wherein the third groove exposes a portion of the top surface of the first insulating layer and the first sacrificial layer; forming a first metal oxide layer, wherein the first metal oxide layer is located in the third groove between the second sacrificial layer and the second channel layer; A second metal oxide layer is formed, wherein the second metal oxide layer is located in the third groove on the top surface of the first insulating layer.

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