Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of high resistance of word line structures. The semiconductor structure comprises a substrate and a plurality of word line structures; the substrate comprises a plurality of active structures which are arranged at intervals; the plurality of word line structures are arranged in the substrate at intervals along a first direction; each word line structure extends along a second direction and is connected with a plurality of active structures arranged along the second direction; each word line structure comprises a barrier layer and a conductive layer, the barrier layer is arranged between the substrate and the conductive layer and at least covers part of the peripheral surface of the conductive layer, and the thickness of the area, opposite to the bottom surface of the conductive layer, of the barrier layer is larger than that of the area, opposite to the side surface of the conductive layer, of the barrier layer; the first direction intersects the second direction. According to the invention, the resistance of the word line structure can be reduced, and the gate-induced drain leakage current can be reduced or even avoided.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the gradual development of storage device technology, dynamic random access memory (DRAM) has been gradually applied in various electronic devices due to its higher density and faster read and write speed.

[0003] Dynamic random access memory is generally composed of multiple storage units, each of which usually includes a transistor and a capacitor. The capacitor stores data information, and the transistor controls the reading and writing of the data information in the capacitor, wherein the gate of the transistor is electrically connected to the word line structure (Word Line, referred to as WL) of the dynamic random access memory, and the voltage on the word line structure controls the opening and closing of the transistor; one of the source and drain of the transistor is electrically connected to the bit line structure (Bit Line, referred to as BL), and the other of the source and drain is electrically connected to the capacitor, and the data information is stored or output through the bit line.

[0004] However, the current word line structure cannot take into account both resistance and gate induced drain leakage (GIDL) at the same time. Summary of the invention

[0005] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are used to reduce the resistance of the word line structure and also to reduce the gate induced drain leakage current.

[0006] A first aspect of an embodiment of the present disclosure provides a semiconductor structure, comprising:

[0007] A substrate comprising a plurality of active structures arranged at intervals;

[0008] A plurality of word line structures are arranged in the substrate at intervals along a first direction; each of the word line structures extends along a second direction and connects the plurality of active structures arranged along the second direction; each of the word line structures comprises a blocking layer and a conductive layer, the blocking layer is arranged between the substrate and the conductive layer and covers at least a portion of the outer circumference of the conductive layer, wherein the thickness of the blocking layer and the bottom surface relative to the conductive layer is greater than the thickness of the blocking layer and the side surface relative to the conductive layer; the first direction intersects with the second direction.

[0009] In some embodiments, the conductive layer includes a first segment and a second segment, the second segment is disposed at an end of the first segment facing the bottom surface of the substrate, and an outer surface of the second segment is arc-shaped;

[0010] The thickness of the barrier layer is the same along the direction from the top surface of the first section to the bottom surface of the first section;

[0011] The thickness of the barrier layer gradually increases along a direction from the top surface of the second segment to the bottom surface of the second segment.

[0012] In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer;

[0013] The first barrier layer at least covers a portion of the outer circumference of the conductive layer, the second barrier layer is arranged on the first barrier layer, and the second barrier layer at least covers the outer circumference of the second segment.

[0014] In some embodiments, the thickness of the second barrier layer is 1.5 to 2 times the thickness of the first barrier layer.

[0015] In some embodiments, the active structure includes an active region, and the active region extends along a third direction; wherein the first direction, the second direction and the third direction intersect;

[0016] Each of the word line structures extends along the second direction and passes through the active region, and the bottom of the word line structure is located in the active region.

[0017] In some embodiments, the active structure includes active pillars, and a plurality of the active pillars are arranged in a multi-row and multi-column array;

[0018] Each of the word line structures extends along the second direction and wraps around at least a portion of the outer circumference of the active pillar.

[0019] In some embodiments, the top surface of the conductive layer is higher than the top surface of the barrier layer;

[0020] The semiconductor structure further includes an insulating layer, which is disposed on the word line structure, and the insulating layer, the word line structure and the substrate form an air gap.

[0021] A second aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0022] patterning a substrate to form a plurality of active structures spaced apart within the substrate;

[0023] A plurality of word line structures are formed in the substrate and are arranged at intervals along a first direction; each of the word line structures extends along a second direction and connects a plurality of the active structures, and the plurality of the active structures extend along the second direction; each of the word line structures includes a blocking layer and a conductive layer, the blocking layer is arranged between the substrate and the conductive layer, and covers at least a portion of the outer circumference of the conductive layer, wherein the thickness of the blocking layer and the bottom surface relative to the conductive layer is greater than the thickness of the blocking layer and the side surface relative to the conductive layer; the first direction intersects with the second direction.

[0024] In some embodiments, the step of forming a plurality of word line structures comprises:

[0025] forming a plurality of first trenches, wherein the plurality of first trenches are arranged at intervals along the first direction, and each of the first trenches extends along the second direction and exposes a plurality of the active structures, wherein the plurality of the active structures are arranged along the second direction;

[0026] forming a first barrier material layer, wherein the first barrier layer covers the inner wall of the first trench;

[0027] forming a second barrier layer, wherein the second barrier layer covers a portion of the first barrier material layer;

[0028] forming a conductive material layer, wherein the conductive material layer completely fills the area enclosed by the first barrier material layer and the second barrier layer;

[0029] Part of the first barrier material layer and the conductive material layer is removed, the remaining first barrier material layer constitutes a first barrier layer, the first barrier layer and the second barrier layer constitute a barrier layer; the remaining conductive material layer constitutes a conductive layer.

[0030] In some embodiments, the step of forming the second barrier layer includes:

[0031] Forming a metal layer on the bottom wall of the first trench and part of the sidewall of the first trench by a plasma deposition process, wherein the metal layer covers part of the first barrier material layer; wherein the thickness of the metal layer gradually increases in a direction from the top surface of the metal layer to the bottom surface;

[0032] The metal layer is nitrided by a rapid nitriding process to form a second barrier layer.

[0033] In some embodiments, the active structure includes an active column; the step of removing part of the first barrier material layer and the conductive material layer further includes:

[0034] Removing a portion of the conductive material layer located on the top surface of the substrate and in the first trench, and removing a portion of the first barrier material layer located in the first trench; the remaining conductive material layer constitutes an intermediate conductive material layer, and the remaining first barrier material layer constitutes a first barrier layer;

[0035] A second trench is formed in the intermediate conductive material layer, the second trench extends along a second direction, and the second trench exposes the substrate; the remaining intermediate conductive material layer constitutes a conductive layer, wherein the conductive layer surrounds at least a portion of the outer circumference of the active column.

[0036] In some embodiments, after the step of forming the plurality of first trenches in the substrate and before the step of forming the first barrier material layer, the method further includes:

[0037] A dielectric layer is formed on the inner wall of the first trench.

[0038] In the semiconductor structure and preparation method provided by the embodiments of the present disclosure, by making the thickness of the area where the blocking layer and the conductive layer are relative to each other greater than the thickness of the area where the blocking layer and the conductive layer are relative to each other on the side, the thickness of part of the blocking layer is reduced, the area of ​​the conductive layer is increased, and the resistance of the word line structure is reduced.

[0039] In addition, when voltage is applied to the word line structure, charges usually accumulate on the bottom surface of the word line structure. Therefore, by increasing the thickness of the relative area between the bottom surfaces of the blocking layer and the conductive layer, the gate induced drain leakage current of the semiconductor structure is reduced while reducing the resistance of the word line structure.

[0040] In addition to the technical problems solved by the embodiments of the present disclosure, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 Schematic diagram of the active structure and word line structure of the semiconductor structure provided in the embodiment of the present disclosure Figure 1 ;

[0043] Figure 2 Schematic diagram of the active structure and word line structure of the semiconductor structure provided in the embodiment of the present disclosure Figure 2 ;

[0044] Figure 3 Schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0045] Figure 4 Schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0046] Figure 5 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figure 6 A schematic diagram of forming a first trench in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0048] Figure 7 A schematic diagram of forming a dielectric layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0049] Figure 8 A schematic diagram of forming a first barrier material layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0050] Fig. 9 A schematic diagram of forming a metal layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0051] Fig.10 A schematic diagram of forming a second barrier layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Fig.11 A schematic diagram of forming a conductive material layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Fig.12 A schematic diagram of removing part of a conductive material layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0054] Fig.13 Schematic diagram of forming a conductive layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0055] Fig.14 Schematic diagram of forming a conductive layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 .

[0056] Reference numerals:

[0057] 100: substrate; 110: active structure; 120: shallow trench isolation structure; 130: first trench;

[0058] 200: word line structure; 211: first barrier layer; 212: second barrier layer; 213: first barrier material layer; 220: conductive layer; 221: first segment; 222: second segment; 223: conductive material layer; 224: second trench;

[0059] 300: insulation layer; 400: air gap; 500: dielectric layer. DETAILED DESCRIPTION

[0060] As described in the background technology, the semiconductor structure in the related art has a technical problem that the word line structure has a large resistance. The inventor has found that the reason for this problem is that the word line structure usually includes a barrier layer and a conductive layer arranged on the barrier layer, wherein the barrier layer is usually formed on the inner wall of the word line groove by an atomic layer deposition process, so that the barrier layer has a good step coverage, so that the thickness of the barrier layer is equal everywhere. However, the resistivity of the barrier layer is greater than the resistivity of the conductive layer, which will increase the resistance of the word line structure and reduce the performance of the semiconductor structure. In the related art, in order to reduce the resistance of the word line structure, the barrier layer is usually thinned, but excessive thinning of the barrier layer will increase the gate induced drain leakage (GIDL) of the semiconductor structure.

[0061] In response to the above technical problems, the embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, by making the thickness of the area where the blocking layer and the conductive layer are relative to each other greater than the thickness of the area where the blocking layer and the conductive layer are relative to each other on the side, thereby reducing the partial thickness of the blocking layer, increasing the area of ​​the conductive layer, and reducing the resistance of the word line structure.

[0062] In addition, when voltage is applied to the word line structure, charges usually accumulate on the bottom surface of the word line structure. Therefore, by increasing the thickness of the relative area between the bottom surfaces of the blocking layer and the conductive layer, the gate induced drain leakage current of the semiconductor structure is reduced while reducing the resistance of the word line structure.

[0063] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0064] The present embodiment does not limit the semiconductor structure. The semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto. The semiconductor structure in the present embodiment may also be other structures.

[0065] Please refer to the attached Figure 1 To Attachment Figure 4 An embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 100, wherein the substrate 100 serves as a supporting component of the semiconductor structure, and is used to support other components arranged thereon, wherein the substrate 100 is a semiconductor substrate, for example, the substrate 100 includes a silicon substrate, a germanium substrate, a silicon carbide (SiC) substrate, a silicon germanium (SiGe) substrate, or a silicon on insulator (SOI) substrate.

[0066] The substrate 100 includes a plurality of active structures 110, and the plurality of active structures 110 are arranged in the substrate 100 at intervals. The shapes of the active structures 110 can be implemented in various ways. Figure 1 The active structure 110 includes an active region. A plurality of active regions are arranged in the substrate 100 at intervals, each active region extends along the third direction, and each active region is arranged obliquely relative to the horizontal direction. That is, the third direction, the first direction, and the second direction intersect each other. The first direction is the Figure 1 The second direction is the X direction. Figure 1 The Y direction in the middle; the third direction is the Figure 1 As another example, see the attached Figure 2 The active structure 110 includes active pillars, and a plurality of active pillars are arranged in a multi-row and multi-column array in the substrate 100 . The extension direction of each active pillar is perpendicular to the substrate 100 , that is, the height direction of each active pillar is perpendicular to the substrate 100 .

[0067] The semiconductor structure also includes a plurality of word line structures 200. Figure 1 and attached Figure 2 , a plurality of word line structures 200 are arranged in the substrate 100 at intervals along the first direction, and each word line structure 200 extends along the second direction and connects a plurality of active structures 110 arranged along the second direction. In other words, each word line structure 200 connects the active structures 110 located in the same second direction. The first direction intersects the second direction.

[0068] It should be noted that the active structure 110 is used to form part of the transistor, for example, part of the active structure 110 is used to form the source region, the drain region and the channel region between the source region and the drain region of the transistor; wherein the part of the word line structure 200 opposite to the channel region of the active structure 110 forms the gate of the transistor. In this way, when a voltage is provided to each word line structure 200, the word line structure 200 can control multiple transistors arranged along the second direction to be turned on or off at the same time, which has the advantage of improving the integration of the semiconductor structure and facilitates the development of the semiconductor structure towards a small size.

[0069] When the active structure 110 includes an active area, each word line structure 200 extends along the second direction and penetrates the active area, and the bottom of the word line structure 200 is located in the active area. That is, the bottom of the part of the word line structure 200 opposite to the active area is located in the active area, so that the formed gate is a buried gate, and then the formed transistor is a buried transistor. In this way, on the one hand, the channel length can be extended, the threshold voltage of the semiconductor structure can be reduced, and the short channel effect can be reduced, thereby improving the stability of the semiconductor structure. On the other hand, compared with the planar gate structure, the gate structure can be set in the substrate 100, so that the size of the semiconductor structure can be reduced and the integration of the semiconductor structure can be improved.

[0070] When the active structure 110 includes an active column, each word line structure 200 extends along the second direction and wraps at least part of the outer peripheral surface of the active column. Wherein, along the extension direction of the active column, that is, along the direction perpendicular to the substrate 100, the active column includes a channel region and a source region and a drain region respectively located on both sides of the channel region. Each word line structure 200 extends along the second direction and wraps at least part of the outer peripheral surface of the channel region of the active column. In one example, the word line structure 200 wraps the entire outer peripheral surface of the channel region of a plurality of active columns arranged along the second direction, so that the transistor formed is a full-ring gate transistor. In another example, the word line structure 200 wraps part of the outer peripheral surface of the channel region of a plurality of active columns arranged along the second direction, so that the transistor formed is a half-ring gate transistor.

[0071] Please refer to the attached Figure 3 and attached Figure 4 Each word line structure 200 includes a barrier layer 210 and a conductive layer 220, wherein the barrier layer 210 is disposed between the substrate 100 and the conductive layer 220 and covers at least a portion of the outer peripheral surface of the conductive layer 220, wherein the thickness of the barrier layer 210 and the conductive layer 220 in the relative bottom area is greater than the thickness of the barrier layer 210 and the conductive layer 220 in the relative side area.

[0072] In this embodiment, the thickness of the blocking layer 210 is improved so that the thickness of the bottom relative area of ​​the blocking layer 210 and the conductive layer 220 is greater than the thickness of the side relative area of ​​the blocking layer 210 and the conductive layer 220, thereby reducing the partial thickness of the blocking layer 210, increasing the area of ​​the conductive layer 220, and reducing the resistance of the word line structure 200.

[0073] In addition, when voltage is applied to the word line structure 200, charges are usually accumulated on the bottom surface of the word line structure 200. Therefore, by increasing the thickness of the relative area between the bottom surfaces of the blocking layer 210 and the conductive layer 220, the gate induced drain leakage current of the semiconductor structure is reduced while reducing the resistance of the word line structure 200.

[0074] In a possible implementation, please refer to the attached Figure 3 and attached Figure 4 The conductive layer 220 includes a first section 221 and a second section 222. The second section 222 is connected to the first section 221 and is located at one end of the first section 221 facing the substrate 100. The outer surface of the second section 222 is arc-shaped. In other words, the first section 221 is disposed on the second section 222.

[0075] It should be noted that when the active structure 110 is an active region, part of the word line structure 200 is located in the active region, and part of the word line structure 200 is located in a shallow trench isolation structure of an adjacent active region. Figure 2 When the active structure 110 is an active area, the longitudinal section of the first section 221 is cylindrical, and the longitudinal section of the second section 222 is conical.

[0076] When the active structure 110 is a columnar active column, the longitudinal section of the first section 221 is a hollow ring structure, and the first section 221 surrounds at least the outer peripheral surface of the channel region of the active column. The longitudinal section of the second section 222 is a hollow ring structure and is connected to the bottom end of the first section 221.

[0077] The barrier layer 210 is disposed between the conductive layer 220 and the substrate 100 , and the barrier layer 210 covers the second segment 222 and at least a portion of the first segment 221 .

[0078] The thickness of the barrier layer 210 is the same along the direction from the top surface of the first segment 221 to the bottom surface of the first segment 221; the thickness of the barrier layer 210 gradually increases along the direction from the top surface of the second segment 222 to the bottom surface of the second segment 222, so that the thickness of the lowest end of the barrier layer 210 is the largest. In this embodiment, the thickness of the barrier layer 210 is not uniform, but changes linearly. In this way, the conductive layer 220 can be formed at the location where the reduced barrier layer 210 is located to increase the area of ​​the first segment 221 of the conductive layer 220, thereby reducing the resistance of the word line structure 200 and improving the performance of the semiconductor structure.

[0079] In addition, the thickness of the lowest end of the barrier layer 210 is the largest, which can reduce or even avoid the risk of the barrier layer 210 being broken down, thereby reducing the defect of the gate induced drain leakage current of the semiconductor structure.

[0080] In this example, the material of the barrier layer 210 includes a conductive material such as titanium nitride, which prevents the conductive material in the word line structure 200 from penetrating into the substrate 100 while also having conductivity, thereby ensuring the performance of the semiconductor device. The material of the conductive layer 220 includes metal tungsten, which has good conductivity and low resistance, thereby improving the performance of the semiconductor structure.

[0081] In a possible implementation, please continue to refer to the attached Figure 2 and attached Figure 3 , the barrier layer 210 includes a first barrier layer 211 and a second barrier layer 212; the first barrier layer 211 covers at least a portion of the outer circumference of the conductive layer 220, the second barrier layer 212 is disposed on the first barrier layer 211, and the second barrier layer 212 covers at least the outer circumference of the second segment 222. In one example, the second barrier layer 212 may only cover the outer circumference of the second segment 222. In another example, the second barrier layer 212 covers the outer circumference of the second segment 222 and covers a portion of the outer circumference of the first segment 221.

[0082] In this embodiment, by reducing the thickness of the barrier layer 210 in the region opposite to the first segment 221 of the conductive layer 220 , the area of ​​the first segment 221 can be increased to the greatest extent, thereby reducing the resistance of the word line structure 200 .

[0083] In this embodiment, the thickness of the second barrier layer 212 is greater than the thickness of the first barrier layer 211. Exemplarily, the thickness of the second barrier layer 212 is 1.5 to 2 times the thickness of the first barrier layer 211. For example, the thickness of the first barrier layer 211 is 1 nm to 2 nm, and the thickness of the second barrier layer 212 is 2 nm to 3 nm. In this way, the thickness of the lowest end of the barrier layer 210 can be maximized as much as possible, the risk of the barrier layer 210 being broken down can be reduced or even avoided, and the defect of the gate induced drain leakage current of the semiconductor structure is reduced.

[0084] In a possible embodiment, the top surface of the conductive layer 220 is higher than the top surface of the blocking layer 210; illustratively, the distance between the top surface of the conductive layer 220 and the top surface of the substrate 100 ranges from 30nm to 90nm, and the distance between the top surface of the blocking layer 210 and the top surface of the substrate 100 ranges from 30nm to 120nm.

[0085] The semiconductor structure further includes an insulating layer 300 . The insulating layer 300 is disposed on the word line structure 200 . The insulating layer 300 , the word line structure 200 and the substrate 100 form an air gap 400 .

[0086] In this embodiment, the material of the insulating layer 300 includes silicon nitride; the insulating property of the air gap 400 is higher than that of the insulating layer 300, which can prevent leakage current from forming between the word line structure 200 and the source and drain regions, thereby improving the performance of the semiconductor structure.

[0087] In addition, the air gap 400 has a low dielectric constant, which can reduce the parasitic capacitance formed by the adjacent word line structure 200 and improve the performance of the semiconductor structure.

[0088] Please refer to the attached Figure 5 , a method for preparing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:

[0089] Step S100: patterning a substrate to form a plurality of active structures spaced apart in the substrate.

[0090] When the active structure 110 is an active region, please continue to refer to the attached Figure 1 , a trench is formed in the substrate 100 through a patterning process, and an insulating material (such as silicon oxide or silicon oxynitride) is filled in the trench, so as to define a plurality of active areas independent of each other by shallow trench isolation structures 120 on the substrate 100. Exemplarily, the patterning process may be a Self-Aligned Double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process.

[0091] When the active structure 110 is an active column, a plurality of second separation grooves spaced apart along the second direction are formed in the substrate 100 through a patterning manufacturing process, each second separation groove extends along the first direction, and first separation grooves spaced apart along the first direction are formed, each first separation groove extends along the second direction; wherein the plurality of first separation grooves and the plurality of second separation grooves separate the substrate 100 into a plurality of relatively independent active columns.

[0092] It should be noted that the depths of the first separation groove and the second separation groove can be different. For example, the depth of the second separation groove is greater than the depth of the first separation groove. In this way, the bottoms of the active columns located in the same second direction are connected together, so as to facilitate the subsequent formation of bit lines in the area where the bottoms of the active columns located in the same second direction are connected together, thereby making it possible to make the voltages of the source regions or drain regions of multiple active columns formed subsequently the same, thereby ensuring the critical voltage stability of the semiconductor structure and reducing the floating body effect.

[0093] Step S200: forming a plurality of word line structures spaced apart along a first direction in a substrate; each word line structure extends along a second direction and connects a plurality of active structures, and the plurality of active structures extend along the second direction; each word line structure comprises a blocking layer and a conductive layer, the blocking layer is arranged between the substrate and the conductive layer, and covers at least a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the barrier layer and the bottom surface relative to the conductive layer is greater than the thickness of the barrier layer and the side surface relative to the conductive layer; the first direction intersects with the second direction.

[0094] For example, please refer to the attached Figure 6 , a plurality of first trenches 130 are formed, and the depth direction of the first trenches 130 is perpendicular to the substrate 100. The plurality of first trenches 130 are arranged at intervals along the first direction, and each first trench 130 extends along the second direction.

[0095] Each first trench 130 exposes a plurality of active structures 110 arranged along the second direction. It should be noted that, when the active structure 110 is an active region, the first trench 130 can be formed by a patterning process, the first trench 130 extends along the second direction, and penetrates a plurality of active regions and a shallow trench isolation structure 120 located between adjacent active regions, and the depth of the first trench 130 relative to the active region is less than the depth of the first trench 130 relative to the shallow trench isolation structure 120. When the active structure 110 is an active column, the first trench 130 can be formed in the process of forming the active column, that is, it can be understood that the first separation groove can be the first trench 130.

[0096] After the first groove 130 is formed, please refer to the attached Figure 7, a dielectric layer 500 is formed on the inner wall of the first trench 130. Exemplarily, a thermal diffusion process or an in-situ steam generation process (ISSG) can be used to form the dielectric layer 500 on the inner wall of the first trench 130. The dielectric layer 500 also extends outside the first trench 130 and covers the top surface of the substrate 100.

[0097] In this embodiment, the material of the dielectric layer 500 includes silicon oxide, but is not limited thereto.

[0098] Please refer to the attached Figure 8 , forming a first barrier material layer 213, using an atomic layer deposition process (Atomic Layer Deposition, ALD for short) or a supercritical fluid deposition process (Supercritical Fluid Deposition, SFD for short) to form the first barrier material layer 213 on the inner wall of the first trench 130. It should be noted that when there is a dielectric layer 500 on the inner wall of the first trench 130, the first barrier material layer 213 covers the dielectric layer 500. The thickness of the first barrier material layer 213 ranges from 1 nm to 2 nm.

[0099] In this embodiment, the first barrier material layer 213 is formed by an atomic layer deposition process or a supercritical fluid deposition process at a process temperature of 400°C to 700°C, so that the first barrier material layer 213 has a higher step coverage, and thus the thickness of the first barrier material layer 213 is uniform, thereby ensuring that the quality of the first barrier material layer 213 meets the requirements.

[0100] Afterwards, a second barrier layer 212 is formed, and the second barrier layer 212 covers a portion of the first barrier material layer 213; for example, please refer to the attached Fig. 9 A metal layer 214 is formed on the bottom wall of the first trench 130 and part of the sidewall of the first trench 130 by a plasma deposition process, and the metal layer 214 covers part of the first barrier material layer 213; wherein the thickness of the metal layer 214 gradually increases along the direction from the top surface of the metal layer 214 to the bottom surface. The metal layer 214 is a metal titanium layer.

[0101] In this step, the weight of the metal is relatively large, and under the influence of gravity during the deposition process, the metal will be deposited to the bottom of the first trench 130, so that the formed metal layer 214 mainly covers the bottom wall of the first trench 130, and part of the metal layer 214 is deposited on part of the side wall of the first trench 130.

[0102] Afterwards, please refer to the attached Fig.10The metal layer is nitrided by a rapid nitriding process to form a second barrier layer 212. For example, under a certain RF power and reaction temperature, a nitrogen-containing gas, such as ammonia, is passed into the reaction chamber, and the nitrogen-containing gas reacts with the metal layer 214 to form the second barrier layer 212, and the material of the second barrier layer 212 includes titanium nitride.

[0103] In this step, under the premise that the reaction temperature is 400°C to 700°C and the RF power is 300W to 1500W, nitrogen-containing gas is introduced into the reaction chamber at a gas flow rate of 500sccm to 4000sccm, so that the metal layer 214 and the nitrogen-containing gas can react quickly to quickly form the second barrier layer 212 on the first barrier material layer 213 and improve the quality of the second barrier layer 212.

[0104] When forming the second barrier layer 212 , an inert gas is passed into the reaction chamber to clean up unreacted nitrogen-containing gas or other impurity particles to improve the surface cleanliness of the second barrier layer 212 , thereby facilitating improving the bonding strength between the second barrier layer 212 and the conductive layer 220 .

[0105] Please refer to the attached Fig.11 , forming a conductive material layer 223 , the conductive material layer 223 fills the area surrounded by the first barrier material layer 213 and the second barrier layer 212 , and covers the top surface of the first barrier material layer 213 above the substrate 100 .

[0106] In this step, the reaction temperature can be controlled to ensure uniformity of the formed conductive material layer 223. For example, at a reaction temperature of 200°C to 500°C, the conductive material layer 223 is deposited into the upper region surrounded by the first barrier layer 213 and the second barrier layer 212.

[0107] In this embodiment, by preparing the barrier layer 210 in two steps, the ratio of the barrier layer to the conductive layer can be flexibly adjusted, and the gate induced drain leakage (GIDL) current can be prevented while reducing the resistance of the word line structure.

[0108] Please refer to the attached Fig.12 To Attachment Fig.14 , part of the first barrier material layer 213 and the conductive material layer 223 are removed, the remaining first barrier material layer 213 constitutes the first barrier layer 211, the first barrier layer 211 and the second barrier layer 212 constitute the barrier layer; the remaining conductive material layer 223 constitutes the conductive layer 220.

[0109] For example, please refer to the attached Fig.12The semiconductor structure is polished by a chemical mechanical polishing (CMP) process to remove the film layer on the top surface of the substrate 100 , so that the top surface of the remaining conductive material layer 223 is flush with the top surface of the substrate 100 .

[0110] Afterwards, please refer to the attached Fig.13 , by utilizing the different materials of the conductive material layer 223, the first barrier material layer 213 and the dielectric layer 500, the etching selectivity of the etching process can be reasonably adjusted, so that the etching rate of the etching process on the first barrier material layer 213 is greater than the etching rate of the etching process on the conductive material layer 223, and the conductive material layer 223 of the first preset thickness is removed, so that the remaining conductive material layer 223 constitutes the conductive layer 220, wherein the material of the conductive layer 220 is metal tungsten, and the thickness of the conductive layer 220 is 10nm to 50nm. At the same time, the first barrier material layer 213 of the second preset thickness is removed, so that the remaining first barrier material layer 213 constitutes the first barrier layer 211. The first preset thickness is less than the second preset thickness. For example, the value range of the first preset thickness is 30nm to 90nm, and the value range of the second preset thickness is 30nm to 120nm. In this way, the top surface of the conductive layer 220 can be lower than the top surface of the first barrier layer 211. It should be noted that the above forming steps are for the active structure 110 to be an active region, and the formed structure is a buried gate structure.

[0111] When the active structure 110 is an active pillar, the above process is different. Exemplarily, the conductive material layer 223 located on the top surface of the substrate 100 and a portion of the thickness located in the first trench 130 is removed, and the first barrier material layer 213 located in the first trench 130 is removed; the remaining conductive material layer 223 constitutes the intermediate conductive material layer, and the remaining first barrier material layer 213 constitutes the first barrier layer 211.

[0112] Afterwards, please refer to the attached Fig.14 , continue to remove part of the intermediate conductive material layer to form a second trench 224 in the intermediate material layer, and the second trench 224 extends along the second direction. The depth direction of the second trench 224 is parallel to the direction perpendicular to the substrate 100, and the second trench 224 exposes the substrate 100 to separate the intermediate conductive material layer, so that the remaining intermediate conductive material layer constitutes the conductive layer 220. The conductive layer 220 surrounds at least part of the outer peripheral surface of the active pillar to form a full surround gate structure, or a semi-surround gate structure.

[0113] Please continue to refer to 3 and Attachment Figure 4, an insulating layer 300 may be formed on the word line structure 200 by a deposition process, and the insulating layer 300 is used to realize the insulation setting between adjacent word line structures 200, and the top surface of the insulating layer 300 is flush with the top surface of the substrate 100. The deposition process includes any one of chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), physical vapor deposition (Physical Vapor Deposition, referred to as PVD) or atomic layer deposition (Atomic Layer Deposition, referred to as ALD).

[0114] The insulating layer 300, the word line structure 200 and the substrate 100 form an air gap 400. In this embodiment, the material of the insulating layer 300 includes silicon nitride; the insulating property of the air gap 400 is higher than that of the insulating layer 300, which can prevent leakage current from forming between the word line structure 200 and the source and drain regions, thereby improving the performance of the semiconductor structure.

[0115] In addition, the air gap 400 can reduce the parasitic capacitance between adjacent word line structures 200 , thereby improving the performance of the semiconductor structure.

[0116] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0117] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0118] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a plurality of active structures spaced apart from each other; A plurality of word line structures, wherein the plurality of word line structures are spaced apart and arranged in the substrate along a first direction; Each of the word line structures extends along the second direction and connects a plurality of the active structures arranged along the second direction; each of the word line structures includes a blocking layer and a conductive layer, the blocking layer is arranged between the substrate and the conductive layer, and covers at least a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the blocking layer and the bottom surface relative to the conductive layer is greater than the thickness of the blocking layer and the side surface relative to the conductive layer; the first direction intersects with the second direction.

2. The semiconductor structure according to claim 1, wherein: The conductive layer includes a first section and a second section, the second section is arranged at one end of the first section facing the bottom surface of the substrate, and the outer surface of the second section is arc-shaped; The barrier layer has the same thickness along a direction from the top surface of the first segment to the bottom surface of the first segment; The thickness of the barrier layer gradually increases along a direction from the top surface of the second segment to the bottom surface of the second segment.

3. The semiconductor structure according to claim 2, wherein: The barrier layer includes a first barrier layer and a second barrier layer; The first barrier layer covers at least a portion of the outer circumference of the conductive layer. The second barrier layer is provided on the first barrier layer, and the second barrier layer covers at least the outer circumference of the second segment.

4. The semiconductor structure according to claim 3, wherein: The thickness of the second barrier layer is 1.5 to 2 times the thickness of the first barrier layer.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The active structure includes an active area, and the active area extends along a third direction; wherein the first direction, the second direction and the third direction intersect; Each of the word line structures extends along the second direction and passes through the active area, and the bottom of the word line structure is located in the active area.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The active structure includes active pillars, and a plurality of the active pillars are arranged in a multi-row and multi-column array; Each of the word line structures extends along the second direction and wraps at least a portion of the outer circumference of the active pillar.

7. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The top surface of the conductive layer is higher than the top surface of the barrier layer; The semiconductor structure further includes an insulating layer, which is disposed on the word line structure. The insulating layer, the word line structure and the substrate form an air gap.

8. A method for preparing a semiconductor structure, characterized in that: The steps include: patterning a substrate to form a plurality of spaced-apart active structures within the substrate; A plurality of word line structures are formed in the substrate and are spaced apart along a first direction; each of the word line structures extends along a second direction and connects a plurality of the active structures, and the plurality of the active structures extend along the second direction; each of the word line structures includes a blocking layer and a conductive layer, the blocking layer is arranged between the substrate and the conductive layer, and covers at least a portion of the outer peripheral surface of the conductive layer, wherein the thickness of the blocking layer in the area relative to the bottom surface of the conductive layer is greater than the thickness of the blocking layer in the area relative to the side surface of the conductive layer; the first direction intersects with the second direction.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The steps of forming a plurality of word line structures include: forming a plurality of first trenches, wherein the plurality of first trenches are spaced apart along the first direction, and each of the first trenches extends along the second direction and exposes a plurality of the active structures, wherein the plurality of active structures are arranged along the second direction; forming a first barrier material layer, wherein the first barrier layer covers an inner wall of the first trench; forming a second barrier layer, wherein the second barrier layer covers a portion of the first barrier material layer; forming a conductive material layer, wherein the conductive material layer completely fills the area enclosed by the first barrier material layer and the second barrier layer; Part of the first barrier material layer and the conductive material layer is removed, and the remaining first barrier material layer constitutes a first barrier layer, and the first barrier layer and the second barrier layer constitute a barrier layer; the remaining conductive material layer constitutes a conductive layer.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The step of forming the second barrier layer comprises: forming a metal layer on a bottom wall of the first trench and a portion of the sidewalls of the first trench using a plasma deposition process, wherein the metal layer covers a portion of the first barrier material layer; wherein the thickness of the metal layer gradually increases from the top surface of the metal layer to the bottom surface; The metal layer is nitrided by a rapid nitriding process to form a second barrier layer.

11. The method for preparing a semiconductor structure according to claim 10, wherein: The active structure includes an active column; the step of removing part of the first barrier material layer and the conductive material layer further includes: removing a portion of the conductive material layer located on the top surface of the substrate and within the first trench, and removing a portion of the first barrier material layer located within the first trench; The remaining conductive material layer constitutes an intermediate conductive material layer, and the remaining first barrier material layer constitutes a first barrier layer; A second trench is formed in the intermediate conductive material layer, the second trench extending along a second direction and exposing the substrate; the remaining intermediate conductive material layer constitutes a conductive layer, wherein the conductive layer surrounds at least a portion of the outer periphery of the active pillar.

12. The method for preparing a semiconductor structure according to any one of claims 9 to 11, characterized in that: After the step of forming a plurality of first trenches in the substrate and before the step of forming the first barrier material layer, the method further includes: A dielectric layer is formed on the inner wall of the first trench.

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