Semiconductor structure, preparation method thereof and storage system

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and a storage system, relates to the technical field of semiconductor chips, and aims to solve the problems of complex preparation process and high process difficulty of a semiconductor structure in the prior art. The preparation method of the semiconductor structure comprises the following steps: forming a plurality of first grooves in a first surface of a substrate, wherein the first grooves extend along a first direction; forming a plurality of gate structures in the plurality of first grooves; a plurality of second grooves are formed in the first surface of the base material, each second groove is located between every two adjacent first grooves, and the second grooves extend in the first direction; and forming a plurality of isolation structures in the plurality of second grooves. The semiconductor structure is applied to a storage system so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, and a storage system. Background Art

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the memory density for planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral circuits for facilitating operation of the memory array. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a storage system, aiming to solve the problems of complex and difficult manufacturing processes of semiconductor structures in related technologies.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a method for preparing a semiconductor structure is provided, comprising: forming a plurality of first grooves on a first surface of a substrate, the first grooves extending along a first direction; forming a plurality of gate structures in the plurality of first grooves; forming a plurality of second grooves on the first surface of the substrate, each second groove being located between two adjacent first grooves, the second grooves extending along the first direction; and forming a plurality of isolation structures in the plurality of second grooves.

[0007] The method for preparing a semiconductor structure provided by the present disclosure can improve the problem that the semiconductor structure is prone to bending by filling the first groove with an insulating material before forming the second groove. Since the second groove is formed and an isolation structure is formed in the second groove, a larger number of semiconductor pillars can be formed, thereby improving the transistor density in the semiconductor structure. Furthermore, since the semiconductor structure can be a memory or a part of a memory, it is also beneficial to improve the storage density of the memory. In addition, in some embodiments, the second groove is formed by self-alignment, so the preparation method also improves the process window, increases the overlay margin, and reduces the process difficulty and cost.

[0008] In some embodiments, before the step of forming a plurality of first grooves on the first surface of the substrate, the step also includes: setting a mask layer on the first surface of the substrate, the mask layer including a plurality of openings; the step of forming a plurality of first grooves on the first surface of the substrate includes: etching the substrate using the plurality of openings of the mask layer to form a plurality of first grooves.

[0009] In some embodiments, after the step of forming multiple gate structures in the multiple first grooves and before the step of forming multiple second grooves on the first surface of the substrate, the method further includes: forming multiple insulating filling structures, one of the insulating filling structures is located in a connected first groove and an opening; the portion of the insulating filling structure located in the opening is defined as a first portion; at least a first sublayer located between two adjacent insulating filling structures is removed, the first sublayer being at least a portion of the film layer of the mask layer; forming an isolation layer, the isolation layer covering the multiple insulating filling structures and the first surface; using a first etching process to etch the semiconductor structure along a target direction to form multiple blocking portions and multiple third grooves; wherein the target direction is from the substrate toward the isolation layer side to the substrate away from the isolation layer side; the blocking portion includes at least a portion of the first portion and the isolation layer around the first portion that is not etched by the first etching process; the third groove is located between two adjacent blocking portions, and the third groove exposes the first surface; the step of forming multiple second grooves on the first surface of the substrate is: using a second etching process to etch the substrate along the target direction using the multiple third grooves to form multiple second grooves.

[0010] In some embodiments, the first etching process and the second etching process both include dry etching processes.

[0011] In some embodiments, the step of forming the isolation layer includes: forming a first dielectric layer and a second dielectric layer in sequence; the material of the first dielectric layer is different from the material of the second dielectric layer.

[0012] In some embodiments, a material of the first dielectric layer includes silicon nitride, and a material of the second dielectric layer includes oxide.

[0013] In some embodiments, providing a mask layer on the first surface of the substrate includes: forming the first sub-layer on the first surface of the substrate; the material of the first sub-layer includes silicon nitride or oxide.

[0014] In some embodiments, the providing of a mask layer on the first surface of the substrate includes: a second sublayer and the first sublayer are sequentially formed on the first surface of the substrate; the first sublayer and the second sublayer are made of different materials.

[0015] In some embodiments, the material of the first sub-layer includes silicon nitride, and the material of the second sub-layer includes oxide.

[0016] In some embodiments, the mask layer is set on the first surface of the substrate further includes: forming a third sublayer and a fourth sublayer in sequence on the first sublayer, the first sublayer and the fourth sublayer are made of the same material, and the first sublayer and the third sublayer are made of different materials; the third sublayer serves as a stop layer when removing the fourth sublayer.

[0017] In some embodiments, the material of the third sub-layer includes polysilicon or titanium nitride, and the material of the fourth sub-layer includes silicon nitride.

[0018] In some embodiments, the mask layer is set on the first surface of the substrate further includes: forming a fifth sublayer and a sixth sublayer in sequence on the second sublayer, the fifth sublayer and the sixth sublayer are located between the second sublayer and the first sublayer; the second sublayer and the sixth sublayer are made of the same material, and the second sublayer and the fifth sublayer are made of different materials; the fifth sublayer serves as a stop layer when removing the sixth sublayer.

[0019] In some embodiments, the material of the fifth sub-layer includes silicon nitride, and the material of the sixth sub-layer includes oxide.

[0020] In some embodiments, after the step of forming a plurality of first grooves on the first surface of the substrate and before forming a plurality of gate structures in the plurality of first grooves, it also includes: forming a first insulating layer on the inner wall of the first groove, enclosing a first sub-groove in the first insulating layer; forming a stop block at the bottom of the first sub-groove to obtain a second sub-groove; forming a plurality of gate structures in the plurality of first grooves, including: forming a gate layer on the side wall of the second sub-groove, leaving a distance between the gate layer and the first surface.

[0021] In some embodiments, forming a plurality of gate structures in the plurality of first grooves further includes: oxidizing the sidewalls of the second sub-grooves to form a gate insulating layer.

[0022] In some embodiments, multiple isolation structures are formed in the multiple second grooves, including: forming a second insulating layer on the inner wall of the second groove, and the second insulating layer encloses a receiving groove; forming an isolation column in the receiving groove; and filling the receiving groove with insulating material to cover the isolation column.

[0023] In some embodiments, forming a plurality of isolation structures in the plurality of second grooves includes: filling the second grooves with an insulating material to form the isolation structures including air gaps.

[0024] On the other hand, a semiconductor structure is provided, comprising: a plurality of gate filling structures, a plurality of isolation structures and a plurality of semiconductor pillars. The plurality of gate filling structures extend along a first direction. Each isolation structure is located between two adjacent gate filling structures, the isolation structure extends along the first direction, and the arrangement direction of the isolation structure and the gate filling structure is a second direction. Each semiconductor pillar is located between the isolation structure and the gate filling structure, the semiconductor pillar extends along a third direction, the third direction intersects with a first reference plane, and the first direction and the second direction are located on the first reference plane; wherein the length of the isolation structure along the first direction is less than the length of the gate filling structure along the first direction.

[0025] In this embodiment, a plurality of semiconductor pillars may be provided between the isolation structure and the gate filling structures on both sides thereof, thereby forming a plurality of vertical transistors, which is beneficial to improving the storage density of the semiconductor structure. In addition, the length of the isolation structure along the first direction is less than the length of the gate filling structure along the first direction, which makes the length of the isolation structure shorter, for example, the isolation structure may not extend to the edge area (such as the non-effective storage area), which is beneficial to reducing the cost when manufacturing the semiconductor structure.

[0026] In some embodiments, the first direction and the third direction are located on a second reference plane; the orthographic projection of the isolation structure on the second reference plane is a first orthographic projection, and the orthographic projection of the gate filling structure on the second reference plane is a second orthographic projection; along the first direction, two ends of the first orthographic projection are located between two ends of the second orthographic projection.

[0027] In some embodiments, the semiconductor structure has a core region and an edge region; the gate filling structure is located in the core region and the edge region; and the isolation structure is located in the core region.

[0028] In some embodiments, along the second direction, the distances between the isolation structure and two adjacent gate filling structures are equal.

[0029] In some embodiments, along the second direction, a distance difference between two adjacent gate filling structures of the isolation structure is less than or equal to 10 nm.

[0030] In some embodiments, the gate filling structure includes: a stop structure and a gate structure stacked along the third direction, the stop structure includes a stop block and a first insulating layer, the first insulating layer is located between the stop block and the semiconductor column, the gate structure includes a gate layer and a gate insulating layer, the gate insulating layer is located between the gate layer and the semiconductor column; along the second direction, the distance between the isolation structure and the gate insulating layer in two adjacent gate filling structures is equal.

[0031] In some embodiments, the semiconductor column includes a channel portion, a first pole and a second pole; along the third direction, the channel portion is located between the first pole and the second pole; along the second direction, the channel portion overlaps with the gate layer; and a storage unit is electrically connected to the first pole.

[0032] On the other hand, a storage system is provided, comprising: a semiconductor structure prepared by the preparation method as described in any one of the above embodiments, or a semiconductor structure as described in any one of the above embodiments; and a controller coupled to the semiconductor structure.

[0033] It can be understood that the beneficial effects that can be achieved by the storage system provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure and the preparation method thereof mentioned above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0035] Figure 1 A structural block diagram of an electronic device provided for some embodiments of the present disclosure;

[0036] Figure 2 is a structural block diagram of a memory in some embodiments of the present disclosure;

[0037] Figure 3 is a structural diagram of a memory unit in some embodiments of the present disclosure;

[0038] Figure 4A A flow chart of a method for preparing a semiconductor structure provided for some embodiments of the present disclosure;

[0039] Figure 4BA flow chart of another method for preparing a semiconductor structure provided for some embodiments of the present disclosure;

[0040] Figure 4C A flow chart of another method for preparing a semiconductor structure provided for some embodiments of the present disclosure;

[0041] Figure 4D A flow chart of another method for preparing a semiconductor structure provided for some embodiments of the present disclosure;

[0042] Figure 5A to Figure 5K Structural diagrams corresponding to some steps in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0043] Figure 6A to Figure 6C Structural diagrams corresponding to some steps in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0044] FIG. 7A to FIG. 7D Structural diagrams corresponding to some steps in the method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0045] Figure 8 To disclose a top view of a semiconductor structure in some embodiments;

[0046] Fig. 9 To disclose projection views of isolation structures and gate filling structures in some embodiments;

[0047] Fig.10 A structural diagram of a memory in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0049] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0053] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0059] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0060] Figure 1 The electronic device 9000 is a block diagram of a structure of an electronic device 9000 provided in some embodiments of the present disclosure. The electronic device 9000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown, the electronic device 9000 may include a storage system 910 and a host 920, and the storage system 910 may have one or more memories 911 and a controller 912. The host 920 may be a processor of the electronic device 9000, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 920 may be configured to send data to the memory 911 or receive data from the memory 911.

[0061] The controller 912 is coupled to the memory 911 and the host 920, and is configured to control the memory 911. The number of memories 911 may be one or more. Figure 1 911 as an example. The controller 912 can manage the data stored in each memory 911 and communicate with the host 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write and refresh operations. The controller 912 can also be configured to manage various functions about the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity that the computer system can use, the number of memory banks, memory type and speed, memory granule data depth and data width, and other important parameters. Any other suitable function can also be performed by the controller 912. The controller 912 can communicate with an external device (e.g., the host 920) according to a specific communication protocol. For example, the controller 912 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-E protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0062] Figure 2FIG. 1 is a structural block diagram of a memory in some embodiments of the present disclosure. Figure 2 As shown, the memory 911 includes a memory cell array and a peripheral circuit for controlling the memory cell array, and the peripheral circuit (also referred to as a control and sensing circuit) may include any suitable digital, analog and / or mixed signal circuit for facilitating the operation of the memory cell array. For example, the peripheral circuit may include a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the above functional circuit (e.g., a subcircuit), or one or more of any active or passive components of the circuit (e.g., a transistor, a diode, a resistor or a capacitor). Exemplarily, the peripheral circuit may use complementary metal-oxide-semiconductor (CMOS) technology, for example, it may be implemented using a logic process (e.g., a technology node of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0063] The memory cell array and the peripheral circuit can be arranged side by side in the same plane, for example, on the same wafer, that is, the memory cell array and the peripheral circuit can be located in the same semiconductor structure. The memory cell array and the peripheral circuit can also be formed on different wafers and bonded together in a face-to-face manner. Figure 2 As shown, when the memory cell array and the peripheral circuit are formed on different wafers and bonded together in a face-to-face manner, the memory 911 may include a first semiconductor structure 901 and a second semiconductor structure 902, and between the first semiconductor structure 901 and the second semiconductor structure 902 (in the vertical direction, for example, Figure 2The first semiconductor structure 901 may include a memory cell array, and the second semiconductor structure 902 may include a peripheral circuit. A large number of interconnections (e.g., bonding contacts) are formed through the bonding interface 903, and a direct short-distance (e.g., micrometer-level) electrical connection can be made between the first semiconductor structure 901 and the second semiconductor structure 902, rather than a long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on a circuit board (e.g., a printed circuit board (PCB)), thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transmission between the memory cell array in the first semiconductor structure 901 and the peripheral circuit in the second semiconductor structure 902 can be performed through the interconnections (e.g., bonding contacts) through the bonding interface 903. By vertically integrating the first semiconductor structure 901 and the second semiconductor structure 902, the chip size can be reduced, and the storage density of the memory 911 can be increased.

[0064] The memory cell array may be an array of memory cells using vertical transistors as switches and selection devices. In some embodiments, the memory cell array may be a DRAM cell array. For ease of description, a DRAM cell array may be used as an example for describing a memory cell array in the present disclosure. However, it should be understood that the memory cell array is not limited to a DRAM cell array, and may include, for example, any other suitable type of memory cell array that may use vertical transistors as switches and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, and the like.

[0065] When the memory cell array is a DRAM cell array, the memory cells therein are DRAM cells, which include a capacitor for storing data bits as positive or negative charges and one or more transistors (also called pass transistors) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and a capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by a peripheral circuit to maintain data.

[0066] Figure 3 FIG. 1 is a structural diagram of a memory unit in some embodiments of the present disclosure. Figure 3As shown, the memory cell 80 includes a vertical transistor 810 and a memory cell 820 coupled to the vertical transistor 810. The vertical transistor 810 includes a semiconductor column 801, a gate insulating layer 802, and a gate layer 803. The two ends of the semiconductor column 801 along the Y direction are a source and a drain, respectively, and one of the source and the drain is coupled to the memory cell 820. In some embodiments, the memory cell 80 is a DRAM cell, and the memory cell 820 is a capacitor for storing charge as binary information stored by the corresponding DRAM cell. In some embodiments, the memory cell 80 is a PCM cell, and the memory cell 820 is a PCM element (for example, including a chalcogenide alloy) for storing binary information of the corresponding PCM cell based on different resistivities of the PCM element in the amorphous phase and the crystalline phase. In some embodiments, the memory cell 80 is a FRAM cell array, and the memory cell 820 is a ferroelectric capacitor for storing binary information of the corresponding FRAM cell based on switching between two polarization states of the ferroelectric material under an external electric field.

[0067] The memory cells 80 may be arranged in a two-dimensional (2D) array having rows and columns. The memory 911 may include word lines coupling the peripheral circuit with the memory cell array for controlling the switching of the vertical transistors 810 in the memory cells 80 located in the rows, and bit lines coupling the peripheral circuit with the memory cell array for sending data to the memory cells 80 located in the columns and / or receiving data from the memory cells 80 located in the columns. That is, each word line may be coupled to the memory cells 80 of the corresponding rows, and each bit line may be coupled to the memory cells 80 of the corresponding columns.

[0068] Some embodiments of the present disclosure provide a semiconductor structure 100 and a method for manufacturing the same. The semiconductor structure 100 may be the aforementioned memory 911, or may be a portion of the aforementioned memory 911 (e.g., the first semiconductor structure 901). When the semiconductor structure 100 is applied to a storage system 910, the semiconductor structure 100 may be coupled to a controller 912.

[0069] Figure 4A A flowchart of a method for preparing a semiconductor structure 100 provided in some embodiments of the present disclosure is provided. Figure 4B A flowchart of another method for preparing a semiconductor structure 100 provided in some embodiments of the present disclosure is provided. Figure 4C A flowchart of another method for preparing a semiconductor structure 100 provided in some embodiments of the present disclosure is provided. Figure 4D A flowchart of another method for preparing a semiconductor structure 100 provided in some embodiments of the present disclosure is provided. Figure 5A to Figure 5K Structural diagrams corresponding to some steps in the method for preparing the semiconductor structure 100 provided in some embodiments of the present disclosure.

[0070] See also Figure 4A , the preparation method of the semiconductor structure 100 includes S1 to S4.

[0071] S1. Form a plurality of first grooves on a first surface of a substrate, wherein the first grooves extend along a first direction.

[0072] In this step, refer to Figure 5A , the substrate 10 includes a plurality of parallel semiconductor walls 102 extending in the X direction, and adjacent semiconductor walls 102 are separated by trench isolation walls 104. In some embodiments, for example, a photolithography process may be performed to pattern the silicon substrate 101 using an etching mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) may be performed to etch trenches 103 in the silicon substrate 101. Thus, semiconductor walls 102 extending vertically in the silicon substrate 101 may be formed. The bottom of the semiconductor wall 102 may be below the top surface of the silicon substrate 101. Since the semiconductor wall 102 is formed by etching the silicon substrate 101, the semiconductor wall 102 may have the same material as the silicon substrate 101, such as single crystal silicon.

[0073] Trench isolation walls 104 are formed in the trenches 103. In some embodiments, a dielectric (e.g., silicon oxide) is deposited using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to completely fill the trenches 103. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric deposited beyond the top surface of the silicon substrate 101. As a result, the parallel semiconductor walls 102 may be separated by the trench isolation walls 104.

[0074] Further, see Figure 5B A plurality of first grooves 110 are formed on the first surface a1 of the substrate 10 (eg, the top surface of the silicon substrate 101), and the first grooves 110 extend along a first direction. The first direction may be parallel to the Z direction. Figure 5A and Figure 5B It can be seen from the reference coordinate system XYZ that the first groove 110 alternately passes through the semiconductor wall 102 and the trench isolation wall 104 along the Z direction, and Figure 5B The interception position of the semiconductor wall 102 is just located, that is, the trench isolation wall 104 is blocked by the semiconductor wall 102 and is not shown in FIG. Figure 5B In addition, the first groove 110 also separates the semiconductor wall 102 into a plurality of semiconductor bodies 1021. Here, the semiconductor body may include Figure 3The semiconductor pillar 801 of the vertical transistor 810 shown, for example, in some examples, one semiconductor body 1021 is one semiconductor pillar 801; in other examples, one semiconductor body 1021 can be separated into two semiconductor pillars 801 along the X direction. The specific separation process will be described below.

[0075] In some embodiments, before the above step S1, S00 may also be included.

[0076] See also Figure 4B , S00, setting a mask layer on the first surface of the substrate, the mask layer including a plurality of openings.

[0077] In this step, refer to Figure 5B , a mask layer 20 is disposed on the first surface a1 of the substrate 10, and the mask layer 20 includes a plurality of openings. Figure 4B The subsequent step S1 may include: S001 , etching the substrate 10 using the multiple openings of the mask layer 20 to form a plurality of first grooves 110 .

[0078] S2. Forming a plurality of gate structures in the plurality of first grooves.

[0079] In this step, refer to Figure 5E , a gate structure 120 may be formed in the first groove 110, and the gate structure 120 may be a vertical structure extending along the Y direction (e.g., parallel to the sidewall of the first groove 110), and the gate structure 120 may also extend along the Z direction so that the channel portions of the plurality of semiconductor bodies 1021 arranged at intervals in the Z direction overlap in the X direction. The gate structure 120 includes a gate insulating layer 121 (e.g., including one or more Figure 3 The gate insulating layer 802 in the embodiment of the present invention) and the gate layer 122 (for example, including one or more Figure 3 The gate layer 803 in the semiconductor body 1021 is provided, and the gate insulating layer 121 is located between the semiconductor body 1021 and the gate layer 122. Exemplarily, the gate layer 122 may include a stacked first conductive layer 1221 and a second conductive layer 1222, and the first conductive layer 1221 is closer to the gate insulating layer 121 than the second conductive layer 1222. In some examples, the first conductive layer 1221 may be titanium nitride, and the second conductive layer 1222 may be a tungsten layer.

[0080] In some embodiments, see Figure 4C , between the above steps S1 and S2, it also includes S01 and S02.

[0081] S01. Form a first insulating layer on an inner wall of a first groove, wherein a first sub-groove is formed in the first insulating layer.

[0082] In this step, refer to Figure 5C, a first insulating layer 131 is formed on the inner wall of the first groove 110, and a first sub-groove 1101 is formed in the first insulating layer 131. The first insulating layer 131 can be formed by depositing oxide through a thin film deposition process (including but not limited to CVD, PVD or ALD, etc.). Here, it can be understood that in the embodiment in which the mask layer 20 is provided in front, the first insulating layer 131 can also cover the mask layer 20 at the same time.

[0083] S02. Form a stop block at the bottom of the first sub-groove to obtain a second sub-groove.

[0084] In this step, continue to refer to Figure 5C , a stop block 132 can be formed at the bottom of the first sub-recess 1101 to obtain a second sub-recess 1102. Wherein, a dielectric (e.g., silicon nitride, silicon oxide) can be deposited by using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to fill the bottom of the first sub-recess 1101. Exemplarily, the stop block 132 may include a stop portion 1322 and a barrier layer 1321, and the barrier layer 1321 is located between the stop portion 1322 and the first insulating layer 131. Wherein, the material of the barrier layer 1321 may be silicon nitride, and the material of the stop portion 1322 may be an oxide, such as silicon oxide. When forming the stop block 132, for example, a layer of silicon nitride material can be formed first, and then filled with silicon oxide material, and finally, part of the silicon nitride material and silicon oxide material are etched away to obtain the stop block 132.

[0085] In some embodiments, see Figure 4C , between the above steps S1 and S2, S03 is also included.

[0086] S03, performing oxidation treatment on the sidewall of the second sub-recess to form a gate insulating layer.

[0087] In this step, refer to Figure 5D After the sidewall of the second sub-recess 1102 is oxidized, the gate insulating layer 121 can be formed. It can be seen that the thickness of the gate insulating layer 121 is greater than that of the first insulating layer 131, so that the gate layer 122 can be better separated from the semiconductor body 1021.

[0088] S3, forming a plurality of second grooves on the first surface of the substrate, each second groove being located between two adjacent first grooves, and the second grooves extending along a first direction, wherein the first direction may be parallel to the Z direction.

[0089] In this step, refer to Fig.5IA plurality of second grooves 160 may be further formed on the first surface a1 of the substrate 10 . The second grooves 160 may divide a semiconductor body 1021 into two semiconductor pillars 801 opposite to each other along the X direction. Such a configuration is beneficial to improving the transistor configuration density, and further beneficial to improving the storage density of the semiconductor structure 100 .

[0090] S4. Forming a plurality of isolation structures in the plurality of second grooves.

[0091] In this step, refer to Figure 5J and Figure 5K As shown, an isolation structure 16 may be formed in the second groove 160, so that the two semiconductor pillars 801 may be well separated. Figure 5J As shown, a second insulating layer 161 may be formed on the inner wall of the second groove 160, and a receiving groove is formed in the second insulating layer 161; an isolation column 162 is formed in the receiving groove; and an insulating material 163 is filled in the receiving groove to cover the isolation column 162. The isolation column 162 may be made of metal, such as W, Co, Cu, Al, etc., or the isolation column 162 may be made of TiN, TaN, etc. With such a configuration, the isolation structure 16 may have a better supporting effect. In other embodiments, such as Figure 5K As shown, an insulating material 164 is filled in the second groove 160 to form an isolation structure 16 including an air gap 165. The air in the air gap 165 has a relatively large dielectric constant (for example, about 4 times the dielectric constant of silicon oxide), which can improve the insulation effect between the two semiconductor pillars 801.

[0092] In summary, some embodiments of the present disclosure provide a method for preparing a semiconductor structure 100. Since a second groove 160 is formed and an isolation structure 16 is formed in the second groove 160, a larger number of semiconductor pillars 801 can be formed, thereby improving the transistor density in the semiconductor structure 100. Furthermore, since the semiconductor structure 100 is a memory or a part of a memory, it is also beneficial to improve the storage density of the memory.

[0093] It is worth pointing out that in some implementations, when forming the first groove 110 and the second groove 160, a lithography-etching-lithography-etching (Litho etch Litho etch, LELE) method can be adopted, that is, a layer of lithography patterns is split onto two or more masks to achieve image density superposition. However, when the LELE process is adopted to split the lithography patterns of the first groove 110 and the second groove 160 onto different masks, the overlay (OVL) accuracy in multiple lithography processes is not easy to control. For example, it will cause the thickness of the semiconductor pillars 801 on both sides of the second groove 160 along the X direction to be quite different, so there are problems of high process difficulty and high cost. In other implementations, when forming the first groove 110 and the second groove 160, a self-aligned double patterning (SADP) method can also be used, that is, an axis pattern is formed by a single photolithography and etching process, and then a sidewall pattern is formed on the sidewall by atomic layer deposition and etching process, and the axis pattern (i.e., sacrificial layer) is removed to form a sidewall hard mask pattern. However, when forming the first groove 110 and the second groove 160, there are also problems of high cost and high process difficulty. Moreover, the above two implementations are to form the first groove 110 and the second groove 160 at the same time, and the problem of the semiconductor structure 100 being easy to bend is also easy to occur. However, in the above embodiments of the present disclosure, the first groove 110 can be formed first, the gate structure 120 can be formed in the first groove 110, and then the second groove 160 can be formed, and the isolation structure 16 can be formed in the second groove 160. In this way, the first groove 110 and the second groove 160 are formed twice, which can reduce the process difficulty and cost on the one hand, and make the semiconductor structure 100 not easy to bend on the other hand.

[0094] Next, the preparation method of the semiconductor structure 100 provided by some embodiments of the present disclosure is further introduced, which is used to improve the process window and increase the overlay margin. For example, the problem of large overlay (OVL) deviation caused by the above-mentioned LELE method is improved. At the same time, it is also beneficial to reduce the process difficulty and cost, and make the semiconductor structure 100 less likely to bend.

[0095] In some embodiments, Figure 4D As shown, after step S2 and before step S3 of the preparation method, the method further includes steps S04 to S07.

[0096] S04. Form a plurality of insulating filling structures, wherein one insulating filling structure is located in a first groove and an opening that are connected to each other; a portion of the insulating filling structure located in the opening is defined as a first portion.

[0097] In this step, refer to Figure 5E , and combined with Figure 5B As shown, the insulating filling structure 140 can fill the first groove 110 and the opening of the mask layer 20. At this time, the insulating filling structure 140 can be divided into a first part 141 and a second part 142, the first part 141 is located in the opening of the mask layer 20, and the second part 142 is located in the first groove 110. In some examples, the material of the insulating filling structure 140 may include an insulating material, for example, a carbon-containing organic matter. Here, by filling the first groove 110 with an insulating material before forming the second groove, the problem that the semiconductor structure 100 is prone to bending can be improved.

[0098] Continue reading Figure 5E , an insulating material may be deposited to form an insulating filling structure 140, and the insulating material may also cover Figure 5D The first insulating layer 131 located above the mask layer 20 is then removed from the first insulating layer 131 located above the mask layer 20 and the insulating material used to form the insulating filling structure 140 to form a Figure 5E The structure shown.

[0099] In other examples, after depositing the insulating material, at least part of the insulating material in the opening of the mask layer 20 may be removed, for example, removed along the -Y direction to be flush with the first surface a1 of the substrate 10, or removed to any height position above the first surface a1 (above in the figure, i.e., in the Y direction), and then filled with other materials (which may be other insulating materials or metal materials, and in some examples, materials with a harder hardness than the original insulating material may be selected), and ground until the first sublayer 201 is exposed. For example, in Figure 5E On the basis of the structure shown, the first portion 141 of the insulating filling structure 140 can be replaced with other materials, and a portion (one tenth, one fifth, or one half, etc.) of the first portion 141 of the insulating filling structure 140 along the -Y direction can also be replaced with other materials. In some examples, the hardness of the first portion 141 of the insulating filling structure 140 is greater than the hardness of the second portion 142 of the insulating filling structure 140. In some examples, the first portion 141 of the insulating filling structure 140 can be a metal material.

[0100] S05. At least remove a first sublayer located between two adjacent insulating filling structures, where the first sublayer is at least a portion of a film layer of the mask layer.

[0101] In this step, refer to Fig. 5F , part of the first sub-layer 201 can be removed, and the first sub-layer 201 is at least a part of the film layer of the mask layer 20. Fig. 5FIn the example, the mask layer 20 also includes the second sub-layer 202. It can be understood that in this embodiment, the second sub-layer 202 may not be present, and the second sub-layer 202 is not introduced here. Here, the material of the first sub-layer 201 may be silicon nitride or oxide (such as silicon oxide). Fig. 5F In the example, the material of the first sub-layer 201 is different from the material of the first insulating layer. For example, the material of the first sub-layer 201 may be silicon nitride, and the material of the first insulating layer 131 may be oxide. In this way, when the first sub-layer 201 is removed, the first insulating layer 131 may be retained on the side of the first portion 141 of the insulating filling structure 140.

[0102] S06, forming an isolation layer, wherein the isolation layer covers the plurality of insulating filling structures and the first surface;

[0103] In this step, refer to Figure 5G , the isolation layer 180 may cover the plurality of insulating filling structures 140 and the first surface a1. Figure 5G In the embodiment of the present invention, the second sub-layer 202 can be temporarily ignored, so that the isolation layer 180 can directly cover the first surface a1. When the second sub-layer 202 is provided, the isolation layer 180 here can be as follows: Figure 5G As shown, the second sub-layer 202 is covered to indirectly cover the first surface a1. In addition, the isolation layer 180 covers the insulating filling structure 140, and can cover the first portion 141 of the insulating filling structure 140, and when there is a first insulating layer 131 on the side of the first portion 141, it can also cover the first insulating layer 131 to indirectly cover the side of the first portion 141.

[0104] S07, using a first etching process to etch the semiconductor structure along a target direction to form a plurality of blocking portions and a plurality of third grooves. Figure 5G , the target direction is from the side of the substrate 10 toward the isolation layer 180 to the side of the substrate 10 away from the isolation layer 180 (i.e., the -Y direction in the figure). In the scheme where the mask layer 20 only includes the first sublayer 201, etching the semiconductor structure 100 can be to only etch the isolation layer 180, that is, to expose part of the first surface a1 and the surface of the first part of the insulating filling structure 140, thereby forming a blocking portion and a third groove. When the mask layer 20 also includes the second sublayer 202, for example, the first etching process can be used to continue to etch downward to remove part of the first part 141 and part of the second sublayer 202 to expose the first surface a1, forming a structure such as Figure 5H The blocking portion 150 and the third groove 170 are shown. Figure 5HThe blocking portion 150 includes at least a portion of the first portion 141 and the isolation layer 180 around the first portion 141 that is not etched by the first etching process; the third groove 170 is located between two adjacent blocking portions 150, and the third groove 170 exposes the first surface a1. Here, the first etching process may be a dry etching process.

[0105] In some embodiments, see Figure 4D , S3, the step of forming a plurality of second grooves on the first surface of the substrate is: S08, using a second etching process, using the plurality of third grooves to etch the substrate along a target direction to form a plurality of second grooves.

[0106] In this step, refer to Fig.5I , a second etching process (such as a dry etching process) can be used to etch the substrate 10 along the target direction (-Y direction) using the third groove 170 to form a second groove 160. Here, the blocking portion 150 formed previously is used as a mask to form the second groove 160 by self-alignment, and there is no need to set a new mask layer separately. The position accuracy of the second groove 160 is relatively high, for example, it is relatively centered, and a semiconductor body 1021 can be separated into two semiconductor pillars 801 that are mirror-symmetrical. That is, some of the above embodiments can adopt the LE+Self aligned process method, improve the process window, increase the overlay margin, for example, improve the problem of large overlay (OVL) deviation caused by the above LELE method, and at the same time reduce the process difficulty and cost, and make the prepared semiconductor structure 100 less likely to bend.

[0107] In some embodiments, continue to refer to Figure 5G-Figure 5I , the isolation layer 180 may include a first dielectric layer 181 and a second dielectric layer 182. The material of the first dielectric layer 181 is different from the material of the second dielectric layer 182. In this way, the position and width of the third groove 170 (i.e., the size of the third groove 170 along the X direction) can be better controlled by the first dielectric layer 181 and the second dielectric layer 182. For example, a third groove 170 with a centered position and a suitable width can be formed between adjacent blocking parts 150, so that the third groove 170 can be used to etch and form a second groove 160 with a suitable position and width. Of course, in other embodiments, the number of layers of the isolation layer 180 can also be set to one layer, three layers or more layers. In this case, the different design size requirements of the third groove 170 and the second groove 160 can still be met by controlling the number of layers of the isolation layer 180 and the thickness of each layer.

[0108] Exemplarily, the material of the first dielectric layer 181 may include silicon nitride, and the material of the second dielectric layer 182 may include oxide (such as silicon oxide). Here, the material of the second dielectric layer 182 may be the same as the material of the first insulating layer 131. In this way, the position and width of the third groove 170 can be better controlled, so that the third groove 170 can be used to etch and form a suitable second groove 160.

[0109] In some embodiments, Figure 5B to Figure 5F As shown, S00, the mask layer 20 is arranged on the first surface a1 of the substrate 10, including: a second sublayer 202 and a first sublayer 201 are sequentially formed on the first surface a1 of the substrate 10; the first sublayer 201 and the second sublayer 202 are made of different materials, and in such an arrangement, the second sublayer 202 can be used as a stop layer in the previous step of removing the first sublayer 201. When forming the blocking portion 150, the remaining second sublayer 202 can also be used as a part of the blocking portion 150, and the height (dimension along the Y direction) of the blocking portion 150 can also be raised.

[0110] Exemplarily, the material of the first sublayer 201 includes silicon nitride, and the material of the second sublayer 202 includes oxide (such as silicon oxide). Thus, since silicon nitride and oxide have a large etching selectivity, the second sublayer 202 acts as a good etching barrier, so as to facilitate the removal of the first sublayer 201.

[0111] In some examples, such as Fig. 6A As shown, S00, setting a mask layer on the first surface of the substrate further includes: sequentially forming a third sub-layer 203 and a fourth sub-layer 204 on the first sub-layer 201, the first sub-layer 201 and the fourth sub-layer 204 are made of the same material, and the first sub-layer 201 and the third sub-layer 203 are made of different materials; the third sub-layer 203 is used as a stop layer when removing the fourth sub-layer 204. Figure 6BWhen forming the insulating filling structure 140, it is necessary to fill the second groove with insulating material, and then it is necessary to remove the excess insulating material and the first insulating layer located above the mask layer 20 (in the direction shown in the figure), and when only the first sub-layer 201 is provided, after removing the excess insulating material and the first insulating layer, the top surface of the mask layer 20 (i.e., the surface of the mask layer 20 facing away from the substrate 10, which is the top surface of the first sub-layer 201 at this time) is likely to be uneven. In this example, by providing the third sub-layer 203 and the fourth sub-layer 204, the third sub-layer 203 can be used as a stop layer, and the excess insulating material and the first insulating layer are removed together with the fourth sub-layer 204 (for example, by a CMP grinding process), and then stop at the third sub-layer 203, so that the top surface of the mask layer 20 (the top surface of the third sub-layer 203 at this time) can be more flat, and the process difficulty is reduced. Exemplarily, the material of the third sub-layer 203 includes polysilicon or titanium nitride, and the material of the fourth sub-layer 204 includes silicon nitride. With such a configuration, when the redundant insulating material and the first insulating layer are removed together with the fourth sub-layer 204 , they can be well retained on the third sub-layer 203 .

[0112] Afterwards, see Figure 6C When removing the first sublayer 201 between two adjacent insulating filling structures 140 , the third sublayer 203 thereon may be removed simultaneously. Subsequent steps are substantially the same as those in the previous embodiment and will not be described in detail herein.

[0113] In other examples, such as Fig. 7A As shown, S00, setting a mask layer on the first surface of the substrate also includes: forming a fifth sub-layer 205 and a sixth sub-layer 206 in sequence on the second sub-layer 202, and the fifth sub-layer 205 and the sixth sub-layer 206 are located between the second sub-layer 202 and the first sub-layer 201; the second sub-layer 202 and the sixth sub-layer 206 are made of the same material, and the second sub-layer 202 and the fifth sub-layer 205 are made of different materials; the fifth sub-layer 205 is used as a stop layer when removing the sixth sub-layer 206. Fig. 7A The first sublayer 201, the third sublayer 203 and the fourth sublayer 204 are also shown in FIG. 1 , and these three layers are not described in detail here. Figure 7B to Figure 7D ,exist Figure 7B In the embodiment, the isolation layer 180 may cover the surface of the sixth sub-layer 206 facing away from the substrate 10, and then, as shown in FIG. Figure 7C As shown, while etching the first isolation layer 180, the second sub-layer 202, the fifth sub-layer 205 and the sixth sub-layer 206 can also be opened to expose the first surface a1, and then, as shown in Fig.7D As shown, the second groove 160 can be formed by etching the third groove 170. Figure 5J and Figure 5KAs shown, after forming the isolation structure 16, the excess portion above the first surface needs to be removed. At this time, the CMP grinding process can be used to stop the rough grinding process at the fifth sub-layer 205. Compared with not providing the fifth sub-layer 205 and the sixth sub-layer 206, this embodiment can better control the grinding process and reduce the process difficulty. Afterwards, only the remaining second sub-layer 202 and the fifth sub-layer 205 need to be finely ground to form, for example Figure 5J or Figure 5K The structure shown. Exemplarily, the material of the fifth sublayer 205 includes silicon nitride, and the material of the sixth sublayer 206 includes oxide. In this configuration, since the difference between silicon nitride and silicon oxide is obvious, after removing the sixth sublayer 206, the grinding process can be well stopped at the fifth sublayer 205.

[0114] Combine the following Figure 5J , Figure 5K and Figure 8 , Fig. 9 The semiconductor structure 100 provided by some embodiments of the present disclosure is further introduced. Figure 8 To disclose a top view of a semiconductor structure in some embodiments, Fig. 9 A projection view of an isolation structure and a gate filling structure in some embodiments is disclosed.

[0115] like Figure 5J , Figure 5K and Figure 8 , Fig. 9 As shown, the semiconductor structure 100 provided by some embodiments of the present disclosure includes a plurality of gate filling structures 30, a plurality of isolation structures 16 and a plurality of semiconductor pillars 801. The plurality of gate filling structures 30 extend along a first direction (i.e., the Z direction). Each isolation structure 16 is located between two adjacent gate filling structures 30, the isolation structure 16 extends along the first direction (i.e., the Z direction), and the arrangement direction of the isolation structure 16 and the gate filling structure 30 is a second direction (i.e., the X direction). Each semiconductor pillar 801 is located between the isolation structure 16 and the gate filling structure 30, the semiconductor pillar 801 extends along a third direction (i.e., the Y direction), the third direction intersects with the first reference plane, and the first direction and the second direction are located on the first reference plane; wherein, the length L1 of the isolation structure 16 along the first direction is less than the length L2 of the gate filling structure 30 along the first direction.

[0116] The semiconductor structure 100 in this embodiment can be provided with a plurality of semiconductor pillars 801 between the isolation structure 16 and the gate filling structures 30 on both sides thereof, so as to form a plurality of vertical transistors, which is beneficial to improving the storage density of the semiconductor structure 100. In addition, the length L1 of the isolation structure 16 along the first direction is less than the length L2 of the gate filling structure 30 along the first direction, which makes the length of the isolation structure 16 shorter, for example, the isolation structure 16 may not extend to the edge area Q2 (such as the non-effective storage area), therefore, the isolation structure 16 can be provided only in the core area Q1 where electrical isolation is required, and there is no need to provide the isolation structure 16 in the edge area Q2 where electrical isolation is not required, which is also beneficial to reducing the cost when manufacturing the semiconductor structure 100.

[0117] In some embodiments, Figure 8 As shown, the semiconductor structure 100 has a core region Q1 and an edge region Q2; the gate filling structure 30 is located in the core region Q1 and the edge region Q2; and the isolation structure 16 is located in the core region Q1. Such a configuration is conducive to shortening the isolation structure 16 and reducing the manufacturing cost.

[0118] In some embodiments, Fig. 9 As shown, the first direction (i.e., Z direction) and the third direction (i.e., Y direction) are located on the second reference plane M2; the orthographic projection of the isolation structure 16 on the second reference plane M2 is the first orthographic projection 01, and the orthographic projection of the gate filling structure 30 on the second reference plane M2 is the second orthographic projection 02; along the first direction, the two ends of the first orthographic projection 01 are located between the two ends of the second orthographic projection 02. Such a setting is conducive to preventing the isolation structure 16 from extending or extending as little as possible to the edge area Q2. It is conducive to shortening the isolation structure 16 and reducing the manufacturing cost.

[0119] In some embodiments, see Figure 5J , Figure 5K and Figure 8 , along the second direction (i.e., the X direction), the distances (D1, D2) between the isolation structure 16 and the two adjacent gate filling structures 30 are equal. In this way, the thickness of the semiconductor pillars 801 on both sides of the isolation structure 16 can be equal, which is beneficial to ensure the yield of the vertical transistors on both sides of the isolation structure 16. In addition, the isolation structure 16 is relatively centered, which can also achieve a good isolation effect.

[0120] In some embodiments, along the second direction (i.e., the X direction), the distance difference between two adjacent gate filling structures 30 of the isolation structure 16 is less than or equal to 10 nm. Exemplarily, along the second direction, the distance difference between two adjacent gate filling structures 30 of the isolation structure 16 may also be less than or equal to 5 nm. Exemplarily, along the second direction, the distance difference between two adjacent gate filling structures 30 of the isolation structure 16 may be 10 nm, 8 nm, 6 nm, 5 nm, 4 nm, 2 nm, 1 nm, etc. In this embodiment, the distance difference between two adjacent gate filling structures 30 of the isolation structure 16 is relatively small, which is conducive to ensuring the yield of the vertical transistors on both sides of the isolation structure 16. In addition, the isolation structure 16 is relatively centered, which can also achieve a good isolation effect.

[0121] It should be noted that the distance (D1, D2) between the isolation structure 16 and the gate filling structure 30 may refer to the distance between the mutually adjacent boundaries of the isolation structure 16 and the gate filling structure 30 (ie, Figure 5J , Figure 5K and Figure 8 ), or it may be the distance between the center of the isolation structure 16 and the center of the gate filling structure 30, or it may be the distance between the edge of the isolation structure 16 close to the gate filling structure 30 and any reference object in the gate filling structure 30. In some embodiments, Figure 5J and Figure 5K As shown, the gate filling structure 30 includes: a stop structure 130 and a gate structure 120 stacked along the third direction (Y direction), the stop structure 130 includes a stop block 132 and a first insulating layer 131, the first insulating layer 131 is located between the stop block 132 and the semiconductor column 801, and the gate structure 120 includes a gate layer 122 and a gate insulating layer 121, and the gate insulating layer 121 is located between the gate layer 122 and the semiconductor column 801. The above-mentioned reference object can be the gate insulating layer 121 here, or the gate layer 122 here, or the first insulating layer 131 or the stop block 132 here. In some examples, along the second direction (X direction), the distance between the isolation structure 16 and the gate insulating layer 121 in two adjacent gate filling structures 30 is equal (that is, as shown in FIG. 1 ). Figure 5J , Figure 5K and Figure 8 shown).

[0122] In some embodiments, Figure 8As shown, it also includes a plurality of gate cut-off structures 40. It can be understood that when a plurality of gate structures 120 are formed in the first groove, the gate layer 122 in the gate structure 120 is annular, so that the gate layers (or word lines) of the two rows of vertical transistors are connected together, and the gate cut-off structure 40 can cut off the two word lines, thereby facilitating independent control of the two rows of vertical transistors.

[0123] In some embodiments, Figure 5J and Figure 5K As shown, the semiconductor column 801 includes a channel portion 001, a first pole 002 and a second pole 003; along the third direction (Y direction), the channel portion 001 is located between the first pole 002 and the second pole 003; along the second direction (X direction), the channel portion 001 overlaps with the gate layer 122. Figure 3 The storage unit 820 shown in the figure can be electrically connected to the first electrode 002. In this way, the front Figure 3 A memory cell 80 is shown.

[0124] For example, in the formation Figure 5J and Figure 5K After the structure is formed, a storage unit 820, such as a capacitor, can be continuously made above the first pole 002 of the semiconductor pillar 801. Thereafter, the semiconductor structure 100 can be flipped over and the substrate can be ground to the stop structure 130 to expose the second poles 003 of the plurality of semiconductor pillars 801. Thereafter, a plurality of bit lines can be made to connect the second poles 003 of the plurality of semiconductor pillars 801.

[0125] As described above, the semiconductor structure provided in the embodiment of the present application may be a memory or a part of a memory. A memory formed based on the semiconductor structure provided in the embodiment of the present application is introduced below.

[0126] Fig.10 A structural diagram of a memory in some embodiments of the present disclosure.

[0127] like Fig.10 As shown, the memory includes a first semiconductor structure 901 (for example, a semiconductor structure provided by an embodiment of the present disclosure) and a second semiconductor structure 902. According to some embodiments, the first semiconductor structure 901 and the second semiconductor structure 902 are bonded at a bonding interface therebetween. Fig.10 As shown, the second semiconductor structure 902 may include a substrate 1710 , which may include silicon (eg, single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0128] The second semiconductor structure 902 may also include a peripheral circuit 1712 on the substrate 1710. In some embodiments, the peripheral circuit 1712 includes a plurality of transistors 1714 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 1714) may also be formed on or in the substrate 1710.

[0129] In some embodiments, the second semiconductor structure 902 also includes an interconnect layer 1716 above the peripheral circuit 1712 to transmit electrical signals to and from the peripheral circuit 1712. The interconnect layer 1716 may include a plurality of interconnects (also referred to herein as "contacts"), the interconnects including lateral interconnects and VIA contacts. The interconnect layer 1716 may also include one or more ILD layers, in which interconnects and via contacts may be formed. That is, the interconnect layer 1716 may include interconnects and via contacts in a plurality of ILD layers. In some embodiments, the peripheral circuits 1712 are coupled to each other via the interconnects in the interconnect layer 1716. The interconnects in the interconnect layer 1716 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0130] like Fig.10 As shown, the second semiconductor structure 902 may also include a bonding layer 1718 at the bonding interface 106 and above the interconnect layer 1716 and the peripheral circuit 1712. The bonding layer 1718 may include a plurality of bonding contacts 1719 and a dielectric that electrically isolates the bonding contacts 1719. The bonding contacts 1719 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 1718 may be formed with a dielectric material (e.g., silicon oxide). The bonding contacts 1719 in the bonding layer 1718 and the surrounding dielectric may be used for hybrid bonding. Similarly, as Fig.10 As shown, the first semiconductor structure 901 may also include a bonding layer 1720 at the bonding interface 106 and above the bonding layer 1718 of the second semiconductor structure 902. The bonding layer 1720 may include a plurality of bonding contacts 1721 and a dielectric that electrically isolates the bonding contacts 1721. The bonding contacts 1721 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 1720 may be formed by a dielectric material (e.g., silicon oxide). The bonding contacts 1721 in the bonding layer 1720 and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the bonding contacts 1721 are in contact with the bonding contacts 1719 at the bonding interface 106.

[0131] The first semiconductor structure 901 can be bonded in a face-to-face manner on top of the second semiconductor structure 902 at a bonding interface 106. In some embodiments, the bonding interface 106 is set between the bonding layers 1720 and 1718 as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface 106 is the location where the bonding layers 1720 and 1718 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness that includes the top surface of the bonding layer 1718 of the second semiconductor structure 902 and the bottom surface of the bonding layer 1720 of the first semiconductor structure 901. In some embodiments, the first semiconductor structure 901 further includes an interconnect layer 1722, which includes a bit line 1723 above the bonding layer 1720 to transmit electrical signals. The interconnect layer 1722 may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. In some embodiments, the interconnects in the interconnect layer 1722 also include local interconnects. The interconnect layer 1722 may also include one or more ILD layers, in which interconnect lines and via contacts may be formed. The interconnects in the interconnect layer 1722 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the peripheral circuit 1712 includes a word line driver / row decoder coupled to a word line contact in the interconnect layer 1722 through bonding contacts 1721 and 1719 in the bonding layers 1720 and 1718 and the interconnect layer 1716. In some embodiments, peripheral circuitry 1712 includes a bit line driver / column decoder coupled to bit lines 1723 and bit line contacts (if any) in interconnect layer 1722 through bonding contacts 1721 and 1719 in bonding layers 1720 and 1718 and interconnect layer 1716 .

[0132] In some embodiments, the first semiconductor structure 901 includes a DRAM device, wherein the memory cells are provided in the form of an array of DRAM cells 1724 over the interconnect layer 1722 and the bonding layer 1720. That is, the interconnect layer 1722 including the bit lines 1723 may be disposed between the bonding layer 1720 and the array of DRAM cells 1724. It should be understood that Fig.10The cross section of the 3D memory in can be taken along the bit line direction, and a bit line 1723 in the laterally extending interconnect layer 1722 can be coupled to a column of DRAM cells 1724. Each DRAM cell 1724 may include a vertical transistor 1726 (for example, it may be the previous vertical transistor 810) and a capacitor 1728 coupled to the vertical transistor 1726 (for example, it may be the previous memory cell 820). The DRAM cell 1724 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 1724 may be any suitable structure, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 1726 may be a MOSFET for switching the corresponding DRAM cell 1724. In some embodiments, the vertical transistor 1726 includes a vertically extending semiconductor column 1730 (for example, it may be the previous semiconductor column 801), and a gate structure 1736 (for example, it may be the previous gate structure 120) that contacts one side of the semiconductor column 1730 in the bit line direction (y direction). In a single-gate vertical transistor, the semiconductor pillar 1730 may have a cubic shape or a cylindrical shape, and the gate structure 1736 may be adjacent to a single side of the semiconductor pillar 1730 in a plan view, for example, as shown in FIG. Fig.10 According to some embodiments, the gate structure 1736 includes a gate electrode 1734 (which may be, for example, the previous gate layer 122) and a gate dielectric 1732 (which may be, for example, the previous gate insulating layer 121) laterally between the gate electrode 1734 and the semiconductor pillar 1730 in the bit line direction. In some embodiments, the gate dielectric 1732 is adjacent to one side of the semiconductor pillar 1730, and the gate electrode 1734 is adjacent to the gate dielectric 1732.

[0133] In some embodiments, the semiconductor pillar 1730 can have a vertical dimension that is larger than a vertical dimension (e.g., depth) of the gate electrode 1734 (e.g., in the Y direction), and neither the upper end nor the lower end of the semiconductor pillar 1730 is flush with the corresponding end of the gate electrode 1734. Therefore, a short circuit between the bit line 1723 and the word line / gate electrode 1734 or between the word line / gate electrode 1734 and the capacitor 1728 can be avoided. The vertical transistor 1726 can also include a source and a drain (both referred to as 1738 because their positions can be interchanged) respectively arranged at two ends (upper end and lower end) of the semiconductor pillar 1730 in the vertical direction (Y direction). In some embodiments, one of the source and the drain 1738 (e.g., in Fig.10 ) is coupled to capacitor 1728, and the other of the source and drain 1738 (e.g., at Fig.10 ) is coupled to the bit line 1723.

[0134] In some embodiments, the semiconductor pillar 1730 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor pillar 1730 may include single crystal silicon. The source and drain 1738 may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain 1738 and the bit line 1723 or the first electrode 1742 to reduce contact resistance. In some embodiments, the gate dielectric 1732 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 1734 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicide, or any combination thereof. In some embodiments, the gate electrode 1734 includes multiple conductive layers, such as a W layer on a TiN layer, such as Fig.10 In one example, the gate structure 1736 may be a "gate oxide / gate polysilicon" gate, where the gate dielectric 1732 includes silicon oxide, and the gate electrode 1734 includes doped polysilicon. In another example, the gate structure 1736 may be a HKMG, where the gate dielectric 1732 includes a high-k dielectric, and the gate electrode 1734 includes a metal.

[0135] As described above, since gate electrode 1734 can be part of a word line or as a word line in the word line direction (eg, Fig.10 In the Z direction, Fig.10 As shown, the first semiconductor structure 901 of the 3D memory device 1700 may also include a plurality of word lines each extending in a word line direction (Z direction). Each word line 1734 may be coupled to a row of DRAM cells 1724. That is, the bit line 1723 and the word line 1734 may extend in two perpendicular lateral directions, and the semiconductor pillar 1730 of the vertical transistor 1726 may extend in a vertical direction perpendicular to the two lateral directions along which the bit line 1723 and the word line 1734 extend. According to some embodiments, the word line 1734 contacts a word line contact (not shown). In some embodiments, the word line 1734 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 1734 includes a plurality of conductive layers, such as a W layer (such as the previous second conductive layer 1222) on a TiN layer (such as the previous first conductive layer 1221), such as Fig.10. According to some embodiments, vertical transistor 1726 extends vertically through word line 1734 and contacts word line 1734, and source or drain 1738 of vertical transistor 1726 at its lower end contacts bit line 1723 (or contacts bit line contact, if any). Therefore, due to the vertical arrangement of vertical transistor 1726, word line 1734 and bit line 1723 can be arranged in different planes in the vertical direction, which simplifies the wiring of word line 1734 and bit line 1723.

[0136] In some embodiments, the bit line 1723 is vertically disposed between the bonding layer 1720 and the word line 1734, and the word line 1734 is vertically disposed between the bit line 1723 and the capacitor 1728. The word line 1734 can be coupled to the peripheral circuit 1712 in the second semiconductor structure 902 through the word line contact (not shown) in the interconnect layer 1722, the bonding contacts 1721 and 1719 in the bonding layers 1720 and 1718, and the interconnect in the interconnect layer 1716. Similarly, the bit line 1723 in the interconnect layer 1722 can be coupled to the peripheral circuit 1712 in the second semiconductor structure 902 through the bonding contacts 1721 and 1719 in the bonding layers 1720 and 1718, and the interconnect in the interconnect layer 1716.

[0137] As described above, the vertical transistors 1726 can be arranged in a mirror-symmetrical manner to increase the density of the DRAM cells 1724 in the bit line direction (X direction). Fig.10As shown in , according to some embodiments, two adjacent vertical transistors 1726 in the bit line direction are mirror-symmetric to each other with respect to the trench isolation 1760 (e.g., corresponding to the previous isolation structure 16). That is, the first semiconductor structure 901 may include a plurality of trench isolations 1760, each trench isolation 1760 extending parallel to the word line 1734 in the word line direction (x direction) and disposed between the semiconductor pillars 1730 of two adjacent rows of vertical transistors 1726. In some embodiments, the rows of vertical transistors 1726 separated by the trench isolation 1760 are mirror-symmetric to each other with respect to the trench isolation 1760. The trench isolation 1760 may be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. It should be understood that the trench isolation 1760 may include air gaps each disposed laterally between adjacent semiconductor pillars 1730. As described below with respect to the manufacturing process, air gaps may be formed because the spacing of the vertical transistors 1726 in the bit line direction (e.g., y direction) is relatively small. On the other hand, the relatively large dielectric constant of air in the air gaps (e.g., about 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the isolation effect between the vertical transistors 1726 (and the rows of DRAM cells 1724). Similarly, in some embodiments, air gaps are also formed laterally between the word lines / gate electrodes 1734 in the bit line direction, depending on the spacing of the word lines / gate electrodes 1734 in the bit line direction.

[0138] like Fig.10 As shown, in some embodiments, capacitor 1728 includes a first electrode 1742 above and in contact with a source or drain 1738 of a vertical transistor 1726 (e.g., an upper end of a semiconductor pillar 1730). Capacitor 1728 may also include a capacitor dielectric 1744 above and in contact with the first electrode 1742, and a second electrode 1746 above and in contact with the capacitor dielectric 1744. That is, capacitor 1728 may be a vertical capacitor in which electrodes 1742 and 1746 and capacitor dielectric 1744 are stacked vertically (in the Y direction), and capacitor dielectric 1744 may be sandwiched between electrodes 1742 and 1746. In some embodiments, each first electrode 1742 is coupled to a source or drain 1738 of a corresponding vertical transistor 1726 in the same DRAM cell, and all second electrodes 1746 are part of a common plate (e.g., a common ground) coupled to ground. As Fig.10As shown, the first semiconductor structure 901 may further include a capacitor contact 1747 in contact with a common plate of the second electrode 1746 for coupling the second electrode 1746 of the capacitor 1728 to the peripheral circuit 1712 or directly to ground. In some embodiments, the ILD layer in which the capacitor 1728 is formed has the same dielectric material as the two ILD layers into which the semiconductor pillar 1730 extends, such as silicon oxide.

[0139] It should be understood that the structure and construction of capacitor 1728 is not limited to Fig.10 , and may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. In some embodiments, capacitor dielectric 1744 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 1728 can be a ferroelectric capacitor used in a FRAM cell, and capacitor dielectric 1744 can be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, electrodes 1742 and 1746 include a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0140] like Fig.10 As shown, according to some embodiments, the vertical transistor 1726 vertically extends through the word line 1734 and contacts the word line 1734, the source or drain 1738 of the vertical transistor 1726 at the lower end thereof contacts the bit line 1723, and the source or drain 1738 of the vertical transistor 1726 at the upper end thereof contacts the electrode 1742 of the capacitor 1728. That is, due to the vertical arrangement of the vertical transistor 1726, the bit line 1723 and the capacitor 1728 can be arranged in different planes in the vertical direction and coupled to the opposite ends of the vertical transistor 1726 of the DRAM cell 1724 in the vertical direction. In some embodiments, the bit line 1723 and the capacitor 1728 are arranged on opposite sides of the vertical transistor 1726 in the vertical direction, which simplifies the wiring of the bit line 1723 and reduces the coupling capacitance between the bit line 1723 and the capacitor 1728 compared to a conventional DRAM cell in which the bit line and the capacitor are arranged on the same side of a planar transistor.

[0141] like Fig.10As shown, in some embodiments, the vertical transistor 1726 is vertically disposed between the capacitor 1728 and the bonding interface 106. That is, the vertical transistor 1726 can be arranged closer to the peripheral circuit 1712 of the second semiconductor structure 902 and the bonding interface 106 than the capacitor 1728. Since the bit line 1723 and the capacitor 1728 are coupled to opposite ends of the vertical transistor 1726, as described above, according to some embodiments, the bit line 1723 (as part of the interconnect layer 1722) is vertically disposed between the vertical transistor 1726 and the bonding interface 106. As a result, the interconnect layer 1722 including the bit line 1723 can be arranged close to the bonding interface 106 to reduce the interconnect routing distance and complexity.

[0142] In some embodiments, the first semiconductor structure 901 further includes a substrate 1748 disposed above the DRAM cell 1724. As described below with respect to the manufacturing process, the substrate 1748 may be part of a carrier wafer. It should be understood that in some examples, the substrate 1748 may not be included in the first semiconductor structure 901.

[0143] like Fig.10As shown, the first semiconductor structure 901 may also include a substrate 1748 and a pad extraction interconnect layer 1750 above the DRAM cell 1724. The pad extraction interconnect layer 1750 may include interconnects in one or more ILD layers, for example, contact pads 1754. The pad extraction interconnect layer 1750 and the interconnect layer 1722 may be formed on opposite sides of the DRAM cell 1724. According to some embodiments, the capacitor 1728 is vertically disposed between the vertical transistor 1726 and the pad extraction interconnect layer 1750. In some embodiments, the interconnects in the pad extraction interconnect layer 1750 may transmit electrical signals between the 3D memory device 1700 and an external circuit, for example, for the purpose of pad extraction. In some embodiments, the first semiconductor structure 901 also includes one or more contacts 1752 extending through portions of the pad extraction interconnect layer 1750 and the substrate 1748 to couple the pad extraction interconnect layer 1750 to the DRAM cell 1724 and the interconnect layer 1722. As a result, the peripheral circuit 1712 can be coupled to the DRAM cell 1724 through the interconnect layers 1716 and 1722 and the bonding layers 1720 and 1718, and the peripheral circuit 1712 and the DRAM cell 1724 can be coupled to the external circuit through the contact 1752 and the pad lead-out interconnect layer 1750. The contact pad 1754 and the contact 1752 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the contact pad 1754 may include Al, and the contact 1752 may include W. In some embodiments, the contact 1752 includes a via surrounded by a dielectric spacer (e.g., with silicon oxide) to electrically separate the via from the substrate 1748. Depending on the thickness of the substrate 1748, the contact 1752 may be an ILV having a depth of sub-micron level (e.g., between 10 nm and 1 μm), or a TSV having a depth of micron level or tens of microns level (e.g., between 1 μm and 100 μm).

[0144] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Forming a plurality of first grooves on a first surface of the substrate, wherein the first grooves extend along a first direction; forming a plurality of gate structures in the plurality of first grooves; A plurality of second grooves are formed on the first surface of the substrate, each second groove is located between two adjacent first grooves, and the second grooves extend along the first direction; A plurality of isolation structures are formed in the plurality of second grooves.

2. The preparation method according to claim 1, characterized in that: Before the step of forming a plurality of first grooves on the first surface of the substrate, the step further includes: Disposing a mask layer on the first surface of the substrate, wherein the mask layer includes a plurality of openings; The step of forming a plurality of first grooves on the first surface of the substrate comprises: The substrate is etched using the multiple openings of the mask layer to form a plurality of first grooves.

3. The preparation method according to claim 2, characterized in that: After the step of forming a plurality of gate structures in the plurality of first grooves and before the step of forming a plurality of second grooves on the first surface of the substrate, the method further includes: forming a plurality of insulating filling structures, wherein one of the insulating filling structures is located in one of the first grooves and one of the openings that are connected; a portion of the insulating filling structure located in the opening is defined as a first portion; At least removing a first sublayer located between two adjacent insulating filling structures, wherein the first sublayer is at least a portion of the mask layer; forming an isolation layer, wherein the isolation layer covers the plurality of insulating filling structures and the first surface; The semiconductor structure is etched along a target direction by a first etching process to form a plurality of blocking portions and a plurality of third grooves; wherein the target direction is from the substrate toward the isolation layer to the substrate away from the isolation layer; the blocking portion includes at least a portion of the first portion and the isolation layer around the first portion that is not etched by the first etching process; the third groove is located between two adjacent blocking portions, and the third groove exposes the first surface; The step of forming a plurality of second grooves on the first surface of the substrate is: A second etching process is adopted to etch the substrate along the target direction using the plurality of third grooves to form a plurality of second grooves.

4. The preparation method according to claim 3, characterized in that: The first etching process and the second etching process both include dry etching processes.

5. The preparation method according to claim 3, characterized in that: The step of forming the isolation layer includes: forming a first dielectric layer and a second dielectric layer in sequence; the material of the first dielectric layer is different from the material of the second dielectric layer.

6. The preparation method according to claim 5, characterized in that: The material of the first dielectric layer includes silicon nitride, and the material of the second dielectric layer includes oxide.

7. The preparation method according to claim 3, characterized in that: The step of providing a mask layer on the first surface of the substrate includes: forming the first sub-layer on the first surface of the substrate; the material of the first sub-layer includes silicon nitride or oxide.

8. The preparation method according to claim 3, characterized in that: The step of providing a mask layer on the first surface of the substrate includes: a second sublayer and the first sublayer are sequentially formed on the first surface of the substrate; the first sublayer and the second sublayer are made of different materials.

9. The preparation method according to claim 8, characterized in that: The material of the first sub-layer includes silicon nitride, and the material of the second sub-layer includes oxide.

10. The preparation method according to claim 8, characterized in that: The step of providing a mask layer on the first surface of the substrate further comprises: A third sublayer and a fourth sublayer are sequentially formed on the first sublayer. The first sublayer and the fourth sublayer are made of the same material, and the first sublayer and the third sublayer are made of different materials. The third sublayer serves as a stop layer when removing the fourth sublayer.

11. The preparation method according to claim 10, characterized in that: The material of the third sub-layer includes polysilicon or titanium nitride, and the material of the fourth sub-layer includes silicon nitride.

12. The preparation method according to claim 8, characterized in that: The step of providing a mask layer on the first surface of the substrate further comprises: A fifth sublayer and a sixth sublayer are sequentially formed on the second sublayer, and the fifth sublayer and the sixth sublayer are located between the second sublayer and the first sublayer; the second sublayer and the sixth sublayer are made of the same material, and the second sublayer and the fifth sublayer are made of different materials; the fifth sublayer serves as a stop layer when removing the sixth sublayer.

13. The preparation method according to claim 12, characterized in that: The material of the fifth sub-layer includes silicon nitride, and the material of the sixth sub-layer includes oxide.

14. The preparation method according to any one of claims 1 to 13, characterized in that: After the step of forming a plurality of first grooves on the first surface of the substrate and before forming a plurality of gate structures in the plurality of first grooves, the method further includes: forming a first insulating layer on an inner wall of the first groove, wherein a first sub-groove is formed in the first insulating layer; forming a stop block at the bottom of the first sub-groove to obtain a second sub-groove; The forming of a plurality of gate structures in the plurality of first grooves comprises: A gate layer is formed on the sidewall of the second sub-recess, with a distance between the gate layer and the first surface.

15. The preparation method according to claim 14, characterized in that: The forming of a plurality of gate structures in the plurality of first grooves further comprises: The sidewall of the second sub-recess is oxidized to form a gate insulating layer.

16. The preparation method according to any one of claims 1 to 13, characterized in that: The forming of a plurality of isolation structures in the plurality of second grooves comprises: forming a second insulating layer on the inner wall of the second groove, wherein the second insulating layer surrounds a receiving groove; forming an isolation column in the receiving groove; The receiving groove is filled with an insulating material to cover the isolation column.

17. The preparation method according to any one of claims 1 to 13, characterized in that: The forming of a plurality of isolation structures in the plurality of second grooves comprises: The second groove is filled with insulating material to form the isolation structure including an air gap.

18. A semiconductor structure, characterized in that: include: A plurality of gate filling structures extending along a first direction; A plurality of isolation structures, each isolation structure is located between two adjacent gate filling structures, the isolation structure extends along the first direction, and the arrangement direction of the isolation structure and the gate filling structure is the second direction; a plurality of semiconductor pillars, each semiconductor pillar being located between the isolation structure and the gate filling structure, the semiconductor pillar extending along a third direction, the third direction intersecting with a first reference plane, the first direction and the second direction being located on the first reference plane; Wherein, a length of the isolation structure along the first direction is smaller than a length of the gate filling structure along the first direction.

19. The semiconductor structure according to claim 18, characterized in that The first direction and the third direction are located on a second reference plane; the orthographic projection of the isolation structure on the second reference plane is a first orthographic projection, and the orthographic projection of the gate filling structure on the second reference plane is a second orthographic projection; Along the first direction, two ends of the first orthographic projection are located between two ends of the second orthographic projection.

20. The semiconductor structure according to claim 18, characterized in that The semiconductor structure has a core region and an edge region; the gate filling structure is located in the core region and the edge region; and the isolation structure is located in the core region.

21. The semiconductor structure according to claim 18, characterized in that Along the second direction, the distances between the isolation structure and two adjacent gate filling structures are equal.

22. The semiconductor structure according to claim 18, wherein: Along the second direction, a distance difference between two adjacent gate filling structures of the isolation structure is less than or equal to 10 nm.

23. The semiconductor structure according to claim 18, characterized in that The gate filling structure comprises: a stop structure and a gate structure stacked along the third direction, the stop structure comprises a stop block and a first insulating layer, the first insulating layer is located between the stop block and the semiconductor column, the gate structure comprises a gate layer and a gate insulating layer, the gate insulating layer is located between the gate layer and the semiconductor column; Along the second direction, the distance between the isolation structure and the gate insulation layers in two adjacent gate filling structures is equal.

24. The semiconductor structure according to claim 23, characterized in that The semiconductor column comprises a channel portion, a first pole and a second pole; along the third direction, the channel portion is located between the first pole and the second pole; along the second direction, the channel portion overlaps with the gate layer; A storage unit is electrically connected to the first electrode.

25. A storage system, characterized in that: include: A semiconductor structure prepared by the preparation method according to any one of claims 1 to 17, or a semiconductor structure according to any one of claims 18 to 24; A controller is coupled to the semiconductor structure.

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