Preparation method of vertical channel hole

Abstract

The invention discloses a preparation method of a vertical channel hole, and the method comprises the steps: S10, providing a semiconductor structure which comprises an etching stop layer and a to-be-etched layer; s20, forming a patterned mask layer on the semiconductor structure by using a photoetching process; s30, taking the patterned mask layer as a mask, and forming an initial channel hole vertically penetrating through the to-be-etched layer through a dry etching process; s40, performing wet cleaning on the initial channel holes, and measuring to obtain the average aperture of the channel holes subjected to wet cleaning; s50, determining wet etching process parameters based on the average aperture, performing wet etching on the channel holes, and measuring the average aperture of the channel holes after wet etching; s60, judging whether the measured average aperture of the channel holes is smaller than a set aperture lower limit value or not; and if yes, repeating the step 50 and the step S60 until the average aperture of the channel hole measured after wet etching again is not smaller than the set aperture lower limit value. According to the preparation method, the stability of the aperture of the channel hole can be remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a vertical channel hole. Background Art

[0002] According to Moore's Law, integrated circuits continue to develop towards smaller sizes. When DRAM technology exceeds the 1z node and above, the continuous shrinking of the 6F2 fin field-effect transistor structure will face huge challenges in device performance and process development. Researchers have proposed a new generation of DRAM storage transistor architecture, namely 4F2 VCT (Vertical Channel Transistor).

[0003] Currently, for the vertical channel hole of the vertical channel transistor, an initial channel hole is usually formed by photolithography and dry etching processes during preparation, and then the inner surface of the initial channel hole is wet cleaned to form a vertical channel hole with a specific aperture.

[0004] In the above-mentioned preparation process, the aperture of the vertical channel hole is affected by photolithography, dry etching and wet cleaning, with many variables and large fluctuations, and the dimensional stability of the aperture is poor.

[0005] Therefore, it is necessary to improve the preparation process of the vertical channel hole to at least partially solve the above problems. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] In order to at least partially solve the above problems, the present invention provides a method for preparing a vertical channel hole, which comprises the following steps:

[0008] S10: providing a semiconductor structure, wherein the semiconductor structure comprises an etch stop layer and a layer to be etched which are sequentially stacked on a substrate;

[0009] S20: forming a patterned mask layer on the semiconductor structure by using a photolithography process;

[0010] S30: using the patterned mask layer as a mask, forming an initial channel hole vertically penetrating the layer to be etched by a dry etching process, wherein the cross section of the initial channel hole is circular;

[0011] S40: wet-cleaning the initial channel hole to form a wet-cleaned channel hole and measuring the average pore size of the wet-cleaned channel hole; wherein the target average pore size of the wet-cleaned channel hole is d1, and the target average pore size of the vertical channel hole is d2, d2=(1.02-1.2)×d1;

[0012] S50: determining wet etching process parameters based on the measured average pore size of the channel holes, wet etching the channel holes according to the wet etching process parameters to form wet-etched channel holes, and measuring the average pore size of the wet-etched channel holes;

[0013] S60: Determine whether the average pore size of the measured channel hole is less than the set pore size lower limit; if so, repeat step 50 and step S60 until the average pore size of the channel hole measured after wet etching again is not less than the set pore size lower limit, so as to complete the preparation of the vertical channel hole.

[0014] Exemplarily, the set aperture lower limit value = d2 - δ, where δ is the set error.

[0015] Exemplarily, the wet etching process parameters include one or more of the composition of the etching solution, the etching time and the type of the nozzle;

[0016] Wherein, the nozzle is used for spraying etching liquid.

[0017] Exemplarily, when measuring the aperture of the channel hole, the height position of the measuring point in the direction perpendicular to the substrate is controlled to be the same during each measurement.

[0018] Exemplarily, the etch stop layer includes a first oxide layer, and the layer to be etched includes a word line layer and a second oxide layer sequentially stacked on the first oxide layer;

[0019] The word line layer includes a plurality of word lines arranged at intervals, and two adjacent word lines are insulated from each other by insulating materials;

[0020] The semiconductor structure further includes a bit line layer, the bit line layer is arranged between the substrate and the first oxide layer, the bit line layer includes a plurality of bit lines arranged at intervals, and two adjacent bit lines are insulated from each other by an insulating material;

[0021] The word lines and the bit lines extend in directions that intersect with each other, and the word lines and the bit lines extend in directions that are parallel to the substrate.

[0022] Exemplarily, the word line includes a word line material layer and a first barrier layer and a second barrier layer located on two sides of the word line material layer along a direction perpendicular to the substrate.

[0023] Exemplarily, the material of the first barrier layer and the second barrier layer is titanium nitride, the material of the word line material layer is tungsten, and the material of the first oxide layer and the second oxide layer are both silicon oxide.

[0024] Exemplarily, the cleaning solution of the wet cleaning includes one or more of a DHF solution, a DAM solution, a DSP+ solution and an organic solution cleaning solution.

[0025] Exemplarily, the wet etching etchant includes a DHF solution and an SPM solution, the DHF solution is used to etch the second oxide layer, and the SPM solution is used to etch the word line layer;

[0026] The ratio of water to hydrofluoric acid in the DHF solution is 100:1 to 2000:1;

[0027] The ratio of sulfuric acid to hydrogen peroxide in the SPM solution is 2:1 to 18:1.

[0028] Exemplarily, the SPM solution further includes ammonium salt.

[0029] Exemplarily, the SPM solution is configured to have the same etching rate for titanium nitride and tungsten;

[0030] The step of determining the wet etching process parameters includes: designing the etching time of the DHF solution on the second oxide layer and the etching time of the SPM solution on the word line layer to coordinate so that the inner wall of the etched second oxide layer is flush with the inner wall of the etched word line layer.

[0031] According to the preparation method of the vertical channel hole of the present invention, after wet cleaning, the average pore size of the channel hole after wet cleaning is measured, the wet etching process parameters are determined based on the measured average pore size of the channel hole, and the channel hole is wet-etched based on the wet etching process parameters until the average pore size of the channel hole measured after wet etching is not less than the set pore size lower limit value. The pore size compensation of the channel hole after wet cleaning can be effectively adjusted to the target pore size through the wet etching process, thereby improving the dimensional stability of the pore size of the channel hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The following drawings of the present application are hereby used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the device and principle of the present application. In the drawings,

[0033] Figure 1 Schematic diagram of a process for preparing a vertical channel hole according to an embodiment of the present application;

[0034] Figure 2-Figure 7Schematic diagram of top view of the device in each step of the method for preparing a vertical channel hole according to an embodiment of the present application;

[0035] Figure 8-Figure 13 They are Figure 2-Figure 7 Schematic cross-sectional view at AA in the middle.

[0036] Description of reference numerals:

[0037] 100-substrate, 200-etching stop layer, 300-layer to be etched, 310-word line layer, 311-word line material layer, 312-first barrier layer, 313-second barrier layer, 320-second oxide layer, 330-initial channel hole, 340-channel hole after wet cleaning, 350-channel hole after wet etching, 400-insulating material, 500-bit line layer, 600-patterned mask layer, 610-amorphous carbon layer, 620-dielectric anti-reflective coating, 620-bottom anti-reflective coating, 640-photoresist layer, 700-gate dielectric layer. DETAILED DESCRIPTION

[0038] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0039] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0040] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0041] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to display the actual shape of the device and are not intended to limit the scope of the present application.

[0044] See attached Figure 1-13 The method for preparing a vertical channel hole according to an embodiment of the present application is exemplified. Figure 1 , the preparation method comprises the following steps:

[0045] S10: providing a semiconductor structure, the semiconductor structure comprising an etch stop layer 200 and a layer to be etched which are sequentially stacked on a substrate;

[0046] S20: forming a patterned mask layer on the semiconductor structure using a photolithography process;

[0047] S30: using the patterned mask layer as a mask, forming an initial channel hole vertically penetrating the to-be-etched layer by a dry etching process, wherein the cross section of the initial channel hole is circular;

[0048] S40: wet-cleaning the initial channel hole to form a wet-cleaned channel hole and measuring the average aperture of the wet-cleaned channel hole; wherein the target average aperture of the wet-cleaned channel hole is d1, and the target average aperture of the vertical channel hole is d2, d2 = (1.02-1.2) × d1;

[0049] S50: determining wet etching process parameters based on the measured average pore size of the channel hole, wet etching the channel hole according to the wet etching process parameters to form a wet-etched channel hole, and measuring the average pore size of the wet-etched channel hole;

[0050] S60: Determine whether the average pore size of the measured channel hole is less than the set pore size lower limit. If so, repeat step 50 and step S60 until the average pore size of the channel hole measured after wet etching again is not less than the set pore size lower limit, so as to complete the preparation of the vertical channel hole.

[0051] According to the preparation method of the vertical channel hole of the present invention, after wet cleaning, the average pore size of the channel hole after wet cleaning is measured, the wet etching process parameters are determined based on the measured average pore size of the channel hole, and the channel hole is wet-etched based on the wet etching process parameters until the average pore size of the channel hole measured after wet etching is not less than the set pore size lower limit value. The pore size compensation of the channel hole after wet cleaning can be effectively adjusted to the target pore size through the wet etching process, thereby improving the dimensional stability of the pore size of the channel hole.

[0052] The following will refer to the attached Figure 2-13 Each step of a method for preparing a vertical channel hole according to an embodiment of the present application is described in detail.

[0053] In step S10, see the attached Figure 2 , 8 (Attached Figure 8 For attachment Figure 2 ), a semiconductor structure is provided, the semiconductor structure includes a bit line layer 500, an etch stop layer 200 and a layer to be etched 300 sequentially stacked on a substrate.

[0054] The substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a germanium silicon (GeSi) substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator), etc. In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs), etc.

[0055] The bit line layer 500 is disposed between the substrate and the etching stop layer 200. The bit line layer 500 includes a plurality of bit lines arranged at intervals, and two adjacent bit lines are insulated from each other by insulating materials. For example, the material of the bit line can be polysilicon or tungsten, and the insulating material can be silicon oxide.

[0056] The etch stop layer 200 includes a first oxide layer, and the etched layer 300 includes a word line layer 310 and a second oxide layer 320 stacked on the first oxide layer. The word line layer 310 includes a plurality of word lines arranged at intervals, and two adjacent word lines are insulated from each other by an insulating material 400.

[0057] In this embodiment, the word line includes a word line material layer 311 and a first barrier layer 312 and a second barrier layer 313 located on both sides of the word line material layer 311 in a direction perpendicular to the substrate. The first barrier layer 312 is located between the word line material layer 311 and the first oxide layer, and the second barrier layer 313 is located between the word line material layer 311 and the second oxide layer 320. The first barrier layer 312 and the second barrier layer 313 are used to prevent the diffusion of the word line material layer 311, thereby improving the stability and reliability of the overall structure.

[0058] In this embodiment, the first barrier layer 312 and the second barrier layer 313 are made of titanium nitride, the word line material layer 311 is made of tungsten, and the first oxide layer 320 and the second oxide layer 320 are both made of silicon oxide.

[0059] The word lines and bit lines extend in directions that intersect, and the word lines and bit lines extend in directions that are parallel to the substrate. Figure 2 In the up and down directions, the extension direction of the bit line is Figure 2 In the left and right directions of the image, the word lines and the bit lines extend in a perpendicular direction. In other embodiments, the word lines and the bit lines extend in a certain angle, and the angle range is between 0° and 90°. The overlapping projections of each word line and each bit line on the substrate at least partially overlap with the projections of the corresponding transistors on the substrate, that is, selecting a word line and a bit line can select a transistor.

[0060] In step S20, see the attached Figure 3 , 9 (Attached Fig. 9 For attachment Figure 3 A patterned mask layer 600 is formed on the semiconductor structure by using a photolithography process.

[0061] In this embodiment, the patterned mask layer may include a patterned amorphous carbon (Carbon) layer 610 located on the second oxide layer 320, a patterned dielectric anti-reflective coating (DARC) 620 located on the amorphous carbon layer 610, a patterned bottom anti-reflective coating (BARC) 630 located on the dielectric anti-reflective coating 620, and a patterned photoresist layer 640 located on the bottom anti-reflective coating 630. Specifically, an amorphous carbon layer, a dielectric anti-reflective coating, a bottom anti-reflective coating and a photoresist layer can be formed layer by layer on the second oxide layer 320, and then the photoresist layer can be patterned through photolithography process steps such as pre-baking, exposure, development, and hardening to form a patterned photoresist layer 640. Then, the patterned photoresist layer 640 is used as a mask to etch the amorphous carbon layer, the dielectric anti-reflective coating, and the bottom anti-reflective coating to form a patterned amorphous carbon layer 610, a dielectric anti-reflective coating 620 and a patterned bottom anti-reflective coating 630.

[0062] In step S30, see the attached Figure 4 , 10 ( Fig.10 For attachment Figure 4 ), with the patterned mask layer 600 as a mask, an initial channel hole 330 is formed vertically through the layer to be etched 300 by a dry etching process, that is, an initial channel hole 330 is formed vertically through the second oxide layer 320, the second barrier layer 313, the word line material layer 311 and the first barrier layer 312. The cross section of the initial channel hole 330 is circular. The initial channel hole 330 can just expose the upper surface of the etch stop layer 200, or a small part can extend into the etch stop layer 200. After the initial channel hole 330 is formed, the patterned mask layer 600 can be removed by at least one process of ashing, wet etching process, CMP (Chemical Mechanical Polishing) process, etc.

[0063] In step S40, see the attached Figure 5 , 11 ( Fig.11 For attachment Figure 5), the initial channel hole 330 is wet cleaned to form the channel hole 340 after wet cleaning and the average pore size of the channel hole 340 after wet cleaning is measured. Various residues generated during dry etching can be effectively removed by wet cleaning. Exemplarily, the cleaning solution for wet cleaning may include one or more of DHF (Diluted Hydrofluoric Acid, diluted hydrofluoric acid) solution, DAM (Diluted Ammonia Mixture, diluted ammonia mixture) solution, DSP+ (diluted sulfuric acid / hydrogen peroxide mixture, with a trace amount of hydrofluoric acid added) solution and organic solution cleaning solution. Exemplarily, the ratio (volume ratio) of water (deionized water) and hydrofluoric acid in the DHF solution used as a cleaning solution may be 100:1 to 2000:1, the ratio (volume ratio) of water and ammonia in the DAM solution may be 50:1 to 500:1, and the organic solution cleaning solution may include cleaning solutions known to those skilled in the art such as ST250, NE111, SST-A47, etc. It should be noted that the cleaning solution of the wet cleaning process usually etches the inner surface of the channel hole to a certain extent, causing the inner surface of the channel hole to be uneven and causing the aperture of the channel hole to fluctuate. For example, the DHF solution will cause a certain degree of etching on the inner surface of a portion of the channel hole located in the first oxide layer and the second oxide layer 320, and the DSP+ solution will cause a certain degree of etching on the inner surface of a portion of the channel hole located in the first barrier layer 312, the bit line material layer, and the second barrier layer 313.

[0064] It should be noted that the average aperture of the channel hole is the average of the aperture values ​​measured at multiple measurement points at different depths of the channel hole. Specifically, in step S40, a clear morphological image of the channel hole 340 after wet cleaning can be obtained by scanning electron microscope (SEM) or transmission electron microscope (TEM), and then the aperture values ​​of multiple measurement points at the same or different depths of multiple channel holes 340 after wet cleaning are measured based on the image. A channel hole 340 can be set to have one measurement point at a fixed depth position, or a channel hole can be set to have one measurement point at multiple different depth positions, and then the average value is calculated based on the multiple aperture values ​​obtained by measurement, and the average value is also the average aperture of the channel hole 340 after wet cleaning. Further, based on the aperture values ​​measured at multiple measurement points at different depths of the channel hole, the average aperture of part of the channel holes located in the second oxide layer 320 and the average aperture of part of the channel holes located in the word line layer 310 can be further determined.

[0065] In this embodiment, the average pore size of the channel hole 340 after wet cleaning is controlled to be smaller than the target average pore size of the vertical channel hole, and the target average pore size of the vertical channel hole is also the average pore size of the vertical channel hole that needs to be finally prepared, so that the average pore size of the channel hole after cleaning can be subsequently etched to the target average pore size of the vertical channel hole through a wet etching process. Specifically, the target average pore size of the vertical channel hole needs to be 2% to 20% larger than the average pore size of the channel hole 340 after wet cleaning, that is, the target average pore size of the channel hole 340 after wet cleaning is d1, and the target average pore size of the vertical channel hole is d2, d2 = (1.02 to 1.2) × d1.

[0066] In the related art, the average aperture of the channel hole 340 after wet cleaning is usually controlled to directly reach the target average aperture of the vertical channel hole, that is, d1=d2±δ is controlled, where δ is the set error, that is, the allowable deviation between the actual value and the ideal target value. However, the aperture of the vertical channel hole is affected by photolithography, dry etching and wet cleaning, and there are many variables. The average aperture of the channel hole 340 after wet cleaning is difficult to stably reach the target average aperture of the vertical channel hole, and the fluctuation range of the aperture value measured at the measurement point is large.

[0067] In step S50, see the attached Figure 6 , 12 ( Fig.12 For attachment Figure 6 Based on the measured average pore size of the channel hole 340, the wet etching process parameters are determined, the channel hole 340 is wet-etched according to the wet etching process parameters to form the channel hole 350 after wet etching, and the average pore size of the channel hole 350 after wet etching is measured.

[0068] In this embodiment, the wet etching solution includes DHF solution and SPM (Sulfuric-Acid / Hydrogen-Peroxide Mixture) solution. The DHF solution is used to etch the second oxide layer 320 , and the SPM solution is used to etch the word line layer 310 .

[0069] The ratio (volume ratio) of water (deionized water) and hydrofluoric acid in the DHF solution used as a wet etching solution can be 100:1 to 2000:1. The DHF solution can effectively etch silicon oxide, and the reaction equation with silicon oxide is as follows:

[0070] SiO2+4HF→SiF4+2H2O

[0071] The SPM solution can etch tungsten and titanium nitride at the same time. The SPM solution can be formed by mixing sulfuric acid at 35°C to 65°C (preferably, 40°C to 55°C) and hydrogen peroxide at room temperature. The ratio (volume ratio) of sulfuric acid to hydrogen peroxide in the SPM solution can be 2:1 to 18:1, preferably, 4:1 to 12:1. The reaction equations of the SPM solution with tungsten and titanium nitride are as follows:

[0072] 2TiN+6H2SO4→2TiOSO4+4SO2+N2+6H2O

[0073] W+3H2O2→WO3+3H2O

[0074] WO3+6H + →W 6+ +3H2O

[0075] In some embodiments, the SPM solution further includes ammonium salt, and the addition of ammonium salt can react to generate ammonium persulfate ((NH4)2SO5). Ammonium persulfate is easily adsorbed on the tungsten surface, reducing the tungsten etching rate, and changing the etching selectivity of tungsten and titanium nitride. The specific reaction equation is as follows:

[0076] H2SO4+H2O2→H2SO5+H2

[0077] H2SO5+2NH4 + →(NH4)2SO5

[0078] In the present embodiment, the SPM solution is configured to have the same etching rate for titanium nitride and tungsten. Specifically, this can be achieved by adjusting the ratio of sulfuric acid and hydrogen peroxide in the SPM solution. In some embodiments, an appropriate amount of ammonium salt can also be added to the SPM solution in a specific ratio to change the etching selectivity of tungsten and titanium nitride, so that the SPM solution has the same etching rate for titanium nitride and tungsten. Thus, the entire word line layer 310 can be etched at the same etching rate by the SPM solution to form a relatively flat etched surface.

[0079] In this embodiment, the wet etching process parameters include etching time, and the steps of determining the wet etching process parameters include: designing the etching time of the DHF solution on the second oxide layer 320 and the etching time of the SPM solution on the word line layer 310 to coordinate, so that the inner wall of the second oxide layer 320 after etching is flush with the inner wall of the word line layer 310 after etching.

[0080] Specifically, before performing step S50, the etching data of different material layers involved in the channel hole (such as the etching amount at different times, etc.) can be obtained by experiment. In this embodiment, the channel hole penetrates the layer to be etched 300, and the material layers involved include silicon oxide layer, tungsten layer and titanium nitride layer. Therefore, the etching data of silicon oxide layer, tungsten layer and titanium nitride layer under different etching liquid compositions and different nozzle types can be obtained by experiment. It should be noted that the nozzle is also a scanning nozzle (Scan Nozzle), also known as a mobile nozzle, which is used to spray etching liquid to perform a wet etching process. It is well known that each etching machine has more than one type of nozzle, and the etching rate distribution diagram of each type of nozzle at different locations on the wafer is different. After the etching data is obtained, the corresponding relationship between the etching amount and the wet etching process parameters can be established, wherein the wet etching process parameters may include the composition of the etching liquid (such as the proportion of different components in the etching liquid, etc.), the etching time and the type of nozzle, etc.

[0081] Then, in step S50, the corresponding wet etching process parameters can be determined based on the average pore size of the portion of the channel holes located in the second oxide layer 320 and the average pore size of the portion of the channel holes located in the word line layer 310. Specifically, the difference between the average pore size of the portion of the channel holes located in the second oxide layer 320 and the target average pore size can be determined, and the difference is the etching amount corresponding to the portion of the channel holes located in the second oxide layer 320. Then, the wet etching process parameters of the second oxide layer 320 are determined according to the corresponding relationship between the etching amount and the wet etching process parameters. The number, that is, the etching time of the second oxide layer 320 with the DHF solution of a specific ratio is determined; at the same time, the difference between the average pore size of some channel holes located in the word line layer 310 and the target average pore size can be determined, and the difference is the etching amount corresponding to the part of the channel holes located in the word line layer 310. Then, according to the corresponding relationship between the etching amount and the wet etching process parameters, the wet etching process parameters of the word line layer 310 are determined, that is, the etching time of the word line layer 310 with the SPM solution of a specific ratio (the ratio of water to hydrofluoric acid can be 100:1 to 2000:1) is determined. Based on the determined specific ratio (the ratio of sulfuric acid to hydrogen peroxide can be 2:1 to 18:1) of DHF solution for etching the second oxide layer 320 and the specific ratio of SPM solution for etching the word line layer 310, the specific ratio of DHF solution and the specific ratio of SPM solution are respectively used to wet etch the second oxide layer 320 and the word line layer 310 based on the determined etching time to form the wet-etched channel hole 350. In theory, the inner wall of the second oxide layer 320 after etching and the inner wall of the word line layer 310 after etching can be flush, and the average pore size of the wet-etched channel hole 350 reaches the target pore size. Thereby, the fluctuation of the pore size of the channel hole can be significantly reduced, and the uniformity of the pore size can be improved.

[0082] After the channel hole 350 is formed after wet etching, a clear morphological image of the channel hole 350 after wet etching can be obtained by a scanning electron microscope (SEM) or a transmission electron microscope (TEM), and then the aperture values ​​of multiple measurement points at different depths of the channel hole 350 after wet etching are measured based on the image, and then the average value is calculated based on the multiple aperture values ​​obtained by measurement, and the average value is also the average aperture of the entire channel hole after wet etching.

[0083] It should be noted that when measuring the apertures of multiple channel holes, the height position of the measuring point in the direction perpendicular to the substrate 100 when measuring each channel hole can be controlled to be the same, so as to ensure the consistency of measurement and the accuracy of the final average aperture. That is, whether the aperture of the channel hole is measured after wet cleaning or after each wet cleaning, the height position of the measuring points of the multiple channel holes in the direction perpendicular to the substrate 100 when measuring is the same.

[0084] In some other embodiments, the etching time may be fixed, and the wet etching process parameters include the composition of the etching solution (e.g., the ratio of different components in the etching solution), and different etching solutions have different corresponding etching rates. The step of determining the wet etching process parameters may include: designing the composition of the DHF solution and the composition of the SPM solution to achieve that the inner wall of the second oxide layer 320 after etching is flush with the inner wall of the word line layer 310 after etching.

[0085] In some other embodiments, the etching time and the composition of the etching solution may be fixed, and the wet etching process parameters include the type of nozzle. Different nozzle types correspond to different etching rates. Wet Etching Process Parameters The step of determining the wet etching process parameters may include: designing the type of nozzle for spraying the DHF solution and the type of nozzle for spraying the SPM solution to achieve that the inner wall of the second oxide layer 320 after etching is flush with the inner wall of the word line layer 310 after etching.

[0086] In step S60, it is determined whether the average aperture of the measured channel hole is less than the set aperture lower limit. The set aperture lower limit = d2-δ, wherein d2 is the target average aperture of the vertical channel hole, and δ is the set error, that is, the allowable deviation between the actual value and the ideal target value, which is usually difficult to avoid due to the existence of process accuracy, measurement errors, etc. Exemplarily, δ can be 1nm or other suitable values. That is, it is determined whether the average aperture of the measured channel hole is less than d2-δ. If so, it means that the difference between the average aperture of the measured channel hole and the set aperture lower limit is greater than the set error, and the average aperture of the channel hole does not meet the design requirements; if not, it means that the difference between the average aperture of the measured channel hole and the set aperture lower limit is less than or equal to the set error, and the average aperture of the channel hole meets the design requirements. At this time, the preparation of the vertical channel hole is completed.

[0087] When the measured average pore size of the channel hole is less than the set pore size lower limit (that is, when it is judged as yes), repeat step 50 and step S60 until the average pore size of the channel hole measured after wet etching again is not less than the set pore size lower limit, so as to complete the preparation of the vertical channel hole. It should be noted that when repeating step S50, it is necessary to determine the wet etching process parameters based on the average pore size of the channel hole measured after the previous wet etching, and then wet-etch the channel hole after the previous wet etching again according to the wet etching process parameters to form the channel hole after the second wet etching, and measure the average pore size of the channel hole after the second wet etching. The specific process can be referred to the previous description, and will not be repeated here.

[0088] In this embodiment, the aperture compensation of the channel hole 340 after wet cleaning can be effectively adjusted to the target aperture through steps S50 and S60, thereby improving the dimensional stability of the aperture of the channel hole.

[0089] Exemplarily, in step S60, when the average pore size of the measured channel hole is greater than or equal to the set pore size lower limit value (that is, when it is determined to be no), it can be further determined whether the pore sizes of the multiple measurement points measured meet the 3σ principle, that is, the probability that the pore size values ​​measured at the multiple measurement points at different depths of the channel hole are distributed in (μ-3σ, μ+3σ) is greater than or equal to 0.9974, where μ is the average value of the multiple pore size values ​​measured, and σ is the standard deviation of the multiple pore size values ​​measured. When the pore size of the multiple measurement points measured meets the 3σ principle, it means that the preparation quality of the channel hole meets the requirements, and the channel hole size uniformity is good with small fluctuations. At this time, refer to the attached Figure 7 , 13 (Attached Fig.13 For attachment Figure 7), a gate dielectric layer 700 is deposited. Specifically, the inner surface of the channel hole may be pre-cleaned first, and then a gate dielectric layer 700 is formed on the inner surface of the channel hole and the upper surface of the second oxide layer 320 by a deposition process such as a CVD process. The gate dielectric layer 700 includes but is not limited to one or more of a silicon nitride layer, a silicon oxide layer, and a high-k value material layer. The material of the high-k value material layer may be HfO x ,AlO x wait.

[0090] Since the prepared channel holes have good size uniformity and small fluctuation, the formation quality of the gate dielectric layer 700 can be effectively improved.

[0091] So far, the introduction of the relevant steps of the method for preparing the vertical channel hole of the embodiment of the present application has been completed. After the above steps, other conventional steps for making the vertical channel hole may also be included, which will not be repeated here. In addition, in addition to the above steps, the preparation method of this embodiment may also include other steps in the above steps or between different steps, and these steps can be implemented by various processes in the prior art, which will not be repeated here.

[0092] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0093] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0095] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0096] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0097] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0098] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0099] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for preparing a vertical channel hole, characterized in that: The following steps are involved: S10: providing a semiconductor structure, wherein the semiconductor structure comprises an etch stop layer and a layer to be etched which are sequentially stacked on a substrate; S20: forming a patterned mask layer on the semiconductor structure by using a photolithography process; S30: using the patterned mask layer as a mask, forming an initial channel hole vertically penetrating the layer to be etched by a dry etching process, wherein the cross section of the initial channel hole is circular; S40: wet-cleaning the initial channel hole to form a wet-cleaned channel hole and measuring the average pore size of the wet-cleaned channel hole; wherein the target average pore size of the wet-cleaned channel hole is d1, and the target average pore size of the vertical channel hole is d2, d2=(1.02-1.2)×d1; S50: determining wet etching process parameters based on the measured average pore size of the channel holes, wet etching the channel holes according to the wet etching process parameters to form wet-etched channel holes, and measuring the average pore size of the wet-etched channel holes; S60: Determine whether the average pore size of the measured channel hole is less than the set pore size lower limit; if so, repeat step 50 and step S60 until the average pore size of the channel hole measured after wet etching again is not less than the set pore size lower limit, so as to complete the preparation of the vertical channel hole.

2. The preparation method according to claim 1, characterized in that: The set aperture lower limit value = d2 - δ, where δ is the set error.

3. The preparation method according to claim 1, characterized in that: The wet etching process parameters include one or more of the composition of the etching solution, the etching time and the type of the nozzle; Wherein, the nozzle is used for spraying etching liquid.

4. The preparation method according to claim 1, characterized in that: When measuring the aperture of the channel hole, the height position of the measuring point in the direction perpendicular to the substrate is controlled to be the same during each measurement.

5. The preparation method according to claim 1, characterized in that: The etching stop layer comprises a first oxide layer, and the layer to be etched comprises a word line layer and a second oxide layer sequentially stacked on the first oxide layer; The word line layer includes a plurality of word lines arranged at intervals, and two adjacent word lines are insulated from each other by insulating materials; The semiconductor structure further includes a bit line layer, the bit line layer is arranged between the substrate and the first oxide layer, the bit line layer includes a plurality of bit lines arranged at intervals, and two adjacent bit lines are insulated from each other by an insulating material; The word lines and the bit lines extend in directions that intersect with each other, and the word lines and the bit lines extend in directions that are parallel to the substrate.

6. The preparation method according to claim 5, characterized in that: The word line includes a word line material layer and a first barrier layer and a second barrier layer located at two sides of the word line material layer along a direction perpendicular to the substrate.

7. The preparation method according to claim 6, characterized in that: The first barrier layer and the second barrier layer are made of titanium nitride, the word line material layer is made of tungsten, and the first oxide layer and the second oxide layer are both made of silicon oxide.

8. The preparation method according to claim 7, characterized in that: The cleaning solution for wet cleaning includes one or more of DHF solution, DAM solution, DSP+ solution and organic solution cleaning solution.

9. The preparation method according to claim 7, characterized in that: The wet etching solution includes a DHF solution and an SPM solution, wherein the DHF solution is used to etch the second oxide layer, and the SPM solution is used to etch the word line layer; The ratio of water to hydrofluoric acid in the DHF solution is 100:1 to 2000:1; The ratio of sulfuric acid to hydrogen peroxide in the SPM solution is 2:1 to 18:

1.

10. The preparation method according to claim 9, characterized in that: The SPM solution also includes ammonium salt.

11. The preparation method according to claim 9, characterized in that: The SPM solution is configured to have the same etching rate for titanium nitride and tungsten; The step of determining the wet etching process parameters includes: designing the etching time of the second oxide layer by the DHF solution and the etching time of the word line layer by the SPM solution to coordinate so as to achieve that the inner wall of the second oxide layer after etching is flush with the inner wall of the word line layer after etching.

Images