A method for manufacturing a vertical channel hole

Abstract

The application discloses a preparation method of a vertical channel hole, which comprises the following steps: S10, providing a semiconductor structure comprising an etching stop layer and a layer to be etched; S20, forming a patterned mask layer on the semiconductor structure by using a photolithography process; S30, forming an initial channel hole penetrating through the layer to be etched by using a dry etching process with the patterned mask layer as a mask; S40, wet cleaning the initial channel hole, and measuring an average pore diameter of the channel hole after the wet cleaning; S50, determining a wet etching process parameter based on the average pore diameter, wet etching the channel hole, and measuring an average pore diameter of the channel hole after the wet etching; S60, judging whether the measured average pore diameter of the channel hole is smaller than a set lower limit value of the pore diameter; if yes, repeating the step 50 and the step S60 until the measured average pore diameter of the channel hole after the wet etching is not smaller than the set lower limit value of the pore diameter. The preparation method can significantly improve the stability of the pore diameter of the channel hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a vertical channel hole. BACKGROUND

[0002] According to Moore's law, integrated circuits are developing towards more and more fine dimensions, when the DRAM technology exceeds 1z node and above, the continuous reduction of the 6F2 fin field effect transistor structure will face great challenges in device performance and process development, and researchers have proposed a new generation of DRAM memory transistor architecture, i.e. 4F2 VCT (Vertical Channel Transistor).

[0003] At present, for the vertical channel hole of the vertical channel transistor, the initial channel hole is usually formed by a photolithography and dry etching process during preparation, and then the inner surface of the initial channel hole is subjected to wet cleaning to form a vertical channel hole with a specific pore size.

[0004] For the above preparation process, the pore size of the vertical channel hole is affected by photolithography, dry etching and wet cleaning, there are many variables, the fluctuation is large, and the size stability of the pore size is poor.

[0005] Therefore, it is necessary to improve the preparation process of the vertical channel hole to at least partially solve the above problems. SUMMARY

[0006] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and essential technical features of the claimed technical solution, nor to attempt to determine the protection scope of the claimed technical solution.

[0007] In order to at least partially solve the above problems, the present application provides a preparation method of a vertical channel hole, comprising the following steps:

[0008] S10: providing a semiconductor structure, the semiconductor structure comprising an etching stop layer and a to-be-etched layer which are stacked in sequence on a substrate;

[0009] S20: forming a patterned mask layer on the semiconductor structure by a photolithography process;

[0010] S30: forming an initial channel hole vertically penetrating through the to-be-etched layer by a dry etching process with the patterned mask layer as a mask, the cross section of the initial channel hole being circular;

[0011] S40: performing a wet cleaning on the initial channel hole to form a wet cleaned channel hole and measuring an average diameter of the wet cleaned channel hole;

[0012] S50: determining a wet etching process parameter based on the measured average diameter of the channel hole, performing a wet etching on the channel hole according to the wet etching process parameter to form a wet etched channel hole, and measuring an average diameter of the wet etched channel hole;

[0013] S60: determining whether the measured average diameter of the channel hole is less than a set lower limit of the diameter; if yes, repeating the step 50 and the step S60 until the measured average diameter of the channel hole after the re-wet etching is not less than the set lower limit of the diameter to complete the preparation of the vertical channel hole.

[0014] Exemplarily, the set lower limit of the diameter = d2-δ, wherein δ is a set error.

[0015] Exemplarily, the wet etching process parameter includes one or more of a composition of an etching solution, an etching time, and a type of a nozzle;

[0016] The nozzle is used for spraying the etching solution.

[0017] Exemplarily, when measuring the diameter of the channel hole, the height position of a measuring point in a direction perpendicular to the substrate is controlled to be the same each time.

[0018] Exemplarily, the etching stop layer includes a first oxide layer, and the layer to be etched includes a word line layer and a second oxide layer which are sequentially stacked on the first oxide layer.

[0019] The word line layer includes a plurality of word lines arranged at intervals, and adjacent two word lines are arranged to be insulated from each other by an insulating material.

[0020] The semiconductor structure further includes a bit line layer, the bit line layer is arranged between the substrate and the first oxide layer, and the bit line layer includes a plurality of bit lines arranged at intervals, and adjacent two bit lines are arranged to be insulated from each other by an insulating material.

[0021] The extension directions of the word lines and the bit lines intersect, and the extension directions of the word lines and the bit lines are both parallel to the substrate.

[0022] Exemplarily, the word line includes a word line material layer and first and second barrier layers located on both sides of the word line material layer in a direction perpendicular to the substrate.

[0023] Exemplarily, the first barrier layer and the second barrier layer are made of titanium nitride, the word line material layer is made of tungsten, and the first oxide layer and the second oxide layer are both made of silicon oxide.

[0024] Exemplarily, the cleaning solution for the wet cleaning includes one or more of a DHF solution, a DAM solution, a DSP+ solution, and an organic solution cleaning solution.

[0025] Exemplarily, the etching solution for the wet etching includes a DHF solution and an SPM solution, the DHF solution is used to etch the second oxide layer, and the SPM solution is used to etch the word line layer.

[0026] The ratio of water to hydrofluoric acid in the DHF solution is 100:1-2000:1.

[0027] The ratio of sulfuric acid to hydrogen peroxide in the SPM solution is 2:1-18:1.

[0028] Exemplarily, the SPM solution further includes an ammonium salt.

[0029] Exemplarily, the SPM solution is configured to have the same etching rate for titanium nitride and tungsten.

[0030] The step of determining the wet etching process parameters includes designing the etching time of the DHF solution on the second oxide layer and the etching time of the SPM solution on the word line layer to match, so as to realize that the inner wall of the second oxide layer after etching and the inner wall of the word line layer after etching are flush.

[0031] According to the preparation method of the vertical channel hole, the average pore diameter of the channel hole after the wet cleaning is measured after the wet cleaning, the wet etching process parameters are determined based on the measured average pore diameter of the channel hole, and the wet etching is performed on the channel hole based on the wet etching process parameters until the measured average pore diameter of the channel hole after the wet etching is not less than the set lower limit value of the pore diameter, so that the pore diameter of the channel hole after the wet cleaning can be effectively compensated and adjusted to the target pore diameter through the wet etching process, and the size stability of the channel hole pore diameter is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] The following drawings of the present application are hereby incorporated into the present application as part of the present application for the purpose of understanding the present application. The embodiments of the present application and their description shown in the drawings are used to explain the devices and principles of the present application. In the drawings,

[0033] Figure 1 FIG. 1 is a flowchart of a preparation method of a vertical channel hole according to an embodiment of the present application;

[0034] Figures 2-7Fig. 1 is a top view of a device during a step of a method of fabricating a vertical channel hole according to an embodiment of the present application;

[0035] Figures 8-13 respectively, Figures 2-7 Fig. 2 is a cross-sectional view of the device at A-A in Fig. 1.

[0036] Reference Signs List:

[0037] 100 - substrate, 200 - etch stop layer, 300 - layer to be etched, 310 - word line layer, 311 - word line material layer, 312 - first barrier layer, 313 - second barrier layer, 320 - second oxide layer, 330 - initial channel hole, 340 - channel hole after wet clean, 350 - channel hole after wet etch, 400 - insulating material, 500 - bit line layer, 600 - patterned mask layer, 610 - amorphous carbon layer, 620 - dielectric anti-reflective coating, 620 - bottom anti-reflective coating, 640 - photoresist layer, 700 - gate dielectric layer. DETAILED DESCRIPTION

[0038] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application.

[0039] It should be understood that the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. Like numbers refer to like elements throughout.

[0040] It should be understood that, although a term "first", "second", "third", etc., can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, "first element", "second element", "third element", etc., discussed below can represent one element, component, region, layer or section or a combination thereof.

[0041] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over in use, a downward relative term can become an upward relative term, due to the force of gravity. The device can be oriented in any direction, and terms such as "front", "back", "left", "right", "top", "bottom" and the like can be used to describe the device as oriented in one conformation.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of the regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0044] Reference is made to the drawings of the accompanying Figures 1-13 A method for manufacturing a vertical channel hole according to an embodiment of the present application is exemplarily described. Referring to the drawings of the accompanying Figure 1 The method comprises the following steps:

[0045] S10: providing a semiconductor structure, the semiconductor structure comprising an etching stop layer 200 and a to-be-etched layer which are sequentially stacked on a substrate;

[0046] S20: forming a patterned mask layer on the semiconductor structure by using a photolithography process;

[0047] S30: forming an initial channel hole vertically penetrating through the to-be-etched layer by using a dry etching process with the patterned mask layer as a mask, the initial channel hole having a circular cross section;

[0048] S40: performing a wet cleaning on the initial channel hole to form a wet-cleaned channel hole and measuring an average pore diameter of the wet-cleaned channel hole; wherein a target average pore diameter of the wet-cleaned channel hole is d1, a target average pore diameter of the vertical channel hole is d2, and d2 = (1.02-1.2) x d1.

[0049] S50: Based on the average aperture of the channel hole obtained by measurement, determine the wet etching process parameters, perform wet etching on the channel hole according to the wet etching process parameters to form the wet-etched channel hole, and measure the average aperture of the wet-etched channel hole.

[0050] S60: Determine whether the average diameter of the measured channel holes is less than the set lower limit value. If so, repeat steps 50 and S60 until the average diameter of the channel holes measured after the second wet etching is not less than the set lower limit value, so as to complete the preparation of the vertical channel holes.

[0051] According to the method for preparing vertical channel holes of the present invention, after wet cleaning, the average aperture of the channel holes after wet cleaning is measured. Based on the measured average aperture of the channel holes, wet etching process parameters are determined, and the channel holes are wet etched based on the wet etching process parameters until the average aperture of the channel holes measured after wet etching is not less than the set lower limit value of the aperture. The aperture compensation of the channel holes after wet cleaning can be effectively adjusted to the target aperture through the wet etching process, thereby improving the dimensional stability of the channel hole aperture.

[0052] The following will refer to the appendix. Figures 2-13 The steps of a method for preparing a vertical channel hole according to an embodiment of this application will be described in detail.

[0053] In step S10, see Appendix Figure 2 , 8 (Appendix) Figure 8 For the appendix Figure 2 (Cross-sectional view at point AA) provides a semiconductor structure, which includes a bit line layer 500, an etch stop layer 200 and an etchable layer 300 sequentially stacked on a substrate.

[0054] The substrate 100 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a germanium-silicon (GeSi) substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs).

[0055] Bit line layer 500 is disposed between substrate and etch stop layer 200. Bit line layer 500 includes a plurality of spaced-apart bit lines, and adjacent bit lines are insulated from each other by an insulating material. For example, the bit lines can be made of polysilicon or tungsten, and the insulating material can be silicon oxide.

[0056] The etch stop layer 200 includes a first oxide layer, and the etch layer 300 includes a word line layer 310 and a second oxide layer 320 sequentially stacked on the first oxide layer. The word line layer 310 includes a plurality of spaced word lines, and adjacent word lines are insulated from each other by an insulating material 400.

[0057] In this embodiment, the word line includes a word line material layer 311 and a first barrier layer 312 and a second barrier layer 313 located on both sides of the word line material layer 311 along a direction perpendicular to the substrate. The first barrier layer 312 is located between the word line material layer 311 and the first oxide layer, and the second barrier layer 313 is located between the word line material layer 311 and the second oxide layer 320. The first barrier layer 312 and the second barrier layer 313 are used to prevent the diffusion of the word line material layer 311, thereby improving the stability and reliability of the overall structure.

[0058] In this embodiment, the first barrier layer 312 and the second barrier layer 313 are made of titanium nitride, the word line material layer 311 is made of tungsten, and the first oxide layer and the second oxide layer 320 are both made of silicon oxide.

[0059] The extension directions of the word lines and bit lines intersect, and both extension directions are parallel to the substrate. In this embodiment, the extension direction of the word lines is... Figure 2 The vertical direction in the middle, the extension direction of the bit line is Figure 2 In the left-right direction, the extension directions of word lines and bit lines intersect perpendicularly. In other embodiments, the extension directions of word lines and bit lines intersect at a certain angle, ranging from 0° to 90°. The overlapping projections of each word line and each bit line on the substrate at least partially coincide with the projections of the corresponding transistors on the substrate, meaning that selecting one word line and one bit line selects one transistor.

[0060] In step S20, see Appendix Figure 3 , 9 (Appendix) Figure 9 For the appendix Figure 3 (Cross-sectional view at point AA), a patterned mask layer 600 is formed on the semiconductor structure using photolithography.

[0061] In the embodiment, the patterned mask layer can include a patterned amorphous carbon layer 610 on the second oxide layer 320, a patterned dielectric anti-reflective coating (DARC) layer 620 on the amorphous carbon layer 610, a patterned bottom anti-reflective coating (BARC) layer 630 on the DARC layer 620, and a patterned photoresist layer 640 on the BARC layer 630. Specifically, the amorphous carbon layer, the DARC layer, the BARC layer, and the photoresist layer can be formed on the second oxide layer 320 layer by layer, and then the photoresist layer is patterned by a photoetching process including pre-baking, exposure, development, and hardening to form the patterned photoresist layer 640. Then, the patterned photoresist layer 640 is used as a mask to etch the amorphous carbon layer, the DARC layer, and the BARC layer to form the patterned amorphous carbon layer 610, the patterned DARC layer 620, and the patterned BARC layer 630.

[0062] In step S30, referring to FIG. 4, Figure 4 、 10 ( Figure 10 In step S30, referring to FIG. 4, Figure 4 In step S30, referring to FIG. 4,

[0063] In step S40, referring to FIG. 5, Figure 5 、 11 ( Figure 11 In step S40, referring to FIG. 5, Figure 5The initial trench holes 330 are wet cleaned to form wet cleaned trench holes 340 and the average diameter of the wet cleaned trench holes 340 is measured. The wet cleaning can effectively remove various residues generated in the dry etching process. For example, the cleaning solution used in the wet cleaning can include one or more of a DHF (Diluted Hydrofluoric Acid) solution, a DAM (Diluted Ammonia Mixture) solution, a DSP+ (Diluted Sulfuric Acid / Hydrogen Peroxide Mixture) solution, and an organic solution cleaning solution. For example, the ratio (volume ratio) of water (deionized water) to hydrofluoric acid in the DHF solution used as the cleaning solution can be 100:1 to 2000:1, the ratio (volume ratio) of water to ammonia in the DAM solution can be 50:1 to 500:1, and the organic solution cleaning solution can include ST250, NE111, SST-A47, and other cleaning solutions known to those skilled in the art. It should be noted that the cleaning solution used in the wet cleaning will etch the inner surface of the trench holes to some extent, resulting in uneven inner surfaces of the trench holes and fluctuations in the diameter of the trench holes. For example, the DHF solution can etch the inner surface of some of the trench holes located in the first oxide layer and the second oxide layer 320 to some extent, the DSP+ solution can etch the inner surface of some of the trench holes located in the first blocking layer 312, the bit line material layer, and the second blocking layer 313 to some extent, and so on.

[0064] It should be noted that the average diameter of the trench holes is the average of the diameter values measured at multiple measurement points at different depths of the trench holes. Specifically, in step S40, a clear topographic image of the wet cleaned trench holes 340 can be obtained by a scanning electron microscope (SEM) or a transmission electron microscope (TEM), and then the diameter values of multiple measurement points at the same or different depths of the wet cleaned trench holes 340 are measured based on the image. One measurement point can be set at a fixed depth of one trench hole 340, or one measurement point can be set at multiple different depths of one trench hole. Then, the average value of the multiple measured diameter values is calculated, which is the average diameter of the wet cleaned trench holes 340. Further, based on the diameter values measured at multiple measurement points at different depths of the trench holes, the average diameter of some of the trench holes located in the second oxide layer 320 and the average diameter of some of the trench holes located in the word line layer 310 can be further determined.

[0065] In this embodiment, the average aperture of the channel hole 340 after wet cleaning is controlled to be smaller than the target average aperture of the vertical channel hole. The target average aperture of the vertical channel hole is also the average aperture of the vertical channel hole that needs to be finally prepared, so that the average aperture of the cleaned channel hole can be etched to the target average aperture of the vertical channel hole through a subsequent wet etching process. Specifically, the target average aperture of the vertical channel hole needs to be 2% to 20% larger than the average aperture of the channel hole 340 after wet cleaning. That is, the target average aperture of the channel hole 340 after wet cleaning is d1, and the target average aperture of the vertical channel hole is d2, where d2 = (1.02 to 1.2) × d1.

[0066] In related technologies, the average aperture of the channel hole 340 after wet cleaning is typically controlled to directly reach the target average aperture of the vertical channel hole. That is, d1 = d2 ± δ is controlled, where δ is the set error, i.e., the allowable deviation between the actual value and the ideal target value. However, the aperture of the vertical channel hole is affected by photolithography, dry etching, and wet cleaning, resulting in many variables. The average aperture of the channel hole 340 after wet cleaning is difficult to stably reach the target average aperture of the vertical channel hole, and the aperture value measured at the measurement point fluctuates within a large range.

[0067] In step S50, see Appendix Figure 6 , 12 ( Figure 12 For the appendix Figure 6 (Cross-sectional view at AA in the middle), based on the average aperture of the channel hole 340 obtained by measurement, the wet etching process parameters are determined, and the channel hole 340 is wet etched according to the wet etching process parameters to form the wet etched channel hole 350, and the average aperture of the wet etched channel hole 350 is measured.

[0068] In this embodiment, the wet etching solution includes a DHF solution and an SPM (Sulfuric-Acid / Hydrogen-Peroxide Mixture) solution. The DHF solution is used to etch the second oxide layer 320, and the SPM solution is used to etch the word line layer 310.

[0069] The ratio (by volume) of water (deionized water) to hydrofluoric acid in the DHF solution used as a wet etching solution can be from 100:1 to 2000:1. DHF solution can effectively etch silicon oxide, and its reaction equation with silicon oxide is as follows:

[0070] SiO2 + 4HF → SiF4 + 2H2O

[0071] The SPM solution can etch both tungsten and titanium nitride. The SPM solution can be formed by mixing sulfuric acid at 35-65°C (preferably, 40-55°C) and hydrogen peroxide at room temperature, and the ratio (volume ratio) of sulfuric acid to hydrogen peroxide in the SPM solution can be 2:1-18:1, and preferably, 4:1-12:1. The reaction equations of the SPM solution with tungsten and titanium nitride are as follows:

[0072] 2TiN + 6H2SO4→ 2TiOSO4+ 4SO2+ N2+ 6H2O

[0073] W + 3H2O2→ WO3+ 3H2O

[0074] WO3+ 6H2O2→ WO4+ 3H2O + → W 6+ + 3H2O

[0075] In some embodiments, the SPM solution further includes ammonium salt, and the addition of ammonium salt can react to generate ammonium persulfate ((NH4)2SO5), which is easy to be adsorbed on the surface of tungsten, thereby reducing the etching rate of tungsten and changing the etching selectivity ratio of tungsten and titanium nitride. The specific reaction equation is as follows:

[0076] H2SO4+ H2O2→ H2SO5+ H2

[0077] H2SO5+ 2NH4+ → (NH4)2SO5 +

[0078] In this embodiment, the SPM solution is configured to have the same etching rate for titanium nitride and tungsten. Specifically, the ratio of sulfuric acid to hydrogen peroxide in the SPM solution can be adjusted to achieve this. In some embodiments, an appropriate amount of ammonium salt can also be added to the SPM solution with a specific ratio to change the etching selectivity ratio of tungsten and titanium nitride, so that the SPM solution has the same etching rate for titanium nitride and tungsten. Thus, the entire word line layer 310 can be etched at the same etching rate by the SPM solution to form a relatively flat etched surface.

[0079] In this embodiment, the wet etching process parameters include etching time, and the step of determining the wet etching process parameters includes: designing the etching time of the DHF solution on the second oxide layer 320 and the etching time of the SPM solution on the word line layer 310 to match each other, so that the inner wall of the second oxide layer 320 after etching is flush with the inner wall of the word line layer 310 after etching.

[0080] ​Specifically, before step S50, etching data of different material layers involved in the trench hole can be obtained by experiments, for example, etching amount at different times, etc. In the embodiment, the trench hole penetrates the to-be-etched layer 300, and the material layers involved include the silicon oxide layer, the tungsten layer, and the titanium nitride layer. Therefore, etching data of the silicon oxide layer, the tungsten layer, and the titanium nitride layer under different compositions of etching liquid and different types of nozzles can be obtained by experiments. It should be noted that the nozzle, also known as a scan nozzle, is also called a movable nozzle, which is used to spray etching liquid to perform a wet etching process. It is well known that there is not only one type of nozzle for each etching machine, and the etching rate distribution map of each type of nozzle is different at different places on the wafer. After obtaining the etching data, a corresponding relationship between the etching amount and the wet etching process parameters can be established, wherein the wet etching process parameters can include the composition of the etching liquid (for example, the proportion of different components in the etching liquid), the etching time, and the type of nozzle, etc.

[0081] Then, in step S50, based on the average pore diameter of the partial trench holes in the second oxide layer 320 and the average pore diameter of the partial trench holes in the word line layer 310, the corresponding wet etching process parameters can be determined respectively. Specifically, the difference between the average pore diameter of the partial trench holes in the second oxide layer 320 and the target average pore diameter can be determined, which is the etching amount corresponding to the partial trench holes in the second oxide layer 320, and then the wet etching process parameters of the second oxide layer 320 are determined according to the corresponding relationship between the etching amount and the wet etching process parameters, that is, the etching time of the DHF solution with a specific proportion on the second oxide layer 320 is determined; at the same time, the difference between the average pore diameter of the partial trench holes in the word line layer 310 and the target average pore diameter can be determined, which is the etching amount corresponding to the partial trench holes in the word line layer 310, and then the wet etching process parameters of the word line layer 310 are determined according to the corresponding relationship between the etching amount and the wet etching process parameters, that is, the etching time of the SPM solution with a specific proportion (the proportion of water and hydrofluoric acid can be 100:1-2000:1) on the word line layer 310 is determined. Based on the determined etching time of the DHF solution with a specific proportion (the proportion of sulfuric acid and hydrogen peroxide can be 2:1-18:1) on the second oxide layer 320 and the etching time of the SPM solution with a specific proportion on the word line layer 310, the second oxide layer 320 and the word line layer 310 are subjected to wet etching respectively by using the DHF solution with a specific proportion and the SPM solution with a specific proportion based on the determined etching time, to form the wet-etched trench hole 350. In theory, the inner wall of the second oxide layer 320 after etching and the inner wall of the word line layer 310 after etching can be flush, and the average pore diameter of the wet-etched trench hole 350 can reach the target pore diameter. Therefore, the fluctuation of the trench hole diameter can be significantly reduced, and the uniformity of the pore size can be improved.

[0082] After the formation of the channel holes 350 after wet etching, a clear topographic image of the channel holes 350 after wet etching can be obtained by scanning electron microscopy (SEM) or transmission electron microscopy (TEM), and then the aperture values of multiple measurement points at different depths of the channel holes 350 after wet etching are measured based on the image, and then the average value is calculated based on the multiple aperture values obtained by measurement, which is the average aperture of the entire channel hole after wet etching.

[0083] It should be noted that when measuring the aperture of multiple channel holes, the height position of the measurement point of each channel hole during measurement in the direction perpendicular to the substrate 100 can be controlled to be the same to ensure the consistency of the measurement and the accuracy of the final average aperture. That is, whether the aperture of the channel hole is measured after wet cleaning or the aperture of the channel hole is measured after each wet cleaning, the height position of the measurement point of the multiple channel holes during measurement in the direction perpendicular to the substrate 100 is the same.

[0084] In some other embodiments, the etching time can be fixed, and the wet etching process parameters include the composition of the etching solution (for example, the ratio of different components in the etching solution), and the etching rate is different corresponding to different etching solution compositions. The step of determining the wet etching process parameters can include: designing the composition of the DHF solution and the composition of the SPM solution to match, so that the inner wall after etching of the second oxide layer 320 and the inner wall after etching of the word line layer 310 are flush.

[0085] In some other embodiments, the etching time and the composition of the etching solution can be fixed, and the wet etching process parameters include the type of the nozzle. The etching rate is different corresponding to different types of nozzles. The step of determining the wet etching process parameters by the wet etching process parameters can include: designing the type of the nozzle for spraying the DHF solution and the type of the nozzle for spraying the SPM solution to match, so that the inner wall after etching of the second oxide layer 320 and the inner wall after etching of the word line layer 310 are flush.

[0086] In step S60, it is judged whether the average diameter of the measured channel hole is less than the set lower limit of the hole diameter. The set lower limit of the hole diameter is d2-δ, where d2 is the target average diameter of the vertical channel hole, and δ is a set error, i.e., an allowable deviation between an actual value and an ideal target value, which is usually difficult to avoid due to process precision, measurement error, etc. For example, δ can be 1 nm or other suitable values. That is, it is judged whether the average diameter of the measured channel hole is less than d2-δ. If yes, it indicates that the difference between the average diameter of the measured channel hole and the set lower limit of the hole diameter is greater than the set error, and the average diameter of the channel hole does not meet the design requirement. If no, it indicates that the difference between the average diameter of the measured channel hole and the set lower limit of the hole diameter is less than or equal to the set error, and the average diameter of the channel hole meets the design requirement. In this case, the preparation of the vertical channel hole is completed.

[0087] When the average diameter of the measured channel hole is less than the set lower limit of the hole diameter (i.e., the judgment is yes), steps S50 and S60 are repeated until the average diameter of the channel hole measured after the wet etching again is not less than the set lower limit of the hole diameter, so as to complete the preparation of the vertical channel hole. It should be noted that when step S50 is repeated, the wet etching process parameters are determined based on the average diameter of the channel hole measured after the previous wet etching, and then the wet etching is performed again on the channel hole after the previous wet etching according to the wet etching process parameters, to form the channel hole after the wet etching again, and the average diameter of the channel hole after the wet etching again is measured. The specific process can be referred to the foregoing description, which will not be repeated here.

[0088] The embodiment can effectively adjust the hole diameter of the channel hole 340 after the wet cleaning to the target hole diameter through steps S50 and S60, and improve the size stability of the channel hole diameter.

[0089] For example, in step S60, when the average diameter of the measured channel hole is greater than or equal to the set lower limit of the hole diameter (i.e., the judgment is no), it can be further judged whether the diameters of the plurality of measurement points measured satisfy the 3σ principle, i.e., the probability that the diameters of the plurality of measurement points at different depths of the channel hole are distributed in (μ-3σ, μ+3σ) is greater than or equal to 0.9974, where μ is the average value of the plurality of measured diameters, and σ is the standard deviation of the plurality of measured diameters. When the diameters of the plurality of measurement points measured satisfy the 3σ principle, it indicates that the preparation quality of the channel hole meets the requirements, and the channel hole has good size uniformity and small fluctuation. In this case, referring to FIG. 4, the diameters of the plurality of measurement points at different depths of the channel hole are measured, and the diameters of the plurality of measurement points are distributed in (μ-3σ, μ+3σ). For example, the diameters of the plurality of measurement points are measured by the AFM, and the diameters of the plurality of measurement points are distributed in (μ-3σ, μ+3σ). Figure 7 、 13 (Attachment 1) Figure 13 (Attachment 2) Figure 7A-A) is performed. Specifically, a pre-cleaning can be performed on the inner surface of the channel hole, and then a deposition process such as a CVD process is performed to form the gate dielectric layer 700 on the inner surface of the channel hole and the upper surface of the second oxide layer 320 as a whole. The gate dielectric layer 700 includes, but is not limited to, one or more of a silicon nitride layer, a silicon oxide layer, and a high-k material layer, and the high-k material layer can be HfO x , AlO x , etc.

[0090] Since the prepared channel hole has good uniformity and small fluctuation in size, the formation quality of the gate dielectric layer 700 can be effectively improved.

[0091] So far, the related steps of the preparation method of the vertical channel hole of the embodiment of the present application have been introduced. After the above steps, other conventional steps for manufacturing the vertical channel hole can also be included, which will not be described here. In addition to the above steps, the preparation method of the embodiment of the present application can also include other steps in the above steps or between different steps, which can be realized by various processes in the prior art, which will not be described here.

[0092] Although the example embodiments have been described with reference to the drawings, it should be understood that the example embodiments described above are only exemplary and are not intended to limit the scope of the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.

[0093] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0094] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0095] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0096] Similarly, it is to be understood that the embodiments of the present application can be used in the exact form disclosed herein, or with minor modifications, and the present application is not limited to the exact form disclosed herein. It is also to be understood that the features of the present application can be combined, exchanged or removed and that the scope of the application is not limited to the exact construction described herein. Similarly, it should be understood that, in the description of example embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description of related features. This should not be understood as reflecting an intention that the application requires more features than are explicitly recited in each claim. Rather, it will be understood that claims may

[0097] Those skilled in the art will appreciate that all features described herein (including all accompanying claims, abstract and drawings), and steps of any method or procedure so disclosed, can be combined in any combination, except where features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) can be replaced by alternative features serving the same, equivalent or a similar purpose, unless expressly stated otherwise.

[0098] Further, those skilled in the art will appreciate that the features of the different embodiments can be combined in any combination, provided such combinations are not mutually exclusive, and such combinations are within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0099] It is noted that the foregoing examples have been provided merely for the purposes of illustration and are not intended to limit the application of the application, which is defined by the claims and their equivalents.

Claims

1. A method for preparing a vertical channel hole, characterized in that, Includes the following steps: S10: Provide a semiconductor structure, the semiconductor structure comprising an etch stop layer and a layer to be etched sequentially stacked on a substrate; S20: A patterned mask layer is formed on the semiconductor structure using photolithography. S30: Using the patterned mask layer as a mask, an initial channel hole is formed vertically through the layer to be etched by a dry etching process, and the cross-section of the initial channel hole is circular. S40: Perform wet cleaning on the initial channel hole to form a wet-cleaned channel hole and measure the average diameter of the wet-cleaned channel hole; wherein, the target average diameter of the wet-cleaned channel hole is d1, and the target average diameter of the vertical channel hole is d2, d2=(1.02~1.2)×d1; S50: Based on the average aperture of the channel hole obtained by measurement, determine the wet etching process parameters, perform wet etching on the channel hole according to the wet etching process parameters to form the wet-etched channel hole, and measure the average aperture of the wet-etched channel hole. S60: Determine whether the average diameter of the measured channel hole is less than the set lower limit value; if so, repeat steps 50 and S60 until the average diameter of the channel hole measured after wet etching is not less than the set lower limit value, so as to complete the preparation of the vertical channel hole.

2. The preparation method according to claim 1, characterized in that, The lower limit value of the set aperture is d2-δ, where δ is the setting error.

3. The preparation method according to claim 1, characterized in that, The wet etching process parameters include one or more of the following: the composition of the etching solution, the etching time, and the type of nozzle. The nozzle is used to spray etching fluid.

4. The preparation method according to claim 1, characterized in that, When measuring the diameter of the channel hole, the measurement point is controlled to be at the same height in the direction perpendicular to the substrate for each measurement.

5. The preparation method according to claim 1, characterized in that, The etching stop layer includes a first oxide layer, and the layer to be etched includes a word line layer and a second oxide layer sequentially stacked on the first oxide layer. The word line layer includes a number of word lines arranged at intervals, and adjacent word lines are insulated from each other by an insulating material; The semiconductor structure further includes a bit line layer, which is disposed between the substrate and the first oxide layer. The bit line layer includes a plurality of spaced bit lines, and adjacent bit lines are insulated from each other by an insulating material. The word lines and bit lines extend in directions that intersect, and both the word lines and bit lines extend in directions that are parallel to the substrate.

6. The preparation method according to claim 5, characterized in that, The word line includes a word line material layer and a first barrier layer and a second barrier layer located on both sides of the word line material layer along a direction perpendicular to the substrate.

7. The preparation method according to claim 6, characterized in that, The first and second barrier layers are made of titanium nitride, the word line material layer is made of tungsten, and the first and second oxide layers are both made of silicon oxide.

8. The preparation method according to claim 7, characterized in that, The cleaning solution used in the wet cleaning process includes one or more of the following: DHF solution, DAM solution, DSP+ solution, and organic solvent cleaning solution.

9. The preparation method according to claim 7, characterized in that, The wet etching solution includes a DHF solution and an SPM solution. The DHF solution is used to etch the second oxide layer, and the SPM solution is used to etch the word line layer. The ratio of water to hydrofluoric acid in the DHF solution is 100:1 to 2000:1; The ratio of sulfuric acid to hydrogen peroxide in the SPM solution is 2:1 to 18:

1.

10. The preparation method according to claim 9, characterized in that, The SPM solution also includes ammonium salts.

11. The preparation method according to claim 9, characterized in that, The SPM solution was configured to have the same etching rate for titanium nitride and tungsten. The steps for determining the wet etching process parameters include: designing the etching time of the DHF solution on the second oxide layer and the etching time of the SPM solution on the word line layer to achieve flush inner walls of the second oxide layer after etching and the word line layer after etching.

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