A packaging structure and a method of manufacturing the same

Abstract

The present disclosure provides a packaging structure and a preparation method thereof. The packaging structure comprises a substrate, a first chip and at least one stack layer stacked in sequence along a first direction; each stack layer comprises a re-distribution layer structure and at least one chip connecting structure, the at least one chip connecting structure and the re-distribution layer structure are arranged along a second direction; the chip connecting structure comprises a second chip and a first re-distribution layer, the first re-distribution layer is close to a first surface of the chip connecting structure; the re-distribution layer structure comprises a second re-distribution layer and at least one conductive pillar, the second re-distribution layer is close to a first surface of the re-distribution layer structure, and the at least one conductive pillar is electrically connected with the second re-distribution layer; the second chip is electrically connected with the first chip, and the second re-distribution layer is electrically connected with the first chip; each stack layer further comprises a third re-distribution layer close to a first surface of the stack layer, and the at least one conductive pillar is electrically connected with the third re-distribution layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a packaging structure and a method for manufacturing the same. BACKGROUND

[0002] With the continuous progress of semiconductor process and technology, chips and electronic products are developing towards miniaturization, high density and high performance. Integrating higher performance and more functions into chips in a limited area has become an inevitable trend. At the same time, with the gradual slowing down of Moore's Law, chip stacking and packaging technology can not only make up for the limitations of the slowing down of Moore's Law to some extent, but also show significant advantages in some aspects. Therefore, the position of chip stacking and packaging technology in the electronic product industry chain is becoming more and more important.

[0003] However, when manufacturing a high bandwidth memory (HBM), a position of a through silicon via (TSV) needs to be reserved in a dynamic random access memory die (DRAM die), which results in waste of effective area of the DRAM die, increase of cost, and consideration of the influence of the TSV on internal circuits of the chip. In addition, the process difficulty of the TSV is high, which is easy to cause damage to the DRAM die and increase the cost. SUMMARY

[0004] The present disclosure provides a packaging structure and a method for manufacturing the same.

[0005] In a first aspect, the present disclosure provides a packaging structure, which comprises a substrate, a first chip and at least one stacking layer stacked in a first direction; each stacking layer comprises a re-distribution layer structure and at least one chip connecting structure, and the at least one chip connecting structure and the re-distribution layer structure are arranged in a second direction.

[0006] The chip connecting structure comprises a second chip and a first re-distribution layer, and the first re-distribution layer is close to a first surface of the chip connecting structure; the re-distribution layer structure comprises a second re-distribution layer and at least one conductive pillar, the second re-distribution layer is close to a first surface of the re-distribution layer structure, and the at least one conductive pillar is electrically connected with the second re-distribution layer; the second chip is electrically connected with the first chip, and the second re-distribution layer is electrically connected with the first chip.

[0007] Each stacking layer further comprises a third re-distribution layer close to a first surface of the stacking layer, and the at least one conductive pillar is electrically connected with the third re-distribution layer.

[0008] The chip connecting structure is cut from an active chip wafer, and the adapter plate structure is cut from an adapter plate wafer.

[0009] In some embodiments, each of the stack layers further comprises a first bonding layer on the third redistribution layer, the first bonding layer is electrically connected with the third redistribution layer, and two adjacent stack layers are electrically connected through the first bonding layer.

[0010] In some embodiments, the packaging structure further comprises a plurality of first conductive layers in the first chip; the chip connecting structure further comprises at least one second conductive layer in the second chip, and the at least one second conductive layer is close to the first surface of the chip connecting structure.

[0011] The at least one second conductive layer is electrically connected with the first conductive layer through the first redistribution layer, and the second redistribution layer is electrically connected with the first conductive layer.

[0012] In some embodiments, the chip connecting structure further comprises at least one third conductive layer and a fourth redistribution layer, the at least one third conductive layer and the fourth redistribution layer are in the second chip, and the at least one third conductive layer and the fourth redistribution layer are close to the second surface of the chip connecting structure; the first surface of the chip connecting structure and the second surface of the chip connecting structure are opposite.

[0013] The at least one third conductive layer is electrically connected with the third redistribution layer through the fourth redistribution layer.

[0014] In some embodiments, the chip connecting structure further comprises a second bonding layer on the first surface of the chip connecting structure, the second bonding layer is electrically connected with the first redistribution layer; the adapter plate structure further comprises a third bonding layer on the first surface of the adapter plate structure, the third bonding layer is electrically connected with the second redistribution layer.

[0015] The chip connecting structure is electrically connected with the first chip through the second bonding layer, and the adapter plate structure is electrically connected with the first chip through the third bonding layer.

[0016] In some embodiments, each of the stack layers further comprises a dielectric material, the dielectric material fills the gap in the stack layer.

[0017] In a second aspect, the embodiments of the present disclosure provide a method for manufacturing a packaging structure, the method comprising:

[0018] providing a substrate and a first chip, and placing the first chip on the substrate along a first direction;

[0019] forming at least one stack layer on the first chip;

[0020] wherein each of the stack layers comprises a re-distribution layer structure and at least one chip connecting structure, the at least one chip connecting structure and the re-distribution layer structure are arranged along a second direction; the chip connecting structure comprises a second chip and a first re-distribution layer, the first re-distribution layer is close to a first surface of the chip connecting structure; the re-distribution layer structure comprises a second re-distribution layer and at least one conductive pillar, the second re-distribution layer is close to a first surface of the re-distribution layer structure, the at least one conductive pillar is electrically connected with the second re-distribution layer; the second chip is electrically connected with the first chip, and the second re-distribution layer is electrically connected with the first chip; each of the stack layers further comprises a third re-distribution layer close to a first surface of the stack layer, the at least one conductive pillar is electrically connected with the third re-distribution layer; the chip connecting structure is obtained by cutting an active chip wafer, and the re-distribution layer structure is obtained by cutting a re-distribution layer wafer.

[0021] In some embodiments, forming each of the stack layers comprises:

[0022] arranging the re-distribution layer structure and the at least one chip connecting structure on the first chip along the second direction;

[0023] filling a medium layer on exposed surfaces of the re-distribution layer structure and the at least one chip connecting structure, the medium layer is composed of a medium material;

[0024] performing etching treatment on the medium layer and the re-distribution layer structure to expose the at least one conductive pillar;

[0025] forming the third re-distribution layer, and electrically connecting the third re-distribution layer with the at least one conductive pillar.

[0026] In some embodiments, after forming the third re-distribution layer, the method further comprises:

[0027] forming a first bonding layer on the third re-distribution layer, and electrically connecting the first bonding layer with the third re-distribution layer;

[0028] wherein two adjacent stack layers are electrically connected through the first bonding layer.

[0029] In some embodiments, the packaging structure further comprises a plurality of first conductive layers located in the first chip; the chip connecting structure further comprises at least one second conductive layer located in the second chip and close to the first surface of the chip connecting structure; the at least one second conductive layer is electrically connected to the first conductive layer through the first redistribution layer, and the second redistribution layer is electrically connected to the first conductive layer; after the etching treatment of the dielectric layer and the adapter plate structure, the method further comprises:

[0030] forming at least one third conductive layer in the second chip, and the at least one third conductive layer is close to the second surface of the chip connecting structure; the first surface of the chip connecting structure and the second surface of the chip connecting structure are opposite;

[0031] forming a fourth redistribution layer in the second chip, and the fourth redistribution layer is close to the second surface of the chip connecting structure, and the fourth redistribution layer is electrically connected to the at least one third conductive layer;

[0032] electrically connecting the third redistribution layer to the at least one conductive column, comprising:

[0033] electrically connecting the third redistribution layer to the at least one conductive column and the fourth redistribution layer respectively.

[0034] The present disclosure provides a packaging structure and a preparation method thereof. The packaging structure comprises a substrate, a first chip and at least one stacking layer stacked in a first direction in sequence; each stacking layer comprises an adapter plate structure and at least one chip connecting structure, and the at least one chip connecting structure and the adapter plate structure are arranged in a second direction; the chip connecting structure comprises a second chip and a first redistribution layer, and the first redistribution layer is close to a first surface of the chip connecting structure; the adapter plate structure comprises a second redistribution layer and at least one conductive column, the second redistribution layer is close to a first surface of the adapter plate structure, and the at least one conductive column is electrically connected to the second redistribution layer; the second chip is electrically connected to the first chip, and the second redistribution layer is electrically connected to the first chip; each stacking layer further comprises a third redistribution layer close to a first surface of the stacking layer, and the at least one conductive column is electrically connected to the third redistribution layer; wherein the chip connecting structure is obtained by cutting an active chip wafer, and the adapter plate structure is obtained by cutting an adapter plate wafer. In this way, the existing adapter plate structure is integrated into the packaging structure, which can realize vertical interconnection and packaging of multiple chips, increase the stacking number of chips, improve the interconnection density of chips, and simplify the process, reduce the stress warpage of the packaging structure, and reduce the cost. BRIEF DESCRIPTION OF DRAWINGS

[0035] In the drawings, which are not necessarily drawn to scale, like numerals describe similar components throughout the several views. Like numerals having different letter suffixes can represent different instances of the like component. The drawings illustrate generally, by way of example, various embodiments discussed herein.

[0036] Figure 1 A schematic view of a component structure of a packaging structure;

[0037] Figure 2 A schematic view of a component structure of a packaging structure provided by an embodiment of the present disclosure Figure 1 ;

[0038] Figure 3 A schematic view of a component structure of a chip connection structure provided by an embodiment of the present disclosure

[0039] Figure 4 A schematic view of a component structure of a re-distribution layer structure provided by an embodiment of the present disclosure

[0040] Figure 5 A schematic view of a component structure of a packaging structure provided by an embodiment of the present disclosure Figure 2 ;

[0041] Figure 6 A schematic view of a packaging structure provided by an embodiment of the present disclosure

[0042] Figure 7 A flowchart of a preparation method of a packaging structure provided by an embodiment of the present disclosure Figure 1 ;

[0043] Figure 8 A schematic view of a preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 1 ;

[0044] Figure 9 A flowchart of a preparation method of a packaging structure provided by an embodiment of the present disclosure Figure 2 ;

[0045] Figure 10 A schematic view of a preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 2 ;

[0046] Figure 11 A schematic view of a preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 3 ;

[0047] Figure 12 A schematic view of a preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 4 ;

[0048] Figure 13A preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 5 ;

[0049] Figure 14 A preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 6 ;

[0050] Figure 15 A preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 7 . DETAILED DESCRIPTION

[0051] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure can be embodied in various forms without being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0052] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features are not described in detail in order to avoid obscuring the present disclosure. In the interest of clarity, not all of the features of the examples are described. Thus, the detailed description herein is not intended to be limiting.

[0053] In the drawings, the size of layers, regions, elements, and the relative sizes of the same can be exaggerated for clarity. Like reference numbers in different drawings denote like elements.

[0054] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present disclosure.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] Under the catalysis of artificial intelligence (AI) computing power, the demand for HBM has exploded. Currently, HBW has two technical routes of wafer to wafer (W2W) and die to wafer (D2W).

[0057] With the increasing requirement of computing power on the storage capacity of HBM, the stacking height of HBM is also increasing. After 1 layer of logic die combined with 8 layers of storage die (such as DRAM die) (i.e. 1+8), D2W becomes the preferred technical route. However, from 1+8 to 1+12 (i.e. 1 layer of logic die combined with 12 layers of storage die) and 1+16 (i.e. 1 layer of logic die combined with 16 layers of storage die), the process difficulty is also increasing.

[0058] Referring to Figure 1 , a schematic diagram of a composition structure of a packaging structure is shown. As Figure 1As shown, in related technologies, the package structure 10 includes a logic chip 11, a memory chip 12, and a TSV 13 (…). Figure 1 Only one label 13 is shown in the figure, and the rest are omitted. The logic chip 11 and each memory chip 12 are connected using TSV13. The package structure 10 also includes multiple micro-bumps and underfill (labels not shown in the figure).

[0059] exist Figure 1 For example, memory chip 12 is a DRAM chip.

[0060] In the HBM technology roadmap, 3D TSVs can meet the requirements for higher integration and higher bandwidth, but they also present the greatest manufacturing challenges. In related technologies, DRAM chips need to reserve space for TSVs, which wastes valuable DRAM chip area and increases costs. Furthermore, the impact of TSV heat dissipation and capacitance on the internal circuitry of the chip must be considered. Additionally, the manufacturing process for TSVs in active chips is more complex, easily leading to DRAM chip damage and increased costs.

[0061] It should be noted that when fabricating the TSV in an active chip, there will be some capacitor structures in the TSV. These capacitor structures will affect the driving of other areas inside the chip, and will also affect the internal structure and circuitry of the chip.

[0062] Based on this, the present disclosure provides a packaging structure comprising a substrate, a first chip, and at least one stacked layer sequentially stacked along a first direction; each stacked layer includes an adapter board structure and at least one chip connection structure, the at least one chip connection structure and the adapter board structure being placed along a second direction; the chip connection structure includes a second chip and a first redistribution layer, the first redistribution layer being close to a first surface of the chip connection structure; the adapter board structure includes a second redistribution layer and at least one conductive post, the second redistribution layer being close to a first surface of the adapter board structure, the at least one conductive post being electrically connected to the second redistribution layer; the second chip is electrically connected to the first chip, and the second redistribution layer is also electrically connected to the first chip; each stacked layer further includes a third redistribution layer close to a first surface of the stacked layer, the at least one conductive post being electrically connected to the third redistribution layer; wherein, the chip connection structure is obtained by dicing an active chip wafer, and the adapter board structure is obtained by dicing an adapter board wafer. In this way, integrating the existing adapter board structure into the packaging structure enables vertical interconnection and packaging of multiple chips, increases the number of stacked chips, improves the interconnection density of chips, simplifies the process, reduces stress warpage of the packaging structure, and lowers costs.

[0063] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0064] In an embodiment of the present disclosure, referring to Figure 2 which shows a schematic diagram of a component structure of a packaging structure provided by an embodiment of the present disclosure Figure 1 . As shown in Figure 2 , the packaging structure 20 comprises a substrate 21, a first chip 22 and at least one stacked layer 23 stacked in a first direction in sequence; each stacked layer 23 comprises a re-distribution layer structure 231 and at least one chip connecting structure 232, and the at least one chip connecting structure 232 and the re-distribution layer structure 231 are arranged in a second direction;

[0065] As shown in Figure 2 and Figure 3 , the chip connecting structure 232 comprises a second chip 2321 and a first re-distribution layer 2322, and the first re-distribution layer 2322 is close to a first surface of the chip connecting structure 232; as shown in Figure 2 and Figure 4 , the re-distribution layer structure 231 comprises a second re-distribution layer 2311 and at least one conductive pillar 2312, the second re-distribution layer 2311 is close to a first surface of the re-distribution layer structure 231, and the at least one conductive pillar 2312 is electrically connected with the second re-distribution layer 2311; the second chip 2321 is electrically connected with the first chip 22, and the second re-distribution layer 2311 is electrically connected with the first chip 22;

[0066] Each stacked layer 23 further comprises a third re-distribution layer 233 close to a first surface of the stacked layer 23, and the at least one conductive pillar 2312 is electrically connected with the third re-distribution layer 233;

[0067] Wherein, the chip connecting structure 232 is obtained by cutting an active chip wafer, and the re-distribution layer structure 231 is obtained by cutting a re-distribution layer wafer.

[0068] It should be noted that, in order to facilitate the illustration, Figure 2 , the labels inside the re-distribution layer structure 231 and the chip connecting structure 232 are not shown, please refer to Figure 3 and Figure 4 for understanding.

[0069] Here, the first direction and the second direction intersect, that is, the first direction and the second direction are two non-parallel directions. In the embodiments of the present disclosure, the first direction and the second direction can be perpendicular to each other, or can intersect at other angles, which are not limited. Exemplarily, the specific implementation of the embodiments of the present disclosure is described in detail taking the first direction and the second direction perpendicular to each other as an example.

[0070] In the present embodiment, the number of stacked layers 23 is not limited, and can be stacked according to actual needs; when the packaging structure 20 comprises multiple stacked layers 23, the multiple stacked layers 23 are stacked and electrically connected with each other. Exemplarily, the packaging structure 20 in the present embodiment only comprises one stacked layer 23.

[0071] It should be noted that the substrate 21 can be a wafer (also called a bottom wafer), which has a first surface and a second surface. Specifically, the surface closer to the first chip 22 is the first surface, and the surface farther away from the first chip 22 is the second surface. In addition, the substrate 21 can be a logic chip or a memory chip, without specific limitation. The substrate 21 provides protection and support for the first chip 22 and at least one stacked layer 23, and is electrically connected to the first chip 22.

[0072] It should also be noted that the function of the first chip 22 is not limited; it can be a radio frequency chip, a logic chip, a memory chip, etc.

[0073] It should also be noted that the adapter board structure 231 can also be called an adapter board wafer die, which can be obtained by cutting an adapter board wafer. The adapter board wafer is a single, large adapter board that is manufactured separately, and it can be cut into several adapter board wafer dies. Additionally, the chip connection structure 232 can also be called an active chip wafer particle, which is obtained by cutting an active chip wafer. Active chip wafers can include logic chip wafers and memory chip wafers. Logic chip wafers are used to manufacture various logic chips and are one of the most common wafer products in various electronic devices; they are core components of computers, mobile phones, and other electronic devices. Memory chip wafers are used to manufacture various memory chips and are widely used in various storage devices, such as memory modules and solid-state drives.

[0074] It should also be noted that the number and location of the chip connection structures 232 are not specifically limited. When there are a large number of second chips 2321 that need to be interconnected, more chip connection structures 232 can be provided in the package structure 20; when there are multiple chip connection structures 232, the adapter board structure 231 can be located in the middle or on one side of the multiple chip connection structures 232. For example, the package structure 20 includes one adapter board structure 231 and two chip connection structures 232, with the adapter board structure 231 located in the middle of the two chip connection structures 232, through which the chips are interconnected.

[0075] like Figure 2 to Figure 4 As shown, in the encapsulation structure 20, the shape and number of each redistribution layer (RDL), namely the first redistribution layer 2322, the second redistribution layer 2311, and the third redistribution layer 233, are not limited. Each redistribution layer can include 1, 3, 5, or other layers as needed. When each redistribution layer includes multiple layers, the structure of each layer can be the same or different, and no specific limitation is made in this regard. Exemplarily, the specific implementation of the embodiment of this disclosure will be described in detail with the example of each redistribution layer including 1 layer.

[0076] In the embodiment, as shown in Figure 2 and Figure 4 The material of the adapter plate structure 231 can be silicon or glass, that is, the substrate 2313 thereof can be silicon-based or glass-based, and the material of the oxide layer 2314 is not limited in particular. Exemplarily, the material of the adapter plate structure 231 is silicon, and the material of the oxide layer 2314 is silicon dioxide.

[0077] In addition, the number of the conductive pillars 2312 in the adapter plate structure 231 is not limited in particular. Exemplarily, the adapter plate structure 231 includes three conductive pillars 2312.

[0078] It should be further noted that, in each stack layer 23, the surface closer to the first redistribution layer 2322 in the chip connection structure 232 or the second redistribution layer 2311 in the adapter plate structure 231 is the second surface, and the surface opposite thereto is the first surface. In the adapter plate structure 231, the surface exposing the substrate 2313 is the second surface, and the surface opposite thereto is the first surface. In the chip connection structure 232, the surface exposing the second chip 2321 is the second surface, and the surface opposite thereto is the first surface.

[0079] The present disclosure provides a packaging structure 20, which integrates the existing adapter plate structure 231 into the packaging structure 20, so as to realize vertical interconnection and packaging of multiple chips, increase the number of stacked chips, improve the interconnection density of the chips, and simplify the process, reduce the stress warping of the packaging structure, and reduce the cost.

[0080] In some embodiments, as shown in Figure 2 Each stack layer 23 can further include a first bonding layer 234 on the third redistribution layer 233, the first bonding layer 234 being electrically connected to the third redistribution layer 233, and two adjacent stack layers 23 being electrically connected through the first bonding layer 234.

[0081] It should be noted that the first bonding layer 234 can be bonded to the third redistribution layer 233 by any bonding technology, which is not limited in particular. Exemplarily, the first bonding layer 234 is bonded to the third redistribution layer 233 by a hybrid bonding technology. The hybrid bonding technology is a method combining physical bonding and chemical bonding, which can make different kinds of bonding materials form a bond. This bonding method can overcome the limitations of a single bonding method, greatly reduce the bonding pitch, and improve the bonding density.

[0082] It should be noted that the first surface of the stack layer 23 can also be referred to as a bonding interface through the first bonding layer 234. The first bonding layer 234 can include a plurality of first hybrid bonding structures (not shown in the figure), so that the first surface of the stack layer 23 can be a hybrid bonding interface in particular. Figure 2

[0083] In some embodiments, as shown in Figure 2 , the packaging structure 20 can further include a plurality of first conductive layers 24 located in the first chip 22; as shown in Figure 2 and Figure 3 , the chip connection structure 232 can further include at least one second conductive layer 2323 located in the second chip 2321 and close to the first surface of the chip connection structure 232.

[0084] The at least one second conductive layer 2323 is electrically connected to the first conductive layer 24 through the first redistribution layer 2322, and the second redistribution layer 2311 is electrically connected to the first conductive layer 24.

[0085] It should be noted that each conductive layer (the first conductive layer 24 and the second conductive layer 2323) is a metal layer for interconnection, which is a metal layer inside the corresponding chip, and the circuit is led to the outside of the chip through the redistribution layer.

[0086] It should be noted that the number of the first conductive layers 24 is not specifically limited. For example, the packaging structure 20 includes six first conductive layers 24. The number of the second conductive layers 2323 is also not specifically limited. Each chip connection structure 232 can include only one second conductive layer 2323, or a plurality of second conductive layers 2323 can be provided according to actual needs. For example, each chip connection structure 232 includes two second conductive layers 2323, and each second conductive layer 2323 is electrically connected to the corresponding first conductive layer 24. That is, in the packaging structure 20, four first conductive layers 24 are electrically connected to the corresponding second conductive layers 2323, and two first conductive layers 24 are electrically connected to the second redistribution layer 2311.

[0087] In some embodiments, based on the packaging structure 20 as shown in Figure 2 , as shown in Figure 5 , a composition structure of a packaging structure provided by the embodiments of the present disclosure is shown. Figure 2 Figure 5 ​​As shown, the chip connection structure 232 may further include at least one third conductive layer 2324 and a fourth redistribution layer 2325, wherein at least one third conductive layer 2324 and the fourth redistribution layer 2325 are located within the second chip 2321 and are close to the second surface of the chip connection structure 232; the first surface of the chip connection structure 232 and the second surface of the chip connection structure 232 are opposite to each other.

[0088] At least one third conductive layer 2324 is electrically connected to the third wiring layer 233 through a fourth wiring layer 2325.

[0089] It should be noted that the third conductive layer 2324 is also a metal layer inside the second chip 2321, and its lines can be led to the outside of the second chip 2321 through the fourth redistribution layer 2325.

[0090] It should also be noted that the number of third conductive layers 2324 is not limited. Each chip connection structure 232 may include only one third conductive layer 2324, or multiple third conductive layers 2324 may be provided according to actual needs. For example, each chip connection structure 232 includes two third conductive layers 2324, and each third conductive layer 2324 is electrically connected to the third redistribution layer 233.

[0091] It should also be noted that the number of the third conductive layer 2324 and the second conductive layer 2323 can be the same or different, and there is no specific limitation on this.

[0092] exist Figure 2 In the middle, the second chip 2321 has a single-sided redistribution layer (first redistribution layer 2322); in Figure 5 In this design, the second chip 2321 has a double-sided redistribution layer (a first redistribution layer 2322 and a fourth redistribution layer 2325). Specifically, the vertical interconnection between the top and bottom of the second chip 2321 can be achieved using the TSV process. Here, the TSV process refers to fabricating a fourth redistribution layer 2325 on the other surface of the second chip 2321, based on the first redistribution layer 2322, to achieve the interconnection of the chips.

[0093] exist Figure 1 In the related technologies shown, a double-sided redistribution layer needs to be fabricated on the surface of the memory chip 12, which can lead to high stress warpage. In this embodiment, although a double-sided redistribution layer is also fabricated on the surface of the second chip 2321, the second chip 2321 is designed to be smaller than the memory chip 12, which can reduce stress warpage. Furthermore, Figure 2 The encapsulation structure 20 in the middle can be interconnected planarly through the adapter board structure 231, while Figure 5The encapsulation structure 20 in the chip connection structure 232 not only realizes the interconnection of the chips in the adapter board structure 231, but also realizes the vertical interconnection of the second chips 2321 in each of the stacked layers 23 above and below through the at least one third conductive layer 2324 and the fourth redistribution layer 2325, so that the data transmission speed in the stacked layers 23 is faster and the interconnection density is higher.

[0094] In some embodiments, as shown in Figure 3 The chip connection structure 232 can further include a second bonding layer 2326 located on the first surface of the chip connection structure 232, and the second bonding layer 2326 is electrically connected with the first redistribution layer 2322; as shown in Figure 4 The adapter board structure 231 can further include a third bonding layer 2315 located on the first surface of the adapter board structure 231, and the third bonding layer 2315 is electrically connected with the second redistribution layer 2311.

[0095] The chip connection structure 232 is electrically connected with the first chip 22 through the second bonding layer 2326, and the adapter board structure 231 is electrically connected with the first chip 22 through the third bonding layer 2315.

[0096] It should be noted that the second bonding layer 2326 and the first redistribution layer 2322 can be bonded by any bonding technology, and the third bonding layer 2315 and the second redistribution layer 2311 can be bonded by any bonding technology, which is not limited specifically. Exemplarily, the second bonding layer 2326 and the first redistribution layer 2322 are bonded by hybrid bonding technology, and the third bonding layer 2315 and the second redistribution layer 2311 are bonded by hybrid bonding technology.

[0097] It should be further noted that the first surface of the chip connection structure 232 can also be referred to as a bonding interface through the second bonding layer 2326. The second bonding layer 2326 can include a plurality of second hybrid bonding structures (not shown in the figure), so that the first surface of the chip connection structure 232 can be a hybrid bonding interface specifically. Similarly, the first surface of the adapter board structure 231 can also be referred to as a bonding interface through the third bonding layer 2315. The third bonding layer 2315 can include a plurality of third hybrid bonding structures (not shown in the figure), so that the first surface of the adapter board structure 231 can be a hybrid bonding interface specifically. Figure 3 Figure 4 It should be further noted that the first surface of the chip connection structure 232 can also be referred to as a bonding interface through the second bonding layer 2326. The second bonding layer 2326 can include a plurality of second hybrid bonding structures (not shown in the figure), so that the first surface of the chip connection structure 232 can be a hybrid bonding interface specifically. Similarly, the first surface of the adapter board structure 231 can also be referred to as a bonding interface through the third bonding layer 2315. The third bonding layer 2315 can include a plurality of third hybrid bonding structures (not shown in the figure), so that the first surface of the adapter board structure 231 can be a hybrid bonding interface specifically.

[0098] It should be further noted that the first surface of the chip connection structure 232 can also be referred to as a bonding interface through the second bonding layer 2326. The second bonding layer 2326 can include a plurality of second hybrid bonding structures (not shown in the figure), so that the first surface of the chip connection structure 232 can be a hybrid bonding interface specifically. Similarly, the first surface of the adapter board structure 231 can also be referred to as a bonding interface through the third bonding layer 2315. The third bonding layer 2315 can include a plurality of third hybrid bonding structures (not shown in the figure), so that the first surface of the adapter board structure 231 can be a hybrid bonding interface specifically.

[0099] ​In some embodiments, the packaging structure 20 can further include a fourth bonding layer (not shown in the figure) on the first chip 22;

[0100] The chip connection structure 232 is electrically connected with the first chip 22 through the second bonding layer 2326 and the fourth bonding layer, and the adapter plate structure 231 is electrically connected with the first chip 22 through the third bonding layer 2315 and the fourth bonding layer.

[0101] It should be noted that the fourth bonding layer can also include a plurality of fourth hybrid bonding structures.

[0102] In some embodiments, as shown in Figure 2 or Figure 5 The packaging structure 20 can further include a fifth redistribution layer 25, and the first conductive layer 24 is electrically connected with the corresponding fifth redistribution layer 25.

[0103] The first conductive layer 24 is electrically connected with the second conductive layer 2323 through the corresponding fifth redistribution layer 25 and the first redistribution layer 2322, and the first conductive layer 24 is electrically connected with the second redistribution layer 2311 through the corresponding fifth redistribution layer 25.

[0104] In some embodiments, as shown in Figure 2 Each stack layer 23 can further include a dielectric material 235 filled in the gap of the stack layer 23.

[0105] It should be noted that the dielectric material 235 can be silicon dioxide, but is not limited thereto.

[0106] Referring to Figure 6 , a top view of a packaging structure is shown, specifically a top view of a TSV. As shown in Figure 6 (a), the TSVs are uniformly distributed in the entire DRAM chip; as shown in Figure 6 (b), the TSVs are locally distributed in the DRAM chip; as shown in Figure 6 (c), the TSVs are separated from the DRAM chip.

[0107] It should be noted that when the TSVs are locally distributed in the DRAM chip, there can be only a local area of a TSV, or there can be a plurality of local areas of TSVs, and in each local area of a TSV, the TSVs are concentratedly distributed, and the distribution manner is not limited, that is, the plurality of TSVs can be uniformly distributed, or can be non-uniformly distributed. Exemplarily, as shown in Figure 6 (b), there is only a local area of a TSV, and 12 TSVs are concentratedly distributed therein.

[0108] It also needs to be explained that when there are multiple local regions of TSVs, the TSVs can be divided into multiple adapter structures when the TSVs are separated from the DRAM chip; when there is only one local region of TSVs, the TSVs can be divided into one or multiple adapter structures. Exemplarily, Figure 6 (b) in (b) has only one local region including 12 TSVs, Figure 6 (c) is divided into only one adapter structure, but can also be divided into two adapter structures each including 6 TSVs, which is not specifically limited.

[0109] In summary, in the related art, the TSVs and the DRAM chip are prepared together, and the TSVs are uniformly distributed in the entire DRAM chip; in the present disclosure, in order to separately prepare the adapter structure, the TSVs are first concentrated and locally distributed in the DRAM chip, and then further, the adapter structure is separately prepared, and the prepared adapter structure (i.e., the adapter structure 231) is integrated into the packaging structure 20.

[0110] The present disclosure provides a packaging structure 20 including a multi-layer stacked chip, integrates the existing adapter structure 231 into the packaging structure 20, omits the preparation of high-aspect-ratio TSVs in the active chip, and simplifies the process; in the related art, a double-sided redistribution layer needs to be prepared on the surface of the memory chip 12, while the present embodiment can only need to prepare a single-sided redistribution layer (i.e., the first redistribution layer 2322) on one surface of the second chip 2321, thereby reducing the stress warpage of the packaging structure 20; even if a double-sided redistribution layer (i.e., the first redistribution layer 2322 and the fourth redistribution layer 2325) is prepared on the second chip 2321, the stress warpage can also be reduced; through the adapter structure 231, the interconnection of each chip can be realized, and higher interconnection density can be achieved; through each Fan Out redistribution layer (referred to as redistribution layer for short), horizontal interconnection between chips can be realized; through the TSV process, vertical interconnection between chips can be realized.

[0111] In another embodiment of the present disclosure, refer to Figure 7 which shows a flowchart of a preparation method of a packaging structure provided by an embodiment of the present disclosure Figure 1 . As shown in Figure 7 , the method can include:

[0112] S301, providing a substrate and a first chip, and placing the first chip on the substrate along a first direction.

[0113] It needs to be explained that the preparation method provided by the embodiment of the present disclosure is applied to prepare the aforementioned packaging structure 20.

[0114] Refer to Figure 8 , which shows a preparation process diagram of a packaging structure provided by an embodiment of the present disclosure Figure 1 . As shown inFigure 8 As shown in FIG. 1, in preparing the adapter plate structure 20, first, the substrate 21 and the first chip 22 are provided, and the first chip 22 is stacked on the substrate 21.

[0115] S302, forming at least one stacked layer on the first chip.

[0116] Each stacked layer includes an adapter plate structure and at least one chip connection structure, the at least one chip connection structure and the adapter plate structure are placed along a second direction; the chip connection structure includes a second chip and a first redistribution layer, the first redistribution layer is close to a first surface of the chip connection structure; the adapter plate structure includes a second redistribution layer and at least one conductive column, the second redistribution layer is close to a first surface of the adapter plate structure, and the at least one conductive column is electrically connected with the second redistribution layer; the second chip is electrically connected with the first chip, and the second redistribution layer is electrically connected with the first chip; each stacked layer further includes a third redistribution layer close to the first surface of the stacked layer, and the at least one conductive column is electrically connected with the third redistribution layer; the chip connection structure is obtained by wafer cutting of an active chip, and the adapter plate structure is obtained by wafer cutting of an adapter plate.

[0117] Specifically, in some embodiments, referring to FIG. 2, a preparation method of a packaging structure is shown. Figure 9 As shown in FIG. 2, the preparation method of the packaging structure includes the following steps. Figure 2 As shown in FIG. 2, the preparation method of the packaging structure includes the following steps. Figure 9 As shown in FIG. 2, the preparation method of the packaging structure includes the following steps.

[0118] S401, placing an adapter plate structure and at least one chip connection structure on the first chip along a second direction. That is, performing a D2W process.

[0119] As shown in FIG. 2, the preparation method of the packaging structure includes the following steps. Figure 10 As shown in FIG. 2, the preparation method of the packaging structure includes the following steps.

[0120] It should be noted that, because in the adapter plate structure 231 shown in FIG. 2, the side exposing the substrate 2313 is the second surface, and the surface opposite to it is the first surface, the first surface faces upward, so when placing the adapter plate structure 231 on the first chip 22, it needs to be turned upside down, that is, the first surface of the adapter plate structure 231 faces downward. Figure 4 Figure 3 As shown in FIG. 2, the preparation method of the packaging structure includes the following steps.

[0121] As shown in FIG. 2, the preparation method of the packaging structure includes the following steps.​Figure 10 As shown, the first chip 22 has multiple first conductive layers 24, at least one second conductive layer 2323 is electrically connected to the first conductive layer 24 through a first redistribution layer 2322, and the second redistribution layer 2311 is electrically connected to the first conductive layer 24.

[0122] It should be noted that in the adapter plate structure 231, multiple deep holes can be formed by etching in the substrate 2313, and after forming the multiple deep holes, conductive material is filled into the deep holes to form multiple second conductive pillars 2312. The conductive material may include copper, tungsten, polycrystalline silicon, etc., and is not specifically limited thereto. The process of filling the conductive material may include deposition processes, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or may also include electroplating processes, which are not specifically limited in this embodiment.

[0123] It should also be noted that the materials of each redistribution layer (first redistribution layer 2322, second redistribution layer 2311, third redistribution layer 233, and fourth redistribution layer 2325) can be the same as the conductive material of the second conductive post 2312, for example, copper. Alternatively, each redistribution layer can be formed using a damascus steel process.

[0124] S402, A dielectric layer, composed of a dielectric material, is filled and covers the exposed surfaces of the adapter board structure and at least one chip connection structure.

[0125] like Figure 11 As shown, after placing the adapter board structure 231 and at least one chip connection structure 232 on the first chip 22, a dielectric layer 2351 is filled, and the material of the dielectric layer 2351 is the aforementioned dielectric material 235.

[0126] It should be noted that CVD process can be used to fill the dielectric layer 2351, but there are no specific limitations on this.

[0127] S403. Etch the dielectric layer and the adapter plate structure to expose at least one conductive post.

[0128] like Figure 12 As shown, after the dielectric layer 2351 is filled, the dielectric layer 2351 and the adapter plate structure 231 are etched to expose at least one conductive post 2312.

[0129] In some embodiments, etching the dielectric layer and the adapter board structure may include:

[0130] The dielectric layer is etched to be flush with the end face of the adapter board structure (i.e., the second surface of the adapter board structure) using the first process;

[0131] The adapter plate structure is etched through a second process to expose at least one conductive post.

[0132] It should be noted that the first process can be chemical mechanical polishing (CMP); the second process can be backside via reveal (BVR).

[0133] S404. Form a third wiring layer and electrically connect the third wiring layer to at least one conductive post.

[0134] like Figure 2 As shown, after the conductive post 2312 is exposed, a third wiring layer 233 is formed on the conductive post 2312, and at least one conductive post 2312 is electrically connected to the third wiring layer 233.

[0135] It should be noted that after the conductive pillar 2312 is exposed, the dielectric material 235 can be filled first, followed by an etching process, and then a double damask process to form a shape such as... Figure 2 The third wiring layer 233 is shown.

[0136] In some embodiments, after forming the third wiring layer, the fabrication method may further include:

[0137] A first bonding layer is formed on the third wiring layer, and the first bonding layer is electrically connected to the third wiring layer.

[0138] In this configuration, two adjacent stacked layers are electrically connected through a first bonding layer.

[0139] like Figure 2 As shown, after forming the third wiring layer 233, a first bonding layer 234 is formed on the third wiring layer 233, that is, a hybrid bonding interface is formed, thereby obtaining the first stacked layer 23. The first bonding layer 234 is electrically connected to the third wiring layer 233.

[0140] In some embodiments, the first chip 22 has a fourth bonding layer. The chip connection structure 232 is electrically connected to the first chip 22 via the second bonding layer 2326 and the fourth bonding layer, and the adapter board structure 231 is electrically connected to the first chip 22 via the third bonding layer 2315 and the fourth bonding layer.

[0141] In some embodiments, the first conductive layer 24 has a fifth redistribution layer 25 on it. The first conductive layer 24 is electrically connected to the second conductive layer 2323 through the corresponding fifth redistribution layer 25 and the first redistribution layer 2322, and the first conductive layer 24 is electrically connected to the second redistribution layer 2311 through the corresponding fifth redistribution layer 25.

[0142] As shown in FIG. 1, after the first layer of the stack 23 is formed, the adapter structure 231 and the chip connection structure 232 are placed on the first bonding layer 234 of the first layer of the stack 23 along the second direction. Figure 13

[0143] As shown in FIG. 1, after the first layer of the stack 23 is formed, the adapter structure 231 and the chip connection structure 232 are placed on the first bonding layer 234 of the first layer of the stack 23 along the second direction. Figure 13

[0144] Further, as shown in FIG. 1, the process steps of filling the medium layer 2351, etching the medium layer 2351 and the adapter structure 231, exposing the conductive pillar 2312, forming the third redistribution layer 233, electrically connecting the third redistribution layer 233 to the at least one conductive pillar 2312, forming the first bonding layer 234 on the third redistribution layer 233, and electrically connecting the first bonding layer 234 to the third redistribution layer 233 are repeated to form the second layer of the stack 23. Figure 14

[0145] It should be further noted that if the number of stacks 23 needs to be stacked on the second layer of the stack 23, the process steps of other embodiments can be referred to for understanding, which will not be repeated here.

[0146] In some embodiments, the package structure further comprises a plurality of first conductive layers located in the first chip; the chip connection structure further comprises at least one second conductive layer located in the second chip and close to the first surface of the chip connection structure; the at least one second conductive layer is electrically connected to the first conductive layer through the first redistribution layer, and the second redistribution layer is electrically connected to the first conductive layer; after the etching process of the medium layer and the adapter structure, the preparation method can further comprise:

[0147] forming at least one third conductive layer in the second chip, and the at least one third conductive layer is close to the second surface of the chip connection structure; the first surface of the chip connection structure and the second surface of the chip connection structure are opposite to each other;

[0148] ​​​forming a fourth redistribution layer in the second chip, and the fourth redistribution layer is close to the second surface of the chip connecting structure, and the fourth redistribution layer is electrically connected with the at least one third conductive layer;

[0149] electrically connecting the third redistribution layer with the at least one conductive column, comprising:

[0150] electrically connecting the third redistribution layer with the at least one conductive column and the fourth redistribution layer respectively.

[0151] As shown in Figure 5 on the basis of Figure 12 forming at least one third conductive layer 2324 in the second chip 2321, and then forming a fourth redistribution layer 2325. Among them, the at least one third conductive layer 2324 and the fourth redistribution layer 2325 are located in the second chip 2321 and close to the second surface of the chip connecting structure 232; the at least one third conductive layer 2324 is electrically connected with the third redistribution layer 233 through the fourth redistribution layer 2325.

[0152] It can be understood that the first redistribution layer 2322 and the at least one second conductive layer 2323 are close to the first surface of the chip connecting structure 232, and after etching the medium layer 2351 and the adapter plate structure 231 to expose the at least one conductive column 2312, the third conductive layer 2324 and the fourth redistribution layer 2325 are formed on the other surface (second surface) close to the chip connecting structure 232. In this way, in addition to the chip interconnection of the adapter plate structure 231, the vertical interconnection of each second chip 2321 in each stack layer 23 can also be realized through the at least one third conductive layer 2324 and the fourth redistribution layer 2325, so that the data transmission speed in the stack layer 23 is faster and the interconnection density is higher.

[0153] As shown in Figure 15 repeating the foregoing process steps to form the second layer stack layer 23, and the second layer stack layer 23 also includes the third conductive layer 2324 and the fourth redistribution layer 2325.

[0154] It should be further pointed out that if a number of stack layers 23 need to be stacked on the second layer stack layer 23, please refer to the process steps of other embodiments for understanding, which will not be repeated here.

[0155] The present disclosure provides a preparation method of a packaging structure 20 including a plurality of stacked chips, and the packaging structure 20 prepared by using the method can realize vertical interconnection and packaging of a plurality of chips, increase the number of stacked chips, improve the interconnection density of the chips, and can simplify the process, reduce the stress warping of the packaging structure, and reduce the cost.

[0156] For details not disclosed in the embodiments of the present disclosure, please refer to the description of the foregoing embodiments for understanding.

[0157] In several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are merely illustrative, for example, the division of units is merely a logical functional division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the components shown or discussed.

[0158] The disclosed features in several method or structure embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or structure embodiments.

[0159] The above is only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A package structure, characterized by, The packaging structure comprises a substrate, a first chip and at least one stack layer stacked in sequence along a first direction; each of the stack layers comprises a re-distribution layer structure and at least one chip connecting structure, the at least one chip connecting structure and the re-distribution layer structure are arranged along a second direction; The chip connecting structure comprises a second chip and a first re-distribution layer, the first re-distribution layer is close to a first surface of the chip connecting structure; The re-distribution layer structure comprises a second re-distribution layer and at least one conductive pillar, the second re-distribution layer is close to a first surface of the re-distribution layer structure, and the at least one conductive pillar is electrically connected with the second re-distribution layer; the second chip is electrically connected with the first chip, and the second re-distribution layer is electrically connected with the first chip; Each of the stack layers further comprises a third re-distribution layer close to a first surface of the stack layer, and the at least one conductive pillar is electrically connected with the third re-distribution layer; The chip connecting structure is obtained by cutting an active chip wafer, and the re-distribution layer structure is obtained by cutting a re-distribution layer wafer.

2. The package structure of claim 1, wherein, Each of the stack layers further comprises a first bonding layer on the third re-distribution layer, the first bonding layer is electrically connected with the third re-distribution layer, and adjacent two of the stack layers are electrically connected through the first bonding layer.

3. The package structure of claim 1, wherein, The packaging structure further comprises a plurality of first conductive layers in the first chip; the chip connecting structure further comprises at least one second conductive layer in the second chip, and close to a first surface of the chip connecting structure; The at least one second conductive layer is electrically connected with the first conductive layer through the first re-distribution layer, and the second re-distribution layer is electrically connected with the first conductive layer.

4. The package structure of claim 3, wherein, The chip connecting structure further comprises at least one third conductive layer and a fourth re-distribution layer, the at least one third conductive layer and the fourth re-distribution layer are in the second chip, and close to a second surface of the chip connecting structure; the first surface of the chip connecting structure and the second surface of the chip connecting structure are opposite to each other; The at least one third conductive layer is electrically connected with the third re-distribution layer through the fourth re-distribution layer.

5. The package structure of claim 1, wherein, The chip connecting structure further comprises a second bonding layer on the first surface of the chip connecting structure, the second bonding layer is electrically connected with the first re-distribution layer; the re-distribution layer structure further comprises a third bonding layer on a first surface of the re-distribution layer structure, the third bonding layer is electrically connected with the second re-distribution layer; The chip connecting structure is electrically connected with the first chip through the second bonding layer, and the re-distribution layer structure is electrically connected with the first chip through the third bonding layer.

6. The package structure of claim 1, wherein, Each of the stack layers further comprises a dielectric material filled in a gap of the stack layer.

7. A method for preparing a packaging structure, characterized in that, The method comprises: providing a substrate and a first chip, and arranging the first chip on the substrate along a first direction; forming at least one stack layer on the first chip; Each of the stack layers comprises a redistribution layer structure and at least one chip connecting structure, the at least one chip connecting structure and the redistribution layer structure are arranged along a second direction; the chip connecting structure comprises a second chip and a first redistribution layer, the first redistribution layer is close to a first surface of the chip connecting structure; the redistribution layer structure comprises a second redistribution layer and at least one conductive column, the second redistribution layer is close to a first surface of the redistribution layer structure, and the at least one conductive column is electrically connected with the second redistribution layer; the second chip is electrically connected with the first chip, and the second redistribution layer is electrically connected with the first chip; each of the stack layers further comprises a third redistribution layer close to a first surface of the stack layer, and the at least one conductive column is electrically connected with the third redistribution layer; the chip connecting structure is obtained by cutting an active chip wafer, and the redistribution layer structure is obtained by cutting a redistribution layer wafer.

8. The method of claim 7, wherein, Each of the stack layers is formed by: arranging the redistribution layer structure and the at least one chip connecting structure on the first chip along the second direction; filling a medium layer covering exposed surfaces of the redistribution layer structure and the at least one chip connecting structure, the medium layer being composed of a medium material; performing etching treatment on the medium layer and the redistribution layer structure to expose the at least one conductive column; forming the third redistribution layer and electrically connecting the third redistribution layer with the at least one conductive column.

9. The method of claim 8, wherein, After forming the third redistribution layer, the method further comprises: forming a first bonding layer on the third redistribution layer and electrically connecting the first bonding layer with the third redistribution layer; wherein two adjacent stack layers are electrically connected through the first bonding layer.

10. The method of claim 8, wherein, The packaging structure further comprises a plurality of first conductive layers in the first chip; the chip connecting structure further comprises at least one second conductive layer in the second chip and close to a first surface of the chip connecting structure; the at least one second conductive layer is electrically connected with the first conductive layer through the first redistribution layer, and the second redistribution layer is electrically connected with the first conductive layer; After performing etching treatment on the medium layer and the redistribution layer structure, the method further comprises: forming at least one third conductive layer in the second chip and close to a second surface of the chip connecting structure; the first surface of the chip connecting structure and the second surface of the chip connecting structure are opposite to each other; forming a fourth redistribution layer in the second chip and close to the second surface of the chip connecting structure and electrically connecting the fourth redistribution layer with the at least one third conductive layer; electrically connecting the third redistribution layer with the at least one conductive column comprises: electrically connecting the third redistribution layer with the at least one conductive column and the fourth redistribution layer respectively.

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