Formation method of split-gate memory

Abstract

The invention provides a method for forming a split-gate memory. The method comprises the following steps of: forming a floating gate layer, a gate dielectric layer, a control gate layer and a mask layer with a first opening on a substrate; forming a first side wall and a second opening in the first opening, wherein the second opening exposes part of the surface of the control gate layer; injecting ions into the control gate layer with partial thickness through the second opening; etching the control gate layer by using a ashing machine table and gas capable of etching the silicon material to remove part of the thickness of the control gate layer, and etching part of the control gate layer below the first side wall, so that the rest of the control gate layer forms a slope-shaped groove, and a gap is formed at the junction of the first side wall and the control gate layer; removing the control gate layer exposed from the second opening and partial thickness of the gate dielectric layer; forming a second side wall, wherein the second side wall fills the gap; removing the residual gate dielectric layer and the floating gate layer which are not covered by the second side wall; forming a third side wall, and forming a source line opening; and forming a source line in the source line opening.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a split-gate memory. Background Art

[0002] Flash memory cells have the advantages of high storage density, good reliability and portability. Therefore, they have been widely used in mobile and communication devices such as mobile phones, notebooks and USB flash drives since their introduction. Flash memory cells generally include two structures: stack gate and split gate structure. The split gate structure is currently the most widely used.

[0003] Figures 1 to 3 The schematic diagram of the structure corresponding to the corresponding steps of the method for forming the split gate memory in the prior art is as follows: Figure 1 As shown, a gate oxide layer 112, a floating gate layer 113, and a gate dielectric layer are sequentially formed on a substrate 111, and the gate dielectric layer includes a first oxide layer 114, a nitride layer 115, and a second oxide layer 116. A control gate layer 117 and a mask layer 118 are formed on the second oxide layer 116, and a first opening penetrating the mask layer 118 is formed. A first spacer 119 is also formed on the sidewall of the mask layer 118 in the first opening. Figure 2 As shown, the control gate layer 117, the second oxide layer 116 and the nitride layer 115 exposed in the first opening are etched to expose the surface of the first oxide layer 114. The sidewalls of the remaining control gate layer 117 are vertical and the tip is a right angle. Figure 3 , forming a second spacer 120, the second spacer 120 covers the sidewalls of the control gate layer 117, the sidewalls of the second oxide layer 116 and the sidewalls of the nitride layer 115. Etching the first oxide layer 114 and the floating gate layer 113 to expose the surface of the gate oxide layer 112, forming a third spacer 121, the third spacer 121 covers part of the first spacer 119, the sidewalls of the first oxide layer 114 and the sidewalls of the floating gate layer 113, thereby forming a source line opening. Finally, forming a source line in the source line opening.

[0004] However, if Figure 4 As shown, Figure 4 This is a schematic diagram of the electron microscope structure of a split-gate memory. Since the sharp corner of the control gate layer 117 is a right angle and is relatively sharp, and the second sidewall 120 here is relatively thin, the sharp corner of the control gate layer 117 may break through the second sidewall 120, causing the second sidewall 120 to break, resulting in leakage and breakdown of the device, thereby reducing the reliability of the memory. Summary of the invention

[0005] The object of the present invention is to provide a method for forming a split-gate memory, which can reduce the risk of second sidewall fracture, reduce the risk of device leakage and breakdown, and improve the reliability of the memory.

[0006] In order to achieve the above object, the present invention provides a method for forming a split-gate memory, comprising:

[0007] Providing a substrate, and sequentially forming a floating gate layer, a gate dielectric layer, a control gate layer, and a mask layer having a first opening on the substrate, wherein the first opening exposes a portion of the surface of the control gate layer;

[0008] forming a first sidewall spacer in the first opening, the first sidewall spacer covering the sidewall of the mask layer, and forming a second opening by the first sidewall spacer, the second opening exposing a portion of the surface of the control gate layer;

[0009] Implanting ions into a portion of the thickness of the control gate layer through the second opening;

[0010] Etching the control gate layer using an ashing machine and a gas capable of etching silicon materials to remove a portion of the control gate layer, and etching a portion of the control gate layer below the first sidewall, so that the remaining control gate layer forms a slope-shaped groove, and a notch is formed at the junction of the first sidewall and the control gate layer;

[0011] removing the control gate layer and a portion of the gate dielectric layer exposed by the second opening;

[0012] forming a second sidewall spacer, wherein the second sidewall spacer covers the first sidewall spacer, the sidewall of the control gate layer and a portion of the sidewall of the gate dielectric layer, and the second sidewall spacer fills the gap;

[0013] removing the remaining gate dielectric layer and floating gate layer not covered by the second sidewall spacer;

[0014] forming a third spacer, wherein the third spacer covers the second spacer, the sidewall of the gate dielectric layer and the sidewall of the floating gate layer, and forms a source line opening;

[0015] A source line is formed in the source line opening.

[0016] Optionally, in the method for forming a split-gate memory, the substrate includes a wafer.

[0017] Optionally, in the method for forming the split-gate memory, arsenic ions are implanted into a portion of the thickness of the control gate layer through the second opening.

[0018] Optionally, in the method for forming a split-gate memory, materials of the floating gate layer and the control gate layer both include polysilicon.

[0019] Optionally, in the method for forming a split-gate memory, the gate dielectric layer includes a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence.

[0020] Optionally, in the method for forming the split-gate memory, the method further includes: forming a gate oxide layer on the surface of the substrate, wherein the gate oxide layer is located between the substrate and the floating gate layer.

[0021] Optionally, in the method for forming the split-gate memory, the method for forming a source line in the source line opening includes:

[0022] Filling a polysilicon layer into the source line opening;

[0023] The surface of the polysilicon layer is ground to form a source line.

[0024] Optionally, in the method for forming the split-gate memory, after forming the source line in the source line opening, the method further includes:

[0025] The mask layer and the control gate layer, the gate dielectric layer and the floating gate layer located below the mask layer are removed.

[0026] Optionally, in the method for forming the split-gate memory, the control gate layer exposed by the second opening and a portion of the gate dielectric layer are removed by etching.

[0027] Optionally, in the method for forming the split-gate memory, the remaining gate dielectric layer and floating gate layer not covered by the second sidewall spacer are removed by etching.

[0028] The method for forming a split-gate memory provided by the present invention comprises: providing a substrate, sequentially forming a floating gate layer, a gate dielectric layer, a control gate layer and a mask layer having a first opening on the substrate, wherein the first opening exposes a portion of the surface of the control gate layer; forming a first sidewall in the first opening, wherein the first sidewall covers the sidewall of the mask layer, and the first sidewall forms a second opening, wherein the second opening exposes a portion of the surface of the control gate layer; injecting ions into a portion of the control gate layer through the second opening; etching the control gate layer using an ashing machine and a gas capable of etching silicon materials to remove a portion of the control gate layer, and etching a portion of the first sidewall. The control gate layer below the sidewall forms a slope-shaped groove in the remaining control gate layer, and a gap is formed at the junction of the first sidewall and the control gate layer; the control gate layer and the gate dielectric layer with a partial thickness exposed by the second opening are removed; a second sidewall is formed, the second sidewall covers the first sidewall, the sidewall of the control gate layer and the sidewall of a portion of the gate dielectric layer, and the second sidewall fills the gap; the remaining gate dielectric layer and the floating gate layer not covered by the second sidewall are removed; a third sidewall is formed, the third sidewall covers the second sidewall, the sidewall of the gate dielectric layer and the sidewall of the floating gate layer, and a source line opening is formed; a source line is formed in the source line opening. The remaining control gate layer of the present invention forms a slope-shaped groove, a gap is formed at the junction of the first sidewall and the control gate layer, and when the second sidewall covers the first sidewall, the sidewall of the control gate layer and the sidewall of a portion of the gate dielectric layer, the second sidewall fills the gap. The corner of the control gate of the present invention will not break the second sidewall, which reduces the probability of the second sidewall breaking, reduces the leakage and breakdown probability of the device, and improves the reliability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 to Figure 2 It is a structural schematic diagram corresponding to the corresponding steps of the method for forming a split-gate memory in the prior art;

[0030] Figure 3 It is a schematic diagram of the electron microscope structure of a split-gate memory;

[0031] Figure 4 is a flow chart of a method for forming a split-gate memory according to an embodiment of the present invention;

[0032] Figures 5 to 11 It is a structural schematic diagram corresponding to corresponding steps of a method for forming a split-gate memory according to an embodiment of the present invention;

[0033] In the figure: 111-substrate, 112-gate oxide layer, 113-floating gate layer, 114-first oxide layer, 115-nitride layer, 116-second oxide layer, 117-control gate layer, 118-mask layer, 119-first side wall, 120-second side wall, 121-third side wall, 211-substrate, 212-gate oxide layer, 213-floating gate layer, 214-first oxide layer, 215-nitride layer, 216-second oxide layer, 217-control gate layer, 218-mask layer, 219-first side wall, 220-second side wall, 221-third side wall, 222-source line. DETAILED DESCRIPTION

[0034] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0036] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0037] Please refer to Figure 4 The present invention provides a method for forming a split-gate memory, comprising:

[0038] S11: providing a substrate, and sequentially forming a floating gate layer, a gate dielectric layer, a control gate layer, and a mask layer having a first opening on the substrate, wherein the first opening exposes a portion of the surface of the control gate layer;

[0039] S12: forming a first sidewall spacer in the first opening, the first sidewall spacer covers the sidewall of the mask layer, and the first sidewall spacer forms a second opening, the second opening exposes a portion of the surface of the control gate layer;

[0040] S13: injecting ions into a portion of the control gate layer through the second opening;

[0041] S14: etching the control gate layer using an ashing machine and a gas capable of etching silicon materials to remove a portion of the control gate layer, and etching a portion of the control gate layer below the first sidewall spacer, so that the remaining control gate layer forms a slope-shaped groove, and a notch is formed at the junction of the first sidewall spacer and the control gate layer;

[0042] S15: removing the control gate layer and a portion of the gate dielectric layer exposed by the second opening;

[0043] S16: forming a second sidewall spacer, wherein the second sidewall spacer covers the first sidewall spacer, the sidewall of the control gate layer and a portion of the sidewall of the gate dielectric layer, and at the same time, the second sidewall spacer fills the gap;

[0044] S17: removing the remaining gate dielectric layer and floating gate layer not covered by the second spacer;

[0045] S18: forming a third spacer, the third spacer covers the second spacer, the sidewall of the gate dielectric layer and the sidewall of the floating gate layer, and forms a source line opening;

[0046] S19: forming a source line in the source line opening.

[0047] Please refer to Figure 5 First, a substrate 211 is provided. The substrate 211 may be a silicon substrate, such as a wafer. Next, a gate oxide layer 212 is formed on the surface of the substrate 211. The material of the gate oxide layer 212 may be silicon dioxide and may be formed by deposition. Next, a floating gate layer 213 is formed on the surface of the gate oxide layer 212. The material of the floating gate layer 213 may be polysilicon and may be formed by deposition. Next, a gate dielectric layer is formed on the surface of the floating gate layer 213. The gate dielectric layer includes a first oxide layer 214, a nitride layer 215, and a second oxide layer 216. The materials of the first oxide layer 214 and the second oxide layer 216 may be silicon dioxide, and the material of the nitride layer 215 may be silicon nitride. The method for forming the gate dielectric layer may be a method of sequentially depositing the first oxide layer 214, the nitride layer 215, and the second oxide layer 216. Next, a control gate layer 217 and a mask layer 218 are formed on the surface of the second oxide layer 216. The material of the control gate layer 217 is polysilicon. The mask layer 218 is etched to form a first opening penetrating the mask layer 218. Next, a first spacer 219 is formed on the sidewall of the mask layer 218 in the first opening.

[0048] Next, please refer to Figure 6 and Figure 7, ions are injected into the shallow layer of the control gate layer 217 through the first opening, so that the control gate layer 217 of a part of the thickness contains ions, and in addition to injecting ions vertically to the surface of the control gate layer 217, ions can also be injected at a certain angle to the surface of the control gate layer 217, so that the shallow layer of the control gate layer 217 at the bottom of the first sidewall 219 also contains ions. The ions injected in the embodiment of the present invention can be arsenic ions. Then, the control gate layer 217 is etched using an ashing machine and a gas that can etch silicon materials. Since the control gate layer 217 is amorphized after the previous injection of ions, the speed of etching the control gate layer 217 is increased. Therefore, this etching can remove the control gate layer 217 of a part of the thickness, and etch the control gate layer 217 under the part of the sidewall, so that the remaining control gate layer 217 forms a slope-shaped groove.

[0049] Next, please refer to Fig. 9 , etch the remaining control gate layer 217, the second oxide layer 216 and the nitride layer 215 that are not covered by the first sidewall 219 in the first opening to expose the surface of the first oxide layer 214. The remaining control gate layer 217 will not have a vertical sharp corner, and the original sharp corner is sloped. Next, form a second sidewall 220, and the second sidewall 220 covers the sidewalls of the control gate layer 217, the sidewalls of the second oxide layer 216 and the sidewalls of the nitride layer 215. Since the control gate layer 217 has no vertical sharp corners, the height of its sharp corners is lower than that of the sharp corners in the prior art, so the corresponding thickness of the second sidewall 220 is increased, which reduces the probability of the corner of the control gate breaking through the second sidewall 220 and reduces the probability of the second sidewall breaking. Next, please refer to Fig.10 , the first oxide layer 214 and the floating gate layer 213 are etched to expose the surface of the gate oxide layer 212, and a third sidewall 221 is formed. The third sidewall 221 covers part of the first sidewall 219, the sidewall of the first oxide layer 214 and the sidewall of the floating gate layer 213, thereby forming a source line opening.

[0050] Next, please refer to Fig.11 , filling polysilicon in the source line opening, grinding the surface of the polysilicon, thereby forming a source line 222 in the source line opening.

[0051] In summary, the method for forming a split-gate memory provided in an embodiment of the present invention includes: providing a substrate, sequentially forming a floating gate layer, a gate dielectric layer, a control gate layer, and a mask layer having a first opening on the substrate, wherein the first opening exposes a portion of the surface of the control gate layer; forming a first sidewall in the first opening, wherein the first sidewall covers the sidewall of the mask layer, and the first sidewall forms a second opening, wherein the second opening exposes a portion of the surface of the control gate layer; injecting ions into a portion of the control gate layer through the second opening; etching the control gate layer using an ashing machine and a gas capable of etching silicon materials to remove a portion of the control gate layer, and etching a portion of the control gate layer. The control gate layer below the first sidewall is divided, so that the remaining control gate layer forms a groove in the shape of a slope, and a gap is formed at the junction of the first sidewall and the control gate layer; the control gate layer and the gate dielectric layer with a partial thickness exposed by the second opening are removed; a second sidewall is formed, the second sidewall covers the first sidewall, the sidewall of the control gate layer and the sidewall of a part of the gate dielectric layer, and at the same time, the second sidewall fills the gap; the remaining gate dielectric layer and floating gate layer not covered by the second sidewall are removed; a third sidewall is formed, the third sidewall covers the second sidewall, the sidewall of the gate dielectric layer and the sidewall of the floating gate layer, and a source line opening is formed; a source line is formed in the source line opening. The remaining control gate layer of the present invention forms a groove in the shape of a slope, a gap is formed at the junction of the first sidewall and the control gate layer, and when the second sidewall covers the first sidewall, the sidewall of the control gate layer and the sidewall of a part of the gate dielectric layer, the second sidewall fills the gap. The corner of the control gate of the present invention will not break the second sidewall, which reduces the probability of the second sidewall breaking, reduces the leakage and breakdown probability of the device, and improves the reliability of the memory.

[0052] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for forming a split-gate memory, characterized in that: include: Providing a substrate, and sequentially forming a floating gate layer, a gate dielectric layer, a control gate layer, and a mask layer having a first opening on the substrate, wherein the first opening exposes a portion of the surface of the control gate layer; forming a first sidewall spacer in the first opening, the first sidewall spacer covering the sidewall of the mask layer, and forming a second opening by the first sidewall spacer, the second opening exposing a portion of the surface of the control gate layer; Implanting ions into a portion of the thickness of the control gate layer through the second opening; Etching the control gate layer using an ashing machine and a gas capable of etching silicon materials to remove a portion of the control gate layer, and etching a portion of the control gate layer below the first sidewall, so that the remaining control gate layer forms a slope-shaped groove, and a notch is formed at the junction of the first sidewall and the control gate layer; removing the control gate layer and a portion of the gate dielectric layer exposed by the second opening; forming a second sidewall spacer, wherein the second sidewall spacer covers the first sidewall spacer, the sidewall of the control gate layer and a portion of the sidewall of the gate dielectric layer, and the second sidewall spacer fills the gap; removing the remaining gate dielectric layer and floating gate layer not covered by the second sidewall spacer; forming a third spacer, wherein the third spacer covers the second spacer, the sidewall of the gate dielectric layer and the sidewall of the floating gate layer, and forms a source line opening; A source line is formed in the source line opening.

2. The method for forming a split gate memory according to claim 1, wherein: The substrate includes a wafer.

3. The method for forming a split gate memory according to claim 1, wherein: Arsenic ions are implanted into a portion of the thickness of the control gate layer through the second opening.

4. The method for forming a split gate memory according to claim 1, wherein: The materials of the floating gate layer and the control gate layer both include polysilicon.

5. The method for forming a split gate memory according to claim 1, wherein: The gate dielectric layer includes a first oxide layer, a nitride layer and a second oxide layer which are stacked in sequence.

6. The method for forming a split gate memory according to claim 1, wherein: Also includes: A gate oxide layer is formed on the surface of the substrate, and the gate oxide layer is located between the substrate and the floating gate layer.

7. The method for forming a split gate memory according to claim 1, wherein: The method of forming a source line in the source line opening includes: Filling a polysilicon layer into the source line opening; The surface of the polysilicon layer is ground to form a source line.

8. The method for forming a split gate memory according to claim 1, wherein: After forming a source line in the source line opening, the method further includes: The mask layer and the control gate layer, the gate dielectric layer and the floating gate layer located below the mask layer are removed.

9. The method for forming a split gate memory according to claim 1, wherein: The control gate layer and a portion of the gate dielectric layer exposed by the second opening are removed by etching.

10. The method for forming a split gate memory according to claim 1, wherein: The remaining gate dielectric layer and floating gate layer not covered by the second sidewall spacer are removed by etching.

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