Semiconductor memory device and electronic system including the same

Abstract

The semiconductor memory device includes a peripheral circuit structure including a peripheral circuit; a stacked structure on the peripheral circuit structure and including first electrode layers and first inter-electrode insulating layers alternately stacked; a first vertical pattern extending into the stack structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a line separation pattern extending into the second insulating layer, the second electrode layer, and the first insulating layer; and a second vertical pattern extending into the second insulating layer, the second electrode layer, and the first insulating layer, in which the second vertical pattern is electrically connected to the first vertical pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0096632 filed in the Korean Intellectual Property Office on July 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor memory device and an electronic system including the semiconductor memory device. Background Art

[0004] Semiconductor devices for storing high-capacity data in electronic systems requiring data storage are needed. Therefore, measures for increasing the data storage capacity of semiconductor devices have been studied. For example, as a method of increasing the data storage capacity of semiconductor devices, semiconductor devices including three-dimensionally arranged storage cells (rather than two-dimensionally arranged storage cells) have been proposed. Summary of the invention

[0005] An object of the present disclosure is to provide a semiconductor device with improved reliability and integration.

[0006] An object of the present disclosure is to provide an electronic system including a semiconductor device having improved reliability.

[0007] The problems to be solved by the present disclosure are not limited to the above-mentioned problems, and those skilled in the art will clearly understand other problems not mentioned from the following description.

[0008] According to some embodiments of the present disclosure, a semiconductor memory device includes: a peripheral circuit structure, including a peripheral circuit; a stacked structure, on the peripheral circuit structure, and including alternately stacked first electrode layers and first inter-electrode insulating layers; a first vertical pattern, extending into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a line separation pattern, extending into the second insulating layer, the second electrode layer and the first insulating layer; and a second vertical pattern, extending into the second insulating layer, the second electrode layer and the first insulating layer, wherein the second vertical pattern is electrically connected to the first vertical pattern.

[0009] According to some embodiments of the present disclosure, a semiconductor memory device includes: a substrate; a peripheral circuit structure including a peripheral circuit on the substrate, the peripheral circuit structure including a first bonding pad electrically connected to the peripheral circuit; and a cell array structure including a second bonding pad electrically connected to the first bonding pad, wherein the cell array structure includes: a stacked structure including alternately stacked first electrode layers and first inter-electrode insulating layers; a block separation pattern extending into the stacked structure; a central separation pattern extending into the stacked structure and between the block separation patterns; a first vertical pattern extending into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a first line separation pattern extending into the second insulating layer, the second electrode layer and the first insulating layer, wherein the first line separation pattern is respectively on the block separation pattern; a second line separation pattern extending into the second insulating layer, the second electrode layer and the first insulating layer, wherein the second line separation pattern is on the central separation pattern; and a second vertical pattern extending into the second insulating layer, the second electrode layer and the first insulating layer, wherein the second vertical pattern is respectively on the first vertical pattern.

[0010] According to some embodiments of the present disclosure, the electronic system includes: a semiconductor memory device, including a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure; and a controller, electrically connected to the semiconductor memory device through an input / output pad and configured to control the semiconductor memory device, wherein the cell array structure includes: a stacked structure, on the peripheral circuit structure, and including alternately stacked first electrode layers and first inter-electrode insulating layers; a first vertical pattern, extending into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a line separation pattern, extending into the second insulating layer, the second electrode layer and the first insulating layer; and a second vertical pattern, extending into the second insulating layer, the second electrode layer and the first insulating layer, wherein the second vertical pattern is electrically connected to the first vertical pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments described herein.

[0012] Figure 1 is a diagram schematically showing an electronic system including a semiconductor memory device according to an embodiment of the present invention.

[0013] Figure 2 is a perspective view schematically showing an electronic system including a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 3 and Figure 4is a cross-sectional view schematically illustrating a semiconductor package according to an embodiment of the present disclosure.

[0015] Figure 5 is a plan view of a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 6 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line AA′.

[0017] Figure 7 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line BB′.

[0018] Fig. 8A , Figure 8B , Figure 8C and Fig.8D According to the embodiment of the present disclosure Figure 6 Magnified view of the “P2” section in Figure 2.

[0019] Fig. 9 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line AA′.

[0020] Fig.10 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line BB′.

[0021] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F , Fig.11G and Fig.11H is a sequence showing the manufacturing of Figure 6 A cross-sectional diagram of a semiconductor memory device process.

[0022] Fig. 12A , Fig. 12B and Fig. 12C yes Fig.11E The enlarged view of the "P2" portion of the Figure 6 A cross-section of a semiconductor memory device process.

[0023] Fig.13A , Fig. 13B and Fig. 13C is a sequence showing the manufacturing of Figure 7 A cross-sectional diagram of a semiconductor memory device process. DETAILED DESCRIPTION

[0024] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are referred to by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent elements shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0025] It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be an intermediate element. In contrast, when an element is referred to as being "directly" "on" another element, there is no intermediate element. In addition, for ease of description, spatial relative terms such as "under", "below", "below", "above", "on", etc. can be used in this article to describe the relationship of an element or feature relative to another element or feature as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the element described as being "under" or "under" other elements or features will be oriented "above" other elements or features. Therefore, the term "below" can include both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article can be interpreted accordingly.

[0026] In addition, unless explicitly described to the contrary, the word "include" and variants such as "contain" or "include" will be understood to mean including the elements set forth, but not excluding any other elements. As used herein, the phrase "at least one of A, B, and C" refers to the logic (A OR B OR C) using a non-exclusive logical OR, and should not be interpreted as meaning "at least one of A, at least one of B, and at least one of C". As used herein, the singular forms "one", "an", and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include", "contain" and / or "include" when used herein indicate the presence of the features, steps, operations, elements, and / or parts set forth, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The term "and / or" includes any and all combinations of one or more items in the associated listed items. The term "connection" may be used herein to refer to physical and / or electrical connections, and may refer to direct or indirect physical and / or electrical connections.

[0027] As used herein, "element A is at a higher level than element B" or "element A is at a lower level than element B" means that at least one surface of element A is not coplanar with at least one surface of element B and / or at least one surface of element A is spaced apart from a reference element by a distance that is different from the distance that separates element B from the reference element. As an example, "element A is at a higher level than element B" means that element A is spaced apart from the reference element by a distance that is greater than the distance that separates element B from the reference element. Components or layers described as "overlapping" in a particular direction may be at least partially obscured from each other when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction.

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a diagram schematically illustrating an electronic system including a semiconductor memory device according to an embodiment of the inventive concept.

[0030] Reference Figure 1 , the electronic system 1000 according to some embodiments of the present disclosure may include a semiconductor device 1100 and a controller 1200 electrically connected to each other. The electronic system 1000 may be or may include a storage device including one or more semiconductor devices 1100 and / or an electronic device including the storage device. For example, the electronic system 1000 may be or may include at least one of a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical system, or a communication system, in which at least one semiconductor device 1100 is provided.

[0031] The semiconductor device 1100 may be a nonvolatile memory device such as a NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. As an example, the first structure 1100F may be disposed adjacent to the second structure 1100S.

[0032] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0033] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary according to the embodiment.

[0034] In an embodiment, at least one of the upper transistors UT1 and UT2 may include a string selection transistor, and at least one of the lower transistors LT1 and LT2 may include a ground selection transistor. The gate lower lines LL1 and LL2 may correspond to the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may correspond to the gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may correspond to the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0035] In an embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used for an erase operation of erasing data stored in the memory cell transistor MCT using a gate induced drain leakage (GIDL) phenomenon.

[0036] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from a region in the first structure 1100F to a region in the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection line 1125 extending from a region in the first structure 1100F to a region in the second structure 1100S.

[0037] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may be configured to control an operation performed by the selection memory cell transistor on at least one of the memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135, which is provided in the first structure 1100F and extends into the second structure 1100S.

[0038] Although not shown, the first structure 1100F may include a voltage generator (not shown). The voltage generator may generate at least one of a program voltage, a read voltage, a pass voltage, a verification voltage, etc. for operating the memory cell string CSTR. Here, the program voltage may be a relatively high voltage (e.g., 20V to 40V) compared to any one of the read voltage, the pass voltage, and the verification voltage.

[0039] In some embodiments, the first structure 1100F may include a high voltage transistor and a low voltage transistor. The decoder circuit 1110 may include a pass transistor connected to the word line WL of the memory cell string CSTR. The pass transistor may include a high voltage transistor configured to operate at a high voltage (e.g., a programming voltage applied to the word line WL during a programming operation). The page buffer 1120 may also include a high voltage transistor configured to operate at a high voltage.

[0040] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In an embodiment, the electronic system 1000 may include a plurality of semiconductor memory devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100 .

[0041] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on a specific firmware, and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 for communicating with the semiconductor device 1100. The NAND interface 1221 may be used to send and receive control commands for controlling the semiconductor device 1100, data to be written to or read from the memory cell transistors MCT of the semiconductor device 1100, and the like. The host interface 1230 may allow communication between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0042] Figure 2 is a perspective view schematically showing an electronic system including a semiconductor memory device according to an embodiment of the present disclosure.

[0043] Reference Figure 2, the electronic system 2000 according to an embodiment of the present disclosure may include a main substrate 2001 and a controller 2002 mounted on the main substrate 2001, at least one semiconductor package 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 and to each other through a wiring pattern 2005 formed in the main substrate 2001.

[0044] The main substrate 2001 may include a connector 2006 including a plurality of pins coupled to an external host. In the connector 2006, the number and arrangement of the pins may depend on the communication interface between the electronic system 2000 and the external host. In an embodiment, the electronic system 2000 may communicate with an external host according to a known interface, such as a universal serial bus (USB), a peripheral component interconnect fast (PCI-Express), a serial advanced technology attachment (SATA), a universal flash memory (UFS) M-Phy, etc. In an embodiment, the electronic system 2000 may be driven by power provided from an external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power provided from an external host to the controller 2002 and the semiconductor package 2003.

[0045] The controller 2002 may control a write or read operation on the semiconductor package 2003 and may increase an operation speed of the electronic system 2000 .

[0046] DRAM 2004 may be a buffer memory that alleviates technical difficulties caused by the speed difference between semiconductor package 2003 as a data storage device and an external host. In an embodiment, DRAM 2004 in electronic system 2000 may be used as a high-speed cache memory and may provide a storage space to temporarily store data during a control operation of semiconductor package 2003. In the case where electronic system 2000 includes DRAM 2004, controller 2002 may include a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0047] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include: a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on each bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 disposed on the package substrate 2100 to cover the semiconductor chip 2200 and the connection structure 2400.

[0048] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 1 Input / output pads 1101. Each semiconductor chip 2200 may include a gate stack 3210 and a vertical structure 3220. Each semiconductor chip 2200 may include a semiconductor device according to an embodiment of the present disclosure which will be described below.

[0049] In an embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In other embodiments, the semiconductor chips 2200 in each of the first semiconductor package 2003a and the second semiconductor package 2003b may be electrically connected to each other through a connection structure including a through silicon via (TSV) instead of being electrically connected to each other through the connection structure 2400 provided in the form of a bonding wire.

[0050] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In an embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate prepared independently of the main substrate 2001 and may be connected to each other through wiring provided in the interposer substrate.

[0051] Figure 3 and Figure 4 is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. Figure 3 and Figure 4 is along Figure 2, and conceptually shows Figure 2 Embodiments of a semiconductor package.

[0052] Reference Figure 3 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include: a package substrate main body 2120, a package upper pad 2130 (eg, Figure 2 The package upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the wiring pattern 2005 provided in the main substrate 2001 of the electronic system 2000 through the conductive connection portion 2800, as shown in FIG. Figure 2 shown.

[0053] Each semiconductor chip 2200 may include a semiconductor substrate 3010, and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region in which a peripheral line 3110 is disposed. The second structure 3200 may include a source structure 3205, a stack 3210 on the source structure 3205, a vertical structure 3220 and a separation structure 3230 extending into the stack 3210, a bit line 3240 electrically connected to the vertical structure 3220, and a word line WL (e.g., a word line WL) electrically connected to the stack 3210. Figure 1 Each of the first and second structures 3100 and 3200 and the semiconductor chip 2200 may further include a separate structure which will be described below.

[0054] Each semiconductor chip 2200 may include a penetration wire 3245 electrically connected to the peripheral wire 3110 of the first structure 3100 and extending into the second structure 3200. The penetration wire 3245 may be disposed outside the stack 3210, and in an embodiment, the penetration wire 3245 may be disposed to extend into the stack 3210. Each semiconductor chip 2200 may also include an input / output pad 2210 (e.g., see FIG. 2 ) electrically connected to the peripheral wire 3110 of the first structure 3100. Figure 2 Input / output pad 2210).

[0055] Reference Figure 4In the semiconductor package 2003A, each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 on the first structure 4100 and bonded to the first structure 4100 in a wafer bonding manner.

[0056] The first structure 4100 may include a peripheral circuit region in which a peripheral line 4110 and a first junction structure 4150 are disposed. The second structure 4200 may include a source structure 4205, a stack 4210 between the source structure 4205 and the first structure 4100, a vertical structure 4220 and a separation structure 4230 extending into the stack 4210, and word lines WL (e.g., Figure 1 For example, the second junction structure 4250 may be electrically connected to the bit line 4240 electrically connected to the vertical structure 4220 and to the word line WL (eg, Figure 1 The cell contact plugs 4235 electrically connected to the word lines WL) are respectively electrically connected to the vertical structures 4220 and the word lines WL (eg, Figure 1 The first junction structure 4150 of the first structure 4100 may contact and be coupled to the second junction structure 4250 of the second structure 4200. A coupling portion of the first junction structure 4150 and the second junction structure 4250 may be formed of or include, for example, copper (Cu).

[0057] Each of the first structure 4100, the second structure 4200 and the semiconductor chip 2200a may further include a source structure, as will be described below with reference to the embodiments. Each semiconductor chip 2200a may further include an input / output pad 2210 (e.g., Figure 2 Input / output pad 2210).

[0058] Figure 3 or Figure 4 The semiconductor chips 2200 or 2200a may be electrically connected to each other through a connection structure 2400 provided in the form of a bonding wire. Figure 3 or Figure 4 The semiconductor chips 2200 or 2200 a in the same semiconductor package may be electrically connected to each other through a connection structure including through silicon vias (TSVs).

[0059] Figure 3 The first structure 3100 and Figure 4 The first structure 4100 may correspond to the peripheral circuit structure in the embodiment to be described below, and Figure 3 The second structure 3200 and Figure 4 The second structure 4200 may correspond to a cell array structure in an embodiment to be described below.

[0060] Figure 5 is a plan view of a semiconductor memory device according to an embodiment of the present disclosure. Figure 6 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line AA′. Figure 7 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line BB′.

[0061] Reference Figure 5 , Figure 6 , Figure 7 , a semiconductor memory device according to an embodiment of the present disclosure may include a substrate 10 , a peripheral circuit structure PS on the substrate 10 , and a cell array structure CS on the peripheral circuit structure PS.

[0062] According to an embodiment, the cell array structure CS can be coupled to the peripheral circuit structure PS to increase the cell capacity per unit area of ​​the semiconductor memory device according to the present disclosure. In addition, the peripheral circuit structure PS and the cell array structure CS can be manufactured separately and coupled to each other, so damage to the peripheral circuit PTR caused by various heat treatment processes can be suppressed, thereby improving the electrical characteristics and reliability of the semiconductor memory device according to the present disclosure.

[0063] Specifically, the peripheral circuit structure PS can be integrated on the front surface of the substrate 10, and can include a peripheral circuit PTR that controls a memory cell array, a peripheral contact plug PCP, a peripheral circuit wiring PLP electrically connected to the peripheral circuit PTR through the peripheral contact plug PCP, a first bonding pad BP1 electrically connected to the peripheral circuit wiring PLP, and a lower insulating layer 50 that at least partially surrounds at least one of the peripheral circuit PTR, the peripheral contact plug PCP, the peripheral circuit wiring PLP and the first bonding pad BP1.

[0064] The substrate 10 may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. The substrate 10 may have an upper surface parallel to a first direction D1 and a second direction D2 intersecting the first direction D1 and orthogonal to a third direction D3. For example, the first to third directions D1, D2, and D3 may be directions orthogonal to each other. A device isolation layer 11 may be disposed within the substrate 10. The device isolation layer 11 may define an active region of the substrate 10.

[0065] The peripheral circuit PTR may include reference Figure 1The row and column decoders, page buffers and control circuits described above are shown in FIG. 1. Specifically, the peripheral circuit PTR may include NMOS and PMOS transistors. The transistors constituting the peripheral circuit PTR may be disposed on an active region of the substrate 10.

[0066] For example, when the peripheral contact plug PCP extends in the third direction D3, the width of the peripheral contact plug PCP may increase in the first direction D1 or the second direction D2. The peripheral contact plug PCP and the peripheral circuit wiring PLP may include a conductive material such as metal.

[0067] The lower insulating layer 50 may include an insulating layer stacked in multiple layers. For example, the lower insulating layer 50 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and / or a low dielectric layer. As an example, the lower insulating layer 50 may include a first lower insulating layer 51, a second lower insulating layer 55, and an etch stop layer 53 between the first lower insulating layer 51 and the second lower insulating layer 55. The etch stop layer 53 may include an insulating material different from the first lower insulating layer 51 and the second lower insulating layer 55, and may cover the upper surface of the uppermost peripheral circuit wiring PLP or overlap with the upper surface of the uppermost peripheral circuit wiring PLP. In addition, the surface insulating layer 201 may be disposed on the lower surface of the substrate 10.

[0068] The first bonding pad BP1 may be disposed in the uppermost lower insulating layer 50. The lower insulating layer 50 may not cover the upper surface of the first bonding pad BP1 or overlap the upper surface of the first bonding pad BP1. The upper surface of the uppermost lower insulating layer 50 may be substantially coplanar with the upper surface of the first bonding pad BP1. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through the peripheral circuit wiring PLP and the peripheral contact plug PCP.

[0069] The cell array structure CS may be disposed on the peripheral circuit structure PS. The cell array structure CS of the semiconductor memory device may include a cell array region CAR, a first connection region CNR1, and a second connection region CNR2 adjacent to each other in a first direction D1.

[0070] The cell array structure CS may include a memory cell array including memory cells arranged in three dimensions. The cell array structure CS may include a source conductive pattern SCP, a third electrode layer GE3, a stacked structure ST, a first vertical pattern VS1 and a second vertical pattern VS2, a third vertical pattern VS3, a bit line BL, a cell contact plug CPLG, a peripheral contact plug PPLG, and an input / output contact plug IOPLG. The third electrode layer GE3 may be a ground selection gate pattern GGE. The ground selection gate pattern GGE may also be referred to as a ground selection line. The “vertical pattern” in the first vertical pattern VS1 and the third vertical pattern VS3 may also be referred to as a “vertical semiconductor pattern” or a “vertical channel pattern”.

[0071] When Figure 5 When viewed in a plan view of FIG. 1 , the plurality of stacked structures ST may extend in the first direction D1 and be spaced apart from each other in the second direction D2. Hereinafter, for convenience of explanation, a single stacked structure ST will be described, but the following description may be applied to other stacked structures ST.

[0072] The stacked structure ST may include first and second electrode layers GE1 and GE2 and first and second inter-electrode insulating layers ILD1 and ILD2 that are alternately stacked in a third direction D3 (ie, a vertical direction).

[0073] In an embodiment, the first electrode layer GE1 may include a first erase gate pattern EGE1 and a second erase gate pattern EGE2 adjacent to the third electrode layer GE3, and a plurality of cell gate patterns CGE below the second erase gate pattern EGE2. The second electrode layer GE2 may include a plurality of cell gate patterns CGE, and a string selection gate pattern SGE located below the lowermost cell gate pattern CGE.

[0074] The erase control gate patterns EGE1 and EGE2 may be adjacent to the third electrode layer GE3 and may correspond to the erase control transistor LT1 or LT2 ( Figure 1 The gate pattern of the erase control transistor LT1 or LT2 in the memory cell array controls the erase operation by generating a gate induced drain leakage (GIDL) of the memory cell array. The ground selection gate pattern GGE as the third electrode layer (GE3) may correspond to the control common source line CSL ( Figure 1 The ground selection transistor LT1 or LT2 ( Figure 1 The cell gate pattern CGE may correspond to the gate pattern of the memory cell transistor MCT ( Figure 1 The word line WL ( Figure 1The uppermost string selection gate pattern SGE may correspond to a string selection transistor UT1 or UT2 ( UT2 ) that controls electrical connection between the bit line BL and the first vertical pattern VS1 . Figure 1 The gate pattern of the string selection transistor UT1 or UT2).

[0075] In another example, the first electrode layer GE1 may not include the first erase gate pattern EGE1 and the second erase gate pattern EGE2. The first electrode layer GE1 may include only the cell gate pattern CGE. Some of the second electrode layers GE2 may function as erase gates.

[0076] Refer again Figures 5 to 7 The first electrode layer GE1 and the second electrode layer GE2 of the stack structure ST may be stacked in the first connection region CNR1 to have an inverted staircase structure. That is, the lengths of the first electrode layer GE1 and the second electrode layer GE2 may increase along the first direction D1 as the distance from the peripheral circuit structure PS increases.

[0077] In the first connection region CNR1, the first electrode layer GE1, the second electrode layer GE2, and the third electrode layer GE3 may each include a pad portion. The pad portion of each of the first electrode layer GE1, the second electrode layer GE2, and the third electrode layer GE3 may be located at different horizontal and vertical positions. The cell contact plug CPLG may be connected to the pad portions of the first electrode layer GE1, the second electrode layer GE2, and the third electrode layer GE3, respectively.

[0078] In an embodiment, the stacked structure ST may include a first stacked structure ST1 and a second stacked structure ST2 on the first stacked structure ST1. The first stacked structure ST1 may include alternately stacked first inter-electrode insulating layers ILD1 and first electrode layers GE1, and the second stacked structure ST2 may include alternately stacked second inter-electrode insulating layers ILD2 and second electrode layers GE2.

[0079] The second stacked structure ST2 may be disposed between the first stacked structure ST1 and the peripheral circuit structure PS. Specifically, the second stacked structure ST2 may be disposed below the lowest first inter-electrode insulating layer in the first inter-electrode insulating layers ILD1 of the first stacked structure ST1. The uppermost second inter-electrode insulating layer in the second inter-electrode insulating layers ILD2 of the second stacked structure ST2 and the lowest first inter-electrode insulating layer in the first inter-electrode insulating layers ILD1 of the first stacked structure ST1 may contact each other, but the present disclosure is not limited thereto. A single insulating layer may be disposed between the uppermost second electrode layer GE2 of the second stacked structure ST2 and the lowest first electrode layer GE1 of the first stacked structure ST1.

[0080] A lowermost second electrode layer among the second electrode layers GE2 of the second stacked structure ST2 may have a minimum length in the first direction D1 , and an uppermost first electrode layer among the first electrode layers GE1 of the first stacked structure ST1 may have a maximum length in the first direction D1 .

[0081] The first electrode layer GE1, the second electrode layer GE2, and the third electrode layer GE3 may include, for example, at least one selected from a semiconductor doped with impurities (e.g., silicon doped with impurities, etc.), a metal (e.g., tungsten, molybdenum, nickel, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a transition metal (e.g., titanium, tantalum, etc.). According to one example, the first electrode layer GE1 and the second electrode layer GE2 may be formed of a metal such as tungsten, and the third electrode layer GE3 may be formed of polysilicon doped with impurities.

[0082] The first and second inter-electrode insulating layers ILD1 and ILD2 may include silicon oxide, silicon nitride, silicon oxynitride and / or a low dielectric material. For example, the first and second inter-electrode insulating layers ILD1 and ILD2 may include high density plasma oxide (HDP oxide) or tetraethyl orthosilicate (TEOS).

[0083] According to an embodiment, the semiconductor memory device may be a vertical NAND flash memory device, and in this case, the first electrode layer GE1 and the second electrode layer GE2 of the stack structure ST may correspond to the reference Figure 1 Described are gate lower lines LL1 and LL2, word lines WL, and gate upper lines UL1 and UL2.

[0084] The third electrode layer GE3 may correspond to the reference Figure 1 One of the gate lower lines LL1 and LL2 described above or a ground selection line. The third electrode layer GE3 may extend along the first electrode layer GE1 and the second electrode layer GE2. In this example, the third electrode layer GE3 is shown as one layer, but is not limited to this example and may be composed of two or more layers. In addition, the role of the third electrode layer GE3 is not limited to the ground selection line, and may also participate in the erase operation.

[0085] The flat insulating layer 110 may cover the end (i.e., pad portion) of the stacked structure ST having a stepped structure or overlap the end (i.e., pad portion) of the stacked structure ST having a stepped structure. The flat insulating layer 110 may have a substantially flat upper surface. The flat insulating layer 110 may include one insulating layer or a plurality of stacked insulating layers. The flat insulating layer 110 may have a substantially flat upper surface and a lower surface. The upper surface of the flat insulating layer 110 may be substantially coplanar with the upper surface of the first inter-electrode insulating layer ILD1 at the uppermost end of the stacked structure ST, and the lower surface of the flat insulating layer 110 may be substantially coplanar with the lower surface of the second inter-electrode insulating layer ILD2 at the lowermost end of the stacked structure ST.

[0086] The first insulating layer 305 may be interposed between the stacked structure ST and the third electrode layer GE3. The first wiring BW1 is disposed on the first insulating layer 305. The third electrode layer GE3 and the first wiring BW1 may be formed of the same material and have the same thickness. The third electrode layer GE3 and the first wiring BW1 may be covered by the second insulating layer 310 or overlapped with the second insulating layer 310. The source conductive pattern SCP and the second wiring BW2 are disposed on the second insulating layer 310. The source conductive pattern SCP and the second wiring BW2 may be formed of the same material and have the same thickness. For example, the source conductive pattern SCP and the second wiring BW2 may include at least one selected from metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), or transition metals (e.g., titanium, tantalum, etc.).

[0087] The source conductive pattern SCP may have a uniform thickness and a substantially flat upper surface. The source conductive pattern SCP may extend in a first direction D1 parallel to the stacked structures ST in the cell array region CAR and the first connection region CNR1. In the first direction D1, the length of the source conductive pattern SCP may be greater than the length of the uppermost first electrode layer GE1 of the first stacked structure ST1.

[0088] The source conductive pattern SCP may include, for example, at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., tungsten, molybdenum, nickel, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or a transition metal (e.g., titanium, tantalum, etc.). As an example, the source conductive pattern SCP may include a metal material (e.g., tungsten). The source conductive pattern SCP may correspond to Figure 1 A common source line CSL.

[0089] The plurality of first vertical patterns VS1 may extend into the stacked structure ST in the cell array region CAR and be connected to the source conductive pattern SCP. When viewed in a plan view, the first vertical patterns VS1 may be arranged in one direction or in a zigzag shape. The first vertical patterns VS1 may include a semiconductor material such as silicon. The first vertical patterns VS1 may be used as Figure 1 A channel of at least one of the memory cell transistor MCT, the upper transistors UT1 and UT2, and the lower transistors LT1 and LT2.

[0090] The second vertical pattern VS2 may extend into the stacked structure ST in the first connection region CNR1. The second vertical pattern VS2 may extend into the end (i.e., pad portion) of the first electrode layer GE1 and the second electrode layer GE2 in the first connection region CNR1. The second vertical pattern VS2 may include the same semiconductor material as the first vertical pattern VS1, or may include an insulating material different from the first vertical pattern VS1. The second vertical pattern VS2 may be used as a support portion during the manufacturing process of the stacked structure ST.

[0091] The planar shape and size of the second vertical pattern VS2 may be different from the planar shape and size of the first vertical pattern VS1. The upper surface of the second vertical pattern VS2 may have various shapes, such as a circular, oval, or strip shape. The second vertical pattern VS2 may be arranged around each cell contact plug CPLG. When the upper surface of the second vertical pattern VS2 has an oval shape, the major axis of the second vertical pattern VS2 in each pad portion PAD may be arranged in different directions. A plurality of second vertical patterns VS2 may be arranged between adjacent cell contact plugs CPLG.

[0092] In an embodiment, each first vertical pattern VS1 may be disposed in a vertical channel hole extending into the stack structure ST. In an embodiment, the vertical channel hole may include a first vertical channel hole extending into the first stack structure ST1, and a second vertical channel hole extending into the second stack structure ST2 and connected to the first vertical channel hole.

[0093] Each first vertical pattern VS1 may include a first vertical extension within the first vertical channel hole and a second vertical extension within the second vertical channel hole. The first vertical extension and the second vertical extension may be a structure that extends continuously without an interface. In this case, the first vertical extension may have a sidewall having a uniform slope from its lower portion to its upper portion. Similarly, the second vertical extension may have a sidewall having a uniform slope from its lower portion to its upper portion. That is, the width of each of the first vertical extension and the second vertical extension in the first direction D1 or the second direction D2 may decrease as the distance from the substrate 10 increases. The portions where the first vertical extension and the second vertical extension are connected to each other may have different diameters. A step may be formed at the portion where the first vertical extension and the second vertical extension are connected to each other.

[0094] However, the present disclosure is not limited thereto, and in one variation, each first vertical pattern VS1 may have three or more vertical extensions, each vertical extension having steps at two or more interfaces. As another example, each first vertical pattern VS1 may have no steps and may have a flat sidewall.

[0095] Reference Figures 5 to 7 , the stack structure ST of the cell array structure CS may be divided into (storage) blocks BLK by the block separation pattern SS1. The first center separation pattern SS2 may extend into the stack structure ST at the center of one block BLK. The second center separation pattern SS3 may be disposed between the block separation pattern SS1 and the first center separation pattern SS2 adjacent to each other, and may extend into the stack structure ST.

[0096] The block separation pattern SS1 , the first center separation pattern SS2 , and the second center separation pattern SS3 may each have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0097] The block separation patterns SS1 may extend in parallel from the cell array region CAR to the first connection region CNR1 in the first direction D1 and may be spaced apart from each other in the second direction D2. The block separation patterns SS1 may have a continuous line shape without a step in the first direction D1.

[0098] The first center separation pattern SS2 may have a continuous line shape along the first direction D1 in the cell array region CAR. The first center separation pattern SS2 may extend into the first connection region CNR1. However, the first center separation pattern SS2 may be cut off at the first connection region CNR1 and have a discontinuous portion. Therefore, the cell gate patterns CGE associated with one block BLK may be connected in the discontinuous portion at the corresponding height and be in an equipotential state.

[0099] The second center separation pattern SS3 has a line shape extending from the first connection region CNR1 in the first direction D1 and has a discontinuous portion. That is, a plurality of second center separation patterns SS3 may be provided and may be arranged to be spaced apart from each other in the first direction D1.

[0100] Reference Figure 5 , the string separation pattern 9 is arranged between the block separation pattern SS1 and the first center separation pattern SS2 in the cell array area CAR. The string separation pattern 9 may be located at the same distance from the block separation pattern SS1 and the first center separation pattern SS2. The string separation pattern 9 may extend through the lowest second electrode layer in the second electrode layer GE2, and separate the lowest second electrode layer in the second electrode layer GE2 into a plurality of string selection gate patterns SGE. The string separation pattern 9 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The string separation pattern 9 may have a line shape extending from the cell array area CAR along the first direction D1. The string separation pattern 9 may be between some of the first vertical patterns VS1. Alternatively, the string separation pattern 9 may extend into some of the first vertical patterns VS1. The first vertical pattern VS1 arranged in the string separation pattern 9 or extended thereto by the string separation pattern 9 may not operate as a channel of a memory cell, but may be a dummy channel. The string separation pattern 9 may be adjacent to the second central separation pattern SS3 in the first direction D1. The string separation pattern 9 does not extend into the cell gate pattern CGE.

[0101] The first line separation pattern GCT1 may extend into the second insulating layer 310, the third electrode layer GE3, and the first insulating layer 305, and may contact the block separation pattern SS1. The second line separation pattern GCT2 may extend into the second insulating layer 310, the third electrode layer GE3, and the first insulating layer 305, and may contact the first center separation pattern SS2. The first line separation pattern GCT1 and the second line separation pattern GCT2 separate the third electrode layer GE3 into a plurality of ground selection gate patterns GGE or ground selection lines GGE.

[0102] In the semiconductor memory device according to the present disclosure, the first line separation pattern GCT1 and the second line separation pattern GCT2 for separating the ground selection line GGE may be disposed on the stacked structure ST, so the first electrode layer GE1 and the second electrode layer GE2 of the stacked structure ST may be formed to be flat. This may prevent a seagull-shaped word line contact defect and may improve the reliability of the semiconductor memory device.

[0103] The first and second line separation patterns GCT1 and GCT2 may extend in parallel from the cell array region CAR to the first connection region CNR1 in the first direction D1, and may be spaced apart from each other in the second direction D2. The first and second line separation patterns GCT1 and GCT2 may have a shape of a continuous line without a step in the first direction D1. The first and second line separation patterns GCT1 and GCT2 may be coplanar with an upper surface of the second insulating layer 310.

[0104] The first interlayer insulating layer 120, the second interlayer insulating layer 130, the third interlayer insulating layer 140, and the fourth interlayer insulating layer 150 may be disposed between the peripheral circuit structure PS and the stacked structure ST and between the peripheral circuit structure PS and the flat insulating layer 110. The first to fourth interlayer insulating layers 120, 130, 140, and 150 may be sequentially stacked on the flat insulating layer 110. The first interlayer insulating layer 120 may cover or overlap the lower surfaces of the first vertical pattern VS1 and the second vertical pattern VS2. The first interlayer insulating layer 120, the second interlayer insulating layer 130, the third interlayer insulating layer 140, and the fourth interlayer insulating layer 150 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric material.

[0105] The bit line BL, the lower contacts LCTa and LCTb, the lower conductive lines LCLa and LCLb, the upper conductive lines UCLa and UCLb, and the second bonding pad BP2 may be disposed in the first, second, third, and fourth interlayer insulating layers 120 , 130 , 140 , and 150 .

[0106] exist Figure 5 In the plan view, the bit lines are omitted. Figure 6 and Figure 7 , the bit line BL may be disposed on the second interlayer insulating layer 130 in the cell array region CAR, and may extend across the stack structure ST in the second direction D2. The bit line BL may be electrically connected to the first vertical pattern VS1 through a bit line contact plug BCT. A bit line conductive pad BPD may be formed at a lower end of the first vertical pattern VS1, and the bit line contact plug BCT may contact the bit line conductive pad BPD. The bit line conductive pad BPD may be formed of a semiconductor material not doped with impurities, a semiconductor material doped with impurities, or a conductive material.

[0107] Reference Figure 6, the cell contact plug CPLG may extend into the first interlayer insulating layer 120, into the flat insulating layer 110, and into the end of the stacked structure ST to be connected to the corresponding pad portion of the first electrode layer GE1 and the second electrode layer GE2. The cell contact plug CPLG may be in direct contact with a corresponding one of the first electrode layer GE1 and the second electrode layer GE2, but the contact insulating layer SW1 may be between the non-corresponding first electrode layer GE1 and the second electrode layer GE2 and the cell contact plug CPLG. The contact insulating layer SW1 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The cell contact plugs CPLG may have the same height (or vertical length) as each other. The outermost cell contact plug CPLG is connected to the third electrode layer GE3.

[0108] The peripheral contact plug PPLG and the input / output contact plug IOPLG penetrate the first and second interlayer insulating layers 120 and 130 and the planar insulating layer 110 in the second connection region CNR2 to be connected to the first and second wirings BW1 and BW2 .

[0109] Each of the cell contact plug CPLG, the peripheral contact plug PPLG, and the input / output contact plug IOPLG may include a barrier metal layer including a conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.) and a metal layer including a metal (eg, tungsten, titanium, tantalum, etc.).

[0110] The first lower contact LCTa is disposed in the second interlayer insulating layer 130 of the first connection region CNR1. The first lower conductive line LCLa may be disposed under the second interlayer insulating layer 130 in the first connection region CNR1 and may be connected to the cell contact plug CPLG through the first lower contact LCTa.

[0111] The second lower contact LCTb is disposed in the second interlayer insulating layer 130 of the second connection region CNR2. The second lower conductive line LCLb may be disposed under the second interlayer insulating layer 130 of the second connection region CNR2 and may be connected to the peripheral contact plug PPLG and the input / output contact plug IOPLG through the second lower contact LCTb.

[0112] The first upper conductive line UCLa and the second upper conductive line UCLb may be disposed under the third interlayer insulating layer 140. The first upper conductive line UCLa may be electrically connected to the bit line BL in the cell array region CAR. The second upper conductive line UCLb may be electrically connected to the second lower conductive line LCLb in the first and second connection regions CNR1 and CNR2.

[0113] The first lower conductive line LCLa and the second lower conductive line LCLb and the first upper conductive line UCLa and the second upper conductive line UCLb may include at least one selected from metal (e.g., tungsten, copper, aluminum, etc.), conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), or transition metal (e.g., titanium, tantalum, etc.). For example, the first lower conductive line LCLa and the second lower conductive line LCLb may be formed of tungsten having a relatively high resistivity, and the first upper conductive line UCLa and the second upper conductive line UCLb may be formed of copper having a relatively low resistivity.

[0114] The second bonding pad BP2 may be disposed in the uppermost interlayer insulating layer 150. The second bonding pad BP2 may be electrically connected to the first upper conductive line UCLa and the second upper conductive line UCLB. The second bonding pad BP2 may be formed of aluminum, copper, or tungsten.

[0115] The second bonding pad BP2 may be electrically and physically connected to the first bonding pad BP1 by bonding. That is, the second bonding pad BP2 may be in direct contact with the first bonding pad BP1.

[0116] The second bonding pad BP2 may include the same metal material as the first bonding pad BP1. The width of the second bonding pad BP2 may be the same as or different from the width of the first bonding pad BP1.

[0117] Reference Figure 6 , the outermost cell contact plugs in the cell contact plugs CPLG are connected to the pad portion of the third electrode layer GE3 through the first contact portion CT1 extending into the first insulating layer 305. The second contact portion CT2 may extend into the first insulating layer 305 and may connect one of the peripheral contact plugs PPLG to the first wiring BW1. The third contact portion CT3 may extend into the first insulating layer 305 and the second insulating layer 310 to connect another of the peripheral contact plugs PPLG to the source conductive pattern SCP. The fourth contact portion CT4 may extend into the first insulating layer 305 and the second insulating layer 310 to connect one of the input / output contact plugs IOPLG to the second wiring BW2.

[0118] The source conductive pattern SCP and the second wiring BW2 may be covered by the third insulating layer 320 or overlapped with the third insulating layer 320. The input / output pad PD may be disposed on the third insulating layer 320. The passivation layer 330 may be disposed on the third insulating layer 320. The first to third insulating layers 305, 310, and 320 may each have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The passivation layer 330 may be, for example, a polyimide-based material such as photosensitive polyimide (PSPI). The passivation layer 330 may have a pad opening OP exposing a portion of the input / output pad PD. The fifth contact CT5 may penetrate the third insulating layer 320 and connect the second wiring BW2 to the input / output pad PD.

[0119] FIG. 8A to FIG. 8D According to the embodiment of the present disclosure Figure 6 Magnified view of the “P2” section in Figure 2.

[0120] Reference Fig. 8A , the first vertical pattern VS1 is disposed in the vertical channel hole VH extending into the stacked structure ST. The first vertical pattern VS1 may be formed of a semiconductor layer (e.g., a silicon layer or a germanium layer) doped or undoped with impurities. The first vertical pattern VS1 may have a non-linear shape (e.g., a tube shape, a macaroni shape, or a shell shape with an open top and / or bottom). The first impurity region IMR may be disposed on the first vertical pattern VS1. The first impurity region IMR may be doped with impurities of the same conductivity type as the impurities doped in the source conductive pattern SCP.

[0121] The upper surface or upper end VS1_t of the first vertical pattern VS1 may extend above the upper surface ILD1t of the uppermost first inter-electrode insulating layer ILD1. That is, the second level LV2 of the upper surface or upper end VS1_t of the first vertical pattern VS1 may be higher than the first level LV1 of the upper surface ILD1t of the uppermost first inter-electrode insulating layer ILD1 (for example, the second level LV2 extends from the substrate 10 or the peripheral circuit structure PS by a greater distance than the first level LV1 extends from the substrate 10 or the peripheral circuit structure PS).

[0122] The first buried insulating pattern IL may be located inside the first vertical pattern VS1. The first buried insulating pattern IL may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0123] The first gate insulating layer GO1 may be interposed between the first vertical pattern VS1 and the first and second electrode layers GE1 and GE2. The first gate insulating layer GO1 may include a tunnel insulating layer L1, a charge storage layer L2, and a blocking insulating layer L3 sequentially interposed from the sidewall of the first vertical pattern VS1 toward the first and second electrode layers GE1 and GE2. The tunnel insulating layer L1 and the blocking insulating layer L3 may include silicon oxide. The charge storage layer L2 may include silicon nitride. Alternatively, the charge storage layer L2 may be a trap insulating layer, a floating gate electrode, or an insulating layer including conductive nanodots.

[0124] The high-k dielectric layer HP may be interposed between the first and second electrode layers GE1 and GE2 and the first and second inter-electrode insulating layers ILD1 and ILD2. The high-k dielectric layer HP may include, for example, a metal oxide. The high-k dielectric layer HP may extend to be interposed between the first gate insulating layer GO1 and the first and second electrode layers GE1 and GE2.

[0125] An upper surface of the first gate insulating layer GO1 may be coplanar with an upper surface ILD1 t of the uppermost first inter-electrode insulating layer ILD1 .

[0126] The third vertical pattern VS3 may extend into the second insulating layer 310, the third electrode layer GE3, and the first insulating layer 305, and may be in contact with the first vertical pattern VS1, respectively. The third vertical patterns VS3 are respectively disposed in the upper holes UH. The third vertical pattern VS3 may be formed of a semiconductor layer doped or undoped with impurities (e.g., a silicon layer or a germanium layer). An upper surface of the third vertical pattern VS3 is in contact with the source conductive pattern SCP. As the distance between the third vertical pattern VS3 and the first gate insulating layer GO1 decreases, the width of the third vertical pattern VS3 may become narrower. The lower portion of the third vertical pattern VS3 covers the upper side wall of the first vertical pattern VS1 or overlaps with the upper side wall of the first vertical pattern VS1, as shown in FIG. Fig. 8A shown.

[0127] When viewed in a plan view, the position and arrangement of the third vertical pattern VS3 may be different from Figure 5 The third vertical pattern VS3 may be arranged in the same position and arrangement as the first vertical pattern VS1 and may overlap with the first vertical pattern VS1. In another example, the third vertical pattern VS3 may not overlap with the string separation pattern 9. The thickness of the third vertical pattern VS3 may be the same as or different from the thickness of the first vertical pattern VS1. The third vertical pattern VS3 may have a hollow and non-linear shape (e.g., a macaroni shape, a cylindrical shape, or a shell shape).

[0128] The second buried insulating pattern 29 may be inside the third vertical pattern VS3. The second buried insulating pattern 29 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second buried insulating pattern 29 may contact the upper surface VS1_t of the first vertical pattern VS1, such as Fig. 8A The second buried insulating pattern 29 is spaced apart from the first buried insulating pattern IL. The upper portion of the first vertical pattern VS1 is interposed between the second buried insulating pattern 29 and the first buried insulating pattern IL.

[0129] The second gate insulating layer GO2 may be interposed between the third vertical pattern VS3 and the third electrode layer GE3. The second gate insulating layer GO2 may be formed, for example, as a single layer of silicon oxide. The thickness of the second gate insulating layer GO2 may be different from the thickness of the first gate insulating layer GO1. The high-k dielectric layer HP is not interposed between the third electrode layer GE3 and the first insulating layer 305 and the second insulating layer 310.

[0130] Reference Figure 8B , the second buried insulating pattern 29 may extend into the upper portion VS1_t of the first vertical pattern VS1 and may contact the first buried insulating pattern IL. Other structures may be similar to those of reference Fig. 8A The structures described are the same / similar.

[0131] Alternatively, refer to Figure 8C , the lower portion of the third vertical pattern VS3 may be in contact with the upper portion VS1_t of the first vertical pattern VS1. The lower portion of the third vertical pattern VS3 and the upper portion VS1_t of the first vertical pattern VS1 are interposed between the second buried insulating pattern 29 and the first buried insulating pattern IL. The third vertical pattern VS3 may cover the upper surface VS1_t of the first vertical pattern VS1 or overlap the upper surface VS1_t of the first vertical pattern VS1, and may have a non-linear cross-section (e.g., a "U"-shaped cross-section or an "H"-shaped cross-section).

[0132] Alternatively, refer to Fig.8D , an upper surface VS1_t of the first vertical pattern VS1 and an upper surface of the first gate insulating layer GO1 may be coplanar with an upper surface ILD1t of the uppermost first inter-electrode insulating layer ILD1. The second buried insulating pattern 29 may contact the first buried insulating pattern IL.

[0133] Fig. 9 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line AA′. Fig.10 is along Figure 5 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, taken along line BB′.

[0134] Reference Fig. 9 and Fig.10 In the semiconductor memory device according to the present embodiment, the first electrode layer GE1 may not include the first erase gate pattern EGE1 and the second erase gate pattern EGE2. The first electrode layer GE1 may include only the cell gate pattern CGE. The third electrode layer GE3 may be composed of three layers. The third electrode layer GE3 may include the first erase gate pattern EGE1 and the second erase gate pattern EGE2 and the ground selection gate pattern GGE. The ground selection gate pattern GGE and the first wiring BW1 are disposed on the first insulating layer 305. The ground selection gate pattern GGE and the first wiring BW1 are covered by the fourth insulating layer 306 or overlap the fourth insulating layer 306. The second erase gate pattern EGE2 is disposed on the fourth insulating layer 306. The second erase gate pattern EGE2 is covered by the fifth insulating layer 307 or overlaps the fifth insulating layer 307. The first erase gate pattern EGE1 is disposed on the fifth insulating layer 307. The first erase gate pattern EGE1 is covered by the second insulating layer 310 or overlaps the second insulating layer 310. The third electrode layer GE3 may become longer in the first direction D1 as the distance between the third electrode layer GE3 and the substrate 10 increases. An end portion of the third electrode layer GE3 may have an inverted step shape.

[0135] The sixth contact portion CT6 extends into the first insulating layer 305 and the fourth insulating layer 306, and connects the pad portion of the second erase gate pattern EGE2 to one of the cell contact plugs CPLG. The seventh contact portion CT7 extends into the first insulating layer 305, the fourth insulating layer 306, and the fifth insulating layer 307, and connects the pad portion of the first erase gate pattern EGE1 to another of the cell contact plugs CPLG. The third contact portion CT3 extends into the first insulating layer 305, the fourth insulating layer 306, the fifth insulating layer 307, and the second insulating layer 310, and connects the pad portion of the source conductive pattern SCP to another peripheral contact plug PPLG.

[0136] The second vertical pattern VS3 extends into the third electrode layer GE3 and contacts the first vertical pattern VS1. The first and second line separation patterns GCT1 and GCT2 extend into the third electrode layer GE3 and contact the block separation pattern SS1 and the first center separation pattern SS2, respectively. Other structures may be the same / similar to the above structures.

[0137] FIG. 11A to FIG. 11H is a sequence showing the manufacturing of Figure 6 A cross-sectional diagram of a semiconductor memory device process. FIG. 12A to FIG. 12C yes Fig.11E The enlarged view of the "P2" portion of the Figure 6 A cross-section of a semiconductor memory device process. FIG. 13A to FIG. 13C is a sequence showing the manufacturing of Figure 7 A cross-sectional diagram of a semiconductor memory device process.

[0138] Reference Fig.11A , a peripheral circuit structure PS including a peripheral circuit PTR formed on the first substrate 10 may be formed.

[0139] Forming the peripheral circuit structure PS may include: forming a device isolation layer 11 defining an active area within the first substrate 10; forming a peripheral circuit PTR on the active area of ​​the first substrate 10; and forming a peripheral contact plug PCP, a peripheral circuit wiring PLP, a first bonding pad BP1 electrically connected to the peripheral circuit PTR, and a peripheral circuit insulation layer 50 thereon.

[0140] The first substrate 10 may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0141] Row and column decoders, a page buffer, and a control circuit may be formed as a peripheral circuit PTR on the first substrate 10. Here, the peripheral circuit PTR may include a MOS transistor using the first substrate 10 as a channel.

[0142] The peripheral circuit insulation layer 50 may include one insulation layer or a plurality of stacked insulation layers covering or overlapping the peripheral circuit PTR. As an example, the peripheral circuit insulation layer 50 may include a first lower insulation layer 51, a second lower insulation layer 55, and an etch stop layer 53 between the first lower insulation layer 51 and the second lower insulation layer 55. The peripheral circuit insulation layer 50 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0143] The peripheral contact plug PCP may be formed to extend into a portion of the peripheral circuit insulating layer 50 and be connected to the peripheral circuit. The peripheral circuit wiring PLP may be formed by performing a conductive layer deposition process and a conductive layer patterning process.

[0144] The first bonding pad BP1 may be formed in the uppermost second lower insulating layer 55 of the peripheral circuit insulating layer 50. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through the peripheral contact plug PCP and the peripheral circuit wiring PLP.

[0145] The first bonding pad BP1 may be formed using a damascene process. Since a planarization process may be performed, an upper surface of the first bonding pad BP1 may be substantially coplanar with an upper surface of the second lower insulating layer 55. For example, the planarization process may be performed by a chemical mechanical polishing (CMP) process or an etch-back process.

[0146] Reference Figure 5 and Fig. 11B , a first mold structure ML1 may be formed on the second substrate 100 .

[0147] Forming the first mold structure ML1 may include: forming a first thin film structure (not shown) in which first inter-electrode insulating layers ILD1 and first sacrificial layers SL1 are vertically and alternately stacked; and repeatedly performing a patterning process on the first thin film structure. Therefore, the first mold structure ML1 may have a step structure in the first connection region CNR1.

[0148] The first inter-electrode insulating layer ILD1 and the first sacrificial layer SL1 may be deposited using a thermal CVD process, a plasma enhanced CVD process, a physical CVD process, or an atomic layer deposition (ALD) process.

[0149] In the first mold structure ML1, the first sacrificial layer SL1 may be formed of a material that can be etched with an etching selectivity relative to the first inter-electrode insulating layer ILD1. For example, the first sacrificial layer SL1 may be formed of an insulating material different from the first inter-electrode insulating layer ILD1. For example, the first sacrificial layer SL1 may be formed of a silicon nitride layer, and the first inter-electrode insulating layer ILD1 may be formed of a silicon oxide layer.

[0150] After forming the first mold structure ML1 , a flat insulation layer 110 covering or overlapping the stepped structure of the first mold structure ML1 may be formed.

[0151] Subsequently, the second mold structure ML2 may be formed on the first mold structure ML1. According to some embodiments, before forming the second mold structure ML2, a vertical sacrificial pattern (not shown) extending into the first mold structure ML1 may be formed.

[0152] Forming the second mold structure ML2 may be substantially the same as forming the first mold structure ML1 described above. That is, forming the second mold structure ML2 may include: forming a second thin film structure (not shown) in which the second inter-electrode insulating layer ILD2 and the second sacrificial layer SL2 are vertically and alternately stacked on the first mold structure ML1; and repeatedly performing a patterning process on the second thin film structure. Therefore, the second mold structure ML2 may have a step structure in the first connection region CNR1.

[0153] The second sacrificial layer SL2 may be formed of the same material as the first sacrificial layer SL1, and the thickness of the second sacrificial layer SL2 may be substantially the same as the thickness of the first sacrificial layer SL1. The second sacrificial layer SL2 may be formed of an insulating material different from the second inter-electrode insulating layer ILD2. The second sacrificial layer SL2 may be formed of the same material as the first sacrificial layer SL1. For example, the second sacrificial layer SL2 may be formed of a silicon nitride layer, and the second inter-electrode insulating layer ILD2 may be formed of a silicon oxide layer.

[0154] After forming the second mold structure ML2 , a flat insulation layer 110 covering or overlapping the stepped structure of the second mold structure ML2 may be formed.

[0155] Subsequently, a vertical channel hole penetrating the first and second mold structures ML1 and ML2 and exposing the second substrate 100 may be formed. When a vertical sacrificial pattern (not shown) is formed in the first mold structure ML1, forming the vertical channel hole may include removing the vertical sacrificial pattern to expose the second substrate 100.

[0156] When forming the vertical channel holes, dummy channel holes extending into the planar insulating layer 110 and into portions of the first and second mold structures ML1 and ML2 may be formed in the first connection region CNR1 .

[0157] Forming the vertical channel hole may include: forming a hard mask pattern on the second molding structure ML2; and anisotropically etching the first molding structure ML1 and the second molding structure ML2 using the hard mask pattern as an etching mask. In the anisotropic etching process for forming the vertical channel hole, the upper surface of the second substrate 100 may be over-etched, and thus the upper surface of the second substrate 100 exposed to the vertical channel hole may be recessed to a certain depth. In addition, during the anisotropic etching process for forming the vertical channel hole, the recessed depth of the second substrate 100 may vary depending on the position of the vertical channel hole.

[0158] Subsequently, the first vertical pattern VS1 may be formed in the vertical channel hole of the cell array region CAR, and the second vertical pattern VS2 may be formed in the dummy channel hole of the first connection region CNR1.

[0159] Forming the first and second vertical patterns VS1 and VS2 may include: sequentially depositing the first gate insulating layer GO1 and the first vertical pattern VS1 in the vertical channel hole; and etching and planarizing the first gate insulating layer GO1 and the first vertical pattern VS1.

[0160] Reference Fig. 8A, a first gate insulating layer GO1 having a uniform thickness may be deposited on the bottom surface and inner wall of the vertical channel hole VH using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. The first gate insulating layer GO1 may include a blocking insulating layer L3, a charge storage layer L2, and a tunnel insulating layer L1 sequentially stacked in the vertical channel hole. A first vertical pattern VS1 having a uniform thickness may be deposited on the first gate insulating layer GO1 using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) method. After forming the first gate insulating layer GO1 and the first vertical pattern VS1, the vertical channel hole VH may be filled with the first buried insulating pattern IL.

[0161] Subsequently, a bit line conductive pad BPD may be formed on the upper end of the first vertical pattern VS1. The bit line conductive pad BPD may be an impurity region doped with impurities or may be formed of a conductive material. The upper surface of the bit line conductive pad BPD may be coplanar with the upper surface of the uppermost second inter-electrode insulating layer ILD2.

[0162] Reference Figure 5 and Fig. 11C , a first interlayer insulating layer 120 may be formed on the planar insulating layer 110 to cover or overlap upper surfaces of the first and second vertical patterns VS1 and VS2 .

[0163] Subsequently, a process of replacing the first and second sacrificial layers SL1 and SL2 of the first and second mold structures ML1 and ML2 with the first and second electrode layers GE1 and GE2 may be performed. Thus, a stack structure ST may be formed on the second substrate 100 .

[0164] The process of replacing the first sacrificial layer SL1 and the second sacrificial layer SL2 with the first electrode layer GE1 and the second electrode layer GE2 may include isotropically etching the first sacrificial layer SL1 and the second sacrificial layer SL2 using an etching recipe having an etching selectivity with respect to the first inter-electrode insulating layer ILD1 and the second inter-electrode insulating layer ILD2, the first vertical pattern VS1 and the second vertical pattern VS2, and the second substrate 100. After forming the stack structure ST, a Figure 5 , Figure 7 and Fig.13A The block separation pattern SS1, the first center separation pattern SS2 and the second center separation pattern SS3.

[0165] Then, a second interlayer insulating layer 130 may be formed on the first interlayer insulating layer 120 , and a cell contact plug CPLG, a peripheral contact plug PPLG, and an input / output contact plug IOPLG connected to the stack structure ST may be formed.

[0166] The peripheral contact plug PPLG and the input / output contact plug IOPLG may be formed by forming contact holes in the first interlayer insulating layer 120 and the planar insulating layer 110 in the second connection region CNR2 to expose the second substrate 100 and then by depositing a conductive material in the contact holes.

[0167] A second interlayer insulating layer 130 may be formed on the first interlayer insulating layer 120 , and bit line contact plugs BCT of the cell array region CAR and connection contact plugs of the first and second connection regions CNR1 and CNR2 may be formed.

[0168] The bit line contact plug BCT may extend into the first and second interlayer insulating layers 120 and 130 and be connected to the first vertical pattern VS1. The bit line contact plug BCT may contact the bit line conductive pad. The bit line conductive pad may be formed of an undoped semiconductor material, a semiconductor material doped with impurities, or a conductive material.

[0169] The first connection contact plug may extend into the second interlayer insulating layer 130 and be connected to the cell contact plug CPLG. The second connection contact plug may extend into the second interlayer insulating layer 130 and be connected to the peripheral contact plug PPLG and the input / output contact plug IOPLG.

[0170] A bit line BL and lower conductive lines LCLa and LCLb may be formed on the second interlayer insulating layer 130. The bit line BL may be connected to the bit line contact plug BCT, and the lower conductive lines LCLa and LCLb may be connected to the connection contact plug.

[0171] Reference Figure 5 and Fig.11D , a third interlayer insulating layer 140 and a fourth interlayer insulating layer 150 may be deposited on the second interlayer insulating layer 130, and first and second upper conductive lines UCLa and UCLb may be formed on the third interlayer insulating layer 140. The first and second upper conductive lines UCLa and UCLb may be connected to the first and second lower conductive lines LCLa and LCLb.

[0172] A second bonding pad BP2 may be formed in the fourth interlayer insulating layer 150 and may be connected to the first and second upper conductive lines UCLa and UCLb.

[0173] The first and second upper conductive lines UCLa and UCLb and the second bonding pad BP2 may be formed using a damascene process. An upper surface of the second bonding pad BP2 may be substantially coplanar with an upper surface of the fourth interlayer insulating layer 150.

[0174] Reference Figure 5 , Fig.11D and Fig.11E, by referring to Fig.10 The cell array structure CS formed on the second substrate 100 and the peripheral circuit structure PS formed on the first substrate 10 by the described method may be bonded to each other. Specifically, a first bonding pad BP1 of the peripheral circuit structure PS and a second bonding pad BP2 of the cell array structure CS may be bonded to each other.

[0175] Thus, the first bonding pad BP1 and the second bonding pad BP2 may be bonded to each other, and the second lower insulating layer 55 on the first substrate 10 and the fourth interlayer insulating layer 150 on the second substrate 100 may be bonded to each other.

[0176] When the first and second bonding pads BP1 and BP2 are bonded to each other, the cell array structure CS may be inverted. That is, the second substrate 100 of the cell array structure CS may be located at the uppermost end, and the stepped structure of the stack structure ST may be arranged in an inverted form.

[0177] Reference Fig.11E and Fig. 12A , after the first bonding pad BP1 and the second bonding pad BP2 are bonded to each other, the second substrate 100 may be removed. Removing the second substrate 100 may include a grinding process, a planarization process, a dry etching process, and a wet etching process. When the second substrate 100 is removed, the upper surface 110t of the lowermost first inter-electrode insulating layer ILD1 of the stacked structure ST and the upper surface 110t of the flat insulating layer 110 may be exposed. In addition, when the second substrate 100 is removed, the first vertical pattern VS1 and the upper portion of the first gate insulating layer GO1 covering the first vertical pattern VS1 or overlapping the first vertical pattern VS1 may extend on the lowermost first inter-electrode insulating layer ILD1, and the peripheral contact plug PPLG and the input / output contact plug IOPLG may be exposed.

[0178] Reference Fig. 12B , an upper portion of the first gate insulating layer GO1 extending over the lowermost first inter-electrode insulating layer ILD1 may be removed to expose an upper surface VS1_t of the first vertical pattern VS1.

[0179] Reference Fig. 12C An ion implantation process is performed to form a first impurity region IMR on an upper portion of the first vertical pattern VS1. The first impurity region IMR may be doped with, for example, N-type impurities.

[0180] Reference Fig.11F and Fig.13A, a first insulating layer 305 may be deposited on the stacked structure ST and a planarization process may be performed. The first insulating layer 305 may be in contact with the first vertical pattern VS1, the cell contact plug CPLG, the peripheral contact plug PPLG, and the input / output contact plug IOPLG. The first insulating layer 305 may be etched to form a first contact hole exposing at least one of the outermost cell contact plug CPLG and the peripheral contact plug PPLG. The first contact hole is filled with a conductive layer to form a first contact portion CT1 and a second contact portion CT2. A conductive layer is deposited on the first insulating layer 305 and etched to form a third electrode layer GE3 and a first wiring BW1. The third electrode layer GE3 is formed to contact the first contact portion CT1. The first wiring BW1 is formed to contact the second contact portion CT2. The second insulating layer 310 is formed to cover the third electrode layer GE3 and the first wiring BW1 or overlap the third electrode layer GE3 and the first wiring BW1.

[0181] Reference Figure 5 , Fig. 8A , Fig.11G and Fig. 13B , the second insulating layer 310, the third electrode layer GE3 and the first insulating layer 305 are etched in the cell array area CAR to form an upper hole UH exposing the first vertical pattern VS1. The second gate insulating layer GO2 is conformally deposited on the second insulating layer 310, and then anisotropic etching is performed. Thus, a second gate insulating layer GO2 covering the inner wall of the upper hole UH or overlapping with the inner wall of the upper hole UH and exposing the first vertical pattern VS1 can be formed. After the semiconductor layer is conformally deposited on the second insulating layer 310, an anisotropic etching process is performed to form a third vertical pattern VS3 covering the sidewall of the second gate insulating layer GO2 or overlapping with the sidewall of the second gate insulating layer GO2. A second buried insulating layer is deposited on the second insulating layer 310 and in the upper hole UH, and an anisotropic etching process is performed to expose the upper end of the third vertical pattern VS3 and form a second buried insulating pattern 29 in the upper hole UH. Then, the second insulating layer 310 and the first insulating layer 305 in the second connection region CNR2 are etched to form a second contact hole exposing at least one of the peripheral contact plug PPLG and the input / output contact plug IOPLG. The second contact hole is filled with a conductive layer to form third and fourth contacts CT3 and CT4.

[0182] Reference Figure 5 and Fig. 13C, the second insulating layer 310, the third electrode layer GE3, and the first insulating layer 305 in the cell array region CAR and the first connection region CNR1 are etched to form a first groove GRi exposing the block separation pattern SS1 and a second groove GR2 exposing the first center separation pattern SS2. After an insulating layer is deposited on the second insulating layer 310 to fill the first groove GR1 and the second groove GR2, an etch-back process or a polishing process is performed to form a first line separation pattern GCT1 and a second line separation pattern GCT2 in the first groove GR1 and the second groove GR2, respectively, and an upper surface of the third vertical pattern VS3 is exposed.

[0183] Reference Fig.11H A conductive layer is deposited on the second insulating layer 310 and etched to form a source conductive pattern SCP and a second wiring BW2. The source conductive pattern SCP and the second wiring BW2 are formed of a conductive layer (eg, polysilicon doped with N-type impurities).

[0184] Refer again Figure 6 and Figure 7 , a third insulating layer 320 is formed to cover the source conductive pattern SCP and the second wiring BW2. A fifth contact portion CT5 is formed inside the third insulating layer 320. An input / output pad PD is formed on the third insulating layer 320. A passivation layer 330 is formed on the third insulating layer 320. A portion of the passivation layer 330 is removed to form a pad opening OP exposing the input / output pad PD. Thus, a Figures 5 to 7 semiconductor memory devices.

[0185] Conventionally, the stack structure ST has been formed to include the ground selection line GGE and the first and second line separation patterns GCT1 and GCT2, and the first and second electrode layers GE1 and GE2 are formed to be bent in a "seagull" shape by the first and second line separation patterns GCT1 and GCT2. As a result, contact defects occur at places where some of the first and second electrode layers GE1 and GE2 contact each other, or an operation error occurs because the first and second electrode layers GE1 and GE2 are not spaced apart by more than a certain distance.

[0186] However, in the present disclosure, after forming the stacked structure ST, the first line separation pattern GCT1 and the second line separation pattern GCT2 may be formed to separate the ground selection line GGE, so the first electrode layer GE1 and the second electrode layer GE2 may be formed to be flat. Thus, the "seagull"-shaped word line contact defect may be prevented, thereby improving the reliability of the semiconductor memory device.

[0187] In the semiconductor memory device according to the present disclosure, the first line separation pattern and the second line separation pattern for ground selection line separation are arranged on the stacked structure, so the first electrode layer and the second electrode layer of the stacked structure can be formed to be flat. This can suppress the "seagull" shaped word line contact defect and can improve the reliability of the semiconductor memory device.

[0188] Although the embodiments are described above, it will be appreciated by those skilled in the art that many modifications and variations may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. Therefore, the exemplary embodiments of the present disclosure should be considered in all aspects to be illustrative and not restrictive, and the spirit and scope of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor memory device, comprising: Peripheral circuit structure, including peripheral circuits; A stacked structure, on the peripheral circuit structure, and comprising alternately stacked first electrode layers and first inter-electrode insulating layers; a first vertical pattern extending into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a line separation pattern extending into the second insulating layer, the second electrode layer and the first insulating layer; as well as A second vertical pattern extends into the second insulating layer, the second electrode layer, and the first insulating layer, wherein the second vertical pattern is electrically connected to the first vertical pattern.

2. The semiconductor memory device according to claim 1, further comprising a plurality of line separation patterns, wherein The plurality of line separation patterns separate the second electrode layer into a plurality of ground selection lines.

3. The semiconductor memory device according to claim 2, wherein: The plurality of line separation patterns include a first line separation pattern and a second line separation pattern, Wherein, the semiconductor memory device further comprises: a block separation pattern extending into the stack structure and separating the stack structure into a plurality of blocks; and a central separation pattern extending into the stacked structure and located at the center of each of the plurality of blocks, wherein the first line separation patterns are respectively on the block separation patterns, and Wherein, the second line separation patterns are respectively on the central separation patterns.

4. The semiconductor memory device according to claim 3, wherein: The stacked structure includes a cell array region and a connection region. The first line separation pattern, the second line separation pattern, and the block separation pattern are continuous in both the cell array region and the connection region, and Each of the central separation patterns includes a discontinuous portion in the connection region.

5. The semiconductor memory device according to claim 1, wherein An upper surface of the line separation pattern and an upper surface of the second vertical pattern are coplanar with an upper surface of the second insulating layer. 6 . The semiconductor memory device of claim 1 , further comprising a source layer on the second insulating layer and on the second vertical patterns.

7. The semiconductor memory device according to claim 1, further comprising at least one third electrode layer on the second insulating layer, wherein The second vertical pattern extends into the at least one third electrode layer.

8. The semiconductor memory device according to claim 7, wherein: A portion of the at least one third electrode layer is adjacent to the second electrode layer, and Wherein, the semiconductor memory device further comprises: a first contact portion extending into the first insulating layer and electrically connected to the second electrode layer and the peripheral circuit structure; and A second contact portion extends into the first insulating layer and the second insulating layer and is electrically connected to the third electrode layer and the peripheral circuit structure.

9. The semiconductor memory device according to claim 1, wherein: An upper end of the first vertical pattern extends a first distance from the peripheral circuit structure; The upper surface of the stacked structure extends a second distance from the peripheral circuit structure; The first distance is greater than or equal to the second distance; and The semiconductor memory device also includes a first impurity region on the upper end of the first vertical pattern.

10. The semiconductor memory device according to claim 1, further comprising: a first gate insulating layer, between the first vertical pattern and the first electrode layer; as well as a second gate insulating layer, between the second vertical pattern and the second electrode layer, The first gate insulating layer includes a tunnel insulating layer, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. wherein the first gate insulating layer extends from one side of the first vertical pattern toward a side surface of the stacked structure, and Wherein, the second gate insulating layer does not include the charge storage layer.

11. The semiconductor memory device according to claim 10, further comprising a high-k dielectric layer between the first electrode layer and the first gate insulating layer, wherein The second electrode layer is directly on the second gate insulating layer.

12. The semiconductor memory device according to claim 1, wherein: The second vertical pattern overlaps an upper surface of the first vertical pattern and has a cross-section in a non-linear shape.

13. A semiconductor memory device comprising: substrate; a peripheral circuit structure including a peripheral circuit on the substrate, the peripheral circuit structure including a first bonding pad electrically connected to the peripheral circuit; as well as a cell array structure comprising a second bonding pad electrically connected to the first bonding pad, Wherein, the cell array structure comprises: A stacked structure comprising alternately stacked first electrode layers and first inter-electrode insulating layers; a block separation pattern extending into the stacked structure; a central separation pattern extending into the stacked structure and between the block separation patterns; a first vertical pattern extending into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a first line separation pattern extending into the second insulating layer, the second electrode layer and the first insulating layer, wherein the first line separation patterns are respectively on the block separation patterns; a second line separation pattern extending into the second insulating layer, the second electrode layer, and the first insulating layer, wherein the second line separation pattern is on the central separation pattern; and The second vertical patterns extend into the second insulating layer, the second electrode layer and the first insulating layer, wherein the second vertical patterns are respectively on the first vertical patterns.

14. The semiconductor memory device according to claim 13, wherein: The stacked structure includes a cell array region and a connection region. The first line separation pattern, the second line separation pattern, and the block separation pattern are continuous in both the cell array region and the connection region, and The central separation pattern includes discontinuous portions in the connection region.

15. The semiconductor memory device according to claim 13, wherein: An upper surface of the first line separation pattern, an upper surface of the second line separation pattern, and an upper surface of the second vertical pattern are coplanar with an upper surface of the second insulating layer. 16 . The semiconductor memory device of claim 13 , further comprising a source layer on the second insulating layer and on the first line separation pattern, the second line separation pattern, and the second vertical pattern.

17. The semiconductor memory device according to claim 13, further comprising at least one third electrode layer on the second insulating layer, wherein The first line separation pattern, the second line separation pattern, and the second vertical pattern extend into the at least one third electrode layer.

18. The semiconductor memory device according to claim 17, wherein: A portion of the at least one third electrode layer is adjacent to the second electrode layer, and Wherein, the semiconductor memory device further comprises: a first contact portion extending into the first insulating layer and electrically connected to the second electrode layer and the peripheral circuit structure; and A second contact portion extends into the first insulating layer and the second insulating layer and is electrically connected to the third electrode layer and the peripheral circuit structure.

19. The semiconductor memory device according to claim 13, wherein: An upper end of a given one of the first vertical patterns extends a first distance from the substrate; The upper surface of the stack structure extends a second distance from the substrate; The first distance is greater than or equal to the second distance, and The semiconductor memory device further includes a first impurity region on the upper end of the given first vertical pattern.

20. An electronic system comprising: A semiconductor memory device, comprising a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure; as well as a controller electrically connected to the semiconductor memory device through an input / output pad and configured to control the semiconductor memory device, Wherein, the cell array structure comprises: A stacked structure, on the peripheral circuit structure, and comprising alternately stacked first electrode layers and first inter-electrode insulating layers; a first vertical pattern extending into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a line separation pattern extending into the second insulating layer, the second electrode layer, and the first insulating layer; and A second vertical pattern extends into the second insulating layer, the second electrode layer, and the first insulating layer, wherein the second vertical pattern is electrically connected to the first vertical pattern.

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