Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The manufacturing method comprises the steps of providing a semiconductor structure which comprises a semiconductor layer, an initial laminated structure located on the semiconductor layer, an initial grid line isolation structure and an initial contact structure; wherein the initial laminated structure comprises gate sacrificial layers and interlayer insulating layers which are alternately stacked; the initial grid line isolation structure comprises a grid line isolation groove and a first sacrificial layer located in the grid line isolation groove; the initial contact structure comprises a contact hole, an isolation column located in the contact hole and a second sacrificial layer located in the contact hole, and the initial contact structure extends in the stacking direction and is connected to the target gate sacrificial layer; removing the first sacrificial layer in the grid line separation groove and the second sacrificial layer in the contact hole; removing a part of the gate sacrificial layer through the gate line isolation groove to form a first gap; the first gaps are communicated with the corresponding contact holes; and forming a conductive structure in the first gap and the contact hole.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] As the number of stacked layers of three-dimensional memory continues to increase, the etching depth of the contact holes (CT) extending to different gate layers is getting deeper and deeper, and higher requirements are also put forward for the etching process of the contact holes and the process of etching the stop layer. In order to reduce the difficulty of the process, the staircase contact (SCT) architecture is proposed in the relevant technical solution, which combines the stair step (SS) process and the contact hole process into one, greatly simplifying the process flow. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0006] A semiconductor structure is provided, comprising a semiconductor layer, an initial stacked structure located on the semiconductor layer, an initial gate line isolation structure and an initial contact structure; wherein the initial stacked structure comprises alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate line isolation structure comprises a gate line isolation groove and a first sacrificial layer located in the gate line isolation groove; the initial contact structure comprises a contact hole, an isolation column located in the contact hole and a second sacrificial layer located in the contact hole, and the initial contact structure extends along a stacking direction and is connected to a target gate sacrificial layer;

[0007] removing the first sacrificial layer in the gate line spacing groove and the second sacrificial layer in the contact hole;

[0008] Removing part of the gate sacrificial layer through the gate line spacing groove to form a first gap; the first gap is connected to the corresponding contact hole;

[0009] A conductive structure is formed in the first gap and the contact hole.

[0010] In some embodiments, the contact hole includes a first portion and a second portion that are connected, the first portion extends along the stacking direction and penetrates the target gate sacrificial layer, the second portion extends along a direction parallel to the semiconductor layer and exposes the side wall of the target gate sacrificial layer, and the second portion surrounds the first portion; wherein the isolation column extends along the stacking direction and is located within the first portion.

[0011] In some embodiments, providing a semiconductor structure includes:

[0012] forming an initial stacked structure on the semiconductor layer;

[0013] forming a gate line trench penetrating the initial stacked structure and extending to the semiconductor layer;

[0014] A first sacrificial layer is formed in the gate line isolation groove; wherein the gate line isolation groove and the first sacrificial layer together form the initial gate line isolation structure.

[0015] In some embodiments, after forming the first sacrificial layer in the gate line trench, the manufacturing method further includes:

[0016] forming a contact hole extending to the target gate sacrificial layer along a stacking direction;

[0017] forming a second sacrificial layer in the contact hole, wherein the second sacrificial layer covers the sidewall and the bottom of the first portion of the contact hole and fills the second portion of the contact hole;

[0018] removing the second sacrificial layer covering the bottom of the first portion of the contact hole;

[0019] An isolation column is formed in the first portion of the contact hole; wherein the contact hole, the isolation column and the second sacrificial layer together form the initial contact structure.

[0020] In some embodiments, providing a semiconductor structure includes:

[0021] forming an initial stacked structure on the semiconductor layer;

[0022] forming a contact hole extending to the target gate sacrificial layer along a stacking direction;

[0023] forming a second sacrificial layer in the contact hole, wherein the second sacrificial layer covers the sidewall and the bottom of the first portion of the contact hole and fills the second portion of the contact hole;

[0024] removing the second sacrificial layer covering the bottom of the first portion of the contact hole;

[0025] An isolation column is formed in the first portion of the contact hole; wherein the contact hole, the isolation column and the second sacrificial layer together form the initial contact structure.

[0026] In some embodiments, after forming the isolation column in the first portion of the contact hole, the manufacturing method further includes:

[0027] forming a gate line trench penetrating the initial stacked structure and extending to the semiconductor layer;

[0028] A first sacrificial layer is formed in the gate line isolation groove; wherein the gate line isolation groove and the first sacrificial layer together form the initial gate line isolation structure.

[0029] In some embodiments, the initial contact structure further includes an oxide layer covering a first portion of a sidewall of the contact hole;

[0030] Before removing the first sacrificial layer in the gate line trench and the second sacrificial layer in the contact hole, the manufacturing method further includes:

[0031] Etching the initial contact structure along the stacking direction to form at least one groove; wherein the size of the groove along the direction parallel to the semiconductor layer is greater than or equal to the distance between the isolation column and the oxide layer along the direction parallel to the semiconductor layer;

[0032] The groove is filled with insulating material to form a supporting structure.

[0033] In some embodiments, the semiconductor structure includes a core region and a connection region; the gate line spacer includes a portion of the gate line spacer located in the core region and a portion of the gate line spacer located in the connection region;

[0034] Before removing the first sacrificial layer in the gate line trench and the second sacrificial layer in the contact hole, the manufacturing method further includes:

[0035] forming a protective layer, the protective layer covering the surface of the initial stacked structure of the core region and the connection region;

[0036] removing the protective layer covering the surface of the initial laminated structure of the core area;

[0037] removing the first sacrificial layer in a portion of the gate line spacing grooves in the core area;

[0038] Removing the gate sacrificial layer located in the core area through a portion of the gate line spacing grooves located in the core area to form a second gap;

[0039] The protective layer covering the surface of the initial laminate structure in the connection area is removed.

[0040] In some embodiments, removing the first sacrificial layer in the gate line trench and the second sacrificial layer in the contact hole includes:

[0041] removing the first sacrificial layer in a portion of the gate line spacing grooves located in the connection area and the second sacrificial layer in the contact hole;

[0042] The step of removing a portion of the gate sacrificial layer through the gate line spacing groove to form a first gap includes:

[0043] A portion of the gate sacrificial layer located in the connection area is removed through a portion of the gate line spacing groove located in the connection area to form a first gap; wherein the first gap is connected to the second gap.

[0044] In some embodiments, forming a conductive structure in the first gap and the contact hole includes:

[0045] A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line spacer and the contact hole; wherein the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap jointly form a gate layer, and the gate layer and the interlayer insulating layer jointly form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole jointly form a connecting layer, and the connecting layer simultaneously fills the first part and the second part of the contact hole to form a contact structure.

[0046] In some embodiments, forming a conductive structure in the first gap and the contact hole includes:

[0047] A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line spacer and the contact hole; wherein the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap jointly form a gate layer, and the gate layer and the interlayer insulating layer jointly form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole jointly constitute a connecting layer, and the connecting layer fills up the second part of the contact hole, and the connecting layer does not fill up the first part of the contact hole.

[0048] In some embodiments, after sequentially forming a dielectric layer, a first conductive layer, and a second conductive layer in the first gap, the second gap, and the contact hole through the gate line spacer and the contact hole, the manufacturing method further includes:

[0049] A first filling layer is formed, wherein the first filling layer fills the gap between the first part of the side wall of the contact hole and the isolation column to form a contact structure.

[0050] In some embodiments, the first filling layer is formed using an atomic layer deposition process.

[0051] In some embodiments, after forming the conductive structure in the first gap and the contact hole, the manufacturing method further includes:

[0052] The second conductive layer and the first conductive layer in the gate line isolation groove are removed.

[0053] In some embodiments, after removing the second conductive layer and the first conductive layer in the gate line isolation groove, the manufacturing method further includes:

[0054] forming an isolation layer, wherein the isolation layer covers the sidewalls and the bottom of the gate line isolation groove;

[0055] A second filling layer is formed; wherein the gate line isolation groove, the isolation layer and the second filling layer together form a gate line isolation structure.

[0056] In some embodiments, the semiconductor structure further includes a channel structure located in the core region and a dummy channel structure located in the connection region;

[0057] After forming the second filling layer, the manufacturing method further includes:

[0058] forming a dielectric layer covering the channel structure, the dummy channel structure and the contact structure;

[0059] Etching the dielectric layer to form a first through hole, a second through hole and a third through hole respectively connected to the channel structure, the dummy channel structure and the conductive structure in the contact structure;

[0060] Conductive material is filled in the first through hole, the second through hole and the third through hole to form a first lead-out structure, a second lead-out structure and a third lead-out structure respectively.

[0061] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0062] A stacked structure, the stacked structure comprising a core region and a connection region; the stacked structure comprising alternately stacked gate layers and interlayer insulating layers;

[0063] A contact structure extending along the stacking direction to the target gate layer in the stacked structure; the contact structure comprises an isolation column extending along the stacking direction and a conductive structure located between the sidewall of the contact hole and the isolation column; the contact structure is located in the connection area.

[0064] In some embodiments, the contact structure includes a first part and a second part that are connected to each other, the first part extends to the target gate layer along the stacking direction, the second part extends perpendicular to the stacking direction and is connected to the target gate layer, and the second part surrounds the first part; wherein the first part includes an isolation column and a conductive structure located between the side wall of the first part and the isolation column, and the second part includes a conductive structure.

[0065] In some embodiments, the semiconductor device further comprises:

[0066] a channel structure located in the core region and a dummy channel structure located in the connection region;

[0067] A dielectric layer covering the stacked structure located in the core area and the connection area;

[0068] A first lead-out structure, a second lead-out structure and a third lead-out structure are located in the dielectric layer and are respectively connected to the channel structure, the dummy channel structure and the conductive structure in the contact structure.

[0069] In some embodiments, the conductive structure of the second portion of the contact structure includes a dielectric layer, a first conductive layer, and a second conductive layer; wherein the dielectric layer, the first conductive layer, and the second conductive layer together form a connecting layer;

[0070] The conductive structure of the first part of the contact structure includes the connecting layer.

[0071] In some embodiments, the third lead-out structure is connected to one of the connection layers.

[0072] In some embodiments, the conductive structure of the second portion of the contact structure includes a dielectric layer, a first conductive layer, and a second conductive layer; wherein the dielectric layer, the first conductive layer, and the second conductive layer together form a connecting layer;

[0073] The conductive structure of the first part of the contact structure includes the connection layer, the first filling layer and the connection layer in sequence along the radial outward direction.

[0074] In some embodiments, the third lead-out structure is connected to two of the connection layers.

[0075] In some embodiments, the contact structure further includes an oxide layer located on a sidewall of the first portion; and the semiconductor device further includes:

[0076] At least one supporting structure is embedded in the contact structure along the stacking direction, and a dimension of the supporting structure along the direction perpendicular to the stacking direction is greater than or equal to a distance between the isolation column and the oxide layer along the direction perpendicular to the stacking direction.

[0077] In some embodiments, the semiconductor device further comprises:

[0078] A gate line isolation structure passes through the stacked structure along the stacking direction.

[0079] In a third aspect, an embodiment of the present disclosure provides a memory system, including:

[0080] A semiconductor device as described in the above technical solution;

[0081] and a controller coupled to the semiconductor device, the controller being configured to control the semiconductor device.

[0082] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system. In the embodiments of the present disclosure, a contact hole has been formed before performing a gate replacement process, so that when the gate replacement process is performed first and then the contact hole is formed, damage to the gate layer during the formation of the contact hole can be improved, thereby affecting the structural stability and breakdown voltage. In addition, an isolation column is also provided in the contact hole, so that when filling the sacrificial material in the contact hole, only the remaining space except the isolation column needs to be filled, which can save sacrificial material and thus save manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1A A schematic diagram of a cross-sectional structure of a memory provided as an example;

[0084] Figure 1B A three-dimensional structure diagram of a contact hole provided as an example;

[0085] Figure 2 A schematic diagram of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0086] Figure 3A A top view of a semiconductor device provided by an embodiment of the present disclosure;

[0087] Figure 3B A top view of another semiconductor device provided by an embodiment of the present disclosure;

[0088] Figures 4A to 4X A schematic diagram of a cross-sectional structure of a semiconductor device during a manufacturing process provided by an embodiment of the present disclosure;

[0089] FIG. 5A to FIG. 5J A schematic cross-sectional structure diagram of another semiconductor device during the manufacturing process provided by an embodiment of the present disclosure;

[0090] Fig. 6A A schematic diagram of a top view of a support structure in a semiconductor device provided in an embodiment of the present disclosure;

[0091] Figure 6B A schematic diagram of a top view of a support structure in a semiconductor device provided in an embodiment of the present disclosure Figure 2 ;

[0092] Figure 6C A third schematic diagram of a top view of a support structure in a semiconductor device provided in an embodiment of the present disclosure;

[0093] Figure 7 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure;

[0094] Figure 8 A schematic cross-sectional structure diagram of another semiconductor device provided in an embodiment of the present disclosure;

[0095] Fig. 9 A block diagram of a system having a semiconductor device provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0096] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0097] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0098] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0099] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0100] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0101] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0102] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0103] refer to Figure 1A , Figure 1A The cross-sectional structure diagram of a memory provided as an example. Figure 1A As shown, the memory may include a composite substrate 100 and a stacked structure 101 located on the composite substrate 100, wherein the stacked structure 101 includes alternately stacked gate layers 102 and interlayer insulating layers 103. The memory may include an array region, wherein the array region includes a core region ( Figure 1A The core region may include a plurality of channel structures (not shown) and a connection region 104. As an example, the core region may include a plurality of channel structures (Channel Hole, CH) for storing data. The connection region 104 may include a contact hole 105, and a contact structure may be formed after the contact hole 105 is filled. The contact structure may extend to the target gate layer along the stacking direction and be used to realize the electrical connection between the contact structure and the target gate layer. The connection region 104 may also include a dummy channel structure (Dummy Channel Hole, DCH) 106 for supporting. The array region may include a gate line spacer, which extends from the core region to the connection region. The function of the gate line spacer includes but is not limited to providing an etchant path for replacing the gate sacrificial layer in the stacked structure 101 with the gate layer. After the gate sacrificial layer located in the core region and part of the gate sacrificial layer located in the connection region 104 are replaced with the gate layer 102 through the gate line spacer, the gate line spacer may be filled to form a gate line isolation structure 107.

[0104] refer to Figure 1B , Figure 1B The three-dimensional structure diagram of the contact hole provided as an example. Figure 1B As shown, it should be noted that each contact hole 105 has its corresponding target gate sacrificial layer, and after the gate replacement process is performed, each contact structure has its corresponding target gate layer. Each contact structure can be connected to the target gate layer in a direction parallel to the composite substrate 100, but will not be connected to other gate layers except the target gate layer, so that after applying a voltage, an electrical connection is achieved between the contact structure and the target gate layer, while there is no electrical connection between the contact structure and other gate layers except the target gate layer.

[0105] Still Figure 1AAs shown, in some embodiments, during the manufacturing process of the memory, a gate replacement process is performed through the gate line spacer, and the gate line spacer is filled to form a gate line isolation structure 107; and a contact hole 105 is formed by etching, wherein the contact hole 105 is formed in the connection area 104. Since the gate replacement process has been performed at this time, the gate layer 102 and the interlayer insulating layer 103 may be damaged in the process of etching the stacked structure to form the contact hole, thereby affecting the stability of the structure and the breakdown voltage. More specifically, the gate layer may include a dielectric layer 108, a titanium nitride layer 109, and a tungsten layer 110. The dielectric layer 108 may include a high dielectric constant material, for example, the material of the dielectric layer may include aluminum oxide. The dielectric layer 108 may be damaged in the process of etching to form the contact hole.

[0106] Furthermore, during the manufacturing process of the memory, a gate replacement process is performed through a gate line spacer to form a word line (e.g., a dielectric layer, a titanium nitride layer, and a tungsten layer); a contact hole is formed by etching, and the contact hole needs to be filled, for example, to form a titanium nitride layer and a tungsten layer, so as to achieve electrical connection between the contact structure and the target gate layer. In this way, two complete steps of forming a titanium nitride layer and a tungsten layer are required, and the process steps are relatively complicated and the process cost is relatively high.

[0107] refer to Figure 2 , Figure 2 The flowchart of the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure is as follows. Figure 2 As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0108] Step S201: providing a semiconductor structure, including a semiconductor layer, an initial stacked structure located on the semiconductor layer, an initial gate line isolation structure, and an initial contact structure; wherein the initial stacked structure includes alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate line isolation structure includes a gate line isolation groove and a first sacrificial layer located in the gate line isolation groove; the initial contact structure includes a contact hole, an isolation column located in the contact hole, and a second sacrificial layer located in the contact hole, and the initial contact structure extends along a stacking direction and is connected to a target gate sacrificial layer;

[0109] Step S202: removing the first sacrificial layer in the gate line trench and the second sacrificial layer in the contact hole;

[0110] Step S203: removing a portion of the gate sacrificial layer through the gate line spacer to form a first gap; the first gap is connected to the corresponding contact hole;

[0111] Step S204: forming a conductive structure in the first gap and the contact hole.

[0112] In the disclosed embodiment, the first sacrificial layer in the gate line spacer and the second sacrificial layer in the contact hole are removed simultaneously, and part of the gate sacrificial layer is removed through the gate line spacer to form a first gap; the first gap and the contact hole are connected to form an "L-shaped" path in the cross-sectional structural schematic diagram, and then the conductive structure (for example, the dielectric layer, the first conductive layer, and the second conductive layer) is filled in one step to achieve electrical connection between the contact structure and the target gate layer.

[0113] The following will be combined Figure 3A as well as Figures 4A to 4X , the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure is described in detail. Figure 3A A top view of a semiconductor device provided in an embodiment of the present disclosure, Figures 4A to 4X A schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. Figures 4A to 4X The schematic cross-sectional structure diagram of the connection area of ​​the semiconductor device can be regarded as Figure 3A Schematic diagram of the cross-sectional structure along the AA direction.

[0114] like Figure 3A As shown, the semiconductor device includes an array region 200, and the array region 200 includes a core region 201 and a connection region 202. The core region 201 of the semiconductor device may include a channel structure 203. The connection region 202 of the semiconductor device may include a dummy channel structure 204 and a contact structure 241. The array region 200 of the semiconductor device may include a gate line isolation structure 244, and the gate line isolation structure 244 may extend from the core region 201 to the connection region 202.

[0115] It should be noted that Figure 3A A top view of the channel structure 203 and the dummy channel structure 204 is shown, and Figures 4A to 4X The cross-sectional structure diagrams of the dummy channel structure 204 are shown, and these drawings only show an optional structure of the channel structure 203 and the dummy channel structure 204. The embodiments of the present disclosure do not specifically limit the specific structures of the channel structure 203 and the dummy channel structure 204.

[0116] Here, the stacking direction of the stacked structure of the semiconductor device is defined as the Z direction, and the X direction and the Y direction intersecting each other are defined in the surface perpendicular to the Z direction. For example, the X direction and the Y direction may be perpendicular to each other. In this way, the X direction, the Y direction and the Z direction are perpendicular to each other. Here, the direction parallel to the semiconductor layer may be any direction in the XY plane, for example, the X direction and the Y direction. Figure 3A It is shown that the gate line isolation structure 244 is parallel to the Y direction.

[0117] For ease of explanation, Figure 3AIt is illustrated that the orthographic projections of the channel structure 203, the dummy channel structure 204 and the contact structure 241 in the XY plane are all circles. In fact, the orthographic projections of the channel structure 203, the dummy channel structure 204 and the contact structure 241 in the XY plane may be other shapes. The embodiments of the present disclosure do not impose any special limitation on the shapes of the orthographic projections of the channel structure 203, the dummy channel structure 204 and the contact structure 241 in the XY plane.

[0118] For illustration purposes, Figure 3A The illustrated channel structure 203, the dummy channel structure 204, the gate line isolation structure 244 and the contact structure 241 are not filled with graphics. In fact, the channel structure 203, the dummy channel structure 204, the gate line isolation structure 244 and the contact structure 241 are all formed by filling multiple material layers, which will be explained later in conjunction with the cross-sectional structural schematic diagram of the gate line isolation structure 244 and the contact structure 241.

[0119] In the embodiment of the present disclosure, in step S201, a semiconductor structure is provided, including a semiconductor layer, an initial stacked structure located on the semiconductor layer, an initial gate line isolation structure and an initial contact structure; wherein the initial stacked structure includes alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate line isolation structure includes a gate line isolation groove and a first sacrificial layer located in the gate line isolation groove; the initial contact structure includes a contact hole, an isolation column located in the contact hole and a second sacrificial layer located in the contact hole, and the initial contact structure extends along the stacking direction and is connected to the target gate sacrificial layer.

[0120] In the embodiment of the present disclosure, there is no particular limitation on the process sequence of forming the initial gate line isolation structure 206 and forming the initial contact structure 205. In some embodiments, the initial contact structure 205 may be formed first, and then the initial gate line isolation structure 206 may be formed. FIG. 4A to FIG. 4M , the process of first forming the initial contact structure 205 and then forming the initial gate line isolation structure 206 is described in detail.

[0121] In the embodiment of the present disclosure, step S201 includes:

[0122] forming an initial stacked structure on the semiconductor layer;

[0123] forming a contact hole extending to the target gate sacrificial layer along the stacking direction;

[0124] forming a second sacrificial layer in the contact hole, wherein the second sacrificial layer covers the sidewall and the bottom of the first portion of the contact hole and fills the second portion of the contact hole;

[0125] removing the second sacrificial layer covering the bottom of the first portion of the contact hole;

[0126] An isolation column is formed in the first portion of the contact hole; wherein the contact hole, the isolation column and the second sacrificial layer together form an initial contact structure.

[0127] Such as 3A and Figure 4A As shown, an initial stacked structure 208 is formed on the semiconductor layer 207, and the initial stacked structure 208 includes alternately stacked gate sacrificial layers 209 and interlayer insulating layers 210. The initial stacked structure 208 includes an array region, and the array region 200 includes a core region 201 and a connection region 202; a channel structure 203 and a dummy channel structure 204 that penetrate the initial stacked structure 208 along the Z direction and extend to the semiconductor layer 207 can also be formed; wherein the channel structure 203 is located in the core region 201, and the dummy channel structure 204 is located in the connection region 202.

[0128] Figure 4A Only the connection region 202 of the semiconductor device and the dummy channel structure 204 located in the connection region 202 are shown. Figure 4A The core region of the semiconductor device and the channel structure located in the core region are not shown schematically. Figure 4A Only two dummy channel structures 204 located in the connection region 202 are illustrated. In fact, the number of dummy channel structures 204 in the connection region 202 of the semiconductor device provided in the embodiment of the present disclosure is not limited thereto.

[0129] In some embodiments, semiconductor layer 207 may be a composite semiconductor layer, for example, semiconductor layer 207 may sequentially include substrate 211, first silicon oxide layer 212, stop layer 213, second silicon oxide layer 214 and polysilicon layer 215. In a specific example, the material of stop layer 213 may also include silicon oxide.

[0130] In some embodiments, the substrate 211 may be a single semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate; or the substrate 211 may be a composite semiconductor material substrate, such as a silicon germanium (SiGe) substrate; or the substrate may be a silicon on insulator (SOI) substrate, a germanium on insulator (GeOI) substrate, and the like.

[0131] In some embodiments, the gate sacrificial layer 209 and the interlayer insulating layer 210 may be formed on the semiconductor layer 207 by one or more deposition processes, wherein the deposition process may include but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof.

[0132] It is understood that the number and thickness of the gate sacrificial layer 209 and the interlayer insulating layer 210 are not limited to Figure 4A The number and thickness shown. Those skilled in the art can set any number and thickness of the gate sacrificial layer 209 and the interlayer insulating layer 210 according to actual needs. In addition, the materials of the gate sacrificial layer 209 and the interlayer insulating layer 210 can be selected from suitable materials known in the art. Here, the interlayer insulating layer 210 can be an oxide layer, such as a silicon oxide layer; the gate sacrificial layer 209 can be a nitride layer, such as a silicon nitride layer.

[0133] In some embodiments, the channel structure 203 and the dummy channel structure 204 are formed simultaneously in the initial stacked structure 208 and have the same structure. The difference between the channel structure 203 and the dummy channel structure 204 is that the channel structure 203 can be used to store data, while the dummy channel structure 204 does not have the function of storing data and is only used to support the stability and reliability of the semiconductor device structure. Figure 4A The virtual channel structure 204 shown is used as an example for explanation. The virtual channel structure 204 can be in the shape of a cylinder, an elliptical cylinder, a truncated cone or a rectangular parallelepiped. The virtual channel structure 204 includes a blocking layer, a charge trapping layer, a tunneling layer, a channel layer and a channel oxide layer in the radial inward direction. In a specific example, the materials of the blocking layer, the charge trapping layer, the tunneling layer, the channel layer and the channel oxide layer can be silicon oxide, silicon nitride, silicon oxide, polysilicon and silicon oxide in sequence.

[0134] like Figure 4B As shown, the initial stacked structure 208 is etched along the Z direction to form a first sub-contact hole 216 , and the bottom of the first sub-contact hole 216 exposes a portion of the interlayer insulating layer 210 above the target gate sacrificial layer 217 .

[0135] Here, the bottom of the first sub-contact hole 216 exposes a portion of the interlayer insulating layer 210 above the target gate sacrificial layer 217, which means that the initial stacked structure 208 is etched until a portion of the interlayer insulating layer 210 above the target gate sacrificial layer 217 is etched, and the bottom of the first sub-contact hole 216 stays in the interlayer insulating layer 210. In other words, compared with the initial thickness of the interlayer insulating layer 210, the thickness of the interlayer insulating layer 210 located below the bottom of the first sub-contact hole 216 is reduced.

[0136] In some embodiments, the initial stacked structure 208 is etched to form a first sub-contact hole 216 , and the bottom of the first sub-contact hole 216 may also expose the target gate sacrificial layer 217 .

[0137] like Figure 4CAs shown, an oxide material layer 218 is formed, and the oxide material layer 218 covers the bottom and sidewalls of the first sub-contact hole 216 , and the oxide material layer 218 covers the surface of the initial stacked structure 208 located in the connection region 202 .

[0138] Combination Figure 4C and Figure 4D As shown, the oxide material layer 218 covering the bottom of the first sub-contact hole 216 is removed, and the oxide material layer 218 covering the sidewall of the first sub-contact hole 216 is retained to form an oxide layer 219 .

[0139] It should be noted that, while removing the oxide material layer 218 covering the bottom of the first sub-contact hole 216 , the interlayer insulating layer 210 exposed at the bottom of the first sub-contact hole 216 is also removed to expose the target gate sacrificial layer 217 .

[0140] like Figure 4E As shown, a portion of the target gate sacrificial layer 217 is etched away along a direction parallel to the semiconductor layer 207 through the first sub-contact hole 216 to form a second sub-contact hole 220, the second sub-contact hole 220 and the target gate sacrificial layer 217 are located in the same layer, the bottom of the second sub-contact hole 220 exposes the interlayer insulating layer 210 adjacent to the target gate sacrificial layer 217, and the sidewall of the second sub-contact hole 220 exposes the sidewall of the target gate sacrificial layer 217; more specifically, the bottom of the second sub-contact hole 220 exposes the interlayer insulating layer 210 below the target gate sacrificial layer 217; wherein the size of the second sub-contact hole 220 in a direction perpendicular to the stacking direction (i.e., a direction parallel to the semiconductor layer 207) is greater than the size of the first sub-contact hole 216 in a direction perpendicular to the stacking direction (i.e., a direction parallel to the semiconductor layer 207), and the first sub-contact hole 216 and the second sub-contact hole 220 together form a contact hole 221.

[0141] It should be noted that according to the process sequence, Figure 4E As shown in the dashed box, the contact hole 221 can be divided into a first sub-contact hole 216 and a second sub-contact hole 220. The etching depth of the first sub-contact hole 216 extends from the surface of the initial stacked structure 208 to the surface of the target gate sacrificial layer 217, and the etching depth of the second sub-contact hole 220 is the same as the thickness of the target gate sacrificial layer 217. Figure 4EAs shown in the dotted line box, the contact hole 221 can also be divided into a first portion 222 and a second portion 223. The etching depth of the first portion 222 of the contact hole 221 is from the surface of the initial stacked structure 208 to the target gate sacrificial layer 217. The second portion 223 of the contact hole 221 and the target gate sacrificial layer 217 are located in the same layer and the second portion 223 surrounds the first portion 222. The second portion 223 extends in a direction parallel to the semiconductor layer 207 and exposes the sidewall of the target gate sacrificial layer 217. The first portion 222 extends in the Z direction to the first portion in a direction parallel to the semiconductor layer 207 and is connected to the second portion 223, and the second portion 223 surrounds the first portion 222. The etching depth of the first portion 222 of the contact hole 221 is greater than the etching depth of the first sub-contact hole 216. Here, the etching depth refers to the etching depth along the Z direction.

[0142] Figure 4E Only one contact hole 221 is shown. In fact, the number of contact holes 221 in the semiconductor device provided by the embodiment of the present disclosure is not limited thereto. In some embodiments, the number of contact holes 221 can be the same as the number of gate sacrificial layers 209 in the initial stacked structure 208. Each contact hole 221 has a corresponding gate sacrificial layer 209, that is, a target gate sacrificial layer 217. Different contact holes 221 correspond to different target gate sacrificial layers 217.

[0143] Combination Figure 4E and Figure 4F As shown, a second sacrificial material layer 224 is formed in the contact hole 221, and the second sacrificial material layer 224 covers the sidewall and bottom of the first portion 222 of the contact hole 221, and fills the second portion 223 of the contact hole 221. At this time, the second sacrificial material layer 224 is in direct contact with the oxide layer 219 covering the sidewall of the first sub-contact hole 216. Of course, during the process of forming the second sacrificial material layer 224, the second sacrificial material layer 224 will also cover the surface of the initial stacked structure 208.

[0144] In some embodiments, the process of forming the second sacrificial material layer 224 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0145] In some embodiments, the material of the second sacrificial material layer 224 may include, but is not limited to, polysilicon.

[0146] Combination Figure 4F and Figure 4G, the second sacrificial material layer 224 covering the bottom of the first portion 222 of the contact hole 221 is removed, and only the second sacrificial material layer 224 covering the sidewall of the first portion 222 of the contact hole 221 and filling the second portion 223 of the contact hole 221 is retained to form a second sacrificial layer 225. Of course, in the process of removing the second sacrificial material layer 224 covering the bottom of the first portion 222 of the contact hole 221, the second sacrificial material layer 224 covering the surface of the initial stacked structure 208 will also be removed.

[0147] In some embodiments, a process including but not limited to an etch back process may be used to remove the second sacrificial material layer 224 covering the bottom of the first portion 222 of the contact hole 221 .

[0148] like Figure 4H As shown, a first isolation material layer 226 is formed in the contact hole 221. Since an oxide layer 219 and a second sacrificial layer 225 have been formed in the first portion 222 of the contact hole 221, and the second portion 223 of the contact hole 221 has been filled with the second sacrificial layer 225, the isolation material is located in the first portion of the contact hole 221. Of course, the first isolation material layer 226 will also cover the surface of the initial stacked structure 208 and the surface of the oxide layer 219 and the second sacrificial layer 225 in the first portion 222 of the contact hole 221.

[0149] Combination Figure 4H and Fig. 4I As shown, the first isolation material layer 226 is planarized, and the first isolation material layer 226 covering the surface of the initial stacked structure 208 is removed to expose the oxide layer 219 in the first portion 222 of the contact hole 221 and the surface of the second sacrificial layer 225, and the first isolation material layer 226 in the first portion 222 of the contact hole 221 is retained to form an isolation column 227. Here, the contact hole 221, the isolation column 227, the second sacrificial layer 225 and the oxide layer 219 together form the initial contact structure 205.

[0150] In some embodiments, the planarization process may include but is not limited to a chemical mechanical polishing (CMP) process.

[0151] In the disclosed embodiment, after forming the channel structure and the dummy channel structure in the core region and the connection region respectively, a contact hole is directly formed, and polysilicon material can be filled in the contact hole to form a second sacrificial layer; subsequently, an oxide material can be filled in the contact hole to form an isolation column. In this way, on the one hand, when the contact hole is formed after the gate replacement process is performed, the gate layer is damaged during the formation of the contact hole, thereby affecting the structural stability and breakdown voltage; on the other hand, the polysilicon material filled in the contact hole is reduced, thereby reducing the process cost.

[0152] In the embodiment of the present disclosure, after forming the isolation column in the first portion of the contact hole, the manufacturing method further includes:

[0153] forming a gate line slit (GLS) penetrating the initial stacked structure and extending to the semiconductor layer;

[0154] A first sacrificial layer is formed in the gate line isolation groove; wherein the gate line isolation groove and the first sacrificial layer together form an initial gate line isolation structure.

[0155] like Figure 4J As shown, the initial stacked structure 208 is etched to form a gate line trench 228 that penetrates the initial stacked structure 208 and extends to the semiconductor layer 207; wherein the gate line trench 228 is located in the array area, for example, the gate line trench 228 can extend from the core area to the connection area 202. Figure 3A Correspondingly, the gate line isolation structure is located in the array area 200 and can extend from the core area 201 to the connection area 202 .

[0156] like Figure 4K As shown, the substrate 211 exposed at the bottom of the gate line trench 228 and the polysilicon layer 215 exposed at the sidewall of the gate line trench 228 can be oxidized, and the material of the substrate 211 can be, for example, polysilicon. In this way, the polysilicon exposed at the bottom and sidewall of the gate line trench 228 can be oxidized to form silicon oxide.

[0157] In the disclosed embodiment, the silicon oxide formed on the bottom and sidewalls of the gate line isolation groove 228 can play an isolation role.

[0158] In some embodiments, the process of oxidizing the substrate exposed at the bottom of the gate line spacer and the polysilicon layer exposed at the sidewall of the gate line spacer includes but is not limited to wet oxidation.

[0159] like Figure 4L As shown, a first sacrificial material layer 229 is formed in the gate line isolation groove 228 , and the first sacrificial material layer 229 also covers the surface of the initial stacked structure 208 and the surface of the initial contact structure 205 .

[0160] In some embodiments, the material of the first sacrificial material layer 229 may be, but is not limited to, polysilicon.

[0161] In some embodiments, the process of forming the first sacrificial material layer 229 may include, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0162] Combination Figure 4L and Figure 4MAs shown, the first sacrificial material layer 229 may be planarized, and the first sacrificial material layer 229 covering the surface of the initial stacked structure 208 may be removed to expose the surface of the initial stacked structure 208, and the first sacrificial material layer 229 located in the gate line isolation groove 228 may be retained to form a first sacrificial layer 230. The gate line isolation groove 228 and the first sacrificial layer 230 together form the initial gate line isolation structure 206.

[0163] In the embodiment of the present disclosure, there is no special limitation on the process sequence of forming the first gap 232 and forming the second gap. In some embodiments, the first gap 232 can be formed by first removing a portion of the gate sacrificial layer 209 located in the connection area 202 through a portion of the gate line spacing groove 228 located in the connection area 202, and then the gate sacrificial layer 209 located in the core area 201 can be removed through a portion of the gate line spacing groove 228 located in the core area 201 to form the second gap. Figure 4N to Figure 4Q , the process of first forming the first gap 232 and then forming the second gap is described in detail.

[0164] In the embodiment of the present disclosure, the gate line spacing groove includes a portion of the gate line spacing groove located in the core area and a portion of the gate line spacing groove located in the connection area; before step S202, the manufacturing method further includes:

[0165] forming a protective layer, the protective layer covering the surface of the initial laminated structure of the core region and the connection region;

[0166] The protective layer covering the surface of the initial laminate structure in the connection area is removed.

[0167] like Figure 4N As shown, a protection layer 231 is formed, and the protection layer 231 covers the surface of the initial stacked structure 208 located in the core area and the connection area 202. Of course, the protection layer 231 also covers the surface of the initial gate line isolation structure 206 and the initial contact structure 205. Figure 4N The protective layer 231 only covers the surface of the initial stacked structure 208 of the connection area 202, the surface of the initial gate line isolation structure 206 and the surface of the initial contact structure 205. Figure 4N The protective layer 231 is not shown to cover the surface of the initial stacked structure 208 in the core area.

[0168] In some embodiments, the material of the protection layer 231 may include, but is not limited to, silicon oxide.

[0169] In some embodiments, the formation of the protection layer 231 may be achieved by an ALD deposition process.

[0170] Combination Figure 4N and Fig.4OAs shown, the protection layer 231 covering the surface of the initial stacked structure 208 in the connection area 202 may be removed, and the protection layer 231 covering the surface of the initial stacked structure 208 in the core area may be retained.

[0171] In the embodiment of the present disclosure, the purpose of retaining the protection layer 231 covering the surface of the initial stacked structure 208 of the core area 201 is to protect the initial stacked structure 208 of the core area 201 from being damaged during subsequent processes.

[0172] In the embodiment of the present disclosure, step S202 includes: removing the first sacrificial layer in a portion of the gate line isolation grooves located in the connection area and the second sacrificial layer in the contact hole;

[0173] Step S203 includes: removing a portion of the gate sacrificial layer located in the connection area through a portion of the gate line spacing groove located in the connection area to form a first gap.

[0174] Combination Fig.4O and Figure 4P As shown, the first sacrificial layer 230 in the gate line isolation groove 228 of the connection area 202 and the second sacrificial layer 225 in the contact hole 221 are removed, and the isolation column 227 in the first portion 222 of the contact hole 221 is retained.

[0175] like Figure 4Q As shown, a portion of the gate sacrificial layer 209 located in the connection area 202 is removed through a portion of the gate line isolation groove 228 located in the connection area 202 to form a first gap 232 (as shown in FIG. Figure 4Q As shown in the dashed box in the middle). In this way, the first gap 232 located in the connection area 202 is connected to the contact hole 221, so as to form a conductive structure in the subsequent process.

[0176] In the disclosed embodiment, after the gate line trench is formed, polysilicon material may be filled in the gate line trench to form a first sacrificial layer; in a subsequent process, the first sacrificial layer in the gate line trench and the second sacrificial layer in the contact hole may be removed simultaneously.

[0177] In the embodiment of the present disclosure, after step S203, the manufacturing method further includes:

[0178] removing a protective layer on the surface of the initial laminate structure covering the core area;

[0179] removing the first sacrificial layer in a portion of the gate line spacing grooves located in the core area;

[0180] The gate sacrificial layer located in the core area is removed through a portion of the gate line spacing grooves located in the core area to form a second gap; wherein the first gap and the second gap are connected.

[0181] Here, the first sacrificial layer 230 in part of the gate line groove 228 located in the connection area 202 and the second sacrificial layer 225 in the contact hole 221 are removed, and part of the gate sacrificial layer 209 is removed through part of the gate line groove 228 located in the connection area 202 to form a first gap 232; then the first sacrificial layer in part of the gate line groove located in the core area is removed, and the gate sacrificial layer is removed through part of the gate line groove located in the core area to form a second gap.

[0182] Illustratively, before removing the protective layer covering the surface of the initial stacked structure in the core area, a protective material, such as a photoresist material, can be filled in the first gap 232 and the contact hole 221 in the connection area 202 to reduce damage to the structure in the connection area caused by the subsequent process of removing the first sacrificial layer in the gate line spacer in the core area and the gate sacrificial layer in the core area.

[0183] In the embodiment of the present disclosure, step S204 includes:

[0184] A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through gate line grooves and contact holes; wherein the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap jointly form a gate layer, and the gate layer and the interlayer insulating layer jointly form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole jointly constitute a connecting layer, and the connecting layer fills up the second part of the contact hole, and the connecting layer does not fill up the first part of the contact hole.

[0185] Combination Figure 4Q and Figure 4RAs shown, a dielectric layer 233, a first conductive layer 234 and a second conductive layer 235 are sequentially formed in the first gap 232, the second gap and the contact hole 221 through the gate line spacer 228 and the contact hole 221. Among them, the dielectric layer 233, the first conductive layer 234 and the second conductive layer 235 located in the core area and the connection area 202 jointly form a gate layer 236. That is, the gate layer 236 located in the core area is connected to the gate layer 236 located in the connection area 202, and the gate layer 236 and the interlayer insulating layer 210 jointly form a stacked structure 237. Of course, in the process of forming the dielectric layer 233, the first conductive layer 234 and the second conductive layer 235, the dielectric layer 233, the first conductive layer 234 and the second conductive layer 235 will also cover the surface of the stacked structure 237. The dielectric layer 233, the first conductive layer 234 and the second conductive layer 235 located in the contact hole 221 jointly form a connecting layer 238, and the connecting layer 238 is connected to the corresponding target gate layer 250. In the first portion 222 of the contact hole 221, the connection layer 238 covers the sidewalls of the first portion 222 of the contact hole 221 and the sidewalls of the isolation column 227, but the connection layer 238 does not fill the remaining space of the first portion 222 of the contact hole 221 except the isolation column 227, so there is still a gap between the connection layer 238 covering the sidewalls of the first portion 222 of the contact hole 221 and the connection layer 238 covering the sidewalls of the isolation column 227. In the embodiment of the present disclosure, the dielectric layer, the first conductive layer and the second conductive layer are simultaneously formed in the first gap, the second gap and the contact hole through the gate line spacer and the contact hole, and the first gap, the second gap and the contact hole are filled in a one-step method, thereby further reducing the manufacturing cost.

[0186] In the embodiment of the present disclosure, after sequentially forming a dielectric layer, a first conductive layer, and a second conductive layer in the first gap, the second gap, and the contact hole through the gate line trench and the contact hole, the manufacturing method further includes:

[0187] A first filling layer is formed, and the first filling layer fills the gap between the first part of the side wall of the contact hole and the isolation column to form a contact structure.

[0188] Combination Figure 4R and Figure 4S As shown, a first filling material layer 239 is formed, and the first filling material layer 239 can fill the gap between the sidewall of the first portion 222 of the contact hole 221 and the isolation column 227. Of course, the first filling material layer 239 also covers the sidewall and bottom of the gate line isolation groove 228 and covers the surface of the stacked structure 237.

[0189] In the embodiment of the present disclosure, the first filling layer is formed by using an ALD process.

[0190] Combination Figure 4S and Figure 4TAs shown, the first filling material layer 239 covering the sidewall and bottom of the gate line spacer 228 and the surface of the stacked structure 237 is removed, and the first filling material layer 239 located between the sidewall of the first part 222 of the contact hole 221 and the isolation column 227 is retained to form a first filling layer 240.

[0191] In the embodiment of the present disclosure, the distance between the oxide layer and the isolation column in the first part of the contact hole in a direction parallel to the semiconductor layer is greater than or equal to the thickness of the gate layer, so that at least one connecting layer (i.e., the dielectric layer, the first conductive layer, and the second conductive layer) is formed between the oxide layer and the isolation column of the contact hole. Figure 4T It is schematically shown that two connection layers are formed between the oxide layer of the contact hole and the isolation column, and the gap between the two connection layers is filled with the first filling layer, so as to fill the contact hole. Figure 5J It is schematically shown that a connection layer is formed between the oxide layer of the contact hole and the isolation column.

[0192] Here, the contact structure 241 includes a first portion 222 and a second portion 223. The first portion 222 includes an isolation column 227 and a conductive structure located between the oxide layer 219 on the sidewall of the first portion 222 and the isolation column 227. Figure 4T The conductive structure between the oxide layer 219 and the isolation pillar 227 on the sidewall of the first portion 222 shown in the diagram includes two connection layers 238 and a first filling layer 240 located between the two connection layers 238 .

[0193] In the embodiment of the present disclosure, after step S204, the manufacturing method further includes:

[0194] The second conductive layer and the first conductive layer in the gate line spacing groove are removed.

[0195] Combination Figure 4R and Figure 4U As shown, the first conductive layer 234 and the second conductive layer 235 covering the sidewalls and the bottom of the gate line groove 228 are removed, so that different gate layers 236 cannot be electrically connected. Of course, while removing the first conductive layer 234 and the second conductive layer 235 in the gate line groove 228, the first conductive layer 234 and the second conductive layer 235 covering the surface of the stacked structure 237 can also be removed to expose the dielectric layer 233 covering the surface of the stacked structure 237.

[0196] In some embodiments, a recess etching process may be used to remove the first conductive layer and the second conductive layer in the gate line isolation groove.

[0197] For example, a process including but not limited to dry etching may be used to remove the dielectric layer at the bottom of the gate line trench and the surface of the stacked structure.

[0198] In the embodiment of the present disclosure, after removing the second conductive layer and the first conductive layer in the gate line isolation groove, the manufacturing method further includes:

[0199] forming a second isolation layer, wherein the second isolation layer covers the sidewalls and the bottom of the gate line isolation groove;

[0200] A second filling layer is formed; wherein the gate line isolation groove, the second isolation layer and the second filling layer together form a gate line isolation structure.

[0201] like Figure 4V As shown, a second isolation layer 242 is formed in the gate line groove 228. Of course, the second isolation layer 242 also covers the surface of the stacked structure 237 and the surface of the contact structure 241. A second filling material is filled in the gate line groove 228 to form a second filling layer 243. The second filling layer 243 fills the gate line groove 228. The gate line groove 228, the second isolation layer 242 and the second filling layer 243 together form a gate line isolation structure 244.

[0202] In the disclosed embodiment, the semiconductor structure further includes a channel structure located in the core region and a dummy channel structure located in the connection region;

[0203] After forming the second filling layer, the manufacturing method further includes:

[0204] forming a dielectric layer covering the channel structure, the dummy channel structure and the contact structure;

[0205] Etching the dielectric layer to form a first through hole, a second through hole and a third through hole respectively connected to the channel structure, the dummy channel structure and the conductive structure in the contact structure;

[0206] Conductive material is filled in the first through hole, the second through hole and the third through hole to form a first lead-out structure, a second lead-out structure and a third lead-out structure respectively.

[0207] like Figure 4W As shown, a dielectric layer 245 is formed to cover the connection region 202 and the core region. More specifically, the dielectric layer 245 covers the dummy channel structure 204 , the channel structure and the contact structure 241 .

[0208] like Figure 4X As shown, the dielectric layer 245 is etched to form a first through hole, a second through hole 246 and a third through hole 247 that penetrate the dielectric layer 245 and are respectively connected to the channel structure of the core area, the dummy channel structure 204 of the connection area 202 and the conductive structure in the contact structure 241. Conductive materials are filled in the first through hole, the second through hole 246 and the third through hole 247 to form a first lead-out structure, a second lead-out structure 248 and a third lead-out structure 249, respectively. Figure 4XOnly the second lead-out structure 248 and the third lead-out structure 249 of the connection area 202 are shown. Figure 4X The first lead-out structure of the core region 201 is not shown.

[0209] In a specific example, the material of the dielectric layer 245 may include, but is not limited to, silicon oxide.

[0210] In some embodiments, the dielectric layer 245 and the conductive material filling may be formed by one or more deposition processes, wherein the deposition process may include but is not limited to PVD, CVD, ALD or any combination thereof.

[0211] In the embodiment of the present disclosure, after the gate line isolation structure is formed, the electrical signal of the channel structure is led out, and the electrical signal of the contact structure is also led out, that is, the first lead-out structure, the second lead-out structure and the third lead-out structure are formed at the same time. In fact, the second lead-out structure is connected to the dummy channel structure, and the second lead-out structure does not lead out the electrical signal of the dummy channel structure.

[0212] The following will be combined Figure 3B as well as FIG. 5A to FIG. 5J , another method for manufacturing a semiconductor device provided in an embodiment of the present disclosure is described in detail. Figure 3B A top view of another semiconductor device provided in an embodiment of the present disclosure. FIG. 5A to FIG. 5D , FIG. 5F to FIG. 5J The schematic cross-sectional structure diagram of the connection area can be regarded as Figure 3B Schematic diagram of the cross-sectional structure along the BB direction, Figure 5E The cross-sectional structure diagram showing the core area can be regarded as Figure 3B Schematic diagram of the cross-sectional structure along the CC direction.

[0213] The following will be combined Figure 5A and Figure 5B , the process of first forming an initial gate line isolation structure and then forming an initial contact structure is described in detail.

[0214] In the embodiment of the present disclosure, step S201 includes:

[0215] forming an initial stacked structure on the semiconductor layer;

[0216] forming a gate line spacer that penetrates the initial stacked structure and extends to the semiconductor layer;

[0217] A first sacrificial layer is formed in the gate line isolation groove; wherein the gate line isolation groove and the first sacrificial layer together form an initial gate line isolation structure.

[0218] like Figure 5AAs shown, an initial stacked structure 303 is formed on the semiconductor layer 302, and the initial stacked structure 303 includes alternately stacked gate sacrificial layers 304 and interlayer insulating layers 305; a dummy channel structure 306 can be formed that penetrates the initial stacked structure 303 and extends to the semiconductor layer 302; a gate line groove 307 is formed that penetrates the initial stacked structure 303 and extends to the semiconductor layer 302; a first sacrificial layer 308 is formed in the gate line groove 307; wherein the gate line groove 307 and the first sacrificial layer 308 together form an initial gate line isolation structure 309.

[0219] Here, the process of forming the initial gate line isolation structure can refer to FIG. 4A to FIG. 4M The relevant description will not be repeated here.

[0220] In the embodiment of the present disclosure, after forming the first sacrificial layer in the gate line trench, the manufacturing method further includes:

[0221] forming a contact hole extending to the target gate sacrificial layer along the stacking direction;

[0222] forming a second sacrificial layer in the contact hole, wherein the second sacrificial layer covers the sidewall and the bottom of the first portion of the contact hole and fills the second portion of the contact hole;

[0223] removing the second sacrificial layer covering the bottom of the first portion of the contact hole;

[0224] An isolation column is formed in the first portion of the contact hole; wherein the contact hole, the isolation column and the second sacrificial layer together form an initial contact structure.

[0225] Still Figure 5A As shown, a covering layer 341 is formed to cover the surface of the initial gate line isolation structure 309 and the initial stacked structure 303; the covering layer 341 and the initial stacked structure 303 are etched along the Z direction to form a first sub-contact hole 310, and the bottom of the first sub-contact hole 310 exposes a portion of the interlayer insulating layer 305 above the target gate sacrificial layer 311; an oxide layer 312 is formed, and the oxide layer 312 covers the sidewalls of the first sub-contact hole 310.

[0226] Here, the purpose of forming the capping layer 341 is to reduce the damage to the initial gate line isolation structure 309 caused by the process of forming the contact hole.

[0227] Exemplarily, an oxide material layer can be formed, the oxide material layer covers the bottom and side walls of the first sub-contact hole, and the oxide material layer covers the surface of the initial stacked structure located in the connection area; the oxide material layer covering the bottom of the first sub-contact hole and the surface of the initial stacked structure is removed, and the oxide material layer covering the side walls of the first sub-contact hole is retained to form an oxide layer.

[0228] like Figure 5BAs shown, a portion of the target gate sacrificial layer 311 is etched away in a direction parallel to the semiconductor layer 302 through the first sub-contact hole 310 to form a second sub-contact hole 313; wherein the first sub-contact hole 310 and the second sub-contact hole 313 together form a contact hole 314 (as shown in FIG. Figure 5B shown in the dashed box).

[0229] Here, reference Figure 5B As shown in the dotted line box, the contact hole 314 can also be divided into a first portion 315 and a second portion 316. For the first portion 315 and the second portion 316 of the contact hole 314, please refer to FIG. 4A to FIG. 4M The relevant description will not be repeated here.

[0230] Still Figure 5B As shown, the initial contact structure 317 includes a contact hole 314 , an isolation column 319 located in the contact hole 314 , and a second sacrificial layer 318 located in the contact hole 314 .

[0231] In the embodiment of the present disclosure, before step S202, the manufacturing method further includes:

[0232] Etching the initial contact structure along the stacking direction to form at least one groove; wherein the size of the groove along the direction parallel to the semiconductor layer is greater than or equal to the distance between the isolation column and the oxide layer along the direction parallel to the semiconductor layer;

[0233] Fill the groove with insulating material to form a support structure.

[0234] In some embodiments, in combination Figure 5C and 5D As shown, the initial contact structure 317 is etched along the stacking direction to form at least one trench 320; wherein the dimension of the trench 320 along the direction parallel to the semiconductor layer 302 is greater than or equal to the distance between the isolation column 319 and the oxide layer 312 along the direction parallel to the semiconductor layer 302. The trench 320 is filled with insulating material to form a support structure 321. The support structure 321 is used to reinforce the isolation column 319 to ensure the stability of the isolation column 319 structure. Of course, while filling the trench 320 with insulating material to form the support structure 321, the insulating material will also cover the surface of the core area and the connection area 301 to form a protective layer 326 on the surface of the core area and the connection area 301. The dimension of the support structure 321 along the direction parallel to the semiconductor layer 302 is greater than the distance between the isolation column 319 and the oxide layer 312 along the direction parallel to the semiconductor layer 302.

[0235] Here, while filling the groove with insulating material to form a support structure, a protective layer covering the surface of the initial stacked structure is also formed. The purpose of forming the protective layer is to reduce the damage to the structure in the connection area caused by the subsequent process of removing the gate sacrificial layer in the core area.

[0236] In the disclosed embodiment, a support structure is formed which can play a function similar to that of a "rivet" and is used to connect the side wall of the contact hole (for example, the oxide layer on the side wall of the contact hole) and the isolation column in the contact hole, thereby fixing the isolation column and reducing damage to the isolation column caused by the subsequent process of removing the second sacrificial layer in the contact hole and forming a conductive structure in the contact hole.

[0237] refer to Fig. 6A , Fig. 6A Schematic diagram 1 of a top view of a support structure in a semiconductor device provided in an embodiment of the present disclosure. Fig. 6A The diagram shows three different supporting structures, namely a first supporting structure 322, a second supporting structure 323, and a third supporting structure 324. The first supporting structure 322 includes two sub-supporting structures. Figure 5C , the size of each sub-support structure in a direction parallel to the semiconductor layer 302 is equal to the maximum size of the first part 315 of the contact hole in a direction parallel to the semiconductor layer 302, and a certain angle may be formed between the two sub-support structures. Exemplarily, the first part 315 of the contact hole appears circular in a top view, then the size of the sub-support structure in a direction parallel to the semiconductor layer 302 is equal to the diameter of the first part 315 of the contact hole. The second support structure 323 includes four sub-support structures, and the four sub-support structures can be arranged at intervals along the outer contour of the first part 315 of the contact hole. The third support structure 324 includes eight sub-support structures, and the eight sub-support structures can be arranged at intervals along the outer contour of the first part 315 of the contact hole.

[0238] The embodiments of the present disclosure do not have any special restrictions on the number of sub-support structures included in the support structure. The support structure may include only one sub-support structure or multiple sub-support structures. In the case where the support structure includes multiple sub-support structures, the embodiments of the present disclosure do not have any special restrictions on the arrangement of the multiple sub-support structures, or the embodiments of the present disclosure do not have any special restrictions on the angles between the multiple sub-support structures. Moreover, the embodiments of the present disclosure do not have any special restrictions on the size of the support structure, as long as the support structure can realize the function of fixing the isolation column.

[0239] The following will be combined FIG. 5E to FIG. 5H , the process of first forming the second gap and then forming the first gap is described in detail.

[0240] In the embodiment of the present disclosure, the semiconductor structure includes a core region and a connection region; the gate line spacer includes a portion of the gate line spacer located in the core region and a portion of the gate line spacer located in the connection region;

[0241] Before removing the first sacrificial layer in the gate line spacing groove and the second sacrificial layer in the contact hole, the manufacturing method further includes:

[0242] forming a protective layer, the protective layer covering the surface of the initial laminated structure of the core region and the connection region;

[0243] removing a protective layer on the surface of the initial laminate structure covering the core area;

[0244] removing the first sacrificial layer in a portion of the gate line spacing grooves located in the core area;

[0245] Removing the gate sacrificial layer located in the core area through a portion of the gate line spacing grooves located in the core area to form a second gap;

[0246] The protective layer covering the surface of the initial laminate structure in the connection area is removed.

[0247] Here, the protective layer covering the surface of the initial stacked structure 303 of the core area 300 is removed, and the protective layer covering the surface of the initial stacked structure 303 of the connection area 301 is retained. The purpose of retaining the protective layer covering the surface of the initial stacked structure 303 of the connection area 301 is to protect the initial stacked structure 303 of the connection area 301 from being damaged during subsequent processes.

[0248] Figure 5E The cross-sectional structure of the core region 300 is shown schematically, and a channel structure 339 is formed in the core region. Figure 5E As shown, the first sacrificial layer in a portion of the gate line trench 307 in the core area 300 is removed, and then the gate sacrificial layer in the core area 300 is removed through a portion of the gate line trench 307 in the core area 300 to form a second gap 327 .

[0249] Fig. 5F The cross-sectional structure diagram of the connection area 301 is shown. Figure 5D and Fig. 5F As shown, after the second gap is formed, the protection layer 326 covering the surface of the initial stacked structure 303 in the connection area 301 is removed.

[0250] In the embodiment of the present disclosure, step S202 includes:

[0251] removing the first sacrificial layer in a portion of the gate line spacing grooves located in the connection area and the second sacrificial layer in the contact hole;

[0252] Step S203 includes:

[0253] A portion of the gate sacrificial layer located in the connection area is removed through a portion of the gate line spacing groove located in the connection area to form a first gap; wherein the first gap is connected to the second gap.

[0254] Combination Fig. 5F and Figure 5G As shown, the first sacrificial layer 308 in a portion of the gate line isolation groove 307 in the connection area 301 and the second sacrificial layer 318 in the contact hole 314 are removed.

[0255] refer to Figure 6B , Figure 6B A schematic diagram of a top view of a support structure in a semiconductor device provided in an embodiment of the present disclosure Figure 2 .like Figure 6B As shown, after removing the second sacrificial layer in the contact hole, the first support structure 322 or the second support structure 323 or the third support structure 324 can be used to connect the oxide layer 312 and the isolation column 319 to play a supporting and fixing role.

[0256] like Figure 5H As shown, a portion of the gate sacrificial layer 304 in the connection area 301 is removed through a portion of the gate line spacing groove 307 in the connection area 301 to form a first gap 328. Thus, the first gap 328 in the connection area 301, the second gap in the core area and the contact hole 314 are connected.

[0257] Combination Figure 5H and Fig.5I As shown, a dielectric layer 329, a first conductive layer 330 and a second conductive layer 331 are sequentially formed in the first gap 328, the second gap and the contact hole 314 through the gate line spacer 307 and the contact hole 314. Among them, the dielectric layer 329, the first conductive layer 330 and the second conductive layer 331 located in the core area and the connection area 301 jointly form a gate layer 332. That is, the gate layer 332 located in the core area is connected to the gate layer 332 located in the connection area 301, and the gate layer 332 and the interlayer insulating layer 305 jointly form a stacked structure 333. The dielectric layer 329, the first conductive layer 330 and the second conductive layer 331 located in the contact hole 314 jointly constitute a connecting layer 334, and the connecting layer 334 is connected to the gate layer 332. The connecting layer 334 simultaneously fills the first part 315 and the second part 316 of the contact hole 314 to form a conductive structure in the contact hole 314. For ease of explanation, Fig.5I Only the gate layer 332 is schematically shown in the first gap in FIG. Specifically, the gate layer 332 may include a dielectric layer 329, a first conductive layer 330, and a second conductive layer 331, as shown in a dotted box.

[0258] refer to Figure 6C , Figure 6CFIG3 is a top view structural diagram of a support structure in a semiconductor device provided in an embodiment of the present disclosure. Figure 6C As shown, a connection layer 334 is formed in the contact hole, and the connection layer 334 occupies the space originally occupied by the second sacrificial layer. The first support structure 322 or the second support structure 323 or the third support structure 324 can be used to connect the oxide layer 312 and the isolation column 319 to play a supporting and fixing role.

[0259] Another example Fig.5I As shown, the first conductive layer 330 and the second conductive layer 331 on the sidewall and the bottom of the gate line isolation groove 307 are removed, and the second conductive layer 331 on the surface of the stacked structure 333 is removed at the same time.

[0260] like Figure 5J As shown, a second isolation layer 336 is formed to cover the sidewalls and bottom of the gate line trench 307, and the second isolation layer 336 may also cover the surface of the stacked structure 333. A second filling layer 337 is formed in the gate line trench 307, and the second filling layer 337 fills the gate line trench 307; wherein the gate line trench 307, the second isolation layer 336 and the second filling layer 337 together form a gate line isolation structure 338.

[0261] refer to Figure 7 , Figure 7 A schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present disclosure.

[0262] like Figure 7 As shown, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0263] The stacked structure 237 includes a core region and a connection region 202; the stacked structure 237 includes alternately stacked gate layers 236 and interlayer insulating layers 210;

[0264] The contact structure 241 extends along the stacking direction to the target gate layer 250 in the stacked structure 237 ; the contact structure 241 includes an isolation column 227 extending along the stacking direction and a conductive structure located between the side wall of the contact hole 221 and the isolation column 227 ; the contact structure 241 is located in the connection area 202 .

[0265] In the embodiment of the present disclosure, the contact structure 241 includes a first part 222 and a second part 223 that are connected to each other, the first part 222 extends along the stacking direction to the target gate layer 250, the second part 223 extends perpendicular to the stacking direction and is connected to the target gate layer 250, and the second part 223 surrounds the first part 222; wherein the first part 222 includes an isolation column 227 and a conductive structure located between the side wall of the first part 222 and the isolation column 227, and the second part 223 includes a conductive structure.

[0266] In the embodiment of the present disclosure, the semiconductor device further includes:

[0267] a channel structure located in the core region and a dummy channel structure 204 located in the connection region 202;

[0268] A dielectric layer 245 covering the stacked structure 237 located in the core region and the connection region 202;

[0269] The first lead structure, the second lead structure 248 and the third lead structure 249 are located in the dielectric layer 245 and are respectively connected to the channel structure, the dummy channel structure 204 and the conductive structure in the contact structure 241. In the embodiment of the present disclosure, the conductive structure of the second portion 223 of the contact structure 241 includes a dielectric layer 233, a first conductive layer 234 and a second conductive layer 235; wherein the dielectric layer 233, the first conductive layer 234 and the second conductive layer 235 together form a connecting layer 238;

[0270] The conductive structure of the first portion 222 of the contact structure 241 includes a connection layer 238 , a first filling layer 240 , and a connection layer 238 in sequence along the radial outward direction.

[0271] In the disclosed embodiment, the third lead-out structure 249 is connected to the two connection layers 238 .

[0272] In the embodiment of the present disclosure, the semiconductor device further includes:

[0273] A gate line isolation structure 244 penetrates the stacked structure 237 along the stacking direction.

[0274] In the embodiment of the present disclosure, the semiconductor device may further include a source layer 251. Exemplarily, the semiconductor layer is thinned on the back side to expose the end of the channel structure; the source layer 251 is formed to lead out the electrical signal of the channel structure.

[0275] refer to Figure 8 , Figure 8 FIG. 1 is a schematic cross-sectional view of another semiconductor device provided by an embodiment of the present disclosure. Figure 8 As shown, an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:

[0276] The stacked structure 333 includes a core region and a connection region 301; the stacked structure 333 includes alternately stacked gate layers 332 and interlayer insulating layers 305;

[0277] The contact structure 335 extends along the stacking direction to the target gate layer 340 in the stacked structure 333 ; the contact structure 335 includes an isolation column 319 extending along the stacking direction and a conductive structure located between the sidewall of the contact hole 314 and the isolation column 319 ; the contact structure 335 is located in the connection area 301 .

[0278] In the embodiment of the present disclosure, the contact structure 335 includes a first part 315 and a second part 316 that are connected to each other, the first part 315 extends along the stacking direction to the target gate layer 340, the second part 316 extends perpendicular to the stacking direction and is connected to the target gate layer 340, and the second part 316 surrounds the first part 315; wherein the first part 315 includes an isolation column 319 and a conductive structure located between the side wall of the first part 315 and the isolation column 319, and the second part 316 includes a conductive structure.

[0279] In the embodiment of the present disclosure, the semiconductor device further includes:

[0280] The channel structure located in the core region and the dummy channel structure 306 located in the connection region 301;

[0281] A dielectric layer covering the stacked structure 333 located in the core region and the connection region 301;

[0282] A first lead-out structure, a second lead-out structure and a third lead-out structure are located in the dielectric layer and are respectively connected to the channel structure, the dummy channel structure 306 and the conductive structure in the contact structure 335 .

[0283] In the embodiment of the present disclosure, the semiconductor device further includes:

[0284] A gate line isolation structure 338 penetrates the stacked structure 333 along the stacking direction.

[0285] In the embodiment of the present disclosure, the semiconductor device further includes a source layer 342. Exemplarily, the semiconductor layer is thinned on the back side to expose the end of the channel structure; the source layer 342 is formed to lead out the electrical signal of the channel structure.

[0286] It should be noted that Figure 8 The cross-sectional structure diagram provided only illustrates the dummy channel structure, gate line isolation structure and contact structure located in the connection area, and does not illustrate the dielectric layer and the second lead structure and the third lead structure formed in the subsequent process. For relevant contents about the dielectric layer, the second lead structure and the third lead structure, please refer to Figure 7 .

[0287] It should be noted that Figure 7 and Figure 8 The cross-sectional structural schematic diagrams provided only illustrate the connection region of the semiconductor device, and do not illustrate the core region of the semiconductor device and the channel structure and the first lead-out structure located in the core region.

[0288] In the embodiment of the present disclosure, the conductive structure of the second portion 316 of the contact structure 335 includes a dielectric layer 329, a first conductive layer 330 and a second conductive layer 331; wherein the dielectric layer 329, the first conductive layer 330 and the second conductive layer 331 together form a connecting layer 334;

[0289] The electrically conductive structure of the first portion 315 of the contact structure 335 includes a connecting layer 334 .

[0290] In the disclosed embodiment, the third lead-out structure is connected to a connection layer 334 .

[0291] Figure 8 Combination Figure 5C In the embodiment of the present disclosure, the contact structure 335 further includes an oxide layer 312 located on the sidewall of the first portion 315; the semiconductor device further includes:

[0292] At least one support structure 321 is embedded in the contact structure 335 along the stacking direction, and the size of the support structure 321 along the direction perpendicular to the stacking direction is greater than or equal to the distance between the isolation column 319 and the oxide layer 312 along the direction perpendicular to the stacking direction.

[0293] refer to Fig. 9 , Fig. 9 A block diagram of a memory system provided by an embodiment of the present disclosure. Fig. 9 As shown, the embodiment of the present disclosure provides a memory system 400, which includes:

[0294] At least one semiconductor device 402 as in the above technical solution; and

[0295] The controller 401 is coupled to the semiconductor device 402 and is configured to control the semiconductor device 402 .

[0296] In the embodiments of the present disclosure, the semiconductor device may be a part of a memory, that is, the semiconductor device includes a memory cell array, and the memory cell array and the peripheral circuit may form a memory together; or, the semiconductor device may be a memory.

[0297] The memory system 400 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the memory system 400 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0298] In some embodiments, the controller 401 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0299] In other embodiments, the controller 401 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0300] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system. In the embodiments of the present disclosure, a contact hole has been formed before performing a gate replacement process, so that when the gate replacement process is performed first and then the contact hole is formed, the gate layer is damaged during the formation of the contact hole, thereby affecting the structural stability and breakdown voltage. In addition, an isolation column is also provided in the contact hole, so that when the sacrificial material is filled in the contact hole, only the remaining space except the isolation column needs to be filled, which can save sacrificial material and thus save manufacturing costs.

[0301] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0302] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: A semiconductor structure is provided, comprising a semiconductor layer, an initial stacked structure located on the semiconductor layer, an initial gate line isolation structure and an initial contact structure; wherein the initial stacked structure comprises alternately stacked gate sacrificial layers and interlayer insulating layers; the initial gate line isolation structure comprises a gate line isolation groove and a first sacrificial layer located in the gate line isolation groove; the initial contact structure comprises a contact hole, an isolation column located in the contact hole and a second sacrificial layer located in the contact hole, and the initial contact structure extends along a stacking direction and is connected to a target gate sacrificial layer; removing the first sacrificial layer in the gate line spacing groove and the second sacrificial layer in the contact hole; Removing part of the gate sacrificial layer through the gate line spacing groove to form a first gap; the first gap is connected to the corresponding contact hole; A conductive structure is formed in the first gap and the contact hole.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The contact hole includes a first part and a second part that are connected, the first part extends along the stacking direction and penetrates the target gate sacrificial layer, the second part extends along a direction parallel to the semiconductor layer and exposes the side wall of the target gate sacrificial layer, and the second part surrounds the first part; wherein the isolation column extends along the stacking direction and is located in the first part.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The semiconductor structure provided comprises: forming an initial stacked structure on the semiconductor layer; forming a gate line trench penetrating the initial stacked structure and extending to the semiconductor layer; A first sacrificial layer is formed in the gate line isolation groove; wherein the gate line isolation groove and the first sacrificial layer together form the initial gate line isolation structure.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: After forming the first sacrificial layer in the gate line spacing groove, the manufacturing method further includes: forming a contact hole extending to the target gate sacrificial layer along a stacking direction; forming a second sacrificial layer in the contact hole, wherein the second sacrificial layer covers the sidewall and the bottom of the first portion of the contact hole and fills the second portion of the contact hole; removing the second sacrificial layer covering the bottom of the first portion of the contact hole; An isolation column is formed in the first portion of the contact hole; wherein the contact hole, the isolation column and the second sacrificial layer together form the initial contact structure.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The semiconductor structure provided comprises: forming an initial stacked structure on the semiconductor layer; forming a contact hole extending to the target gate sacrificial layer along a stacking direction; forming a second sacrificial layer in the contact hole, wherein the second sacrificial layer covers the sidewall and the bottom of the first portion of the contact hole and fills the second portion of the contact hole; removing the second sacrificial layer covering the bottom of the first portion of the contact hole; An isolation column is formed in the first portion of the contact hole; wherein the contact hole, the isolation column and the second sacrificial layer together form the initial contact structure.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: After forming the isolation column in the first portion of the contact hole, the manufacturing method further includes: forming a gate line trench penetrating the initial stacked structure and extending to the semiconductor layer; A first sacrificial layer is formed in the gate line isolation groove; wherein the gate line isolation groove and the first sacrificial layer together form the initial gate line isolation structure.

7. The method for manufacturing a semiconductor device according to claim 2, wherein: The initial contact structure further includes an oxide layer covering a first portion of a sidewall of the contact hole; Before removing the first sacrificial layer in the gate line spacing groove and the second sacrificial layer in the contact hole, the manufacturing method further includes: Etching the initial contact structure along the stacking direction to form at least one groove; wherein the size of the groove along the direction parallel to the semiconductor layer is greater than or equal to the distance between the isolation column and the oxide layer along the direction parallel to the semiconductor layer; The groove is filled with insulating material to form a supporting structure.

8. The method for manufacturing a semiconductor device according to claim 2, wherein: The semiconductor structure includes a core region and a connection region; the gate line spacing groove includes a portion of the gate line spacing groove located in the core region and a portion of the gate line spacing groove located in the connection region; Before removing the first sacrificial layer in the gate line spacing groove and the second sacrificial layer in the contact hole, the manufacturing method further includes: forming a protective layer, the protective layer covering the surface of the initial stacked structure of the core region and the connection region; removing the protective layer covering the surface of the initial laminated structure of the core area; removing the first sacrificial layer in a portion of the gate line spacing grooves in the core area; Removing the gate sacrificial layer located in the core area through a portion of the gate line spacing grooves located in the core area to form a second gap; The protective layer covering the surface of the initial laminate structure in the connection area is removed.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The removing of the first sacrificial layer in the gate line spacing groove and the second sacrificial layer in the contact hole comprises: removing the first sacrificial layer in a portion of the gate line spacing grooves located in the connection area and the second sacrificial layer in the contact hole; The step of removing a portion of the gate sacrificial layer through the gate line spacing groove to form a first gap includes: A portion of the gate sacrificial layer located in the connection area is removed through a portion of the gate line spacing groove located in the connection area to form a first gap; wherein the first gap is connected to the second gap.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The forming of a conductive structure in the first gap and the contact hole comprises: A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line spacer and the contact hole; wherein the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap jointly form a gate layer, and the gate layer and the interlayer insulating layer jointly form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole jointly form a connecting layer, and the connecting layer simultaneously fills the first part and the second part of the contact hole to form a contact structure.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: The forming of a conductive structure in the first gap and the contact hole comprises: A dielectric layer, a first conductive layer, and a second conductive layer are sequentially formed in the first gap, the second gap, and the contact hole through the gate line spacer and the contact hole; wherein the dielectric layer, the first conductive layer, and the second conductive layer located in the first gap and the second gap jointly form a gate layer, and the gate layer and the interlayer insulating layer jointly form a stacked structure; the dielectric layer, the first conductive layer, and the second conductive layer located in the contact hole jointly constitute a connecting layer, and the connecting layer fills up the second part of the contact hole, and the connecting layer does not fill up the first part of the contact hole.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: After sequentially forming a dielectric layer, a first conductive layer, and a second conductive layer in the first gap, the second gap, and the contact hole through the gate line spacer and the contact hole, the manufacturing method further includes: A first filling layer is formed, wherein the first filling layer fills the gap between the first part of the side wall of the contact hole and the isolation column to form a contact structure.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The first filling layer is formed by using an atomic layer deposition process.

14. The method for manufacturing a semiconductor device according to claim 10 or 12, characterized in that: After forming the conductive structure in the first gap and the contact hole, the manufacturing method further includes: The second conductive layer and the first conductive layer in the gate line isolation groove are removed.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: After removing the second conductive layer and the first conductive layer in the gate line isolation groove, the manufacturing method further includes: forming an isolation layer, wherein the isolation layer covers the sidewalls and the bottom of the gate line isolation groove; A second filling layer is formed; wherein the gate line isolation groove, the isolation layer and the second filling layer together form a gate line isolation structure.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The semiconductor structure further includes a channel structure located in the core region and a dummy channel structure located in the connection region; After forming the second filling layer, the manufacturing method further includes: forming a dielectric layer covering the channel structure, the dummy channel structure and the contact structure; Etching the dielectric layer to form a first through hole, a second through hole and a third through hole respectively connected to the channel structure, the dummy channel structure and the conductive structure in the contact structure; Conductive material is filled in the first through hole, the second through hole and the third through hole to form a first lead-out structure, a second lead-out structure and a third lead-out structure respectively.

17. A semiconductor device, characterized in that: The semiconductor device comprises: A stacked structure, the stacked structure comprising a core region and a connection region; the stacked structure comprising alternately stacked gate layers and interlayer insulating layers; A contact structure extending along the stacking direction to the target gate layer in the stacked structure; the contact structure comprises an isolation column extending along the stacking direction and a conductive structure located between the sidewall of the contact hole and the isolation column; the contact structure is located in the connection area.

18. The semiconductor device according to claim 17, wherein: The contact structure includes a first part and a second part connected to each other, the first part extends to the target gate layer along the stacking direction, the second part extends perpendicular to the stacking direction and is connected to the target gate layer, and the second part surrounds the first part; wherein the first part includes an isolation column and a conductive structure located between the side wall of the first part and the isolation column, and the second part includes a conductive structure.

19. The semiconductor device according to claim 18, characterized in that The semiconductor device further comprises: a channel structure located in the core region and a dummy channel structure located in the connection region; A dielectric layer covering the stacked structure located in the core area and the connection area; A first lead-out structure, a second lead-out structure and a third lead-out structure are located in the dielectric layer and are respectively connected to the channel structure, the dummy channel structure and the conductive structure in the contact structure.

20. The semiconductor device according to claim 19, characterized in that The conductive structure of the second part of the contact structure comprises a dielectric layer, a first conductive layer and a second conductive layer; wherein the dielectric layer, the first conductive layer and the second conductive layer together form a connecting layer; The conductive structure of the first part of the contact structure includes the connecting layer.

21. The semiconductor device according to claim 20, characterized in that The third lead-out structure is connected to one of the connection layers.

22. The semiconductor device according to claim 19, wherein: The conductive structure of the second part of the contact structure comprises a dielectric layer, a first conductive layer and a second conductive layer; wherein the dielectric layer, the first conductive layer and the second conductive layer together form a connecting layer; The conductive structure of the first part of the contact structure includes the connection layer, the first filling layer and the connection layer in sequence along the radial outward direction.

23. The semiconductor device according to claim 22, characterized in that The third lead-out structure is connected to the two connection layers.

24. The semiconductor device according to claim 18, wherein: The contact structure further includes an oxide layer located on a sidewall of the first portion; and the semiconductor device further includes: At least one supporting structure is embedded in the contact structure along the stacking direction, and a dimension of the supporting structure along the direction perpendicular to the stacking direction is greater than or equal to a distance between the isolation column and the oxide layer along the direction perpendicular to the stacking direction.

25. The semiconductor device according to claim 17, wherein: The semiconductor device further comprises: A gate line isolation structure passes through the stacked structure along the stacking direction.

26. A memory system, characterized in that: The memory system comprises: The semiconductor device according to any one of claims 17 to 25; and A controller is coupled to the semiconductor device, the controller being configured to control the semiconductor device.

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