Memory, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a memory, a manufacturing method thereof and electronic equipment, the memory comprises a transistor, the transistor comprises a semiconductor layer and a gate electrode located on the semiconductor layer, and a gate insulating layer and a charge trapping storage layer are arranged between the semiconductor layer and the gate electrode. The charge capture storage layer is located between the semiconductor layer and the gate insulation layer. The memory provided by the embodiment of the invention has relatively high storage capability.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacturing of semiconductor devices, and in particular to a memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] Common dynamic random access memory (DRAM) has multiple repeated "storage cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0003] In order to improve the storage capacity of DRAM, a common idea currently is to increase the integration of storage units on a limited substrate, for example, to develop a DRAM with a three-dimensional (3D) structure. Summary of the invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] The embodiments of the present application provide a memory and a manufacturing method thereof, and an electronic device. The memory has a high storage capacity and a simple manufacturing process.

[0006] An embodiment of the present application provides a memory, which includes a transistor, wherein the transistor includes a semiconductor layer and a gate electrode located on the semiconductor layer, a gate insulating layer and a charge capture storage layer are arranged between the semiconductor layer and the gate electrode, and the charge capture storage layer is located between the semiconductor layer and the gate insulating layer; the charge capture storage layer is configured to capture and store charges.

[0007] In an exemplary embodiment of the present application, the charge capture storage layer may include a tunneling insulating layer, a blocking insulating layer and a charge storage layer located between the tunneling insulating layer and the blocking insulating layer; the tunneling insulating layer is located between the semiconductor layer and the charge storage layer, and the blocking insulating layer is located between the charge storage layer and the gate insulating layer.

[0008] In an exemplary embodiment of the present application, the material of the tunnel insulating layer may be selected from any one or more of silicon oxide, silicon nitride, silicon oxynitride and metal oxide.

[0009] In an exemplary embodiment of the present application, the material of the charge storage layer can be selected from any one or more of polysilicon, nanocrystals, silicon nitride, silicon oxynitride, metal oxides and metal oxynitrides, and the material of the charge storage layer is different from the material of the tunneling insulating layer, and the material of the charge storage layer is different from the material of the blocking insulating layer.

[0010] In an exemplary embodiment of the present application, the material of the blocking insulating layer may be selected from any one or more of silicon oxide, silicon nitride, metal oxide and metal oxynitride, and the dielectric constant of the blocking insulating layer is greater than the dielectric constant of the tunneling insulating layer.

[0011] In an exemplary embodiment of the present application, the tunneling insulating layer may be a single-layer or multi-layer structure.

[0012] In an exemplary embodiment of the present application, the charge storage layer may be a single-layer or multi-layer structure.

[0013] In an exemplary embodiment of the present application, the blocking insulating layer may be a single layer or a multi-layer structure.

[0014] In an exemplary embodiment of the present application, the memory may include a plurality of memory cells located on a substrate, wherein the plurality of memory cells are distributed in different layers, stacked along a direction perpendicular to the substrate, and distributed periodically; each of the memory cells includes the transistor.

[0015] In an exemplary embodiment of the present application, the transistor may further include a first electrode region and a second electrode region, one of the first electrode region and the second electrode region being a source electrode of the transistor, and the other being a drain electrode of the transistor; the semiconductor layer is located between the first electrode region and the second electrode region, the first electrode region and the second electrode region extend along a first direction parallel to the substrate, and a channel between the first electrode region and the second electrode region is a horizontal channel; the gate electrode extends along a direction perpendicular to the substrate; and the multiple semiconductor layers of the transistors of the multiple storage cells located in different layers are spaced apart and disconnected.

[0016] In an exemplary embodiment of the present application, the semiconductor layer and / or the charge trapping storage layer may surround a sidewall of the gate electrode.

[0017] In an exemplary embodiment of the present application, the memory may further include a word line penetrating through each layer of the memory cells, wherein the word line extends in a direction perpendicular to the substrate.

[0018] In an exemplary embodiment of the present application, the memory may further include a bit line extending along a second direction parallel to the substrate; the first electrode regions of transistors of a column of the memory cells located in the same layer and distributed along the second direction are connected to the same bit line.

[0019] In an exemplary embodiment of the present application, the storage unit may further include a capacitor, which includes a third electrode region, a fourth electrode region and a dielectric layer located between the third electrode region and the fourth electrode region, and the third electrode region is connected to the second electrode region of the transistor in the same storage cell.

[0020] The embodiment of the present application also provides a method for manufacturing a memory, wherein the memory includes a transistor, the transistor includes a semiconductor layer and a gate electrode located on the semiconductor layer, a gate insulating layer and a charge trapping storage layer are provided between the semiconductor layer and the gate electrode, and the charge trapping storage layer is located between the semiconductor layer and the gate insulating layer;

[0021] The manufacturing method comprises:

[0022] forming a semiconductor layer of the transistor;

[0023] Depositing a charge trapping storage layer and a gate insulating layer in sequence on the semiconductor layer;

[0024] A gate electrode of the transistor is formed on a side of the gate insulating layer away from the charge trapping storage layer.

[0025] An embodiment of the present application also provides an electronic device, which includes the memory provided in the above embodiment of the present application.

[0026] The memory of the embodiment of the present application introduces a charge capture storage layer between the semiconductor layer and the gate electrode that can capture and store charges, so that the memory can not only use the original transistor structure to store data, but also use the charge capture storage layer to store data, thereby greatly improving the storage capacity of the memory.

[0027] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0029] Figure 1AA cross-sectional view of a memory according to an exemplary embodiment of the present application on a plane parallel to a substrate;

[0030] Figure 1B for Figure 1A A cross-sectional view of the memory shown along the aa' direction;

[0031] Figure 2 A schematic diagram of the structure of a charge trapping storage layer of a memory according to an exemplary embodiment of the present application;

[0032] Figure 3A A cross-sectional view of another memory according to an exemplary embodiment of the present application on a plane parallel to the substrate;

[0033] Figure 3B for Figure 3A A cross-sectional view of the memory shown along the aa' direction;

[0034] Figure 4 A cross-sectional view of another memory according to an exemplary embodiment of the present application along the aa' direction;

[0035] Figure 5 The present invention is a process flow chart of a method for manufacturing a memory according to an exemplary embodiment of the present application.

[0036] The meanings of the symbols in the accompanying drawings are:

[0037] 12-conductive layer; 13-dielectric layer 13; 14-insulating layer; 20-substrate; 23-semiconductor layer; 24-gate insulating layer; 25-charge trapping storage layer; 251-tunneling insulating layer; 252-blocking insulating layer; 253-charge storage layer; 26-gate electrode; 30-bit line; 40-word line; 41-third electrode region; 42-fourth electrode region; 51-first electrode region; 52-second electrode region; 100-storage cell; 200-channel region; 300-parasitic MOS region. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0039] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0040] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0041] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0042] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0043] In the present application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a semiconductor layer domain between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the semiconductor layer domain, and the source electrode. In the present application, the semiconductor layer domain refers to the region through which the current mainly flows.

[0044] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0045] In the present disclosure, "electrical connection" or "connection" includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element having some electrical function" as long as it can transfer electrical signals between connected constituent elements. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0046] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0047] In the embodiments of the present application, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned on a film layer to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0048] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, "dielectric layer" can sometimes be replaced with "dielectric film".

[0049] An embodiment of the present application provides a memory.

[0050] Figure 1A A cross-sectional view of a memory according to an exemplary embodiment of the present application on a plane parallel to a substrate; Figure 1B for Figure 1A The memory is shown in a cross-sectional view along the aa' direction.

[0051] like Figure 1A and Figure 1B As shown, the memory includes a transistor, which includes a semiconductor layer 23 and a gate electrode 26 located on the semiconductor layer 23, a gate insulating layer 24 and a charge capture storage layer 25 are provided between the semiconductor layer 23 and the gate electrode 26, and the charge capture storage layer 25 is located between the semiconductor layer 23 and the gate insulating layer 24; the charge capture storage layer 25 is configured to capture and store charges.

[0052] The memory of the embodiment of the present application introduces a charge capture storage layer between the semiconductor layer and the gate electrode that can capture and store charges, so that the memory can not only use the original transistor structure to store data, but also use the charge capture storage layer to store data, thereby greatly improving the storage capacity of the memory.

[0053] In the embodiments of the present application, the semiconductor layer can be understood as a semiconductor material, where its shape and structure are not emphasized but only its function.

[0054] In an exemplary embodiment of the present application, the material of the tunnel insulating layer may be selected from any one or more of silicon oxide, silicon nitride, silicon oxynitride, metal oxide and metal oxynitride.

[0055] In an exemplary embodiment of the present application, the charge capture storage layer may include a tunneling insulating layer, a blocking insulating layer and a charge storage layer located between the tunneling insulating layer and the blocking insulating layer; the tunneling insulating layer is located between the semiconductor layer and the charge storage layer, and the blocking insulating layer is located between the charge storage layer and the gate insulating layer.

[0056] The tunneling insulating layer may be a layer for charge tunneling. In an exemplary embodiment of the present application, the material of the tunneling insulating layer may be selected from silicon oxide (e.g., SiO 2 ), silicon nitride (e.g., Si 3 N 4 ), silicon oxynitride (e.g., SiON), and metal oxides (e.g., Al 2 O 3 ) Any one or more of the above. For the silicon nitride layer, its impurity concentration cannot be too high. For example, the impurity concentration of the silicon nitride film can be similar to the impurity concentration of the silicon oxide layer.

[0057] The charge storage layer may be a region for storing information by charge storage. In an exemplary embodiment of the present application, the material of the charge storage layer may be selected from any one or more of polysilicon, nanocrystals, silicon nitride, silicon oxynitride, metal oxides, and metal oxynitrides, and the material of the charge storage layer is different from the material of the tunneling insulating layer, and the material of the charge storage layer is different from the material of the blocking insulating layer. For example, the material of the charge storage layer may be selected from polysilicon, nanocrystals, Si nitride, silicon oxynitride, metal oxides, and metal oxynitrides. 3 N 4 、Al 2 O 3 , HfO 2 , HfSiON, HfON, HfAlO, TiO 2 and ZrO 2In addition, the charge storage layer may include a plurality of nanodots arranged discontinuously as charge trapping points, and the nanodots may be formed in the form of nanocrystals.

[0058] The charge storage layer may be formed of a charge trap layer or a floating gate.

[0059] For example, in order to be used as a charge trapping layer, the charge storage layer may include any one or more of silicon nitride, a high-k dielectric material having a relatively high dielectric constant, and nanocrystals, for example, may include Si 3 N 4 、Al 2 O 3 , HfO 2 , HfSiON, HfON, HfAlO and ZrO 2 Any one or more of .

[0060] As another example, to function as a floating gate, the charge storage layer may include polysilicon.

[0061] The blocking insulating layer can reduce the occurrence of charges moving upward after passing through the region where the charge storage layer is formed. In an exemplary embodiment of the present application, the material of the blocking insulating layer can be selected from any one or more of silicon oxide, silicon nitride, metal oxide and metal oxynitride, and the dielectric constant of the blocking insulating layer is greater than the dielectric constant of the tunneling insulating layer. Among them, the metal oxide and the metal oxynitride can be doped metal oxides and doped metal oxynitrides containing doping elements, respectively. For example, the material of the blocking insulating layer can be selected from SiO 2 、Si 3 N 4 、Al 2 O 3 ,La 2 O 3 , HfO 2 、 2 O 5 and ZrO 2 Any one or more of .

[0062] In an exemplary embodiment of the present application, the tunneling insulating layer may be a single layer or a multilayer structure. For example, the tunneling insulating layer may be a double layer structure including a silicon nitride layer and an oxide layer. For another example, the tunneling insulating layer may be a single layer structure of oxide or nitride or a multilayer structure of materials with different energy band gaps.

[0063] In an exemplary embodiment of the present application, the charge storage layer may be a single-layer or multi-layer structure.

[0064] In an exemplary embodiment of the present application, the blocking insulating layer may be a single layer or a multi-layer structure. For example, the blocking insulating layer may include a typical insulating material (e.g., SiO 2 ) and a high dielectric layer formed of a material with a higher dielectric constant than the tunnel insulating layer.

[0065] In an exemplary embodiment of the present application, the charge trapping storage layer may be silicon dioxide (SiO 2 ) / Silicon Nitride / Aluminum Oxide (Al 2 O 3 )、SiO 2 / Al 2 O 3 / SiO 2 or aluminum oxide (Al 2 O 3 ) / Hafnium Oxide (HfO 2 ) / Alumina(Al 2 O 3 ).

[0066] Figure 2 FIG. 1 is a schematic diagram of the structure of the charge trapping storage layer of the memory of the exemplary embodiment of the present application. Figure 2 As shown, in an exemplary embodiment of the present application, the charge trapping storage layer 25 may include a tunneling insulating layer 251, a blocking insulating layer 252, and a charge storage layer 253 located between the tunneling insulating layer 251 and the blocking insulating layer 252. The tunneling insulating layer 251 is located between the semiconductor layer 23 and the charge storage layer 253, and the blocking insulating layer 252 is located between the charge storage layer 253 and the gate insulating layer 24. For example, the tunneling insulating layer 251 may be made of Al 2 O 3 The blocking insulating layer 252 may be formed of Al 2 O 3 The charge storage layer 253 may be formed of HfO 2 The thickness of the tunnel insulating layer 251 and the blocking insulating layer 252 may be 7 nm; however, the Al 2 O 3 are different, and the dielectric constant of the tunneling insulating layer 251 is smaller than the dielectric constant of the blocking insulating layer 252 .

[0067] In an exemplary embodiment of the present application, Figure 1A and Figure 1B As shown, the memory may include a plurality of memory cells 100 located on a substrate 20 , wherein the plurality of memory cells 100 are distributed in different layers, stacked along a direction perpendicular to the substrate 20 and distributed periodically; each memory cell 100 includes the transistor.

[0068] In an exemplary embodiment of the present application, Figure 3A and Figure 3B As shown, the transistor may further include a first electrode region 51 and a second electrode region 52, one of the first electrode region 51 and the second electrode region 52 being a source electrode of the transistor, and the other being a drain electrode of the transistor; the semiconductor layer 23 is located between the first electrode region 51 and the second electrode region 52, and the first electrode region 51 and the second electrode region 52 are both arranged along a first direction parallel to the substrate 20 (for example, it can be Figure 1A The gate electrode 26 extends in a direction perpendicular to the substrate 20; the plurality of semiconductor layers 23 of the transistors of the plurality of memory cells 100 located at different layers are arranged at intervals and disconnected.

[0069] The semiconductor layers of transistors of at least some adjacent layers of the memory of the exemplary embodiment of the present application are arranged at intervals, which can reduce or eliminate at least some parasitic MOS capacitors between the layers and improve the stability of the device.

[0070] In an exemplary embodiment of the present application, the semiconductor layers of the transistors in different layers are spaced apart in a direction perpendicular to the substrate, that is, the semiconductor layers of the transistors in all adjacent layers are spaced apart in a direction perpendicular to the substrate, thereby eliminating parasitic MOS capacitors between all adjacent layers and improving device stability.

[0071] In various embodiments of the present application, the first direction parallel to the substrate may be understood as a lateral direction.

[0072] In an exemplary embodiment of the present application, Figure 1A and Figure 1B As shown, the semiconductor layer 23 and / or the charge trapping storage layer 25 surround the sidewalls of the gate electrode 26 .

[0073] Surrounding can be understood as partially surrounding or completely surrounding. In some embodiments, the surrounding can be completely surrounding, that is, at least the entire side wall of the gate electrode 26 is surrounded by the semiconductor layer 23 and / or the charge capture storage layer 25, and the cross section of the semiconductor layer 23 and / or the charge capture storage layer 25 after the surrounding is a closed ring. The cross section is cut along a direction perpendicular to the substrate and parallel to the first direction. Figure 1B As shown, the entire sidewall of the gate electrode 26 is surrounded by the semiconductor layer 23 and the charge trapping storage layer 25, and this surrounding is considered as full surrounding. In addition, it can be understood that "full surrounding" means full surrounding in the circumferential direction, and does not limit the extension degree of the bit line in the vertical direction of the semiconductor column.

[0074] In some embodiments, the surrounding may be partial surrounding, that is, part of the sidewall of the gate electrode 26 is surrounded by the semiconductor layer 23 and / or the charge capture storage layer 25, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers 23 and / or charge capture storage layers 25. For example, the opposite side surfaces of the gate electrode 26 are surrounded by the semiconductor layer 23 and / or the charge capture storage layer 25, and the cross section of the semiconductor layer 23 and / or the charge capture storage layer 25 is a ring with two openings.

[0075] In an exemplary embodiment of the present application, Figure 1A and Figure 1B As shown, the memory may further include a word line 40 penetrating each layer of the memory cell 100 , and the word line 40 extends in a direction perpendicular to the substrate 10 .

[0076] In an exemplary embodiment of the present application, Figure 1A and Figure 1B As shown, the gate electrode 26 of the transistor located in different layers may be a part of the word line 40 , and the word line 40 is exposed between the semiconductor layers 23 that are spaced apart.

[0077] In an exemplary embodiment of the present application, Figure 1A As shown, the memory may also include a second direction parallel to the substrate (for example, Figure 1A The first electrode regions 51 of the transistors of a column of memory cells 100 located in the same layer and distributed along the second direction may be connected to the same bit line 30 .

[0078] like Figure 1A As shown, the first electrode regions 51 of transistors in two adjacent columns of memory cells 100 located in the same layer and distributed along the second direction may be connected to the same bit line 30 .

[0079] like Figure 1A As shown, the first electrode region 51 of the transistor and the bit line 30 connected thereto may be an integrated structure.

[0080] In an exemplary embodiment of the present application, Figure 1A and Figure 1B As shown, the memory may further include insulating layers 14 and conductive layers 12 alternately distributed from bottom to top in a direction perpendicular to the substrate 20; and

[0081] A through hole K1 penetrating each insulating layer 14 and each conductive layer 12, wherein a word line 40, a gate insulating layer 24 surrounding the side wall of the word line 40, a charge trapping storage layer 25 surrounding the side wall of the gate insulating layer 24, and a plurality of semiconductor layers 23 surrounding different regions of the side wall of the charge trapping storage layer 25 and extending in a direction perpendicular to the substrate 20 are sequentially distributed in the through hole K1 from inside to outside;

[0082] The plurality of semiconductor layers 23 are disconnected at the sidewalls of the insulating layer 14 .

[0083] In an exemplary embodiment of the present application, the conductive layer may include a first conductive portion and a second conductive portion spaced apart from each other, the first conductive portion and the second conductive portion are respectively a first electrode 51 region and a second electrode 52 region of the transistor, one of the first electrode 51 region and the second electrode 52 region is a source electrode, and the other is a drain electrode, and each semiconductor layer 23 is in contact with the source electrode and the drain electrode of the conductive layer 12 of the corresponding layer.

[0084] In an exemplary embodiment of the present application, the channel between the first electrode region and the second electrode region is a horizontal channel.

[0085] A horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction. In practical applications, the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer. In other words, a horizontal channel does not mean that it must extend in one direction in the horizontal plane, and it may extend in different directions. For example, when the semiconductor layer is annular, the source contact area and the drain contact area on the annular semiconductor layer are part of the ring. At this time, the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a certain direction locally. Of course, the carrier transmission direction in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate. The present application protects the channel between the first electrode area and the second electrode area as a channel that is not perpendicular to the substrate.

[0086] In an exemplary embodiment of the present application, the transistor may be an access transistor. The memory cell may also include other components, such as a capacitor in a 1T1C or 2T1C memory cell, or a read transistor and a storage node in a 1T0C or 2T0C memory cell.

[0087] Figure 3A A cross-sectional view of another memory according to an exemplary embodiment of the present application on a plane parallel to the substrate; Figure 3B for Figure 3A The cross-sectional view of the memory along the aa' direction is shown. Figure 3A and Figure 3BAs shown, in an exemplary embodiment of the present application, each of the memory cells includes a transistor and a capacitor, the capacitor includes a third electrode region 41, a fourth electrode region 42 and a dielectric layer 13 located between the third electrode region 41 and the fourth electrode region 42, and the third electrode region 41 is connected to the second electrode region 52 of the transistor in the same memory cell.

[0088] like Figure 3A and Figure 3B The memory shown uses a horizontal structure capacitor, and sets the capacitor on one side of the transistor to construct a 1T1C structure memory cell, and stacks multiple memory cells together in a direction perpendicular to the substrate to form a 3D stacked device, which can improve the storage density of the semiconductor device.

[0089] In an exemplary embodiment of the present application, Figure 3A As shown, the third electrode region 41 of the capacitor and the second electrode region 52 of the transistor connected thereto in the same storage unit may be an integrated structure.

[0090] In an exemplary embodiment of the present application, Figure 3A As shown, the fourth electrode region 42 of the capacitors of a column of memory cells located in the same layer and arranged along the second direction may be an integrated structure.

[0091] In an exemplary embodiment of the present application, Figure 3B As shown, the fourth electrode region 42 of the capacitor of a column of memory cells located in different layers and arranged in a direction perpendicular to the substrate 20 may be an integrated structure.

[0092] In an exemplary embodiment of the present application, Figure 3B As shown, the aperture of the through hole K1 located in the parasitic MOS region 300 is larger than the aperture of the opening K1 located in the channel region 200 in the first direction.

[0093] Figure 4 FIG. 2 is a cross-sectional view of another memory according to an exemplary embodiment of the present application along the aa' direction. Figure 4 As shown, in some embodiments, the aperture of the through hole K1 located in the parasitic MOS region 300 may be smaller than the aperture of the opening K1 located in the channel region 200 in the first direction. In addition, in other embodiments, the aperture of the through hole K1 located in the parasitic MOS region 300 may be the same as the aperture of the opening K1 located in the channel region 200 in the first direction. The memory of the embodiment of the present application does not limit the shape of the gate electrode.

[0094] The substrate in the embodiment of the present application may be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functions or circuits are already distributed. The device involved in the inventive structure of the embodiment of the present application is arranged on the main surface of the supporting structure.

[0095] In an exemplary embodiment of the present application, the material of the semiconductor layer may be a material such as silicon or polysilicon with a band gap less than 1.65 eV, or a wide band gap material such as a metal oxide material with a band gap greater than 1.65 eV.

[0096] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0097] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0098] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0099] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0100] In an exemplary embodiment of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0101] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0102] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0103] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0104] In an exemplary embodiment of the present application, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0105] Low-K materials, such as silicon oxide.

[0106] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. may be included. For example, at least one of the following may be included but is not limited to: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0107] In an exemplary embodiment of the present application, the material of the dielectric layer may be silicon oxide or a High-K dielectric material, that is, a dielectric material with a dielectric constant K ≥ 3.9. The High-K dielectric material may include but is not limited to at least one of the following: aluminum oxide (Al 2 O 3 ), hafnium oxide.

[0108] The present application also provides a method for manufacturing a memory, wherein the memory includes a transistor, the transistor includes a semiconductor layer and a gate electrode located on the semiconductor layer, a gate insulating layer and a charge trapping storage layer are provided between the semiconductor layer and the gate electrode, and the charge trapping storage layer is located between the semiconductor layer and the gate insulating layer. The memory of the present application can be obtained by the method.

[0109] Figure 5 The present invention is a process flow chart of a method for manufacturing a memory according to an exemplary embodiment of the present application.

[0110] like Figure 5 As shown, the manufacturing method comprises:

[0111] forming a semiconductor layer of the transistor;

[0112] Depositing a charge trapping storage layer and a gate insulating layer in sequence on the semiconductor layer;

[0113] A gate electrode of the transistor is formed on a side of the gate insulating layer away from the charge trapping storage layer.

[0114] In an exemplary embodiment of the present application, forming the semiconductor layer of the transistor may include: depositing a semiconductor layer such as IGZO on the inner wall of the pre-formed through hole K1 by using an atomic layer deposition (ALD) process.

[0115] In an exemplary embodiment of the present application, sequentially depositing a charge trapping storage layer and a gate insulating layer on the semiconductor layer may include: sequentially depositing a charge trapping storage layer and a gate insulating layer on an inner wall of the semiconductor layer, wherein a method for depositing the gate insulating layer may adopt an ALD process.

[0116] In an exemplary embodiment of the present application, depositing a charge trapping storage layer on the semiconductor layer may include: depositing a tunneling insulating layer, a charge storage layer and a blocking insulating layer on the semiconductor layer in sequence. The tunneling insulating layer, the charge storage layer and the blocking insulating layer may each independently be a single layer or a multilayer structure.

[0117] In an exemplary embodiment of the present application, forming the gate electrode of the transistor on a side of the gate insulating layer away from the charge capture storage layer may include: filling the through hole K1 deposited with the semiconductor layer, the charge capture storage layer and the gate insulating layer with a gate electrode material, and the method adopted may be an ALD process.

[0118] An embodiment of the present application further provides an electronic device, which includes the 3D stacked semiconductor device provided in the above embodiment of the present application.

[0119] In an exemplary embodiment of the present application, the electronic device may be: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0120] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A memory, characterized in that: The invention comprises a transistor, wherein the transistor comprises a semiconductor layer and a gate electrode located on the semiconductor layer, a gate insulating layer and a charge capture storage layer are arranged between the semiconductor layer and the gate electrode, and the charge capture storage layer is located between the semiconductor layer and the gate insulating layer; the charge capture storage layer is configured to capture and store charges.

2. The memory according to claim 1, characterized in that: The charge capture storage layer includes a tunneling insulating layer, a blocking insulating layer and a charge storage layer located between the tunneling insulating layer and the blocking insulating layer; the tunneling insulating layer is located between the semiconductor layer and the charge storage layer, and the blocking insulating layer is located between the charge storage layer and the gate insulating layer.

3. The memory according to claim 2, characterized in that: The material of the tunnel insulating layer is selected from any one or more of silicon oxide, silicon nitride, silicon oxynitride and metal oxide.

4. The memory according to claim 2, characterized in that: The material of the charge storage layer is selected from any one or more of polysilicon, nanocrystals, silicon nitride, silicon oxynitride, metal oxide and metal oxynitride, and the material of the charge storage layer is different from the material of the tunneling insulating layer, and the material of the charge storage layer is different from the material of the blocking insulating layer.

5. The memory according to claim 2, characterized in that: The material of the blocking insulating layer is selected from any one or more of silicon oxide, silicon nitride, metal oxide and metal oxynitride, and the dielectric constant of the blocking insulating layer is greater than the dielectric constant of the tunneling insulating layer.

6. The memory according to any one of claims 2 to 5, characterized in that: The tunneling insulating layer is a single-layer or multi-layer structure; and / or, The charge storage layer is a single layer or multi-layer structure; and / or, The blocking insulating layer is a single-layer or multi-layer structure.

7. The memory according to any one of claims 1 to 6, characterized in that: It comprises a plurality of memory cells located on a substrate, wherein the plurality of memory cells are distributed in different layers, stacked along a direction perpendicular to the substrate and distributed periodically; each of the memory cells comprises the transistor.

8. The memory according to claim 7, characterized in that: The transistor further comprises a first electrode region and a second electrode region, one of the first electrode region and the second electrode region is a source electrode of the transistor, and the other is a drain electrode of the transistor; The semiconductor layer is located between the first electrode region and the second electrode region, the first electrode region and the second electrode region extend along a first direction parallel to the substrate, and the channel between the first electrode region and the second electrode region is a horizontal channel; the gate electrode extends along a direction perpendicular to the substrate; the semiconductor layers of the transistors of the plurality of memory cells located at different layers are arranged at intervals and disconnected; and / or, The semiconductor layer and / or the charge trapping storage layer surrounds the sidewall of the gate electrode; and / or, The memory further comprises a word line running through each layer of the memory cells, wherein the word line extends in a direction perpendicular to the substrate; and / or, The memory further includes a bit line extending in a second direction parallel to the substrate; The first electrode regions of the transistors of a column of the memory cells located in the same layer and distributed along the second direction are connected to the same bit line; and / or, The memory cell further comprises a capacitor, which comprises a third electrode region, a fourth electrode region and a dielectric layer located between the third electrode region and the fourth electrode region, wherein the third electrode region is connected to the second electrode region of the transistor in the same memory cell.

9. A method for manufacturing a memory, characterized in that: The memory comprises a transistor, wherein the transistor comprises a semiconductor layer and a gate electrode located on the semiconductor layer, a gate insulating layer and a charge trapping storage layer are arranged between the semiconductor layer and the gate electrode, and the charge trapping storage layer is located between the semiconductor layer and the gate insulating layer; The charge trapping storage layer is configured to trap and store charge; The manufacturing method comprises: forming a semiconductor layer of the transistor; Depositing a charge trapping storage layer and a gate insulating layer in sequence on the semiconductor layer; A gate electrode of the transistor is formed on a side of the gate insulating layer away from the charge trapping storage layer.

10. An electronic device, characterized in that: Comprising a memory according to any one of claims 1 to 8.

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