Memory and forming method thereof

Abstract

The embodiment of the invention discloses a memory and a forming method thereof, and the memory comprises a substrate which comprises at least one semiconductor column extending along a first direction; the semiconductor column comprises a first doped region, a channel region and a second doped region which are sequentially arranged along the first direction; the first direction is perpendicular to the thickness direction of the substrate; the gate structure covers the top surface of the channel region and two opposite side walls along a second direction; the second direction is perpendicular to the first direction and the thickness direction of the substrate; and the phase change storage unit is connected with the first doped region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory and a method for forming the memory and an electronic device. Background Art

[0002] Phase Change Memory (PCM), as an emerging non-volatile memory device, has great advantages over flash memory in many aspects such as read and write speed, read and write times, data retention time, unit area, and multi-value realization.

[0003] However, there are still many problems to be solved in phase change memory.

[0004] Public Content

[0005] In view of this, embodiments of the present disclosure provide a memory and a method for forming the memory, and an electronic device.

[0006] According to a first aspect of the present disclosure, there is provided a memory, comprising:

[0007] A substrate, the substrate comprising at least one semiconductor column extending along a first direction; the semiconductor column comprising a first doping region, a channel region and a second doping region sequentially arranged along the first direction; the first direction is perpendicular to a thickness direction of the substrate;

[0008] A gate structure covering the top surface of the channel region and two side walls opposite to each other along a second direction; the second direction is perpendicular to the first direction and the thickness direction of the substrate;

[0009] A phase change memory unit is connected to the first doped region.

[0010] In some embodiments, the phase change memory unit includes: a first electrode, a phase change memory layer, and a second electrode; wherein:

[0011] The first electrode is connected to the first doping region, the phase-change memory layer is located on the first electrode, and the second electrode covers a top surface and a portion of a side wall of the phase-change memory layer.

[0012] In some embodiments, the material of the phase change memory layer is doped with at least one of the following:

[0013] Oxygen, nitrogen, and titanium.

[0014] In some embodiments, the phase change memory unit further includes: a first thermal insulation layer; the first thermal insulation layer includes a first portion and a second portion located on the first portion, the first portion covers the side wall of the first electrode, and the second portion covers the side wall of the phase change memory layer not covered by the second electrode.

[0015] In some embodiments, the phase change memory unit further includes: a second thermal insulation layer; the second thermal insulation layer surrounds the second portion and the second electrode; and the outer wall of the first portion overlaps with the projection of the outer wall of the second thermal insulation layer on the substrate.

[0016] In some embodiments, the material of the first thermal insulation layer includes zirconium oxide.

[0017] In some embodiments, the memory further includes: a doped semiconductor compound layer, wherein the doped semiconductor compound layer covers a top surface of the first doped region and / or a top surface of the second doped region.

[0018] In some embodiments, the substrate includes a silicon-on-insulator (SOI) substrate, and the memory further includes: a bit line, a source line;

[0019] The bit line is connected to the phase change memory unit;

[0020] The source line is connected to the second doping region.

[0021] According to a second aspect of the present disclosure, a method for forming a memory is provided, the method comprising:

[0022] providing a substrate;

[0023] At least one semiconductor column extending along a first direction is formed in the substrate; the semiconductor column comprises a first doping region, a channel region and a second doping region arranged in sequence along the first direction; the first direction is perpendicular to the thickness direction of the substrate;

[0024] forming a gate structure covering the top surface of the channel region and two side walls opposite to each other along a second direction; the second direction is perpendicular to both the first direction and the thickness direction of the substrate;

[0025] A phase change memory unit connected to the first doped region is formed.

[0026] In some embodiments, forming a phase change memory unit connected to the first doping region includes:

[0027] forming a first electrode connected to the first doped region;

[0028] forming a phase change memory layer on the first electrode;

[0029] A second electrode is formed to cover the top surface and a portion of the side wall of the phase change memory layer.

[0030] In some embodiments, the formation of a phase change memory unit connected to the first doping region further includes: forming a first thermal insulation layer; the first thermal insulation layer includes a first part and a second part located on the first part, the first part covers the side wall of the first electrode, and the second part covers the side wall of the phase change memory layer not covered by the first electrode.

[0031] The present disclosure discloses a memory and a method for forming the same, wherein the memory comprises: a substrate, the substrate comprising at least one semiconductor column; the semiconductor column extends along a first direction, comprising a first doping region and a second doping region at two opposite ends along the first direction, and a channel region between the first doping region and the second doping region; the first direction is perpendicular to the thickness direction of the substrate; a gate structure, covering the top surface of the channel region and two opposite side walls along a second direction; the second direction is perpendicular to both the first direction and the thickness direction of the substrate; a phase change memory unit, connected to the first doping region. In the present disclosure embodiment, the gate structure covers the top surface of the channel region and two opposite side walls along the second direction, that is, the channel region is surrounded by the gate structure on three sides, so that the size of the semiconductor column along the second direction can be reduced, thereby improving the integration of the memory, and enabling the memory to have a higher driving current, lower current leakage, and faster switching speed, so that the performance of the memory can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1a Schematic diagram 1 of the structure of a memory according to an embodiment of the present disclosure;

[0033] Figure 1b A schematic diagram of a memory structure according to an embodiment of the present disclosure Figure 2 ;

[0034] Figure 2 A circuit connection diagram of a memory according to an embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of a memory structure according to an embodiment of the present disclosure Figure 4 ;

[0036] Figure 4 Schematic diagram 5 of the structure of a memory according to an embodiment of the present disclosure;

[0037] Figure 5a FIG1 is a partial top view structural diagram of a memory device according to an embodiment of the present disclosure;

[0038] Figure 5b A partial top view of a memory device according to an embodiment of the present disclosure Figure 2 ;

[0039] Figure 5c A partial top view of a memory device according to an embodiment of the present disclosure Figure 3 ;

[0040] Figure 6a Schematic diagram 6 of the structure of a memory according to an embodiment of the present disclosure;

[0041] Figure 6b A schematic diagram of a memory structure according to an embodiment of the present disclosure Figure 7 ;

[0042] Figure 7 A schematic diagram of the relationship between the resistance value and temperature of a phase change memory layer according to an embodiment of the present disclosure;

[0043] Figure 8 A schematic diagram of a memory structure according to an embodiment of the present disclosure Figure 8 ;

[0044] Fig. 9 A schematic diagram of a memory structure according to an embodiment of the present disclosure Figure 9 ;

[0045] Fig.10 A schematic diagram of a method for manufacturing a memory provided by an embodiment of the present disclosure;

[0046] Figure 11-Figure 14 A schematic diagram of the structure of a memory manufacturing process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0048] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0049] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0050] Additionally, for ease of description, spatially relative terms such as "on," "over," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0051] In the disclosed embodiments, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0052] In the disclosed embodiments, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is smaller than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductors and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0053] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0054] Phase change memory can be used for data storage in electronic devices such as mobile phones, tablets, laptops, wearable devices, and vehicle-mounted devices. Phase change memory, as a non-volatile memory, can be prepared based on sulfur-based phase change materials. The phase change memory unit in the phase change memory can realize the conversion of different resistance states under the action of heat. In this way, the resistance difference of the phase change memory unit in different resistance states can be used to realize data reading, writing, and storage.

[0055] The phase change memory includes a phase change memory unit and a transistor. In some embodiments, the transistor is a planar transistor. The gate structure of the transistor is located above the channel region. The drain of the transistor can be connected to the phase change memory unit, the source of the transistor can be connected to the source line (SL), and the gate structure of the transistor can be connected to the word line (WL).

[0056] As the size of phase change memory continues to shrink, traditional planar transistors cannot meet the requirements of high density. The shrinking phase change memory cells may cause a series of problems such as early failure, poor retention rate, and reduced read and write cycles. How to improve the integration density of phase change memory and ensure that the phase change memory has certain performance has become an urgent problem to be solved.

[0057] Based on this, in order to solve the above problems, the present disclosure provides a memory, such as Figure 1a to Figure 1b As shown, the memory includes:

[0058] A substrate 101, wherein the substrate 101 comprises at least one semiconductor column 102 extending along a first direction; the semiconductor column 102 comprises a first doping region 103, a channel region and a second doping region 104 arranged in sequence along the first direction; the first direction is perpendicular to a thickness direction of the substrate 101;

[0059] A gate structure 106, covering the top surface of the channel region and two side walls opposite to each other along a second direction; the second direction is perpendicular to the first direction and the thickness direction of the substrate 101;

[0060] The phase change memory unit 107 is connected to the first doped region 103 .

[0061] In some specific examples, the substrate 101 includes a silicon-on-insulator substrate.

[0062] The silicon-on-insulator substrate introduces a buried oxide layer between the top silicon and the back substrate. The insulation of the buried oxide layer can reduce the parasitic capacitance of the source and drain, thereby reducing the memory delay and dynamic power consumption provided by the embodiment of the present disclosure. In addition, the substrate of the memory in the embodiment of the present disclosure uses a silicon-on-insulator substrate device with better subthreshold characteristics and smaller leakage current; the silicon-on-insulator substrate device does not have a latch-up problem.

[0063] In some specific examples, the semiconductor pillar 102 and the gate structure 106 may constitute a gate transistor, thereby correspondingly controlling the phase change memory unit 107. Here, the first doped region 103 may be a drain, and the second doped region 104 may be a source. The first doped region 103 and the second doped region 104 are doped with impurities, and the doping type may be selected according to the specific situation. When the gate transistor is an N-type transistor, the doping type is N-type doping; when the gate transistor is a P-type transistor, the doping type is P-type doping.

[0064] The gate transistor in the embodiment of the present disclosure is a fin field-effect transistor (Fin Field-Effect Transistor, FinFET) formed on a silicon-on-insulator substrate, and the gate 120 in the gate structure 106 thereof can be as follows: Figure 1a As shown in the fish fin shape, the three sides of the channel region are wrapped by the gate 120. The structure of the gate 120 wrapping the channel region on three sides increases the contact area between the gate 120 and the channel region, enhances the control ability of the gate 120, provides better electrical control over the channel region, and because the gate can be relatively thin, the short channel effect is better suppressed.

[0065] In the embodiment of the present disclosure, a fin field effect transistor formed on a silicon-on-insulator substrate is used to perform corresponding control on a phase change memory unit. Due to the fin field effect transistor formed on the silicon-on-insulator substrate, the memory of the embodiment of the present disclosure has the advantages of smaller size, higher drive current, lower leakage, very fast switching speed, etc., so that the phase change memory unit can have faster write / read speed, lower power consumption, better cycle and retention capabilities, thereby improving the performance of the phase change memory.

[0066] In some specific examples, the number of the phase change memory unit 107 may be one or more. In some examples, a plurality of phase change memory units 107 may be arranged as a layer, or stacked as multiple layers along a direction perpendicular to the substrate 101 (eg, the Z direction).

[0067] It should be noted that Figure 1a to Figure 1b Only two gating transistors and two phase change memory cells 107 are shown as examples, but the number of gating transistors and phase change memory cells 107 in the embodiment of the present disclosure is not limited thereto. The memory in the embodiment of the present disclosure includes multiple gating transistors and multiple phase change memory cells 107, and the multiple gating transistors are arranged in an array along the first direction and the second direction.

[0068] In some specific examples, the memory includes a plurality of semiconductor pillars 102, and the plurality of semiconductor pillars 102 are arranged in an array along a first direction and a second direction. The gate structure 106 includes a gate dielectric layer 121 and a gate 120, the material of the gate dielectric layer 121 includes but is not limited to silicon oxide and silicon nitride, and the material of the gate 120 includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof. The gates 120 of the adjacent selection transistors along the second direction are in contact with each other. The gates of the plurality of selection transistors arranged along the second direction are connected to form a word line 122. The word line 122 can control the conduction and disconnection of the selection transistor to correspond to the heating state of the control phase change memory unit 107.

[0069] Each word line 122 extends along the second direction, and the shape of each word line 122 may be as follows: Figure 1a As shown, the top surface of the portions at the two ends of the word line 122 along the second direction is lower than the top surface of the portion between the two ends. The shape of each word line 122 can be as follows: Figure 1b As shown, the top surface of the word line 122 is a flat top surface. Each word line 122 may also have a shape in which the top surface of the word line 122 located directly above the semiconductor pillar 102 is higher than the top surface of the word line portion between two adjacent semiconductor pillars 102 .

[0070] Here, if Figure 1a to Figure 1b As shown, the first direction may be the Y-axis direction, the second direction may be the X-axis direction, and the thickness direction of the substrate 101 may be the Z-axis direction.

[0071] In the embodiment of the present disclosure, the gate structure 106 covers the top surface of the channel region and the two side walls opposite to each other along the second direction, that is, the channel region is surrounded by the gate structure 106 on three sides. This makes it possible to reduce the size of the semiconductor column 102 along the second direction, thereby improving the integration of the memory, and enabling the memory to have a higher driving current, lower current leakage, and faster switching speed, thereby improving the performance of the memory.

[0072] Figure 2 Schematic diagram of a circuit connection of a phase change memory according to an embodiment of the present disclosure; Figure 2 As shown, the drain of transistor T is connected to PCM, PCM can be equivalent to a variable resistor, the other end of PCM is connected to BL, the source of transistor T is connected to SL, and the gate of transistor T is connected to WL. In the process of reading and writing data in the memory, transistor T is switched to a gated state based on the voltage applied to the word line, and then the data stored in the phase change storage layer can be read, or the phase change storage layer can be heated, thereby completing the data writing to the phase change storage layer.

[0073] In some embodiments, Figure 3As shown, the phase change memory unit 107 includes: a first electrode 108, a phase change memory layer 109, and a second electrode 110; wherein,

[0074] The first electrode 108 is connected to the first doping region 103 , the phase change memory layer 109 is located on the first electrode 108 , and the second electrode 110 covers a top surface and a portion of a side wall of the phase change memory layer 109 .

[0075] In some specific examples, the first electrode 108 may be in a columnar shape, and the second electrode 110 may be in a square shape.

[0076] In some specific examples, such as Figure 3 As shown, the second electrode 110 not only covers the top surface of the phase change memory layer 109, but also covers part of the side wall of the phase change memory layer 109. The cross section of the second electrode 110 can be U-shaped, which can increase heat conduction and improve Joule heat. The size of the second electrode 110 along the Z-axis direction can be set according to actual conditions. It should be noted that the second electrode 110 and the first electrode 108 need to maintain a certain distance along the Z-axis direction to avoid the second electrode 110 and the first electrode 108 being too close to each other along the Z-axis direction to interfere with each other. In actual settings, the appropriate size can be selected by combining the factors of heat conduction and interference effect.

[0077] In some specific examples, such as Figure 3 As shown, the phase change memory unit 107 further includes an adhesion layer 125, which is located between the second electrode 110 and the phase change memory layer 109. The material of the adhesion layer 125 includes but is not limited to titanium, and the adhesion layer 125 can be used to make the second electrode 110 and the phase change memory layer 109 adhere better.

[0078] In some specific examples, the first electrode 108 and the second electrode 110 are arranged opposite to each other in a direction perpendicular to the substrate 101. The phase change memory layer 109 is located between the first electrode 108 and the second electrode 110. In some specific examples, the materials of the first electrode 108 and the second electrode 110 include but are not limited to metals or metal compounds with excellent electrical conductivity. The first electrode 108 and the second electrode 110 can be a single-layer structure or a stacked structure. Exemplarily, the first electrode 108 is a single-layer structure, and the first electrode 108 is, for example, a titanium (Ti) layer or a titanium nitride (TiN) layer, or a mixed layer of a titanium (Ti) layer and a titanium nitride (TiN) layer. Exemplarily, the second electrode 110 is a stacked structure, and the second electrode 110 includes, for example, a stack of a titanium (Ti) layer and a tungsten (W) metal layer stacked, or a stack of a titanium nitride (TiN) layer and a tungsten (W) metal layer.

[0079] The phase change memory unit 107 here is equivalent to an adjustable resistor. By controlling the gate transistor, the phase change memory unit 107 can be in different resistance states as the heat changes, thereby realizing data reading and writing operations based on the resistance change of the phase change memory unit 107.

[0080] In some specific examples, each phase-change memory cell 107 may be a single-level cell (SLC) having two possible memory states and capable of storing one bit of data. In some specific examples, each phase-change memory cell 107 may be a multi-level cell (MLC) having four possible memory states and capable of storing two bits of data, or each phase-change memory cell 107 may be a tri-level cell (TLC) having eight possible memory states and capable of storing three bits of data, or each phase-change memory cell 107 may be a quad-level cell (QLC) having sixteen possible memory states and capable of storing four bits of data.

[0081] In some specific examples, the material of the phase change memory layer 109 may include: an alloy based on chalcogenide, such as a GST (Ge-Sb-Te) alloy, but is not limited thereto. The constituent materials of the phase change memory layer 109 may also include any other appropriate phase change material. It should be noted that when the phase change memory layer 109 undergoes a phase change, the resistance of the phase change memory layer changes. The phase change memory can store data according to the change in the resistance state of the phase change memory layer. The first electrode can be turned on by turning on the selection transistor to heat or quench the phase change memory layer to achieve switching between the crystalline state and the amorphous state of the phase change memory layer. The phase change memory layer corresponds to different resistances when it is in the crystalline state and the amorphous state, respectively. The data writing operation and the erasing operation are completed by switching between the crystalline state and the amorphous state of the phase change memory layer, thereby achieving data storage.

[0082] Here, the phase change memory includes a storage array and a control circuit. Figure 1aThe structure in is only a partial structural diagram of the storage array. If the phase change storage layer of the storage array is in a crystalline state, the control circuit in the phase change memory can heat the phase change storage layer of the storage array according to the received read and write instructions, so that the temperature of the phase change storage layer is higher than the recrystallization temperature, but lower than the melting point temperature. Afterwards, the phase change storage layer is cooled to obtain an amorphous (high resistance) phase change storage layer, and the erase operation is completed. If the phase change storage layer of the storage array is in an amorphous state, the control circuit can heat the phase change storage layer of the storage array according to the received read and write instructions, so that the temperature of the phase change storage layer is slightly higher than the melting point temperature, and then quench the phase change storage layer to cool the phase change storage layer, thereby obtaining a crystalline (low resistance) phase change storage layer, and completing the write operation.

[0083] In some embodiments, the material of the phase change memory layer 109 is doped with at least one of the following:

[0084] Oxygen, nitrogen, and titanium.

[0085] It can be understood that in the embodiment of the present disclosure, by doping the material of the phase change memory layer 109 with oxygen, nitrogen, and titanium, the resistance value of the phase change memory layer 109 can be changed, such as Figure 7 As shown, the horizontal axis is temperature T, and the vertical axis is resistance R. Figure 7 Line L1 in the figure represents undoped GST, line L3 represents GST with less doping, and line L2 represents GST with more doping. Figure 7 It can be seen that the greater the doping amount, the higher the resistance of the phase change memory layer 109 at low temperatures, and the less the doping amount, the higher the resistance of the phase change memory layer 109 at high temperatures; on the other hand, some atomic vacancies in the material of the phase change memory layer 109 can be filled and the bonding can be strengthened to make the structure more stable, reduce element migration, and improve the durability and retention of the memory.

[0086] In some embodiments, Figure 3 As shown, the phase change memory unit 107 also includes: a first thermal insulation layer 111; the first thermal insulation layer 111 includes a first part 112 and a second part 113 located on the first part 112, the first part 112 covers the side wall of the first electrode 108, and the second part 113 covers the side wall of the phase change memory layer 109 not covered by the second electrode 110.

[0087] Here, the second electrode covers a portion of the side wall of the phase change memory layer 109 , the second portion 113 of the first thermal insulation layer 111 covers another portion of the side wall of the phase change memory layer 109 , and the second electrode 110 and the second portion 113 of the first thermal insulation layer 111 completely wrap the side wall and top of the phase change memory layer 109 .

[0088] It can be understood that in the embodiment of the present disclosure, the second electrode 110 and the second portion 113 of the first heat insulating layer 111 completely wrap the sidewalls and the top of the phase change memory layer 109, so that the heat loss can be reduced.

[0089] Here, the width of the first portion 112 along the first direction is not specifically limited. The first portion 112 may be as follows: Figure 3 As shown in , it is smaller than the width of the phase change memory layer 109 .

[0090] In some embodiments, Figure 4 As shown, the second electrode 110 covers another part of the sidewall and the top surface of the phase change memory layer 109;

[0091] The phase change memory unit 107 further includes: a second thermal insulation layer 114 ; the second thermal insulation layer 114 surrounds the second portion 113 and the second electrode 110 ; and the projections of the outer wall of the first portion 112 and the outer wall of the second thermal insulation layer 114 on the substrate 101 coincide with each other.

[0092] It can be understood that the projection of the outer wall of the first part 112 in the above embodiment coincides with the projection of the outer wall of the second heat-insulating layer 114 on the substrate 101, and the first part 112 and the second part 113 completely wrap the heating area of ​​the phase-change memory layer 109, so that the heat-insulating effect is better. The second heat-insulating layer 114 wraps the second electrode 110 and the phase-change memory layer 109, so that the second electrode 110 can be protected and the heat-insulating effect can be increased.

[0093] In some embodiments, the material of the first thermal insulation layer 111 includes zirconium oxide.

[0094] It can be understood that zirconium oxide has a lower thermal conductivity, which can help improve the thermal insulation effect of the first thermal insulation layer 111, thereby effectively improving the heating efficiency.

[0095] In some examples, such as Figure 4 As shown, the memory also includes a second thermal insulation layer 114, and the second thermal insulation layer 114 includes a low-temperature silicon nitride layer and a high-temperature silicon nitride layer stacked. When forming the second thermal insulation layer 114, a low-temperature silicon nitride layer can be formed first, and then a high-temperature silicon nitride layer can be formed, and the high-temperature silicon nitride layer wraps the low-temperature silicon nitride layer, wherein the deposition temperature of the low-temperature silicon nitride layer is less than or equal to 550°C, for example, it can be 350°C, 400°C, 500°C or 550°C. The deposition temperature of the high-temperature silicon nitride layer is greater than or equal to 600°C, for example, it can be 600°C, 800°C, 900°C or 1200°C. The second thermal insulation layer 114 covers the sidewalls of the second portion 113, the sidewalls of the second electrode 110, and the top.

[0096] It can be understood that in the embodiment of the present disclosure, the high-temperature silicon nitride layer wraps the low-temperature silicon nitride layer. The low-temperature silicon nitride layer is looser and can accommodate more heat, while the high-temperature silicon nitride layer is denser and can wrap up the heat, thereby achieving a better thermal insulation effect.

[0097] Figure 5a , Figure 5b , Figure 5c It is a schematic diagram of a partial top view of the memory structure. Figure 6a as well as Figure 6b for Figure 1a A cross-sectional view perpendicular to the X direction. Figure 5a , Figure 5b , Figure 5c As can be seen from the figure, the shape of the phase change memory unit can be cylindrical or square. It should be noted that in order to better show the shape of the phase change memory unit, Figure 5a , Figure 5b , Figure 5c The diagram shown is a perspective view. Figure 5a , Figure 5b , Figure 6a As shown, the second heat insulation layer 114 may surround the second electrode 110, and the second electrode 110 surrounds the phase change memory layer 109. Figure 5c As shown in FIG6 b , the second heat insulating layer 114 may also be located only on two opposite sides of the second electrode 110 along the first direction, and the second electrode 110 may be located only on two sides of the phase change memory layer 109 along the first direction.

[0098] In some embodiments, the memory further includes: a doped semiconductor compound layer 115 , wherein the doped semiconductor compound layer 115 covers a top surface of the first doping region 103 and / or a top surface of the second doping region 104 .

[0099] In some specific examples, the semiconductor compound layer 115 may only cover the top surface of the first doping region 103, or only cover the top surface of the second doping region 104, or may simultaneously cover the top surface of the first doping region 103 and the top surface of the second doping region 104. The semiconductor compound may specifically include silicon carbide, and the doped elements include but are not limited to nitrogen.

[0100] It can be understood that since the stressed silicon induced by the doped silicon nitride can affect the Z-direction lattice, the embodiment of the present disclosure forms a doped semiconductor compound layer 115 on the top surface of the first doped region 103 and / or the top surface of the second doped region 104, which can effectively increase the driving current and improve the performance of the memory.

[0101] In some embodiments, Figure 8 As shown, the memory further includes: a bit line 116 and a source line 117;

[0102] The bit line 116 is connected to the phase change memory unit 107;

[0103] The source line 117 is connected to the second doping region 104 .

[0104] In some specific examples, the memory further includes a metal layer 124 .

[0105] Here, the gate 120 in the selection transistor can be connected to the metal layer 124 through the third contact structure 123, the source can be connected to the source line 117 through the second contact structure 119, and the drain can be connected to the first electrode 108 in the phase change memory unit 107. The bit line 116 can be connected to the second electrode 110 of the phase change memory unit 107 through the first contact structure 118, and the bit line 116 here can be used as a read signal line.

[0106] Here, the materials of the bit line 116 and the source line 117 include but are not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.

[0107] Fig. 9 A schematic diagram of a top view of a phase change memory provided by an embodiment of the present disclosure. Fig. 9 It can be seen that the plurality of semiconductor pillars 102 are arranged in an array along the first direction and the second direction, and the plurality of phase change memory cells 107 are also arranged in an array along the first direction and the second direction accordingly, and one phase change memory cell 107 is connected to one semiconductor pillar 102. The plurality of bit lines 116 are arranged along the second direction, each bit line 116 extends along the first direction, and one bit line 116 can be connected to all the phase change memory cells 107 arranged along the first direction. The plurality of word lines 122 are arranged along the first direction, each word line 122 extends along the second direction, and one word line 122 is connected to all the semiconductor pillars 102 arranged along the second direction. The plurality of source lines 117 are arranged along the first direction, each source line 117 extends along the second direction, and one source line 117 can be connected to all the phase change memory cells 107 arranged along the second direction.

[0108] Based on the above memory, an embodiment of the present disclosure further provides an electronic device, comprising the memory as described in any of the above embodiments.

[0109] In some specific examples, an electronic device includes a circuit board and a phase change memory disposed on the circuit board.

[0110] In some specific examples, electronic devices include computing devices (such as servers), network devices (such as switches), storage devices (such as storage arrays), vehicle-mounted devices (such as vehicle-mounted speakers, vehicle-mounted navigation systems, etc.) and terminal devices (wearable devices, computers, mobile phones and tablets, etc.), etc.

[0111] Based on the above memory, the present disclosure also provides a method for manufacturing the memory. Fig.10 The flowchart of the method for manufacturing the memory provided by the embodiment of the present disclosure is shown in FIG. Fig.10 As shown, the method for manufacturing a memory provided by the embodiment of the present disclosure includes the following steps:

[0112] S1100: providing a substrate;

[0113] S1200: forming at least one semiconductor column extending along a first direction in the substrate; the semiconductor column comprises a first doping region, a channel region, and a second doping region sequentially arranged along the first direction; the first direction is perpendicular to a thickness direction of the substrate;

[0114] S1300: forming a gate structure covering a top surface of the channel region and two side walls opposite to each other along a second direction; the second direction is perpendicular to the first direction and a thickness direction of the substrate;

[0115] S1400: forming a phase change memory unit connected to the first doping region.

[0116] It should be understood that Fig.10 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Fig.10 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0117] In some specific examples, forming a phase change memory unit connected to the first doping region includes:

[0118] forming a first electrode connected to the first doped region;

[0119] forming a phase change memory layer on the first electrode;

[0120] A second electrode is formed to cover the top surface and a portion of the side wall of the phase change memory layer.

[0121] In some specific examples, the formation of a phase change memory unit connected to the first doping region also includes: forming a first thermal insulation layer; the first thermal insulation layer includes a first part and a second part located on the first part, the first part covers the side wall of the first electrode, and the second part covers the side wall of the phase change memory layer not covered by the first electrode.

[0122] In some specific examples, the phase change memory unit further includes: a second thermal insulation layer; the second thermal insulation layer surrounds the second portion and the second electrode; and the outer wall of the first portion overlaps with the projection of the outer wall of the second thermal insulation layer on the substrate.

[0123] In some specific examples, the method further includes: forming a doped semiconductor compound layer on the first doping region and / or on the second doping region.

[0124] In some specific examples, the method further includes:

[0125] forming a bit line connected to the phase change memory cell;

[0126] A source line connected to the second doping region is formed.

[0127] Combine the following Figures 11 to 14 The method for forming the above-mentioned memory is further introduced.

[0128] First, Fig.11 As shown, a substrate 101 is provided, such as a silicon-on-insulator substrate, and at least one semiconductor column 102 extending along a first direction is formed in the substrate 101. Both ends of the semiconductor column 102 are doped to form a first doping region 103 and a second doping region 104, and a portion of the semiconductor column 102 between the first doping region 103 and the second doping region 104 forms a channel region. A gate dielectric layer 121 and a gate 120 covering the top surface of the channel region and two side walls opposite to each other along the second direction are formed, thereby forming a gate structure 106.

[0129] In some specific examples, a portion of the substrate 101 may be removed by an etching process to form at least one semiconductor pillar 102 .

[0130] In some specific examples, the gate dielectric layer 121 and the gate 120 may be formed by a deposition process.

[0131] In some specific examples, the deposition method includes but is not limited to physical vapor deposition (PVD, Physical Vapor Deposition) process, chemical vapor deposition (CVD, Chemical Vapor Deposition) process, atomic layer deposition (ALD, Atomic Layer Deposition) process and the like.

[0132] Next, if Fig.12 As shown, a doped semiconductor compound layer 115 is formed on the first doping region 103 and / or the second doping region 104 .

[0133] In some specific examples, a semiconductor compound material such as silicon carbide can be formed on the first doping region 103 and / or the second doping region 104 by an epitaxial growth process, and then the silicon carbide is subjected to corresponding doping treatment, such as nitrogen doping, to obtain a doped semiconductor compound layer 115.

[0134] Next, if Fig.13 As shown, a phase change memory unit 107 connected to the first doping region 103 is formed.

[0135] Next, if Fig.14 As shown, a first contact structure 118 and a bit line 116 are formed on the phase change memory unit 107 , a second contact structure 119 and a source line 117 are formed on the second doped region 104 , a third contact structure 123 is formed on the gate structure, and a metal layer 124 is formed on the third contact structure 123 .

[0136] In some specific examples, a through hole may be formed in the dielectric layer and a conductive material may be filled in the through hole to form the first contact structure 118, the second contact structure 119, and the third contact structure 123. A groove may be formed in the dielectric layer and a conductive material may be filled in the groove to form the source line 117, the bit line 116, and the metal layer 124.

[0137] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0138] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0139] The specific embodiments of the present disclosure are disclosed, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: A substrate, the substrate comprising at least one semiconductor column extending along a first direction; the semiconductor column comprising a first doping region, a channel region and a second doping region sequentially arranged along the first direction; the first direction is perpendicular to a thickness direction of the substrate; A gate structure covering the top surface of the channel region and two side walls opposite to each other along the second direction; The second direction is perpendicular to the first direction and the thickness direction of the substrate; A phase change memory unit is connected to the first doped region.

2. The memory according to claim 1, characterized in that: The phase change memory unit comprises: a first electrode, a phase change memory layer, and a second electrode; wherein, The first electrode is connected to the first doping region, the phase-change memory layer is located on the first electrode, and the second electrode covers a top surface and a portion of a side wall of the phase-change memory layer.

3. The memory according to claim 2, characterized in that: The material of the phase change memory layer is doped with at least one of the following: Oxygen, nitrogen, and titanium.

4. The memory according to claim 2, characterized in that: The phase change memory unit further includes: a first insulation layer; the first insulation layer includes a first portion and a second portion located on the first portion, the first portion covers the side wall of the first electrode, and the second portion covers the side wall of the phase change memory layer not covered by the second electrode.

5. The memory according to claim 4, characterized in that: The phase change memory unit further includes: a second heat insulation layer; the second heat insulation layer surrounds the second part and the second electrode; and the projection of the outer wall of the first part and the outer wall of the second heat insulation layer on the substrate coincides.

6. The memory according to claim 4, characterized in that: The material of the first thermal insulation layer includes zirconium oxide.

7. The memory according to claim 1, characterized in that: The memory further includes: a doped semiconductor compound layer, wherein the doped semiconductor compound layer covers a top surface of the first doped region and / or a top surface of the second doped region.

8. The memory according to claim 1, characterized in that: The substrate comprises a silicon-on-insulator substrate, and the memory further comprises: a bit line and a source line; The bit line is connected to the phase change memory unit; The source line is connected to the second doping region.

9. A method for forming a memory, characterized in that: include: providing a substrate; At least one semiconductor column extending along a first direction is formed in the substrate; the semiconductor column comprises a first doping region, a channel region and a second doping region arranged in sequence along the first direction; the first direction is perpendicular to the thickness direction of the substrate; forming a gate structure covering the top surface of the channel region and two side walls opposite to each other along a second direction; the second direction is perpendicular to both the first direction and the thickness direction of the substrate; A phase change memory unit connected to the first doped region is formed.

10. The forming method according to claim 9, characterized in that: The phase change memory unit formed to be connected to the first doping region comprises: forming a first electrode connected to the first doped region; forming a phase change memory layer on the first electrode; A second electrode is formed to cover the top surface and a portion of the side wall of the phase change memory layer.

11. The forming method according to claim 10, characterized in that: The phase change memory unit formed to be connected to the first doping region also includes: forming a first thermal insulation layer; the first thermal insulation layer includes a first part and a second part located on the first part, the first part covers the side wall of the first electrode, and the second part covers the side wall of the phase change memory layer not covered by the first electrode.

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