Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and the preparation method comprises the steps: providing a silicon carbide substrate and an epitaxial layer, forming a groove in a third surface, away from the silicon carbide substrate, of the epitaxial layer, and sequentially forming a protection layer and a semiconductor layer in the groove, removing a part of the semiconductor layer to obtain a barrier layer, covering the bottom and at least part of the side wall of the groove by the barrier layer, removing a part of the protective layer to obtain a first insulating layer, covering the bottom and the side wall of the barrier layer by the first insulating layer, processing the barrier layer to obtain a second insulating layer, and then forming a third insulating layer on the side wall of the groove, the thickness of the third insulating layer is smaller than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer, then forming a grid electrode in the groove, forming a source electrode on the third surface, and forming a drain electrode on the second surface. The technical scheme of the invention aims to improve the conductivity and reliability of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] At present, in the manufacturing process of silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET), gate oxide is formed directly in the groove set on the surface of the epitaxial layer by high-temperature oxidation. Due to the different crystal phases of silicon carbide (SiC) at the bottom and side walls of the trench, the rate of silicon oxide generation on the side walls is faster under high temperature environment, thereby forming a gate oxide layer with a thinner bottom and thicker side walls, which increases the threshold voltage of the transistor and the on-resistance, reducing the conductivity of the semiconductor device. At the same time, the thinner gate oxide layer at the bottom will cause the bottom to easily break down prematurely, resulting in insufficient withstand voltage and excessive leakage. Summary of the invention

[0003] The present application proposes a semiconductor device and a preparation method, a power module, a power conversion circuit, and a vehicle, aiming to ensure the reliability of the semiconductor device while improving the conductive performance of the semiconductor device.

[0004] On the one hand, a method for preparing a semiconductor device is provided, the method comprising: providing a silicon carbide substrate, the silicon carbide substrate comprising a first surface and a second surface arranged opposite to each other, forming an epitaxial layer on the first surface of the silicon carbide substrate, the epitaxial layer comprising a third surface away from the silicon carbide substrate, forming a groove on the third surface of the epitaxial layer, forming a protective layer, the protective layer at least covering the bottom and part of the sidewall of the groove, forming a semiconductor layer, at least part of the semiconductor layer fills the groove, removing part of the semiconductor layer to obtain a barrier layer, the barrier layer covers the bottom and at least part of the sidewall of the groove, removing part of the protective layer to obtain a first insulating layer, the first insulating layer covers the bottom and sidewall of the barrier layer, processing the barrier layer to obtain a second insulating layer, forming a third insulating layer on the sidewall of the groove, the thickness of the third insulating layer is less than the sum of the thickness of the first insulating layer and the second insulating layer, forming a gate in the groove, forming a source on the third surface, the source is located on the side of the gate away from the silicon carbide substrate, and forming a drain on the second surface.

[0005] In the embodiment of the present application, a groove is formed on the third surface of the epitaxial layer, and then a protective layer is formed on the side wall and at least part of the bottom of the groove to protect the epitaxial layer. After the semiconductor layer is formed to fill the groove, part of the semiconductor layer is removed to obtain a barrier layer, and the barrier layer is used as a barrier. Part of the protective layer is removed to obtain a first insulating layer, and then the barrier layer is processed to obtain a second insulating layer. Then, a third insulating layer is formed on the side wall of the groove, and the thickness of the third insulating layer is less than the sum of the thickness of the first insulating layer and the second insulating layer. The first insulating layer, the second insulating layer and the third insulating layer can be used as the gate insulating layer of the semiconductor device. Finally, a gate, a source and a drain are formed to form a semiconductor device. The thicker first insulating layer and the second insulating layer can effectively disperse the electric field formed by the gate when the semiconductor device is conductive, thereby reducing the risk of electrical breakdown of the semiconductor device and improving the safety and reliability of the semiconductor device. The thinner third insulating layer helps to enhance the control ability of the gate over the channel, so that a conductive channel can be formed at a lower gate voltage, thereby reducing the threshold voltage and on-resistance of the semiconductor device and improving the conductive performance of the semiconductor device.

[0006] In some embodiments, the material of the second insulating layer includes silicon oxide, and the material of the barrier layer includes polysilicon. The embodiment of processing the barrier layer to obtain the second insulating layer includes thermally oxidizing the barrier layer to obtain the second insulating layer.

[0007] In some embodiments, the implementation of forming the third insulating layer includes performing a thermal oxidation process on the sidewalls of the trench to obtain the third insulating layer.

[0008] On the other hand, a semiconductor device is provided, which is prepared by the above-mentioned preparation method, and the semiconductor device includes a silicon carbide substrate, an epitaxial layer, a gate, a gate oxide layer, a source electrode and a drain electrode. The silicon carbide substrate includes a first surface and a second surface opposite to each other, the epitaxial layer is arranged on the first surface, the epitaxial layer includes a third surface away from the silicon carbide substrate, the gate electrode is embedded in the third surface of the epitaxial layer, the gate oxide layer is arranged between the gate electrode and the epitaxial layer, the source electrode is arranged on the third surface and is located on the side of the gate electrode away from the silicon carbide substrate, and the drain electrode is arranged on the second surface.

[0009] The gate includes a fourth surface close to the silicon carbide substrate and a side surface connected to the fourth surface, the gate oxide layer includes a first portion located between the fourth surface and the epitaxial layer, and a second portion located between the side surface and the epitaxial layer, and the thickness of the first portion is greater than the thickness of the second portion.

[0010] In the embodiment of the present application, the thickness of the first portion of the gate oxide layer located between the fourth surface of the gate and the epitaxial layer is greater than the second portion located between the side of the gate and the epitaxial layer. The thicker first portion can effectively disperse the electric field formed by the gate when the semiconductor device is conductive, thereby reducing the risk of electrical breakdown of the semiconductor device and improving the safety and reliability of the semiconductor device. The thinner second portion helps to enhance the gate's control over the channel, so that a conductive channel can be formed at a lower gate voltage, thereby reducing the threshold voltage and on-resistance of the semiconductor device and improving the conductivity of the semiconductor device.

[0011] In some embodiments, the ratio of the thickness of the first portion to the thickness of the second portion is in the range of 1.25-4.

[0012] In some embodiments, the thickness of the first portion ranges from 1000 angstroms to 2000 angstroms, and the thickness of the second portion ranges from 500 angstroms to 800 angstroms.

[0013] On the other hand, the present application provides a power module, which includes a substrate and at least one of the above-mentioned semiconductor devices, wherein the substrate is used to carry the semiconductor device.

[0014] On the other hand, the present application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0015] On the other hand, the present application provides a vehicle, which includes a load and the above-mentioned power conversion circuit, and the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0016] The power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, which will not be described in detail here. Additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present application, the actual process of the method, etc.

[0018] Figure 1 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0019] Figure 2 to Figure 12 The diagram is a diagram of each step of preparing a semiconductor device in an embodiment of the present application;

[0020] Fig.13 for Fig.12 An enlarged schematic diagram within a dotted frame N in the semiconductor device shown;

[0021] Fig.14 A structural diagram of a power module provided in an embodiment of the present application;

[0022] Fig.15 A structural diagram of a power conversion circuit provided in an embodiment of the present application;

[0023] Fig.16 A structural diagram of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0025] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0026] In the description of the present application, “plurality” means two or more.

[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0028] The embodiment of the present application provides a method for preparing a semiconductor device. Figure 1 The flowchart of the method for preparing a semiconductor device provided in the embodiment of the present application is as follows: Figure 2 to Figure 12 The following are the steps for preparing a semiconductor device in the embodiment of the present application. Figure 1 As shown, the method includes the following steps S1 to S12:

[0029] Step S1 to Step S2: Figure 2 As shown, a silicon carbide substrate 10 is provided, and the silicon carbide substrate 10 includes a first surface 101 and a second surface 102 that are opposite to each other, and then an epitaxial layer 11 is formed on the first surface 100 of the silicon carbide substrate 10. The material of the epitaxial layer 11 is the same as that of the silicon carbide substrate 10, which is also silicon carbide, and the silicon carbide substrate 10 includes a second surface 102 that is opposite to the first surface 101, and the epitaxial layer 11 includes a third surface 110 away from the silicon carbide substrate.

[0030] Step S3: Figure 3 As shown, a trench 120 is formed on the third surface 110 of the epitaxial layer 11 .

[0031] Step S4: Figure 4 As shown, a protective layer 121 is formed, and the protective layer 121 at least covers the bottom and part of the side wall of the groove 120. Exemplarily, the protective layer 121 can be formed by a low-pressure tetraethyl orthosilicate (LPTEOS) chemical vapor deposition process. The LPTEOS process has better step coverage, quality, purity, reflow characteristics and thermal stability, and can be used to deposit dielectric materials such as silicon oxide. The material of the protective layer 121 can be silicon oxide, which is used to protect the epitaxial layer 11 from being etched and damaged in subsequent processes.

[0032] Step S5: Figure 5 As shown, a semiconductor layer 122 is formed, and at least a portion of the semiconductor layer 122 fills the trench 120. Exemplarily, the material of the semiconductor layer 122 may be polysilicon, and the process of forming the semiconductor layer 122 may adopt undoped polysilicon (Upoly) deposition.

[0033] Step S6: Figure 6 As shown, a portion of the semiconductor layer 122 is removed to obtain a barrier layer 123. The process of removing the portion of the semiconductor layer 122 may be performed by polysilicon (poly) etching, and the barrier layer 123 formed covers the bottom and at least a portion of the sidewalls of the trench 120. In the process of removing the semiconductor layer 122, due to the presence of the protective layer 121, the epitaxial layer 11 is covered and protected, so that the epitaxial layer 11 is not damaged by etching, thereby ensuring the flatness of the epitaxial layer 11.

[0034] Step S7: Figure 7 As shown, a portion of the protective layer 121 is removed to obtain the first insulating layer 124 . The process of removing a portion of the protective layer 121 can use LPTEOS etching until the first insulating layer 124 covers the bottom and side walls of the blocking layer 123 , that is, the first insulating layer 124 is located on the side of the blocking layer 123 away from the first surface 101 .

[0035] Step S8: Figure 8 As shown, the barrier layer 123 is processed to obtain a second insulating layer 125, thereby increasing the total thickness of the insulating layer at the bottom of the groove 120. The insulating layer at the bottom of the groove 120 can effectively disperse the electric field formed by the gate 12 when the semiconductor device 1 is turned on, thereby preventing the semiconductor device 1 from electrical breakdown.

[0036] In some embodiments, the material of the second insulating layer 125 includes silicon oxide, the material of the barrier layer 123 includes polysilicon, and a specific implementation of processing the barrier layer 123 to obtain the second insulating layer 125 includes thermally oxidizing the barrier layer 123 to obtain the second insulating layer 125 .

[0037] Step S9: Fig. 9 As shown, a third insulating layer 126 is formed on the sidewall of the trench, and the first insulating layer 124, the second insulating layer 125 and the third insulating layer 126 can be used as the gate insulating layer 13 of the semiconductor device 1, and the thickness of the third insulating layer 126 is less than the sum of the thicknesses of the first insulating layer 124 and the second insulating layer 125. The first insulating layer 124, the second insulating layer 125 and the third insulating layer 126 constitute the gate insulating layer 13.

[0038] In some embodiments, the method of forming the third insulating layer 126 includes thermally oxidizing the sidewalls of the trench 120 to form a layer of silicon oxide film on the trench sidewalls 120 to obtain the third insulating layer 126. The third insulating layer 126 is used to isolate the gate 12 and the epitaxial layer 11 to prevent the two from short circuiting.

[0039] Step S10: Fig.10As shown, a gate 12 is formed in the groove 120. Before forming the gate 12, it is necessary to form a first region 17, a second region 18 and a well region 19 by ion implantation on the side of the epitaxial layer 11 away from the silicon carbide substrate 10. The well region 19 has the same conductivity type as the second region 18, and both are of the first conductivity type. The silicon carbide substrate 10, the epitaxial layer 11 and the first region 17 have the same conductivity type, and both are of the second conductivity type. For example, P-type ions are implanted in the well region 19 and the second region 18, and both are of the P-type conductivity type. The well region 19 can also be referred to as a "P-type well region (P-well)", and the second region 18 can also be referred to as a "P+ contact region". The conductivity type of the silicon carbide substrate 10, the epitaxial layer 11 and the first region 17 is all N-type, and N-type ions are implanted in the first region 17. The first region 17 can also be referred to as an "N+ contact region".

[0040] In the embodiment of the present application, the thicker first insulating layer 124 and the second insulating layer 125 can effectively disperse the electric field formed by the gate 12 when the semiconductor device 1 is conductive, thereby reducing the risk of electrical breakdown of the semiconductor device 1 and improving the safety and reliability of the semiconductor device 1. The thinner third insulating layer 126 helps to enhance the control ability of the gate 12 over the channel, so that a conductive channel can be formed at a lower gate voltage, thereby reducing the threshold voltage and on-resistance of the semiconductor device 1 and improving the conductive performance of the semiconductor device 1.

[0041] Step S11: Fig.11 As shown, a source 14 is formed on the third surface 110. The source 14 is located on the side of the gate 12 away from the silicon carbide substrate 10. An interlayer dielectric layer (ILD) 16 is also provided between the gate 12 and the source 14. The interlayer dielectric layer 16 is used to isolate the gate 12 and the source 14 to prevent a short circuit between the two.

[0042] Step S12: Fig.12 As shown, a drain 15 is formed on the second surface 102, and finally a semiconductor device 1 is formed. The semiconductor device 1 is a silicon carbide trench metal oxide semiconductor field effect transistor (SiC trench MOSFET).

[0043] The embodiment of the present application also provides a semiconductor device, such as Fig.12As shown, the semiconductor device 1 is prepared by the above-mentioned preparation method. The semiconductor device 1 is a silicon carbide trench metal oxide semiconductor field effect transistor (SiCtrench MOSFET), and the semiconductor device 1 includes a silicon carbide substrate 10, an epitaxial layer 11, a gate 12, a gate insulating layer 13, a source 14 and a drain 15. The silicon carbide substrate 10 includes a first surface 101 and a second surface 102 arranged opposite to each other, the epitaxial layer 11 is arranged on the first surface 101, and the epitaxial layer 11 includes a third surface 110 away from the silicon carbide substrate 10. The gate 12 is embedded in the third surface 110 of the epitaxial layer 11, and a gate insulating layer 13 is arranged between the gate 12 and the epitaxial layer 11. The gate insulating layer 13 is used to isolate the gate 12 and the epitaxial layer 11 to prevent the two from short-circuiting. The source 14 is disposed on the third surface 110 and is located on the side of the gate 12 away from the silicon carbide substrate 10. An interlayer dielectric layer (ILD) 16 is disposed between the gate 12 and the source 14. The interlayer dielectric layer 16 is used to isolate the gate 12 and the source 14 to prevent a short circuit between the two. The drain 15 is disposed on the second surface 102.

[0044] Exemplarily, the epitaxial layer 11 also includes a first region 17, a second region 18 and a well region 19 formed by ion implantation, and these regions are all arranged on a side of the epitaxial layer 11 away from the silicon carbide substrate 10. The above-mentioned well region 19 has the same conductivity type as the second region 18, and both are of the first conductivity type. The silicon carbide substrate 10, the epitaxial layer 11 and the first region 17 have the same conductivity type, and both are of the second conductivity type. For example, P-type ions are implanted in the well region 19 and the second region 18, and the conductivity types of both are P-type. The well region 19 can also be referred to as a "P-type well region (P-well)", and the second region 18 can also be referred to as a "P+ contact region". The conductivity types of the silicon carbide substrate 10, the epitaxial layer 11 and the first region 17 are all N-type, and N-type ions are implanted in the first region 17. The first region 17 can also be referred to as an "N+ contact region".

[0045] By transmitting a turn-on voltage to the gate 12 , when the semiconductor device 1 is forward-conducting and the operating current is small, the operating current reaches the drain 15 from the source 14 through the first region 17 , the well region 19 , the epitaxial layer 11 and the silicon carbide substrate 10 .

[0046] Since the P-type ion concentration in the second region 18 is higher than that in the well region 19 , more PN junctions are formed between the second region 18 and the epitaxial layer 11 . When the operating current is large, the operating current flows from the source 14 through the second region 18 , the epitaxial layer 11 and the silicon carbide substrate 10 to the drain 18 , thereby preventing the large operating current from flowing through the well region 19 , thereby protecting the channel in the well region 19 .

[0047] Fig.13 for Fig.12 An enlarged schematic diagram of the semiconductor device within the dotted frame N is shown.

[0048] like Fig.13 As shown, the gate 12 includes a fourth surface 127 close to the silicon carbide substrate 10, and a side surface 128 connected to the fourth surface 127, and the gate insulating layer 13 includes a first portion 131 located between the fourth surface 127 and the epitaxial layer 11, and the first portion 131 is used to disperse the electric field between the drain 15 and the gate 12 when the semiconductor device 1 is reversely stressed, and its thickness will affect the withstand voltage performance of the semiconductor device 1. The gate insulating layer 13 also includes a second portion 132 located between the side surface 128 and the epitaxial layer 11, and the thickness of the second portion 132 will affect the threshold voltage and on-resistance of the semiconductor device 1.

[0049] In the embodiment of the present application, the thickness of the first part 131 is greater than the thickness of the second part 132. The thicker first part 131 effectively reduces the risk of electrical breakdown of the semiconductor device while ensuring current conduction, thereby improving the safety and reliability of the semiconductor device. The thinner second part 132 helps to enhance the control ability of the gate 12 over the channel, so that a conductive channel can be formed at a lower voltage, thereby reducing the threshold voltage and on-resistance of the semiconductor device 1 and improving the conductive performance of the semiconductor device 1.

[0050] In some embodiments, the ratio of the thickness of the first portion 131 to the thickness of the second portion 132 is in the range of 1.25 to 4. Within this thickness ratio range, the conductive performance of the semiconductor device 1 can be optimized, its reliability and safety can be improved, and the manufacturing yield of the semiconductor device can be improved by reducing the probability of electrical breakdown, thereby reducing the manufacturing cost.

[0051] In some embodiments, the thickness of the first portion 131 ranges from 1000 angstroms to 2000 angstroms, and the thickness of the second portion 132 ranges from 500 angstroms to 800 angstroms. The thickness of the first portion 131 and the second portion 132 are within the aforementioned range, which can not only optimize the conductive performance of the semiconductor device 1 and reduce the probability of electrical breakdown, but also avoid the gate insulation layer 13 being too thick, which may weaken the control ability of the gate 12 over the channel.

[0052] The embodiment of the present application further provides a power module, Fig.14 A structural diagram of a power module provided in an embodiment of the present application.

[0053] See also Fig.14 The power module 2 includes a substrate 21 and the semiconductor device 1 in any of the above embodiments, and the substrate 21 is used to carry the semiconductor device 1.

[0054] Exemplarily, the power module 2 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0055] The embodiment of the present application also provides a power conversion circuit, Fig.15 A structural diagram of a power conversion circuit provided in an embodiment of the present application.

[0056] See also Fig.15 The power conversion circuit 3 includes a circuit board 31 and a semiconductor device 1 in any of the above embodiments. The semiconductor device 1 is electrically connected to the circuit board 31. The power conversion circuit 3 can be used for current conversion, voltage conversion or power factor correction.

[0057] Exemplarily, the power conversion circuit 3 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0058] An embodiment of the present application further provides a vehicle, Fig.16 A structural diagram of a vehicle provided in an embodiment of the present application.

[0059] See also Fig.16 The vehicle 4 includes a load 41 and the power conversion circuit 3 in the above embodiment, and the power conversion circuit 3 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 41 to power the load 41.

[0060] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a silicon carbide substrate, the silicon carbide substrate comprising a first surface and a second surface arranged opposite to each other; forming an epitaxial layer on the first surface of the silicon carbide substrate, wherein the epitaxial layer includes a third surface away from the silicon carbide substrate; forming a groove on a third surface of the epitaxial layer; forming a protective layer, wherein the protective layer at least covers the bottom and a portion of the sidewall of the trench; forming a semiconductor layer, wherein at least a portion of the semiconductor layer fills the trench; Removing a portion of the semiconductor layer to obtain a barrier layer, wherein the barrier layer covers a bottom and at least a portion of a sidewall of the trench; Removing part of the protective layer to obtain a first insulating layer, wherein the first insulating layer covers the bottom and side walls of the barrier layer; Processing the barrier layer to obtain a second insulating layer; forming a third insulating layer on the sidewall of the trench, wherein the thickness of the third insulating layer is less than the sum of the thicknesses of the first insulating layer and the second insulating layer; forming a gate in the trench; forming a source electrode on the third surface, wherein the source electrode is located on a side of the gate electrode away from the silicon carbide substrate; A drain electrode is formed on the second surface.

2. The preparation method according to claim 1, characterized in that: The material of the second insulating layer includes silicon oxide, and the material of the barrier layer includes polysilicon; Processing the barrier layer to obtain the second insulating layer comprises: The barrier layer is subjected to thermal oxidation treatment to obtain the second insulating layer.

3. The preparation method according to claim 1, characterized in that: Forming the third insulating layer includes: The sidewalls of the trench are thermally oxidized to obtain the third insulating layer.

4. A semiconductor device, characterized in that: Prepared by the preparation method according to any one of claims 1 to 3, the semiconductor device comprises: A silicon carbide substrate, comprising a first surface and a second surface arranged opposite to each other; an epitaxial layer, disposed on the first surface, the epitaxial layer comprising a third surface away from the silicon carbide substrate; a gate, embedded in the third surface of the epitaxial layer; A gate insulating layer, disposed between the gate and the epitaxial layer; A source electrode, disposed on the third surface and located on a side of the gate electrode away from the silicon carbide substrate; A drain electrode is disposed on the second surface; Wherein, the gate includes a fourth surface close to the silicon carbide substrate, and a side surface connected to the fourth surface; The gate insulating layer includes a first portion located between the fourth surface and the epitaxial layer, and a second portion located between the side surface and the epitaxial layer, and a thickness of the first portion is greater than a thickness of the second portion.

5. The semiconductor device according to claim 4, characterized in that The ratio of the thickness of the first portion to the thickness of the second portion is in the range of 1.25-4.

6. The semiconductor device according to claim 4, characterized in that The thickness of the first portion ranges from 1000 angstroms to 2000 angstroms; The thickness of the second portion ranges from 500 angstroms to 800 angstroms.

7. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to any one of claims 4 to 6, wherein the substrate is used for carrying the semiconductor device.

8. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 4 to 6, wherein the semiconductor device is electrically connected to the circuit board.

9. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 8, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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