Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and the preparation method comprises the steps: providing a semiconductor structure which comprises a first insulating layer, a source electrode layer located on the first insulating layer, and a second insulating layer located on the source electrode layer; forming a plurality of embedded drain electrode parts arranged in an array on the upper part of the second insulating layer; the drain electrode parts serve as masks, the second insulating layer is etched till the source electrode layer is exposed, so that a plurality of columnar bodies arranged in an array mode are formed on the upper surface of the source electrode layer, the columnar bodies comprise insulating columns located on the source electrode layer and the drain electrode parts located on the insulating columns, and the columnar bodies are mutually spaced through first grooves formed by etching the second insulating layer; forming a channel material layer surrounding the cylindrical object along the circumferential direction; and forming a gate dielectric layer and a gate structure on one side, far away from the columnar body, of the channel material layer. According to the preparation method provided by the invention, a straighter channel material layer can be formed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] When preparing existing semiconductor devices with vertical transistor structures, a source layer and a first oxide layer located on the source layer are usually formed first, and then a gate layer and a second oxide layer located on the gate layer are formed above the first oxide layer. Then, a channel hole penetrating the second oxide layer, the gate layer and the first oxide layer is formed, and then a channel material layer is formed in the channel hole. For this preparation method, when forming the channel hole, it is necessary to etch multiple film layers of different materials. The etching selectivity is difficult to control, resulting in an uneven inner wall of the channel hole as a whole, and a non-straight channel material layer is formed along with the hole morphology, which affects the electrical performance of the semiconductor device. In addition, when etching to open the source layer and wet cleaning, it will also cause damage to the top oxide liner, the bottom oxide substrate and the gate oxide layer, which will lead to the device V BD Test failed.

[0003] Therefore, improvements are needed to at least partially solve the above problems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In order to at least partially solve the above problem, according to a first aspect of the present invention, a method for preparing a semiconductor device is provided, comprising:

[0006] Providing a semiconductor structure, the semiconductor structure comprising a first insulating layer, a source layer located on the first insulating layer, and a second insulating layer located on the source layer;

[0007] forming a plurality of drain portions arranged in an inlaid array on the upper portion of the second insulating layer;

[0008] Using the plurality of drain portions as masks, etching the second insulating layer until the source layer is exposed, so as to form a plurality of columns arranged in an array on the upper surface of the source layer, wherein the columns include insulating columns located on the source layer and the drain portions located on the insulating columns, and the plurality of columns are spaced apart from each other by first grooves formed by etching the second insulating layer;

[0009] forming a channel material layer circumferentially surrounding the columnar body;

[0010] A gate dielectric layer and a gate structure are formed on a side of the channel material layer away from the columnar body.

[0011] Exemplarily, the plurality of drain portions arranged in an array inlaid on the upper portion of the second insulating layer comprises:

[0012] forming a first patterned photoresist layer on the upper surface of the second insulating layer;

[0013] Using the first patterned photoresist layer as a mask, etching the second insulating layer to form a plurality of second trenches on an upper portion of the second insulating layer, wherein the second trenches correspond to the drain portions one by one;

[0014] removing the first patterned photoresist layer, and filling the second trench with a drain material;

[0015] The upper surface of the drain electrode material is polished to be flush with the upper surface of the second insulating layer by a chemical mechanical polishing process to form the drain electrode portion.

[0016] Exemplarily, the forming of a channel material layer circumferentially surrounding the columnar body includes:

[0017] Depositing a semiconductor material layer on the inner surface of the first trench and the upper surface of the columnar body;

[0018] Wherein, a portion of the semiconductor material layer surrounding the columnar body in a circumferential direction constitutes the channel material layer.

[0019] Exemplarily, before forming the channel material layer circumferentially surrounding the columnar body, the preparation method further includes:

[0020] A pre-cleaning process is performed on the first groove and the column.

[0021] Exemplarily, the pre-cleaning of the first groove and the columnar body includes:

[0022] Oxidizing the upper surface of the drain portion that is damaged when etching the second insulating layer using the drain portion as a mask;

[0023] The oxide formed on the upper surface of the drain portion is removed by a wet method or a dry method, and the first trench is cleaned at the same time.

[0024] Exemplarily, forming a gate dielectric layer and a gate structure on a side of the channel material layer away from the columnar body includes:

[0025] Forming the gate dielectric layer conformally covering the semiconductor material layer;

[0026] Filling the first trench with an insulating material and performing a surface planarization process to form a third insulating layer, wherein an upper surface of the third insulating layer is higher than an upper surface of the gate dielectric layer;

[0027] forming a second patterned photoresist layer on the upper surface of the third insulating layer;

[0028] Using the second patterned photoresist layer as a mask, etching the third insulating layer, the gate dielectric layer, the semiconductor material layer and the source layer until the first insulating layer is exposed to form a plurality of source line cutting grooves, cutting the source layer into a plurality of source lines extending along a first direction and arranged at intervals along a second direction, each of the source lines connecting a row of the columns arranged along the first direction; the first direction and the second direction are both parallel to the plane where the first insulating layer is located, and the first direction intersects with the second direction;

[0029] Filling the source line cutting groove with insulating material and performing surface planarization to form a fourth insulating layer, wherein the upper surface of the fourth insulating layer is higher than the upper surface of the gate dielectric layer;

[0030] Etching back the fourth insulating layer to form a first etched back groove, wherein the bottom of the first etched back groove is higher than the upper surface of the lowermost side of the gate dielectric layer;

[0031] The gate structure is formed in the first etch-back groove.

[0032] Exemplarily, forming the gate structure in the first etch-back groove includes:

[0033] Filling the first back-etched groove with a gate material and performing surface planarization treatment to form a gate material layer;

[0034] Etching back the gate material layer to form a second etched back groove, wherein the bottom of the second etched back groove is lower than the upper surface of the drain portion;

[0035] Filling the second back-etched groove with insulating material and performing surface planarization treatment to form a fifth insulating layer;

[0036] forming a third patterned photoresist layer on the upper surface of the fifth insulating layer;

[0037] Using the third patterned photoresist layer as a mask, etching the fifth insulating layer and the gate material layer until the gate dielectric layer is exposed to form a plurality of word line cutting grooves, cutting the gate material layer into a plurality of word lines extending along the second direction and arranged at intervals along the first direction, each of the word lines connecting a row of the pillars arranged along the second direction; wherein the portion of the word line surrounding the gate dielectric layer on a side away from the pillars constitutes the gate structure;

[0038] The word line cutting groove is filled with insulating material, and the surface is planarized until the upper surface of the drain portion is exposed.

[0039] Exemplarily, the gate material layer includes a composite layer of a barrier layer and a gate metal layer;

[0040] The step of filling the first back-etching groove with a gate material to form a gate material layer includes:

[0041] Conformally depositing a layer of the barrier layer on the inner surface of the first back-etching groove and the uppermost surface of the gate dielectric layer;

[0042] Filling the remaining space of the first back-etched groove with a gate metal material and performing surface planarization treatment to form a gate metal layer, wherein the upper surface of the gate metal layer is higher than the uppermost surface of the barrier layer;

[0043] The etching back the gate material layer to form a second etching back groove comprises:

[0044] The barrier layer and the gate metal layer are etched back so that the uppermost surface of the barrier layer is flush with the upper surface of the gate metal layer and is lower than the upper surface of the drain portion.

[0045] Exemplarily, the barrier layer is a titanium nitride layer;

[0046] The gate metal layer is a tungsten layer.

[0047] Exemplarily, the gate dielectric layer includes a silicon dioxide layer and a silicon nitride layer sequentially and conformally covered on the semiconductor material layer.

[0048] Exemplarily, in the step of etching back the fourth insulating layer to form the first etched back groove, a non-plasma dry etching process is used to etch back the fourth insulating layer.

[0049] Exemplarily, the source layer includes a tungsten layer, a titanium nitride layer and a polysilicon layer sequentially deposited on the first insulating layer;

[0050] The material of the drain portion is polysilicon;

[0051] The material of the channel material layer is polysilicon.

[0052] According to a second aspect of the present invention, a semiconductor device is provided. The semiconductor device is manufactured by the manufacturing method described above.

[0053] According to the method for preparing a semiconductor device of the present invention, a plurality of drain portions are first formed on the upper portion of a second insulating layer located on the source layer, and then the second insulating layer is etched using the drain portion as a mask until the source layer is exposed, so as to form a plurality of columns arranged in an array on the upper surface of the source layer, and then a channel material layer surrounding the columnar body in a circumferential direction is formed, wherein the columnar body is formed by etching a single material layer of the second insulating layer, without involving multiple material layers, so that its circumferential surface can have a good flatness, and a straight channel material layer can be formed on its circumferential surface, thereby effectively improving the performance of the formed semiconductor device; in addition, the method for preparing a semiconductor device of the present invention first forms a channel material layer surrounding the columnar body in a circumferential direction, and then forms a gate dielectric layer and a gate structure, thereby avoiding the steps of etching to open the source layer and wet cleaning, and thus does not cause damage to the top oxide liner, the bottom oxide substrate and the gate oxide layer, and also avoids the step of depositing a protective film on the surface of the gate oxide layer, thereby simplifying the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The following drawings of the present application are hereby used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the device and principle of the present application. In the drawings,

[0055] Figure 1 is a schematic flow chart of a method for preparing a semiconductor device according to an embodiment of the present application;

[0056] Figure 2-Figure 16 Schematic diagram of a top view of a device in each step of a method for preparing a semiconductor device according to an embodiment of the present application;

[0057] Figure 17-Figure 28 They are Figure 2-Figure 13 A cross-sectional view at XX in the middle;

[0058] Figure 29-Figure 30 They are Figure 14-15 A schematic cross-sectional view at YY in the figure;

[0059] Figure 31-Figure 32 They are Fig.16 Schematic diagram of the cross-section at XX and YY in the figure.

[0060] Description of reference numerals:

[0061] 100-a first insulating layer, 110-a source layer, 111-a tungsten layer, 112-a titanium nitride layer, 113-a polysilicon layer, 120-a second insulating layer, 121-an insulating column, 130-a first patterned photoresist layer, 131-a circular opening, 140-a drain portion, 150-a columnar body, 160-a semiconductor material layer, 161-a channel material layer, 170-a gate dielectric layer, 171-a silicon dioxide layer, 172-a silicon nitride layer, 180-a third insulating layer, 190-a second patterned photoresist layer, 191-a strip-shaped groove, 200-a source line, 210-a fourth insulating layer, 220-a gate material layer, 221-a barrier layer, 222-a gate metal layer, 230-a fifth insulating layer, 240-a third patterned photoresist layer, 241-a strip-shaped groove, 250-a word line, 260-an insulating material;

[0062] 10 - second groove, 20 - first groove, 30 - source line cutting groove, 40 - first back etching groove, 50 - second back etching groove, 60 - word line cutting groove. DETAILED DESCRIPTION

[0063] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0064] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0065] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0066] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures.

[0067] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0068] Embodiments of the invention are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to display the actual shape of the device and are not intended to limit the scope of the present application.

[0069] See attached Figure 1-32 The method for manufacturing a semiconductor device according to an embodiment of the present application is exemplarily described. Figure 1 , the preparation method comprises the following steps:

[0070] S10: providing a semiconductor structure, the semiconductor structure comprising a first insulating layer, a source layer located on the first insulating layer, and a second insulating layer located on the source layer;

[0071] S20: forming a plurality of drain portions arranged in an array inlaid on the second insulating layer;

[0072] S30: using the plurality of drain portions as masks, etching the second insulating layer until the source layer is exposed, so as to form a plurality of columns arranged in an array on the upper surface of the source layer, wherein the columns include an insulating column located on the source layer and a drain portion located on the insulating column, and the plurality of columns are spaced apart from each other by first grooves formed by etching the second insulating layer;

[0073] S40: forming a channel material layer surrounding the columnar body in a circumferential direction;

[0074] S50: forming a gate dielectric layer and a gate structure on a side of the channel material layer away from the columnar body.

[0075] According to the method for preparing a semiconductor device of the present invention, a plurality of drain portions are first formed on the upper portion of a second insulating layer located on the source layer, and then the second insulating layer is etched using the drain portion as a mask until the source layer is exposed, so as to form a plurality of columns arranged in an array on the upper surface of the source layer, and then a channel material layer surrounding the columnar body in a circumferential direction is formed, wherein the columnar body is formed by etching a single material layer of the second insulating layer, without involving multiple material layers, so that its circumferential surface can have a good flatness, and a straight channel material layer can be formed on its circumferential surface, thereby effectively improving the performance of the formed semiconductor device; in addition, the method for preparing a semiconductor device of the present invention first forms a channel material layer surrounding the columnar body in a circumferential direction, and then forms a gate dielectric layer and a gate structure, thereby avoiding the steps of etching to open the source layer and wet cleaning, and thus does not cause damage to the top oxide liner, the bottom oxide substrate and the gate oxide layer, and also avoids the step of depositing a protective film on the surface of the gate oxide layer, thereby simplifying the process.

[0076] The following will refer to the attached Figure 2-32 Each step of a method for preparing a semiconductor device according to an embodiment of the present application is described in detail.

[0077] In step S10, see the attached Figure 2 , 17 (Attached Fig.17 For attachment Figure 2 XX in the cross-sectional schematic diagram), a semiconductor structure is provided, the semiconductor structure includes a first insulating layer 100, a source layer 110 located on the first insulating layer 100 and a second insulating layer 120 located on the source layer 110.

[0078] In this embodiment, the first insulating layer 100 and the second insulating layer 120 are both silicon dioxide layers, and the source layer 110 includes a tungsten layer 111 , a titanium nitride layer 112 , and a polysilicon layer 113 sequentially deposited on the first insulating layer 100 .

[0079] In step S20, first, see the attached Figure 3 , 18 (Attached Fig.18 For attachment Figure 3 XX in the figure), a first patterned photoresist layer 130 is formed on the upper surface of the second insulating layer 120. Specifically, a photoresist layer can be formed on the upper surface of the second insulating layer 120 by a process such as spin coating, and then the photoresist layer is patterned by photolithography process steps such as pre-baking, exposure, development, and hardening to form the first patterned photoresist layer 130. The first patterned photoresist layer 130 has a plurality of circular openings 131 arranged in an array.

[0080] Then, see Appendix Figure 4 , 19 (Attached Fig.19 For attachment Figure 4 XX in the figure), the second insulating layer 120 is etched with the first patterned photoresist layer 130 as a mask to form a plurality of second grooves 10 on the upper part of the second insulating layer 120. The depth of the second grooves 10 is much smaller than the thickness of the second insulating layer 120. The second grooves 10 correspond one to one with the drain portions 140, that is, each second groove 10 is used to form a drain portion 140 later. Afterwards, the first patterned photoresist layer 130 is removed, and the drain material is filled in the second grooves 10. Specifically, the first patterned photoresist layer 130 can be removed by wet degumming, plasma degumming or other degumming methods, and the drain material is filled in the second grooves 10 by a deposition process such as a CVD (Chemical Vapor Deposition) process, and the filled drain material fills the second grooves 10 and protrudes from the upper surface of the second insulating layer 120. Afterwards, the upper surface of the drain material is polished to be flush with the upper surface of the second insulating layer 120 by a chemical mechanical polishing (CMP) process to form a drain portion 140. A plurality of drain portions 140 are embedded in the upper portion of the second insulating layer 120 and arranged in an array in the upper portion of the second insulating layer 120. In this embodiment, the drain material is polysilicon, that is, the material of the formed drain portion 140 is polysilicon.

[0081] In step S30, see the attached Figure 5 , 20 (Attached Fig. 20 For attachment Figure 5 XX in the cross-sectional schematic diagram), using multiple drain portions 140 as masks, the second insulating layer 120 is etched by a dry etching process such as to expose the source layer 110, specifically, the polysilicon layer 113 in the source layer 110 is exposed, so as to form a plurality of columns 150 arranged in an array on the upper surface of the source layer 110. Among them, the column 150 includes an insulating column 121 located on the source layer 110 and a drain portion 140 located on the insulating column 121, and the insulating column 121 is formed by etching the remaining second insulating layer 120. The plurality of columns 150 arranged in an array are spaced apart from each other by the first groove 20 formed by etching the second insulating layer 120.

[0082] Since the etching processes in step S20 and step S30 only involve etching of a single material layer of the second insulating layer 120 and do not involve multiple material layers, the etching process and quality are easier to control, so that the circumferential surface of the columnar body 150 formed by etching can have better flatness.

[0083] In step S40, see the attached Figure 6 , 21 (Attached Fig.21 For attachment Figure 6 ), a semiconductor material layer 160 is deposited on the inner surface of the first trench 20 and the upper surface of the column 150. Specifically, the semiconductor material layer 160 can be deposited on the inner surface of the first trench 20 and the upper surface of the column 150 by a deposition process such as a CVD (Chemical Vapor Deposition) process, wherein a portion of the semiconductor material layer 160 surrounding the column 150 in the circumferential direction constitutes a channel material layer 161, and a portion of the semiconductor material layer 160 located on the upper surface of the column 150 achieves the same function as the drain portion 140, that is, as a drain of the semiconductor device. In this embodiment, the semiconductor material layer 160 is a polycrystalline silicon layer, that is, the material of the channel material layer 161 is polycrystalline silicon.

[0084] Since the circumferential surface of the columnar body 150 has good flatness, a straight channel material layer 161 can be formed on the circumferential surface of the columnar body 150 in step S40, thereby effectively improving the performance of the finally formed semiconductor device, for example, improving the breakdown voltage (Breakdown Voltage, V BD ), making semiconductor devices more reliable and safer.

[0085] Exemplarily, before step S40 (after step S30), the preparation method further includes the step of: pre-cleaning the first groove 20 and the column 150. Through the pre-cleaning treatment, the etching residues can be effectively removed, and the cleanliness of the surface of the first groove 20 and the column 150 can be improved, thereby effectively improving the deposition quality of the semiconductor material layer 160 in step S40.

[0086] Exemplarily, the pre-cleaning treatment includes: oxidation treatment of the damaged upper surface of the drain portion 140 when etching the second insulating layer 120 using the drain portion 140 as a mask, then removing the oxide formed on the upper surface of the drain portion 140 by a wet method or a dry method, and cleaning the first trench 20 at the same time. Exemplarily, a thinner oxide layer can be formed on the upper surface of the drain portion 140 by a thermal oxidation process, and then the upper surface of the drain portion 140 and the inner surface of the first trench 20 are cleaned by a wet cleaning process or a dry cleaning process to remove the oxide layer formed on the upper surface of the drain portion 140 and the etching residue on the inner surface of the first trench 20.

[0087] When the pre-cleaning process is performed before step S40, the channel material layer 161, the gate dielectric layer 170 and the gate structure are not formed, and the pre-cleaning process does not involve these structures and cannot damage them. There is no need to form a specific protective layer to protect the specific structure before the pre-cleaning process, and the process is simple. In the prior art, it is usually necessary to form a specific protective layer to protect the gate oxide layer to prevent it from being damaged during the etching process to open the source layer and the cleaning process. After the pre-cleaning, the protective layer must be removed again, and the process is complicated.

[0088] In step S50, first, see the attached Figure 7 , 22 (Attached Fig. 22 For attachment Figure 7 XX in the figure), a gate dielectric layer 170 conformingly covering the semiconductor material layer 160 is formed. In this embodiment, the gate dielectric layer 170 includes a silicon dioxide layer 171 and a silicon nitride layer 172 conformingly covering the semiconductor material layer 160. Specifically, a deposition process such as a CVD process can be used to first deposit a silicon dioxide layer 171 conformingly covering the semiconductor material layer 160, and then deposit a silicon nitride layer 172 conformingly covering the silicon dioxide layer 171.

[0089] Then, see Appendix Figure 8 , 23 (Attached Fig.23 For attachment Figure 8XX in the cross-sectional schematic diagram), the first trench 20 is filled with insulating material and the surface is flattened to form a third insulating layer 180, and the upper surface of the third insulating layer 180 is higher than the upper surface of the gate dielectric layer 170. Afterwards, a second patterned photoresist layer 190 is formed on the upper surface of the third insulating layer 180. In the present embodiment, the insulating material is silicon dioxide, and the third insulating layer 180 is a silicon dioxide layer. Specifically, when filling the first trench 20 with insulating material, TEOS (tetraethyl orthosilicate) can be used as a precursor and a CVD process is used. In the CVD process, TEOS is introduced into the reaction chamber as a precursor gas. Under certain temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reactions with other reaction gases to generate silicon dioxide deposited in the first trench 20 and on the gate dielectric layer 170 above the columnar body 150. TEOS is a relatively cheap precursor material, and the CVD process is relatively mature, and the equipment cost is relatively low, so it has obvious cost advantages. After the generated silicon dioxide fills the first trench 20, it is planarized by a CMP process to form a third insulating layer 180 whose upper surface is higher than the upper surface of the gate dielectric layer 170. Afterwards, a photoresist layer can be formed on the upper surface of the third insulating layer 180 by a process such as spin coating, and then the photoresist layer is patterned by photolithography process steps such as pre-baking, exposure, development, and hardening to form a second patterned photoresist layer 190. The second patterned photoresist layer 190 has a plurality of strip grooves 191 extending along the first direction and arranged at intervals along the second direction, and the projection of the strip grooves 191 in the first trench 20 is located between two adjacent rows of columnar bodies 150 (and the semiconductor material layer 160 and the gate dielectric layer 170 located on the circumferential surface thereof) extending and arranged along the first direction.

[0090] Then, see Appendix Fig. 9 , 24 (Attached Fig.24 For attachment Fig. 9 XX in the cross-sectional schematic diagram), using the second patterned photoresist layer 190 as a mask, the third insulating layer 180, the gate dielectric layer 170, the semiconductor material layer 160 and the source layer 110 are etched until the first insulating layer 100 is exposed to form a plurality of source line cutting grooves 30, and the source layer 110 is cut into a plurality of source lines 200 extending along the first direction and arranged at intervals along the second direction, and each source line 200 is connected to a row of columns 150 arranged along the first direction. The first direction and the second direction are both parallel to the plane where the first insulating layer 100 is located, and the first direction intersects with the second direction. In this embodiment, the first direction is Fig. 9 The up and down directions in the second direction are Fig. 9 In the left and right directions, the first direction intersects with the second direction perpendicularly. In some other embodiments, the angle formed by the first direction and the second direction ranges from 0° to 90°.

[0091] Then, see Appendix Fig.10 , 25 (Attached Fig.25 For attachment Fig.10 XX in the cross-sectional schematic diagram), the source line cutting groove 30 is filled with insulating material and the surface is flattened to form a fourth insulating layer 210, and the upper surface of the fourth insulating layer 210 is higher than the upper surface of the gate dielectric layer 170. In the present embodiment, the insulating material is silicon dioxide, and the fourth insulating layer 210 is a silicon dioxide layer. Specifically, when filling the source line cutting groove 30 with insulating material, silicon dioxide can be first deposited in the source line cutting groove 30 by an ALD (Atomic Layer Deposition) process. The ALD process is to alternately introduce different precursor gases into the reaction chamber, and chemical reactions occur on the surface of the source line cutting groove 30, thereby depositing a thin film layer by layer. For the ALD deposition of silicon dioxide, silicon-containing precursors (such as silane, tetraethoxysilane, etc.) and oxygen-containing precursors (such as oxygen, ozone, water, etc.) are usually used. The ALD process can uniformly deposit silicon dioxide in a groove with a high aspect ratio, but the deposition speed is slow. When the ALD process deposits silicon dioxide to cover the inner wall of the source line cutting groove 30 to a certain thickness, TEOS (tetraethyl orthosilicate) is used as a precursor to deposit silicon dioxide through a CVD process. The speed of silicon dioxide deposition by the CVD process is relatively fast. In the CVD process, TEOS is introduced into the reaction chamber as a precursor gas. Under certain temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reactions with other reaction gases to generate silicon dioxide deposited on the upper part of the silicon dioxide formed by the ALD process and the upper part of the third insulating layer 180 remaining after etching. TEOS is a relatively cheap precursor material, and the CVD process is relatively mature, and the equipment cost is relatively low, so it has obvious cost advantages. Afterwards, the deposited silicon dioxide is flattened by a CMP process to form a fourth insulating layer 210 whose upper surface is higher than the upper surface of the gate dielectric layer 170. By successively using the ALD process and the CVD process to form the fourth insulating layer 210, the formation quality, production speed and production cost of the fourth insulating layer 210 can be effectively taken into account.

[0092] Then, see Appendix Fig.11 , 26 (Attached Fig.26 For attachment Fig.11XX in the cross-sectional schematic diagram), the fourth insulating layer 210 is back-etched to form a first back-etched groove 40. The bottom of the first back-etched groove 40 is higher than the lowermost upper surface of the gate dielectric layer 170. The first back-etched groove 40 exposes the gate dielectric layer 170 located on the upper part of the column 150 and a portion of the gate dielectric layer 170 located on the circumference of the column 150. It should be noted that when the fourth insulating layer 210 is back-etched, the portion of the third insulating layer 180 remaining from the previous etching is also etched synchronously. Specifically, when the fourth insulating layer 210 is back-etched, a non-plasma dry etching process is used to back-etch the fourth insulating layer 210 to avoid plasma damage to the silicon nitride layer 172 in the gate dielectric layer 170. Exemplarily, the non-plasma dry etching process can be an etching process known to those skilled in the art, such as a chemical vapor reaction etching process.

[0093] Afterwards, a gate structure is formed in the first back-etching groove 40. Fig.12 , 27 (Attached Fig. 27 For attachment Fig.12 ), the gate material is filled into the first back-etched groove 40 and the surface is flattened to form a gate material layer 220. In the present embodiment, the gate material layer 220 includes a composite layer of a barrier layer 221 and a gate metal layer 222. The barrier layer may be a titanium nitride layer, and the gate metal layer may be a tungsten layer. Specifically, a barrier layer 221 is first conformally deposited on the inner surface of the first back-etched groove 40 and the upper surface of the uppermost side of the gate dielectric layer 170. Exemplarily, the barrier layer 221 may be deposited by a deposition process such as a CVD process or a PVD process; then, the gate metal material is filled into the remaining space of the first back-etched groove 40 and the surface is flattened to form a gate metal layer 222. The upper surface of the gate metal layer 222 is higher than the upper surface of the uppermost side of the barrier layer 221, that is, the gate metal layer 222 completely covers the barrier layer 221. For example, the gate metal material may be filled into the remaining space of the first back-etched groove 40 by a deposition process such as a PVD process, a magnetron sputtering process, or an electroplating process, and then the surface thereof may be planarized by a CMP process.

[0094] Then, see Appendix Fig.13 , 28 (Attached Fig.28 For attachment Fig.13XX in the cross-sectional schematic diagram), the gate material layer 220 is etched back to form a second etched back groove 50, wherein the bottom of the second etched back groove 50 is lower than the upper surface of the drain portion 140. The second etched back groove 50 at least exposes the gate dielectric layer 170 located on the upper part of the columnar body 150 and the gate dielectric layer 170 located in the circumferential direction of the drain portion 140. Specifically, the barrier layer 221 and the gate metal layer 222 are etched back so that the upper surface of the uppermost side of the barrier layer 221 is flush with the upper surface of the gate metal layer 222 and is lower than the upper surface of the drain portion 140. Exemplarily, the barrier layer 221 and the gate metal layer 222 can be etched back at the same time by a process such as a wet etching process.

[0095] Then, see Appendix Fig.14 , 29 (Attached Fig.29 For attachment Fig.14 ), the second back etch groove 50 is filled with insulating material and the surface is flattened to form a fifth insulating layer 230, and a third patterned photoresist layer 240 is formed on the upper surface of the fifth insulating layer 230. In the present embodiment, the insulating material is silicon dioxide, and the fifth insulating layer 230 is a silicon dioxide layer. Specifically, when the second back etch groove 50 is filled with insulating material, TEOS (tetraethyl orthosilicate) can be used as a precursor and a CVD process is used. In the CVD process, TEOS is introduced into the reaction chamber as a precursor gas. Under certain temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reactions with other reaction gases to generate silicon dioxide deposited in the second back etch groove 50 and on the upper surface of the uppermost side of the gate dielectric layer 170. TEOS is a relatively cheap precursor material, and the CVD process is relatively mature, and the equipment cost is relatively low, so it has obvious cost advantages. Afterwards, the filled silicon dioxide is planarized by a CMP process to form a fifth insulating layer 230 whose upper surface is higher than the upper surface of the gate dielectric layer 170. Afterwards, a photoresist layer can be formed on the upper surface of the fifth insulating layer 230 by a process such as spin coating, and then the photoresist layer is patterned by photolithography process steps such as pre-baking, exposure, development, and hardening to form a third patterned photoresist layer 240. The third patterned photoresist layer 240 has a plurality of strip grooves 241 extending along the second direction and arranged at intervals along the first direction, and the projection of the strip grooves 241 in the second groove 10 is located between two adjacent rows of columnar bodies 150 (and the semiconductor material layer 160, the gate dielectric layer 170, and a small portion of the gate material layer 220 located on the circumferential surface thereof) extending and arranged along the second direction.

[0096] Then, see Appendix Fig.15 , 30 (Attached Fig.30 For attachment Fig.15), using the third patterned photoresist layer 240 as a mask, the fifth insulating layer 230 and the gate material layer 220 are etched until the gate dielectric layer 170 is exposed to form a plurality of word line cutting grooves 60, and the gate material layer 220 is cut into a plurality of word lines 250 extending along the second direction and arranged in intervals along the first direction, each word line 250 is connected to a row of pillars 150 arranged in the second direction (the word line 250 is connected to the pillars 150 through the gate dielectric layer 170, that is, the word line 250 and the pillars 150 are spaced apart by the gate dielectric layer 170). Among them, part of the word line 250 surrounding the gate dielectric layer 170 away from the pillars 150 constitutes a gate structure.

[0097] Then, see Appendix Fig.16 , 31 、32(Attached Fig.31 For attachment Fig.16 Schematic diagram of the cross section at XX in the middle, attached Fig.32 For attachment Fig.16), the insulating material 260 is filled into the word line cutting groove 60, and the surface is planarized until the upper surface of the semiconductor material layer 160 is exposed. In the present embodiment, the insulating material 260 is silicon dioxide. Specifically, when the insulating material 260 is filled into the word line cutting groove 60, silicon dioxide can be first deposited in the word line cutting groove 60 by an ALD (Atomic Layer Deposition) process. The ALD process is to alternately introduce different precursor gases into the reaction chamber, and chemical reactions occur on the surface of the word line cutting groove 60, thereby depositing a thin film layer by layer. For the ALD deposition of silicon dioxide, silicon-containing precursors (such as silane, tetraethoxysilane, etc.) and oxygen-containing precursors (such as oxygen, ozone, water, etc.) are generally used. The ALD process can uniformly deposit silicon dioxide in a groove with a high aspect ratio, but the deposition rate is slow. When the ALD process deposits silicon dioxide to cover the inner wall of the word line cutting groove 60 to a certain thickness, TEOS (tetraethyl orthosilicate) is used as a precursor to deposit silicon dioxide through a CVD process. The speed of silicon dioxide deposition by the CVD process is relatively fast. In the CVD process, TEOS is introduced into the reaction chamber as a precursor gas. Under certain temperature and pressure conditions, TEOS undergoes thermal decomposition or chemical reactions with other reaction gases to generate silicon dioxide deposited on the upper part of the silicon dioxide formed by the ALD process and the upper part of the fifth insulating layer 230 remaining after etching. TEOS is a relatively cheap precursor material, and the CVD process is relatively mature, and the equipment cost is relatively low, so it has obvious cost advantages. Afterwards, the semiconductor material layer 160 is used as a grinding stop layer, and the filled silicon dioxide and the gate dielectric layer 170 are flattened by a CMP process until the upper surface of the semiconductor material layer 160 is exposed. By using the ALD process and the CVD process to fill the insulating material 260 in succession, the filling quality, production speed and production cost of the insulating material 260 can be effectively taken into account.

[0098] So far, the introduction of the relevant steps of the method for preparing the semiconductor device of the embodiment of the present application has been completed. After the above steps, other conventional steps for making the semiconductor device may also be included, which will not be repeated here. In addition, in addition to the above steps, the preparation method of this embodiment may also include other steps in the above steps or between different steps, and these steps can be implemented by various processes in the prior art, which will not be repeated here.

[0099] The present application also provides a semiconductor device, which is prepared by the preparation method described above. The semiconductor device provided by the present application can be applied to a memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and a flash memory. Of course, it can also be applied to other storage devices not listed, which are not listed here one by one.

[0100] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0101] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0102] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0103] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0104] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0105] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0106] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor structure, the semiconductor structure comprising a first insulating layer, a source layer located on the first insulating layer, and a second insulating layer located on the source layer; forming a plurality of drain portions arranged in an inlaid array on the upper portion of the second insulating layer; Using the plurality of drain portions as masks, etching the second insulating layer until the source layer is exposed, so as to form a plurality of columns arranged in an array on the upper surface of the source layer, wherein the columns include insulating columns located on the source layer and the drain portions located on the insulating columns, and the plurality of columns are spaced apart from each other by first grooves formed by etching the second insulating layer; forming a channel material layer circumferentially surrounding the columnar body; A gate dielectric layer and a gate structure are formed on a side of the channel material layer away from the columnar body.

2. The preparation method according to claim 1, characterized in that: The plurality of drain portions arranged in an array and inlaid on the upper portion of the second insulating layer include: forming a first patterned photoresist layer on the upper surface of the second insulating layer; Using the first patterned photoresist layer as a mask, etching the second insulating layer to form a plurality of second trenches on an upper portion of the second insulating layer, wherein the second trenches correspond to the drain portions one by one; removing the first patterned photoresist layer, and filling the second trench with a drain material; The upper surface of the drain electrode material is polished to be flush with the upper surface of the second insulating layer by a chemical mechanical polishing process to form the drain electrode portion.

3. The preparation method according to claim 1, characterized in that: The forming of a channel material layer circumferentially surrounding the columnar body comprises: Depositing a semiconductor material layer on the inner surface of the first trench and the upper surface of the columnar body; Wherein, a portion of the semiconductor material layer surrounding the columnar body in a circumferential direction constitutes the channel material layer.

4. The preparation method according to claim 3, characterized in that: Before forming the channel material layer surrounding the columnar body in a circumferential direction, the preparation method further includes: A pre-cleaning process is performed on the first groove and the column.

5. The preparation method according to claim 4, characterized in that: The pre-cleaning process of the first groove and the columnar body comprises: Oxidizing the upper surface of the drain portion that is damaged when etching the second insulating layer using the drain portion as a mask; The oxide formed on the upper surface of the drain portion is removed by a wet method or a dry method, and the first trench is cleaned at the same time.

6. The preparation method according to claim 3, characterized in that: The step of forming a gate dielectric layer and a gate structure on a side of the channel material layer away from the columnar body comprises: Forming the gate dielectric layer conformally covering the semiconductor material layer; Filling the first trench with an insulating material and performing a surface planarization process to form a third insulating layer, wherein an upper surface of the third insulating layer is higher than an upper surface of the gate dielectric layer; forming a second patterned photoresist layer on the upper surface of the third insulating layer; Using the second patterned photoresist layer as a mask, etching the third insulating layer, the gate dielectric layer, the semiconductor material layer and the source layer until the first insulating layer is exposed to form a plurality of source line cutting grooves, cutting the source layer into a plurality of source lines extending along a first direction and arranged at intervals along a second direction, each of the source lines connecting a row of the columns arranged along the first direction; the first direction and the second direction are both parallel to the plane where the first insulating layer is located, and the first direction intersects with the second direction; Filling the source line cutting groove with insulating material and performing surface planarization to form a fourth insulating layer, wherein the upper surface of the fourth insulating layer is higher than the upper surface of the gate dielectric layer; Etching back the fourth insulating layer to form a first etched back groove, wherein the bottom of the first etched back groove is higher than the upper surface of the lowermost side of the gate dielectric layer; The gate structure is formed in the first etch-back groove.

7. The preparation method according to claim 6, characterized in that: The forming of the gate structure in the first etch-back groove comprises: Filling the first etching groove with a gate material and performing surface planarization to form a gate material layer; Etching back the gate material layer to form a second etched back groove, wherein the bottom of the second etched back groove is lower than the upper surface of the drain portion; Filling the second back-etched groove with insulating material and performing surface planarization treatment to form a fifth insulating layer; forming a third patterned photoresist layer on the upper surface of the fifth insulating layer; Using the third patterned photoresist layer as a mask, etching the fifth insulating layer and the gate material layer until the gate dielectric layer is exposed to form a plurality of word line cutting grooves, cutting the gate material layer into a plurality of word lines extending along the second direction and arranged at intervals along the first direction, each of the word lines connecting a row of the pillars arranged along the second direction; wherein the portion of the word line surrounding the gate dielectric layer on a side away from the pillars constitutes the gate structure; The word line cutting groove is filled with insulating material, and the surface is planarized until the upper surface of the semiconductor material layer is exposed.

8. The preparation method according to claim 7, characterized in that: The gate material layer includes a composite layer of a barrier layer and a gate metal layer; The step of filling the first back-etching groove with a gate material to form a gate material layer includes: Conformally depositing a layer of the barrier layer on the inner surface of the first back-etching groove and the uppermost surface of the gate dielectric layer; Filling the remaining space of the first back-etched groove with a gate metal material and performing surface planarization treatment to form a gate metal layer, wherein the upper surface of the gate metal layer is higher than the uppermost surface of the barrier layer; The step of etching back the gate material layer to form a second etching back groove comprises: The barrier layer and the gate metal layer are etched back so that the uppermost surface of the barrier layer is flush with the upper surface of the gate metal layer and is lower than the upper surface of the drain portion.

9. The preparation method according to claim 8, characterized in that: The barrier layer is a titanium nitride layer; The gate metal layer is a tungsten layer.

10. The preparation method according to claim 6, characterized in that: The gate dielectric layer comprises a silicon dioxide layer and a silicon nitride layer which sequentially and conformally cover the semiconductor material layer.

11. The preparation method according to claim 10, characterized in that: In the step of etching back the fourth insulating layer to form a first etched back groove, a non-plasma dry etching process is used to etch back the fourth insulating layer.

12. The preparation method according to claim 1, characterized in that: The source layer comprises a tungsten layer, a titanium nitride layer and a polysilicon layer sequentially deposited on the first insulating layer; The material of the drain portion is polysilicon; The material of the channel material layer is polysilicon.

13. A semiconductor device, characterized in that: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 12.

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