Cellular structure and its fabrication method, metal-oxide-semiconductor field-effect transistor

Abstract

This application relates to a cellular structure and its fabrication method, and a metal-oxide-semiconductor field-effect transistor. The cellular structure includes: a current spreading layer; two well regions, each located on the side of the current spreading layer away from the epitaxial layer along a first direction, and separated by the current spreading layer along a second direction; two first injection regions, each located on the side of the corresponding well region away from the current spreading layer along the first direction, and separated by the current spreading layer along the second direction; a trench including a trench bottom and two opposing sidewalls, the trench bottom being located within the current spreading layer between the two well regions, and each sidewall being located within a corresponding portion of the well region and a corresponding first injection region; a gate oxide layer located within the trench; and a gate located within the gate oxide layer in the trench, the gate also being covered by the gate oxide layer; this cellular structure expands the well region to the gate corner, thereby reducing the electric field accumulation of the gate oxide layer at the bottom corner of the trench.

Description

Technical Field

[0001] This application relates to the field of power electronic device technology, and in particular to a cellular structure and its fabrication method, and a metal-oxide-semiconductor field-effect transistor. Background Technology

[0002] In the field of power electronics, silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) are considered the most mature and promising SiC power devices due to their high breakdown voltage, high switching speed, high thermal conductivity, low on-resistance, low switching loss, and low drive power. In high-voltage, low-power applications, vertical MOSFETs (VDMOS) are more commonly used. Common SiC VDMOS devices are mainly divided into two types: flat-gate MOSFETs and trench MOSFETs.

[0003] Flat-gate MOSFETs have been widely used in the automotive and photovoltaic industries. Although the fabrication process of flat-gate MOSFETs is mature and the devices have high reliability, the problems with flat-gate MOSFETs include: 1) rough SiC / SiO2 interface with many defects; 2) the channel uses the 4H-SiC (0001) crystal plane with low mobility.

[0004] Trench MOSFETs, because their channels are located on the sidewalls and perpendicular to the device surface, achieve a significant increase in mobility through different channel crystal planes. They also eliminate the JFET region resistance of planar MOSFETs, further reducing on-resistance and interface losses. However, trench MOSFETs are prone to electric field accumulation at the corners of the gate trench, which can easily break down the thin gate oxide layer at the trench corners, causing gate-source conduction and reducing the reliability of the trench MOSFET. Summary of the Invention

[0005] Therefore, it is necessary to provide a cell structure and its fabrication method that can improve the reliability of trench MOSFETs and metal-oxide-semiconductor field-effect transistors, addressing the aforementioned technical problems.

[0006] In a first aspect, this application provides a cellular structure, comprising:

[0007] Substrate;

[0008] An epitaxial layer is located on one side of the substrate;

[0009] A current spreading layer is located on the side of the epitaxial layer away from the substrate;

[0010] Two well regions are provided, with each well region located on the side of the current spreading layer away from the epitaxial layer along a first direction, and the two well regions being separated by the current spreading layer along a second direction.

[0011] Two first injection regions are located along a first direction, with each first injection region situated on the side of the corresponding well region away from the current spreading layer. Along a second direction, the two first injection regions are separated by the current spreading layer.

[0012] Two second injection regions are provided. Along the first direction, each second injection region is located on the side of the current spreading layer away from the epitaxial layer. Along the second direction, each second injection region is located on the side of the corresponding well region and the first injection region away from the current spreading layer.

[0013] The trench includes a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region. The trench bottom is located within the current spreading layer between the two well regions and the two well regions. Each sidewall is located within a corresponding portion of the well region and a corresponding portion of the first injection region.

[0014] A gate oxide layer is located within the trench;

[0015] A gate, located within the trench, wherein the gate is further covered by the gate oxide layer;

[0016] The first direction is perpendicular to the substrate, and the second direction is parallel to the plane of the substrate.

[0017] The trench of the aforementioned cell structure includes a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region. The trench bottom is located within the two well regions and the current spreading layer between the two well regions. Each of the sidewalls is located within a corresponding portion of the well region and a corresponding first injection region. The gate oxide layer of this cell structure is located within the trench and covers the trench bottom and the two sidewalls. The gate of this cell structure is located within the trench and covers the gate oxide layer. Thus, this cell structure expands the well region to the gate corner, thereby reducing the electric field accumulation of the gate oxide layer at the bottom corner of the trench, in the reverse direction... Under bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is modulated by the well region in an L-shape, thereby preventing the gate oxide electric field at the corner of the gate channel from reaching its peak and breaking down the gate oxide. This improves the reliability of the trench MOSFET device in this embodiment. At the same time, by forming a current spreading layer (CSL) by ion implantation under the trench, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect. Therefore, the on-resistance is greatly reduced and the loss is reduced.

[0018] In one embodiment, it further includes:

[0019] A gate dielectric layer is located on the side of the gate away from the current spreading layer and covers a portion of each of the first injection regions;

[0020] The source electrode is located on the side of the gate dielectric layer away from the gate and covers each of the second injection regions and each of the exposed first injection regions;

[0021] The drain electrode is located on the side of the substrate away from the epitaxial layer.

[0022] In one embodiment, the ion implantation type of the current spreading layer is N-type.

[0023] In one embodiment, the ion implantation type of the trap region is P-type.

[0024] In one embodiment, the ion implantation type of the first implantation region is N-type, and the ion implantation type of the second implantation region is P-type.

[0025] Secondly, this application also provides a metal-oxide-semiconductor field-effect transistor, including the cell structure provided in the first aspect above.

[0026] Thirdly, this application also provides a method for preparing a cellular structure, comprising:

[0027] Provide substrate;

[0028] An epitaxial layer is formed on one side of the substrate;

[0029] A current spreading layer is formed on the side of the epitaxial layer away from the substrate;

[0030] Two well regions are formed. In a first direction, each well region is located on the side of the current spreading layer away from the epitaxial layer. In a second direction, the two well regions are separated by the current spreading layer.

[0031] Two first injection regions are formed. Along a first direction, each first injection region is located on the side of the corresponding well region away from the current spreading layer. Along a second direction, the two first injection regions are separated by the current spreading layer.

[0032] Two second injection regions are formed. Along the first direction, each second injection region is located on the side of the current spreading layer away from the epitaxial layer. Along the second direction, each second injection region is located on the side of the corresponding well region and the first injection region away from the current spreading layer.

[0033] A trench is formed, including a trench bottom and two opposing sidewalls in a direction from the second injection region to the first injection region. The trench bottom is located within the current spreading layer between the two well regions and the two well regions. Each sidewall is located within a corresponding portion of the well region and a corresponding portion of the first injection region.

[0034] A gate oxide layer and a gate are formed, wherein the gate oxide layer is located within the trench, and the gate is located within the gate oxide layer in the trench and is also covered by the gate oxide layer;

[0035] The first direction is perpendicular to the substrate, and the second direction is parallel to the plane of the substrate.

[0036] In one embodiment, forming the trench includes:

[0037] The trenches were etched using plasma etching.

[0038] In one embodiment, forming the gate oxide layer includes:

[0039] The gate oxide layer is formed using a dry oxidation process.

[0040] In one embodiment, forming the gate includes:

[0041] Polysilicon is deposited and ion implanted into the polysilicon to form a gate.

[0042] The aforementioned cell structure and its fabrication method, and metal-oxide-semiconductor field-effect transistor, wherein the cell structure can be a cell structure of a metal-oxide-semiconductor field-effect transistor; an epitaxial layer and a current spreading layer are sequentially disposed on the substrate of the cell structure; along the direction perpendicular to the substrate, each of the two well regions is located on the side of the current spreading layer away from the epitaxial layer, and the two well regions are separated by the current spreading layer along the direction parallel to the plane of the substrate; along the direction perpendicular to the substrate, each of the two first injection regions is located on the side of the corresponding well region away from the current spreading layer, and the two first injection regions are separated by the current spreading layer along the direction parallel to the plane of the substrate; along the direction perpendicular to the substrate, each of the two second injection regions is located on the side of the current spreading layer away from the epitaxial layer, and along the direction parallel to the plane of the substrate, each second injection region is located on the side of the corresponding well region and the first injection region away from the current spreading layer.

[0043] Based on this, the trench of the cell structure includes a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region. The trench bottom is located within the current spreading layer between the two well regions. Each of the sidewalls is located within a corresponding portion of the well region and a corresponding first injection region. The gate oxide layer of the cell structure is located within the trench, and the gate of the cell structure is located within the gate oxide layer in the trench, wherein the gate is also covered by the gate oxide layer. In this way, the cell structure expands the well region to the gate corner, thereby reducing the electric field accumulation of the gate oxide layer at the bottom corner of the trench. Under reverse bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is modulated in an L-shape by the well region, thereby preventing the gate oxide electric field at the corner of the gate channel from reaching its peak and breaking down the gate oxide. This improves the reliability of the trench MOSFET device in this embodiment. At the same time, by forming a current spreading layer (CSL) by ion implantation under the trench, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect. Therefore, the on-resistance is greatly reduced and the loss is reduced. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is one of the schematic diagrams of the cell structure in one embodiment;

[0046] Figure 2 This is a second schematic diagram of the cell structure in one embodiment;

[0047] Figure 3 This is a schematic flowchart of a method for preparing a cellular structure in one embodiment. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0050] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0051] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0052] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0054] The cell structure provided in this application embodiment can be used to construct metal-oxide-semiconductor field-effect transistors, for example, it can be used to construct SiC trench MOSFETs.

[0055] In one exemplary embodiment, reference Figure 1 A cellular structure is provided, comprising a substrate 110, an epitaxial layer 120, a current spreading layer 130, two well regions 140, two first implantation regions 150, two second implantation regions 160, a trench, a gate oxide layer 170, and a gate 180. The epitaxial layer 120 is located on one side of the substrate 110. The current spreading layer 130 is located on the side of the epitaxial layer 120 away from the substrate 110.

[0056] Along a first direction, each well region 140 is located on the side of the current spread layer 130 away from the epitaxial layer 120. Along a second direction, two well regions 140 are separated by the current spread layer 130. Along the first direction, each first injection region 150 is located on the side of its corresponding well region 140 away from the current spread layer 130. Along the second direction, two first injection regions 150 are separated by the current spread layer 130. Along the first direction, each second injection region 160 is located on the side of the current spread layer 130 away from the epitaxial layer 120. Along the second direction, each second injection region 160 is located on the side of its corresponding well region 140 and first injection region 150 away from the current spread layer 130.

[0057] The trench includes a bottom and two opposing sidewalls along the direction from the second injection region 160 to the first injection region 150. The bottom is located within the two well regions 140 and the current spreading layer 130 between the two well regions 140. Each sidewall is located within a corresponding portion of the well region 140 and a corresponding portion of the first injection region 150. A gate oxide layer 170 is located within the trench. A gate 180 is located within the gate oxide layer 170 in the trench, and the gate 180 is also covered by the gate oxide layer 170. The first direction is perpendicular to the substrate 110, and the second direction is parallel to the plane of the substrate 110.

[0058] The substrate 110 can be made of SiC. Compared to traditional silicon (Si) materials, SiC has advantages such as a wider bandgap, higher critical breakdown electric field, higher saturation drift velocity, and higher thermal conductivity, making it an ideal material for fabricating high-voltage, high-power devices. It is widely used in high-efficiency, high-power, and high-temperature power electronics technologies and has become a research hotspot in current power semiconductor technology. Power MOSFET devices fabricated based on SiC have advantages such as high current density, high breakdown voltage, low loss, good high-temperature characteristics, and radiation resistance. Compared to traditional Si-based power MOSFET devices, they can simplify the topology of power electronic systems, reduce system size, and lower power losses. For example, the substrate 110 is an N-type doped silicon carbide substrate 110.

[0059] The epitaxial layer 120 can be made of silicon carbide, and the doping type of the epitaxial layer 120 includes N-type doping. The epitaxial layer 120 can be grown on one side of the substrate 110, and then ion implantation is performed on the epitaxial layer 120 to form a current spreading layer 130 (CSL), two well regions 140, and two first implantation regions 150 in sequence. Then, a trench is etched on the epitaxial layer 120 using a plasma etching method, so that the corners at both ends of the trench are located inside the well region 140. Then, a gate oxide layer 170 is formed inside the trench by dry oxidation, and polysilicon is deposited inside. Ion implantation is performed on the polysilicon to form a cell-structured gate 180. Then, ion implantation is performed to form two second implantation regions 160.

[0060] In this embodiment, the cell structure extends the well region 140 to the corner of the gate 180, thereby reducing the electric field accumulation of the gate oxide layer 170 at the bottom corner of the trench. Under reverse bias, when the source-drain voltage is increased, the well region 140 at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is modulated by the L-shaped well region 140, thereby preventing the electric field of the gate oxide layer 170 at the corner of the gate 180 channel from reaching its peak and breaking down the gate oxide layer 170. This embodiment improves the reliability of the trench MOSFET device. At the same time, by forming an N-type current extension layer 130CSL under the trench, the current path in the vertical direction of the forward conduction path of the two well regions 140 is prevented from being cut off, thereby eliminating the JEFT effect. Therefore, the on-resistance is greatly reduced and the loss is reduced.

[0061] In one exemplary embodiment, reference is made to Figure 2 The cell structure further includes a gate dielectric layer 190, a source electrode 200, and a drain electrode 210. The gate dielectric layer 190 is located on the side of the gate 180 away from the current spreading layer 130 and covers portions of each of the first implantation regions 150. SiO2 and Si3N4 may be further deposited on the polysilicon surface to form a dielectric layer above the gate 180. The source electrode 200 is located on the side of the gate dielectric layer 190 away from the gate 180 and covers each of the second implantation regions 160 and the exposed portions of each of the first implantation regions 150. The drain electrode 210 is located on the side of the substrate 110 away from the epitaxial layer 120.

[0062] In one exemplary embodiment, the ion implantation type of the current spreading layer 130 is N-type.

[0063] In one exemplary embodiment, the ion implantation type of the well region 140 is P-type.

[0064] In an exemplary embodiment, the ion implantation type of the first implantation region 150 is N-type, and the ion implantation type of the second implantation region 160 is P-type.

[0065] In one exemplary embodiment, a metal-oxide-semiconductor field-effect transistor is also provided, which includes the cell structure provided in any of the above embodiments.

[0066] The metal-oxide-semiconductor field-effect transistor and cell structure provided in this application belong to the same inventive concept, can solve the same technical problem, and thus achieve the same technical effect. Specifically, the trench of the cell structure includes a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region. The trench bottom is located within the two well regions and the current spreading layer between the two well regions. Each sidewall is located within a corresponding portion of the well region and a corresponding first injection region. The gate oxide layer of the cell structure is located within the trench and covers the trench bottom and the two sidewalls. The gate of the cell structure is located within the trench and covers the gate oxide layer. Thus, the cell structure [contains] the well regions... The electric field is extended to the gate corner, thereby reducing the electric field accumulation of the gate oxide layer at the bottom corner of the trench. Under reverse bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is modulated by the well region in an L-shape, thereby preventing the electric field of the gate oxide layer at the corner of the gate channel from reaching the peak and breaking down the gate oxide layer. This improves the reliability of the trench MOSFET device in this embodiment. At the same time, by forming a current spreading layer (CSL) by ion implantation under the trench, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect. Therefore, the on-resistance is greatly reduced and the loss is reduced.

[0067] In one exemplary embodiment, reference is made to Figure 3 Furthermore, a method for preparing a cellular structure is provided, which can be used to prepare the cellular structure provided in any of the above embodiments. The method includes:

[0068] S301 provides a substrate.

[0069] S302, forming an epitaxial layer located on one side of the substrate.

[0070] S303, forming a current spreading layer, located on the side of the epitaxial layer away from the substrate.

[0071] S304, forming two well regions, each of which is located on the side of the current spreading layer away from the epitaxial layer along a first direction, and the two well regions are separated by the current spreading layer along a second direction.

[0072] S305, two first injection regions are formed. Along a first direction, each first injection region is located on the side of the corresponding well region away from the current spreading layer. Along a second direction, the two first injection regions are separated by the current spreading layer.

[0073] S306, forming two second injection regions. Along the first direction, each second injection region is located on the side of the current spreading layer away from the epitaxial layer. Along the second direction, each second injection region is located on the side of the corresponding well region and the first injection region away from the current spreading layer.

[0074] S307, forming a trench including a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region, the trench bottom being located within the current spreading layer within the two well regions and between the two well regions, and each of the sidewalls being located within a corresponding portion of the well region and a corresponding portion of the first injection region.

[0075] refer to Figure 1 The epitaxial layer 120 can be made of silicon carbide, and the doping type of the epitaxial layer 120 includes N-type doping. The epitaxial layer 120 can be grown on one side of the substrate 110, and then ion implantation is performed on the epitaxial layer 120 to form a current spreading layer 130 (CSL), two well regions 140, and two first implantation regions 150 in sequence. Then, a trench is etched on the epitaxial layer 120 using a plasma etching method, so that the corners at both ends of the trench are located inside the well region 140. Then, a gate oxide layer 170 is formed inside the trench by dry oxidation, and polysilicon is deposited inside. Ion implantation is performed on the polysilicon to form a cell-structured gate 180. Then, ion implantation is performed to form two second implantation regions 160.

[0076] S308, forming a gate oxide layer located within the trench and covering the trench bottom and the sidewalls.

[0077] S309, forming a gate located within the trench and covering the gate oxide layer.

[0078] The first direction is perpendicular to the substrate, and the second direction is parallel to the plane of the substrate.

[0079] In this embodiment, steps S308 and S309 can be understood as: forming a gate oxide layer and a gate, wherein the gate oxide layer is located within a trench, the gate is located within the gate oxide layer in the trench, and the gate is also covered by the gate oxide layer. Exemplarily, the gate oxide layer may wrap around the gate. Exemplarily, the gate oxide layer may first be formed within the trench, then the gate may be formed on the gate oxide layer within the trench, and then another gate oxide layer may be formed on the gate to cover the gate.

[0080] The cell structure fabrication method and cell structure provided in this application belong to the same inventive concept, can solve the same technical problem, and thus achieve the same technical effect. Specifically, the trench of the cell structure includes a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region. The trench bottom is located within the two well regions and the current spreading layer between the two well regions. Each sidewall is located within a corresponding portion of the well region and a corresponding first injection region. The gate oxide layer of the cell structure is located within the trench and covers the trench bottom and the two sidewalls. The gate of the cell structure is located within the trench and covers the gate oxide layer. Thus, the cell structure expands the well regions. By reducing the electric field accumulation of the gate oxide layer at the gate corner, under reverse bias, the well region at the bottom corner of the trench is depleted when the source-drain voltage is increased. The electric field distribution at the bottom of the trench is modulated by the well region in an L-shape, thereby preventing the gate oxide layer electric field at the corner of the gate channel from reaching its peak and breaking down the gate oxide layer. This improves the reliability of the trench MOSFET device in this embodiment. At the same time, by forming a current spreading layer (CSL) by ion implantation under the trench, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect. Therefore, the on-resistance is greatly reduced and the loss is reduced.

[0081] In one exemplary embodiment, forming the trench includes etching the trench using a plasma etching process.

[0082] In this embodiment, the trenches are etched using plasma etching, which makes the process of forming the trenches simple and low-cost.

[0083] In one exemplary embodiment, forming the gate oxide layer includes forming the gate oxide layer using a dry oxidation process.

[0084] In this embodiment, a dry oxidation process is used to form the gate oxide layer, which makes the process of forming the gate oxide layer simple and low-cost.

[0085] In one exemplary embodiment, forming the gate includes: depositing polysilicon and ion implanting the polysilicon to form the gate.

[0086] The cellular structure and its fabrication method, and the metal-oxide-semiconductor field-effect transistor provided in this application embodiment, wherein the cellular structure can be the cellular structure of a metal-oxide-semiconductor field-effect transistor; an epitaxial layer and a current spreading layer are sequentially disposed on the substrate of the cellular structure; along the direction perpendicular to the substrate, each of the two well regions is located on the side of the current spreading layer away from the epitaxial layer, and along the direction parallel to the plane of the substrate, the two well regions are separated by the current spreading layer; along the direction perpendicular to the substrate, each of the two first injection regions is located on the side of the corresponding well region away from the current spreading layer, and along the direction parallel to the plane of the substrate, the two first injection regions are separated by the current spreading layer; along the direction perpendicular to the substrate, each of the two second injection regions is located on the side of the current spreading layer away from the epitaxial layer, and along the direction parallel to the plane of the substrate, each second injection region is located on the side of the corresponding well region and the first injection region away from the current spreading layer;

[0087] Based on this, the trench of the cell structure includes a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region. The trench bottom is located within the two well regions and the current spreading layer between the two well regions. Each of the sidewalls is located within a corresponding portion of the well region and a corresponding first injection region. The gate oxide layer of the cell structure is located within the trench and covers the trench bottom and the two sidewalls. The gate of the cell structure is located within the trench and covers the gate oxide layer. In this way, the cell structure expands the well region to the gate corner, thereby reducing the electric field accumulation of the gate oxide layer at the bottom corner of the trench. Under reverse bias, when the source-drain voltage is increased, the well region at the bottom corner of the trench is depleted, and the electric field distribution at the bottom of the trench is modulated in an L-shape by the well region, thereby preventing the gate oxide electric field at the corner of the gate channel from reaching its peak and breaking down the gate oxide. This improves the reliability of the trench MOSFET device in this embodiment. At the same time, by forming a current spreading layer (CSL) by ion implantation under the trench, the current path in the vertical direction of the forward conduction path of the two well regions is prevented from being cut off, thereby eliminating the JEFT effect. Therefore, the on-resistance is greatly reduced and the loss is reduced.

[0088] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0090] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A cellular structure, characterized in that, include: Substrate; An epitaxial layer is located on one side of the substrate; A current spreading layer is located on the side of the epitaxial layer away from the substrate; Two well regions are provided, with each well region located on the side of the current spreading layer away from the epitaxial layer along a first direction, and the two well regions being separated by the current spreading layer along a second direction. Two first injection regions are located along a first direction, with each first injection region situated on the side of the corresponding well region away from the current spreading layer. Along a second direction, the two first injection regions are separated by the current spreading layer. Two second injection regions are provided. Along the first direction, each second injection region is located on the side of the current spreading layer away from the epitaxial layer. Along the second direction, each second injection region is located on the side of the corresponding well region and the first injection region away from the current spreading layer. The trench includes a trench bottom and two opposing sidewalls along the direction from the second injection region to the first injection region. The trench bottom is located within the current spreading layer between the two well regions and the two well regions. Each sidewall is located within a corresponding portion of the well region and a corresponding portion of the first injection region. A gate oxide layer is located within the trench; A gate, located within the trench, wherein the gate is further covered by the gate oxide layer; Wherein, the first direction is perpendicular to the substrate, and the second direction is parallel to the plane where the substrate is located; The ion implantation type of the current spreading layer is N-type; The ion implantation type in the trap region is P-type; The ion implantation type of the first implantation region is N-type, and the ion implantation type of the second implantation region is P-type.

2. The cellular structure according to claim 1, characterized in that, Also includes: A gate dielectric layer is located on the side of the gate away from the current spreading layer and covers a portion of each of the first injection regions; The source electrode is located on the side of the gate dielectric layer away from the gate and covers each of the second injection regions and each of the exposed first injection regions; The drain electrode is located on the side of the substrate away from the epitaxial layer.

3. A metal-oxide-semiconductor field-effect transistor, characterized in that, Includes the cellular structure as described in claim 1 or 2.

4. A method for preparing a cellular structure, characterized in that, include: Provide substrate; An epitaxial layer is formed on one side of the substrate; A current spreading layer is formed on the side of the epitaxial layer away from the substrate; Two well regions are formed. In a first direction, each well region is located on the side of the current spreading layer away from the epitaxial layer. In a second direction, the two well regions are separated by the current spreading layer. Two first injection regions are formed. Along a first direction, each first injection region is located on the side of the corresponding well region away from the current spreading layer. Along a second direction, the two first injection regions are separated by the current spreading layer. Two second injection regions are formed. Along the first direction, each second injection region is located on the side of the current spreading layer away from the epitaxial layer. Along the second direction, each second injection region is located on the side of the corresponding well region and the first injection region away from the current spreading layer. A trench is formed, including a trench bottom and two opposing sidewalls in a direction from the second injection region to the first injection region. The trench bottom is located within the current spreading layer between the two well regions and the two well regions. Each sidewall is located within a corresponding portion of the well region and a corresponding portion of the first injection region. A gate oxide layer and a gate are formed, wherein the gate oxide layer is located within the trench, and the gate is located within the gate oxide layer in the trench and is also covered by the gate oxide layer; The first direction is perpendicular to the substrate, and the second direction is parallel to the plane of the substrate.

5. The method for preparing the cellular structure according to claim 4, characterized in that, The formation of the trench includes: The trenches were etched using plasma etching.

6. The method for preparing the cellular structure according to any one of claims 4-5, characterized in that, The formation of the gate oxide layer includes: The gate oxide layer is formed using a dry oxidation process.

7. The method for preparing the cellular structure according to any one of claims 4-5, characterized in that, The formation of the gate includes: Polysilicon is deposited and ion implanted into the polysilicon to form a gate.

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