Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a channel layer, a gate dielectric layer and a gate; the substrate comprises a step area; the channel layer covers the surface of the step region in a conformal manner; the gate dielectric layer is located on the surface of the channel layer; the gate is located on the surface of the gate dielectric layer away from the substrate. According to the semiconductor structure, the substrate is provided with the step area, the channel layer is covered on the surface of the step area in a shape follow-up mode, the length of the channel layer is increased, the short channel effect can be effectively solved, meanwhile, size miniaturization of the semiconductor structure is not affected, and the yield of the semiconductor structure is increased only by adjusting the size of the step area on the substrate or the number of steps. And the channel layers with different channel lengths can be obtained. Through the channel layer, the gate dielectric layer located on the surface of the channel layer and the gate located on the surface of the gate dielectric layer, the contact area between the gate structure and the channel layer can be increased, and the control capability of the gate is enhanced, so that the influence of a drain barrier reduction effect is weakened, and the electrical performance of the device is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] In the field of integrated circuit design and manufacturing technology, methods for increasing device integration usually include reducing the feature size of semiconductor devices or improving the semiconductor unit structure.

[0003] As the characteristic size of semiconductor devices decreases, the channel length of the device also shortens, resulting in a shorter and shorter distance between the source and drain of the semiconductor device, and a worse control ability of the gate over the channel. This means that it becomes more difficult for the gate voltage to pinch off the channel, resulting in subthreshold leakage, also known as the short channel effect. Therefore, how to effectively solve the short channel effect has become an urgent problem to be solved. Summary of the invention

[0004] Based on this, the present disclosure provides a semiconductor structure and a method for preparing the same, which can at least effectively solve the short channel effect.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a semiconductor structure, which includes a substrate, a channel layer, a gate dielectric layer and a gate; the substrate includes a step region; the channel layer conformally covers the surface of at least part of the step region; the gate dielectric layer is located on the surface of the channel layer; and the gate is located on the surface of the gate dielectric layer away from the substrate.

[0006] In the semiconductor structure of the above embodiment, the substrate has a step region, and the length of the channel layer is extended by conformally covering the surface of the step region, which can effectively solve the short channel effect, and at the same time does not affect the size miniaturization of the semiconductor structure. Only by adjusting the size of the step region on the substrate or the number of steps, a channel layer with different channel lengths can be obtained. And through the gate dielectric layer located on the surface of the channel layer and the gate located on the surface of the gate dielectric layer, the contact area between the gate structure and the channel layer can be increased, and the control ability of the gate is enhanced, thereby weakening the influence of the drain barrier lowering effect (Drain Induced Barrier Lowering, DIBL) to optimize the electrical performance of the device.

[0007] In some embodiments, it also includes a source electrode, a gate electrode and a drain electrode; the source electrode and the drain electrode are both located on the exposed surface of the channel layer; the gate electrode is located on the surface of the gate away from the gate dielectric layer and is located between the source electrode and the drain electrode.

[0008] In some embodiments, the substrate includes a platform structure, and a sidewall of the platform structure includes a step region; the channel layer covers a surface of the sidewall of the platform structure and a surface of the substrate.

[0009] In some embodiments, the sidewall of the boss structure includes a multi-step region.

[0010] In some embodiments, a groove is formed in the substrate, and a sidewall of the groove includes a step region; the channel layer covers the sidewall of the groove, the bottom of the groove, and the surface of the substrate.

[0011] In some embodiments, the substrate includes a plurality of step regions in a stair-like shape.

[0012] According to some embodiments, another aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0013] providing a substrate;

[0014] etching the substrate to form a step region;

[0015] forming a channel layer, wherein the channel layer conformally covers the surface of the step region;

[0016] A gate dielectric layer is formed on the surface of the channel layer, and a gate is formed on the surface of the gate dielectric layer away from the channel layer.

[0017] In the method for preparing the semiconductor structure of the above embodiment, the substrate is etched to have a step region, and then a channel layer is formed to conformally cover the surface of the step region, thereby extending the length of the channel layer, which can effectively solve the short channel effect, and does not affect the size miniaturization of the semiconductor structure. Only by adjusting the morphology of the etched substrate, such as the step depth, that is, adjusting the size of the step region or the number of steps, a channel layer with different channel lengths can be obtained. In addition, by forming a gate dielectric layer located on the surface of the channel layer and forming a gate located on the surface of the gate dielectric layer, the control ability of the gate is enhanced, the contact area between the gate structure and the channel layer can be increased, and the control ability of the gate is enhanced, thereby weakening the influence of the drain induced barrier lowering effect (DIBL) to optimize the electrical performance of the device, and electrical connection can be achieved in a one-time process of forming the gate, simplifying the process flow.

[0018] In some embodiments, a gate dielectric layer is formed on a surface of the channel layer, and a gate is formed on a surface of the gate dielectric layer away from the channel layer, including: forming a gate dielectric material layer on a surface of the channel layer; forming a gate material layer on a surface of the gate dielectric material layer away from the channel layer; etching the gate material layer and the gate dielectric material layer to expose a portion of the surface of the channel layer, and obtaining the gate dielectric layer and the gate;

[0019] After forming a gate dielectric layer on the surface of the channel layer and forming a gate on the surface of the gate dielectric layer away from the channel layer, it also includes: forming a source electrode, a drain electrode and a gate electrode; the source electrode and the drain electrode are both located on the exposed surface of the channel layer; the gate electrode is located on the surface of the gate dielectric layer and between the source electrode and the drain electrode.

[0020] In some embodiments, etching the substrate to form a step region includes: etching the substrate to form a platform structure, wherein a sidewall of the platform structure includes the step region; and a channel layer covers the sidewall of the platform structure and a surface of the substrate.

[0021] In some embodiments, the sidewall of the boss structure includes a multi-step region.

[0022] In some embodiments, etching the substrate to form a step region includes: etching the substrate to form a groove in the substrate, and the sidewall surface of the groove has a step region; the channel layer covers the sidewall of the groove, the bottom of the groove and the surface of the substrate.

[0023] In some embodiments, etching the substrate to form a step region includes: etching the substrate to form a multi-step region in a stair-like shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a relationship curve between the gate voltage Vg and the drain current Id of the transistor;

[0026] Figure 2 (a) is a curve showing the subthreshold swing SS changing with the channel length L; (b) is a curve showing the threshold voltage Vth changing with the channel length L; (c) is a curve showing the drain induced barrier lowering effect DIBL changing with the channel length L; (d) is a curve showing the turn-on current Ion changing with the channel length L;

[0027] Figure 3 A schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure;

[0028] Figure 4 A schematic cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure;

[0029] Figure 5 A cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0030] Figure 6 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0031] Figure 7 A schematic cross-sectional view of a structure obtained in step S20 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0032] Figure 8 It is a schematic cross-sectional view of a structure obtained in step S412 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0033] Fig. 9 A schematic cross-sectional view of a structure obtained in step S414 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0034] Fig.10 It is a schematic cross-sectional view of a structure obtained in step S60, step S81 and step S82 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0035] Fig.11 It is a schematic cross-sectional view of a structure obtained in step S83 in a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0036] Fig.12 It is a schematic cross-sectional view of a structure obtained in step S90 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0037] Fig.13 It is a schematic cross-sectional view of a structure obtained in step S42 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0038] Fig.14 It is a cross-sectional schematic diagram of a structure obtained in step S60 and step S81 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0039] Fig.15 It is a schematic cross-sectional view of a structure obtained in step S811 of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0040] Fig.16 It is a schematic cross-sectional view of a structure obtained in step S82 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0041] Fig.17 It is a schematic cross-sectional view of a structure obtained in step S83 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0042] Fig.18It is a schematic cross-sectional view of a structure obtained in step S90 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0043] Fig.19 It is a schematic cross-sectional view of a structure obtained in step S43 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0044] Fig. 20 It is a schematic cross-sectional view of a structure obtained in step S60, step S81 and step S82 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0045] Fig.21 It is a schematic cross-sectional view of a structure obtained in step S83 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0046] Fig. 22 It is a schematic cross-sectional view of a structure obtained in step S90 in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure.

[0047] Explanation of the accompanying drawings: 1. substrate; 11. step area; 12. boss structure; 13. groove; 2. channel layer; 3. gate dielectric layer; 31. gate dielectric material layer; 4. gate; 41. gate material layer; 5. source electrode; 6. gate electrode; 7. drain electrode; 8. first mask layer. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the case of using "including", "having", and "comprising" described herein, another component may be added unless a clear limiting term such as "only", "consisting of", etc. is used. Unless mentioned to the contrary, a term in the singular form may include a plural form and is not to be understood as having one number.

[0051] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0052] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0053] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0054] According to Moore's Law, with the development of semiconductor device structure optimization and process miniaturization, the integration of semiconductor devices increases accordingly. In order to form more devices in the same area, the integration of semiconductor devices continues to increase, and the technical nodes of devices continue to decrease. As the size of semiconductor devices further decreases, when the channel length L is reduced to a certain extent, the approximation of the slowly varying channel in traditional technology no longer holds, and the two-dimensional potential distribution will cause the threshold voltage to decrease as the channel length shortens, the subthreshold characteristic (Subthreshold) is degraded, and the current saturation fails due to the tunneling effect, and two-dimensional potential distribution and high electric field appear in the channel, which are different from the long channel phenomenon. This phenomenon is collectively referred to as the short channel effect.

[0055] Figure 1 The relationship curve between the gate voltage Vg and the drain current Id under different channel lengths L is shown. It can be understood that as the channel length L becomes shorter, the distance between the source and the drain also becomes shorter, that is, the drain-source depletion region becomes closer and closer, which will cause the electric field lines to cross from the drain to the source, increasing the electrons injected from the source into the channel, resulting in an increase in the leakage current. It can be seen that when the channel length L becomes shorter, the leakage current Id under the same gate voltage Vg increases, resulting in a deterioration in the off-state characteristics of the device and an increase in static power consumption. In dynamic circuits and storage cells, an increase in leakage current may also cause confusion in the logic state.

[0056] The short channel effects mainly include the decrease of threshold voltage as the channel length decreases, drain-induced barrier lowering effect, carrier surface scattering effect, velocity saturation effect, ionization effect, and hot electron effect. Figure 2 Figures (a) to (d) in the figure show the curves of different electrical parameters changing with the channel length L. Among them, Figure (a) shows the curve of the subthreshold swing (SS) changing with the channel length L. It can be understood that the subthreshold swing SS is a performance indicator for measuring the mutual conversion rate between the on and off states of a semiconductor device. It represents the change in gate voltage required for the source-drain current to change tenfold. It can be seen that when the channel length L is shortened to a certain extent, for example, when the channel length L is shortened to 300nm or less, the subthreshold swing increases significantly as the channel length L decreases.

[0057] Figure 2 Figure (b) shows a curve of the threshold voltage Vth changing with the channel length L. It can be understood that the threshold voltage Vth is the gate voltage when a specified current appears between the source and the drain. It can be seen that when the channel length L is shortened to a certain extent, for example, when the channel length L is shortened to 300nm and below, the threshold voltage Vth increases significantly as the channel length L decreases. When the channel length L decreases, the proportion of the source-drain depletion region in the entire channel increases, and the amount of charge required for the inversion layer formed under the gate decreases, so the threshold voltage decreases, which indicates that the gate's control over the channel becomes worse, and the difficulty of the gate voltage to open the channel increases accordingly. Since the threshold voltage Vth decreases as the channel length L decreases, the leakage current of the device increases, which may cause the source-drain punch-through device to fail, thereby reducing the reliability and stability of the semiconductor device.

[0058] Figure 2 Figure (c) shows the curve of the drain barrier lowering effect (DIBL) changing with the channel length L. It can be seen that when the channel length L is shortened to a certain extent, for example, when the channel length L is shortened to 300nm and below, the influence of the drain-induced barrier lowering effect (DIBL) gradually becomes significant. It can be understood that when a high level is applied to the drain, the gate becomes shorter due to the reduction of the channel length L, and the source is also affected by the drain electric field. Under the influence of this electric field, the source junction barrier is lowered, and the drain depletion layer expands, and even connects to the depletion region of the source junction, so that the device cannot be turned off.

[0059] Figure 2 Figure (d) shows the curve of the turn-on current Ion changing with the channel length L. It can be seen that when the channel length L is shortened to a certain extent, for example, when the channel length L is shortened to 300nm or less, the turn-on current Ion increases significantly as the channel length L decreases, which indicates that the current required to turn on the device is also gradually increasing.

[0060] Based on this, the present application provides a semiconductor structure and a method for preparing the same, the details of which will be described in subsequent embodiments.

[0061] According to some embodiments, the present disclosure provides a semiconductor structure.

[0062] As an example, the semiconductor structure can be used to form a semiconductor device, for example, it can be used to form a transistor, and further form a memory device, for example, a dynamic random access memory (DRAM). DRAM may include a transistor and a capacitor or an equivalent capacitor connected to the transistor, the capacitor or the equivalent capacitor is used to store data, and the transistor is used to read the data in the equivalent capacitor or write data to the capacitor or the equivalent capacitor. It can be understood that the semiconductor structure provided in the embodiment of the present application can be directly used as a transistor in a DRAM or as a component of a transistor, for example, it can be used as a transistor in a 1T1C (1Transistor-1Capacitor) structure, or a transistor in a 2T0C structure or a 3T0C structure, but it is not limited thereto. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.

[0063] Please refer to Figures 3 to 5 The semiconductor structure includes a substrate 1, a channel layer 2, a gate dielectric layer 3 and a gate 4; the substrate 1 includes a step region 11; the channel layer 2 conformally covers the surface of the step region 11; the gate dielectric layer 3 is located on the surface of the channel layer 2; and the gate 4 is located on the surface of the gate dielectric layer 3 away from the substrate 1.

[0064] In the semiconductor structure of the above embodiment, the substrate 1 has a step region 11, and the length of the channel layer 2 is extended by conformally covering the surface of the step region 11, which can effectively solve the short channel effect, and does not affect the size miniaturization of the semiconductor structure. The channel layer 2 with different channel lengths can be obtained by simply adjusting the size or number of the step region 11 on the substrate 1. And through the gate dielectric layer 3 located on the surface of the channel layer 2 and the gate 4 located on the surface of the gate dielectric layer 3, the contact area between the gate structure and the channel layer 2 can be increased, and the control ability of the gate 4 is enhanced, thereby reducing the influence of the drain-induced barrier lowering effect to optimize the electrical performance of the device.

[0065] For example, the material of the channel layer 2 includes polysilicon or a metal oxide semiconductor of at least one of indium, gallium, zinc or tin, for example, at least one of indium gallium zinc oxide (IGZO), indium gallium arsenide (InGaAs), gallium nitride (GaN) or a combination thereof. By adopting the above materials, the stress and doping problems of traditional materials in the process of stacking can be overcome, thereby reducing the difficulty of the multi-layer deposition process.

[0066] It can be understood that the electrical performance of the transistor depends on the carrier mobility and the size of the leakage current. In the embodiment where the channel layer 2 is made of IGZO material, since the carrier mobility of the IGZO material is 20 to 30 times that of amorphous silicon, the use of IGZO material can increase the charging and discharging rate and response speed, achieve a faster refresh frequency, and, compared with related technologies, the leakage current of the IGZO transistor can be reduced to one thousandth, which can further reduce the leakage current, thereby optimizing the electrical performance of the device.

[0067] For example, the material of the gate 4 may be metal, for example, the material of the gate 4 may be selected from at least one of titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon, or a combination thereof.

[0068] For example, the material of the gate dielectric layer 3 can be selected from at least one of silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide or a combination thereof. For example, in an embodiment where the channel layer 2 is made of IGZO material, the gate dielectric layer 3 can be a hafnium oxide layer.

[0069] In some embodiments, it also includes a source electrode 5, a gate electrode 6 and a drain electrode 7; the source electrode 5 and the drain electrode 7 are both located on the exposed surface of the channel layer 2; the gate electrode 6 is located on the surface of the gate 4 away from the gate dielectric layer 3, and is located between the source electrode 5 and the drain electrode 7. The gate electrode 6 is in contact with the gate 4 and can be used to provide a control voltage for the gate 4.

[0070] It can be understood that the positions of the source electrode 5 and the drain electrode 7 can be interchanged. Figures 3 to 5 The positions of the source electrode 5 and the drain electrode 7 are for illustration only and are not intended to be limiting.

[0071] For example, the materials of the source electrode 5, the gate electrode 6 and the drain electrode 7 can all be metals. For example, the materials of the source electrode 5, the gate electrode 6 and the drain electrode 7 can be selected from at least one of titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon or a combination thereof.

[0072] Please refer to Figure 3 In some embodiments, the substrate 1 includes a platform structure 12, and the sidewall of the platform structure 12 includes a step region 11; the channel layer 2 covers the sidewall surface of the platform structure 12 and the surface of the substrate 1. By covering the sidewall surface of the platform structure 12 and the surface of the substrate 1, the length of the channel layer 2 is extended, which can effectively solve the short channel effect, and does not affect the size miniaturization of the semiconductor structure. Only by adjusting the height of the platform structure 12, the channel layer 2 with different channel lengths can be obtained.

[0073] In some embodiments where the substrate 1 includes the platform structure 12 , the gate dielectric layer 3 covers the surface of the channel layer 2 located on the surface of the platform structure 12 ; and the gate 4 covers the surface of the gate dielectric layer 3 .

[0074] For example, Figure 3 As shown, the source electrode 5 and the drain electrode 7 are respectively located on the channel layer 2 on both sides of the boss structure 12 ; the gate electrode 6 is located on the gate dielectric layer 3 on the top of the boss structure 12 .

[0075] For example, the boss structure 12 may be an axisymmetric structure. In the embodiment where the boss structure 12 is axisymmetric, the source electrode 5 and the drain electrode 7 may be symmetrically located on both sides of the boss structure 12 , and the gate electrode 6 is located on the symmetry axis of the boss structure 12 .

[0076] In some embodiments, the sidewall of the boss structure 12 includes a multi-step region 11. By adjusting the number of steps in the multi-step region 11, a channel layer 2 with different channel lengths can be obtained, thereby avoiding difficult etching operations.

[0077] Please refer to Figure 4 In some embodiments, a groove 13 is provided in the substrate 1, and the sidewall of the groove 13 includes a step region 11; the channel layer 2 covers the sidewall of the groove 13, the bottom of the groove 13, and the surface of the substrate 1. By covering the sidewall of the groove 13, the bottom of the groove 13, and the surface of the substrate 1, the length of the channel layer 2 is extended, which can effectively solve the short channel effect, and does not affect the size miniaturization of the semiconductor structure. Only by adjusting the depth of the groove 13, the channel layer 2 with different channel lengths can be obtained.

[0078] In some embodiments where the substrate 1 includes a groove 13 , the gate dielectric layer 3 covers the surface of the channel layer 2 located at the sidewall of the groove 13 ; the gate 4 covers the surface of the gate dielectric layer 3 and the surface of the channel layer 2 located at the bottom of the groove 13 .

[0079] For example, the source electrode 5 and the drain electrode 7 are respectively located on the channel layer 2 at two sides of the groove 13 ; the gate electrode 6 is located on the surface of the gate 4 covered with the gate dielectric layer 3 .

[0080] For example, the groove 13 may be in an axisymmetric form. In an embodiment where the groove 13 is axisymmetric, the source electrode 5 and the drain electrode 7 may be symmetrically located on both sides of the groove 13 .

[0081] In some embodiments, the sidewall of the groove 13 may also include a multi-step region 11. By adjusting the number of steps in the multi-step region 11, a channel layer 2 with different channel lengths may be obtained, thereby avoiding difficult etching operations.

[0082] In the embodiment where the sidewall of the groove 13 includes the multi-step region 11 , the gate 4 may be located on a top surface of one side of the first step from the bottom to the top of the groove 13 .

[0083] Please refer to Figure 5 In some embodiments, the substrate 1 includes a multi-step region 11 in a stair-like shape. The channel layer 2 covers the surface of the multi-step region 11 and the surface of the substrate 1, the gate dielectric layer 3 covers the sidewalls of the multi-step region 11, and the gate 4 covers the surface of the gate dielectric layer 3. By covering the surface of the multi-step region 11 and the surface of the substrate 1, the length of the channel layer 2 is extended, which can effectively solve the short channel effect, and does not affect the size miniaturization of the semiconductor structure. Only by adjusting the size of the multi-step region 11, the channel layer 2 with different channel lengths can be obtained.

[0084] For example, the source electrode 5 may be located on the channel layer 2 at one side of the bottom of the stair-shaped multi-step region 11 , and the drain electrode 7 may be located on the channel layer 2 at the top of the stair-shaped multi-step region 11 .

[0085] According to some embodiments, the present application also provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure provided by some of the above embodiments.

[0086] Please refer to Figure 6 In some embodiments, the method for preparing a semiconductor structure may include the following steps:

[0087] Step S20: providing a substrate;

[0088] Step S40: etching the substrate to form a step region;

[0089] Step S60: forming a channel layer, wherein the channel layer conformally covers the surface of the step region;

[0090] Step S80: forming a gate dielectric layer on the surface of the channel layer, and forming a gate on the surface of the gate dielectric layer away from the channel layer.

[0091] In the method for preparing the semiconductor structure of the above embodiment, the substrate is etched to have a step region, and then a channel layer is formed to conformally cover the surface of the step region, thereby extending the length of the channel layer, which can effectively solve the short channel effect, and does not affect the miniaturization of the semiconductor structure. Only by adjusting the morphology of the etched substrate, such as the step depth, that is, adjusting the size of the step region or the number of steps, a channel layer with different channel lengths can be obtained. In addition, by forming a gate dielectric layer located on the surface of the channel layer and forming a gate located on the surface of the gate dielectric layer, the control ability of the gate is enhanced, the contact area between the gate structure and the channel layer can be increased, and the control ability of the gate is enhanced, thereby reducing the influence of the drain-induced barrier lowering effect, so as to optimize the electrical performance of the device, and can achieve electrical connection in a one-time process of forming the gate, thereby simplifying the process flow.

[0092] In some embodiments, step S40, etching the substrate to form a step region, includes:

[0093] Step S41: etching the substrate to form a boss structure, wherein the sidewall of the boss structure includes a step region; and the channel layer covers the sidewall of the boss structure and the surface of the substrate.

[0094] In some embodiments, the sidewall of the boss structure includes a multi-step region.

[0095] In some embodiments, step S40, etching the substrate to form a step region, includes:

[0096] Step S42: etching the substrate to form a groove in the substrate, and a step area on the sidewall surface of the groove; the channel layer covers the sidewall of the groove, the bottom of the groove and the surface of the substrate.

[0097] In some embodiments, step S40, etching the substrate to form a step region, includes:

[0098] Step S43: etching the substrate to form a multi-step region in the shape of a staircase.

[0099] In some embodiments, step S80, forming a gate dielectric layer on a surface of the channel layer, and forming a gate on a surface of the gate dielectric layer away from the channel layer, includes:

[0100] Step S81: forming a gate dielectric material layer on the surface of the channel layer;

[0101] Step S82: forming a gate material layer on a surface of the gate dielectric material layer away from the channel layer;

[0102] Step S83: etching the gate material layer and the gate dielectric material layer to expose a portion of the surface of the channel layer and obtain the gate dielectric layer and the gate;

[0103] In some embodiments, after step S80, forming a gate dielectric layer on the surface of the channel layer and forming a gate on the surface of the gate dielectric layer away from the channel layer, the method further includes:

[0104] Step S90: forming a source electrode, a drain electrode and a gate electrode; the source electrode and the drain electrode are both located on the exposed surface of the channel layer; the gate electrode is located on the surface of the gate dielectric layer and between the source electrode and the drain electrode.

[0105] It should be understood that although Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0106] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiments, Figures 7 to 22 Understand some embodiments of the present application.

[0107] The present application embodiment does not specifically limit the constituent materials of the substrate 1. As an example, the substrate 1 can be composed of semiconductor materials, insulating materials, conductor materials or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate 1, a silicon germanium (SiGe) substrate 1, a silicon germanium carbon (SiGeC) substrate 1, a silicon carbide (SiC) substrate 1, a gallium arsenide (GaAs) substrate 1, an indium arsenide (InAs) substrate 1, an indium phosphide (InP) substrate 1 or other III / V semiconductor substrates 1 or II / VI semiconductor substrates 1. Alternatively, for example, the substrate 1 can be a layered substrate 1 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. Those skilled in the art can select the type of substrate 1 according to the type of transistor formed on the substrate 1, so the type of substrate 1 should not limit the scope of protection of the present disclosure.

[0108] In step S20, an ion implantation process may be used to implant P-type ions into the substrate 1 to form a first type doped well region. In an embodiment where the substrate 1 includes a P-type substrate 1, an active region may be formed by implanting N-type ions; correspondingly, in an embodiment where the substrate 1 includes an N-type substrate 1, an active region may be formed by implanting P-type ions. Accordingly, the active region may be a P-type active region or an N-type active region. The P-type active region may form an N-type metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, referred to as NMOS) device, and the N-type active region may form a P-type metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, referred to as PMOS) device.

[0109] By way of example, P-type ions may include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions; N-type impurity ions may include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0110] Before executing step S40, the step of cleaning the substrate 1 can also be included. By cleaning, impurities on the surface of the substrate 1 can be removed to avoid affecting subsequent processes, thereby ensuring the performance of the device. Specifically, the substrate 1 can be cleaned with a cleaning solution, and the substrate 1 can be placed in a cleaning tank containing the cleaning solution for cleaning. The specific cleaning solution and cleaning process used to clean the substrate 1 are known to those skilled in the art, and will not be repeated here. It should be noted that after cleaning the substrate 1, a step of drying the substrate 1 is also required. The method for drying the substrate 1 is well known to those skilled in the art, and will not be repeated here.

[0111] Please combine Figures 7 to 9 Understand some embodiments of the present application.

[0112] Please refer to Figures 7 to 9 In some embodiments, step S40, etching the substrate 1 to form a step region 11, includes:

[0113] Step S42 : etching the substrate 1 to form a boss structure 12 , the sidewall of the boss structure 12 including a step region 11 ; the channel layer 2 covers the sidewall of the boss structure 12 and the surface of the substrate 1 .

[0114] In some embodiments, the sidewall of the boss structure 12 includes a multi-step region 11. By adjusting the number of steps in the multi-step region 11, a channel layer 2 with different channel lengths can be obtained, thereby avoiding difficult etching operations.

[0115] For example, when forming a boss structure 12 having a multi-step region 11 on its sidewall, in step S41, etching the substrate 1 to form the boss structure 12 may be performed in a step-by-step manner to reduce the difficulty of etching. For example, the following steps may be included:

[0116] Step S411: Figure 7 As shown, a first mask layer 8 is formed on the substrate 1, and a first pattern is provided in the first mask layer 8, and the first pattern defines the range of the first step from bottom to top in the multi-step region 11;

[0117] Step S412: Figure 8 As shown, the substrate 1 is etched based on the first mask layer 8 to form an initial boss structure 12 (not shown) having a first step, and the first mask layer 8 is removed;

[0118] Step S413: forming a second mask layer (not shown) on the top surface of the initial boss structure 12, wherein the second mask layer defines the range of the second step from bottom to top in the multi-step region 11;

[0119] Step S414: Fig. 9 As shown, the initial boss structure 12 is etched based on the second mask layer to form a boss structure 12 having a first step and a second step, and the second mask layer is removed;

[0120] It can be understood that when forming the boss structure 12 whose sidewall has a multi-step region 11 with more than two steps, step S413 to step S414 can be repeated until the last step is formed.

[0121] For example, in step S411 , a spin-on hard mask process may be used to form a first mask layer 8 on the substrate 1 . The first mask layer 8 may be a single-layer structure or a multi-layer stacked structure.

[0122] Specifically, in step S411, a first photoresist material layer can be coated on the surface of the first mask layer 8 away from the substrate 1, and a first pattern can be formed through a series of steps such as exposure and development. The photoresist can be positive photoresist or negative photoresist, and the development method can be positive development or negative development.

[0123] In some embodiments, a one-time etching process may also be used to directly form a boss structure 12 having a multi-step region 11 on its sidewall.

[0124] It should be added that the "one-time etching process" mentioned in some embodiments of the present disclosure can be understood as: etching based on the pattern of the same mask plate to form the same pattern; it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.

[0125] Please refer to Fig.10 In step S60 , a channel layer 2 is formed, and the channel layer 2 conformally covers the surface of the step region 11 .

[0126] Please refer to Figure 10 to Figure 11 In some embodiments, step S80, forming a gate dielectric layer 3 on a surface of the channel layer 2, and forming a gate 4 on a surface of the gate dielectric layer 3 away from the channel layer 2, includes:

[0127] Step S81: Fig.10 As shown, a gate dielectric material layer 31 is formed on the surface of the channel layer 2;

[0128] Step S82: Fig.10 As shown, a gate material layer 41 is formed on the surface of the gate dielectric material layer 31 away from the channel layer 2;

[0129] Step S83: Fig.11 As shown, the gate material layer 41 and the gate dielectric material layer 31 are etched to expose a portion of the surface of the channel layer 2 and obtain the gate dielectric layer 3 and the gate 4;

[0130] Please refer to Fig.12 In step S90, a source electrode 5, a drain electrode 7 and a gate electrode 6 are formed; the source electrode 5 and the drain electrode 7 are both located on the exposed surface of the channel layer 2; the gate electrode 6 is located on the surface of the gate dielectric layer 3 and between the source electrode 5 and the drain electrode 7.

[0131] Please combine Figures 13 to 18 Understand other embodiments of the present application.

[0132] Please refer to Fig.13 In some embodiments, step S40, etching the substrate 1 to form a step region 11, includes:

[0133] Step S42 : etching the substrate 1 to form a groove 13 in the substrate 1 , and a sidewall surface step region 11 of the groove 13 ; the channel layer 2 covers the sidewall of the groove 13 , the bottom of the groove 13 and the surface of the substrate 1 .

[0134] In some embodiments, the sidewall of the groove 13 includes a multi-step region 11. By adjusting the number of steps in the multi-step region 11, a channel layer 2 with different channel lengths can be obtained, thereby avoiding difficult etching operations.

[0135] For example, when forming a groove 13 with a multi-step region 11 on the sidewall, in step S42, etching the substrate 1 to form the groove 13, a step-by-step etching method can be adopted to reduce the difficulty of etching, and the relevant steps of step S41 can be referred to, which will not be repeated here. It can be understood that a one-time etching process can also be adopted to directly form the groove 13 with a multi-step region 11 on the sidewall.

[0136] Please refer to Fig.14 In step S60 , a channel layer 2 is formed, and the channel layer 2 conformally covers the surface of the step region 11 .

[0137] Please refer to Figures 14 to 17 In some embodiments, step S80, forming a gate dielectric layer 3 on a surface of the channel layer 2, and forming a gate 4 on a surface of the gate dielectric layer 3 away from the channel layer 2, includes:

[0138] Step S81: Fig.14 As shown, a gate dielectric material layer 31 is formed on the surface of the channel layer 2;

[0139] For example, after step S81, the method further includes: step S811: Fig.15 As shown, a portion of the gate dielectric material layer 31 located on the bottom surface of the groove 13 and the top surface of the substrate 1 is removed to obtain a gate dielectric layer 3;

[0140] Step S82: Fig.16 As shown, a gate material layer 41 is formed on the surface of the gate dielectric material layer 31 away from the channel layer 2;

[0141] Step S83: Fig.17 As shown, the gate material layer 41 is etched to expose a portion of the surface of the channel layer 2 and obtain the gate 4 .

[0142] Please refer to Fig.18 In step S90, a source electrode 5, a drain electrode 7 and a gate electrode 6 are formed; the source electrode 5 and the drain electrode 7 are both located on the exposed surface of the channel layer 2; the gate electrode 6 is located on the surface of the gate dielectric layer 3 and between the source electrode 5 and the drain electrode 7.

[0143] Please combine Figures 19 to 22 Understand some further embodiments of the present application.

[0144] Please refer to Fig.19 In some embodiments, step S40, etching the substrate 1 to form a step region 11, includes:

[0145] Step S43: etching the substrate 1 to form a stair-shaped multi-step region 11. By adjusting the number of steps in the multi-step region 11, channel layers 2 with different channel lengths can also be obtained, thereby avoiding difficult etching operations.

[0146] For example, in the case of a staircase-shaped multi-step region 11, in step S42, etching the substrate 1 to form a groove 13 can be performed in a step-by-step manner to reduce the difficulty of etching. The relevant steps of step S41 can be referred to and will not be described here. It can be understood that a one-time etching process can also be used to directly form the staircase-shaped multi-step region 11.

[0147] Please refer to Figure 20 to Figure 21 In step S60 , a channel layer 2 is formed, and the channel layer 2 conformally covers the surface of the step region 11 .

[0148] Please refer to Figure 20 to Figure 21 In some embodiments, step S80, forming a gate dielectric layer 3 on a surface of the channel layer 2, and forming a gate 4 on a surface of the gate dielectric layer 3 away from the channel layer 2, includes:

[0149] Step S81: Fig. 20 As shown, a gate dielectric material layer 31 is formed on the surface of the channel layer 2;

[0150] Step S82: Fig. 20 As shown, a gate material layer 41 is formed on the surface of the gate dielectric material layer 31 away from the channel layer 2;

[0151] Step S83: Fig.21 As shown, the gate material layer 41 and the gate dielectric material layer 31 are etched to expose a portion of the surface of the channel layer 2 , and to obtain the gate dielectric layer 3 and the gate 4 .

[0152] Please refer to Fig. 22 In step S90, a source electrode 5, a drain electrode 7 and a gate electrode 6 are formed; the source electrode 5 and the drain electrode 7 are both located on the exposed surface of the channel layer 2; the gate electrode 6 is located on the surface of the gate dielectric layer 3 and between the source electrode 5 and the drain electrode 7.

[0153] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0154] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0155] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0156] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, including a step region; A channel layer conformally covers at least a portion of the surface of the step region; A gate dielectric layer, located on a surface of the channel layer; The gate is located on a surface of the gate dielectric layer away from the substrate.

2. The semiconductor structure according to claim 1, characterized in that: It also includes a source electrode, a gate electrode and a drain electrode; the source electrode and the drain electrode are both located on the exposed surface of the channel layer; the gate electrode is located on the surface of the gate away from the gate dielectric layer and is located between the source electrode and the drain electrode.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The substrate includes a boss structure, and a sidewall of the boss structure includes the step region; the channel layer covers a surface of the sidewall of the boss structure and a surface of the substrate.

4. The semiconductor structure according to claim 3, characterized in that: The side wall of the boss structure includes a plurality of step regions.

5. The semiconductor structure according to claim 1 or 2, characterized in that: The substrate has a groove therein, and the sidewall of the groove includes the step region; the channel layer covers the sidewall of the groove, the bottom of the groove and the surface of the substrate.

6. The semiconductor structure according to claim 1 or 2, characterized in that: The substrate includes a plurality of step regions in a stair-like shape.

7. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; Etching the substrate to form a step region; forming a channel layer, wherein the channel layer conformally covers the surface of the step region; A gate dielectric layer is formed on the surface of the channel layer, and a gate is formed on the surface of the gate dielectric layer away from the channel layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: Forming a gate dielectric layer on the surface of the channel layer, and forming a gate on the surface of the gate dielectric layer away from the channel layer, comprising: forming a gate dielectric material layer on the surface of the channel layer; forming a gate material layer on the surface of the gate dielectric material layer away from the channel layer; etching the gate material layer and the gate dielectric material layer to expose a portion of the surface of the channel layer, and obtaining the gate dielectric layer and the gate; After forming a gate dielectric layer on the surface of the channel layer and forming a gate on the surface of the gate dielectric layer away from the channel layer, the method further comprises: A source electrode, a drain electrode and a gate electrode are formed; the source electrode and the drain electrode are both located on the exposed surface of the channel layer; the gate electrode is located on the surface of the gate dielectric layer and between the source electrode and the drain electrode.

9. The method for preparing a semiconductor structure according to claim 7 or 8, characterized in that: Etching the substrate to form a step region, comprising: The substrate is etched to form a boss structure, wherein the sidewall of the boss structure includes the step region; and the channel layer covers the sidewall of the boss structure and the surface of the substrate.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The side wall of the boss structure includes a plurality of step regions.

11. The method for preparing a semiconductor structure according to claim 7 or 8, characterized in that: Etching the substrate to form a step region, comprising: The substrate is etched to form a groove in the substrate, and the sidewall surface of the groove is the step area; the channel layer covers the sidewall of the groove, the bottom of the groove and the surface of the substrate.

12. The method for preparing a semiconductor structure according to claim 7 or 8, characterized in that: Etching the substrate to form a step region, comprising: The substrate is etched to form a plurality of step regions in a stair-like shape.

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