Method of forming a semiconductor device

Abstract

The application provides a forming method of a semiconductor device, comprising the following steps: providing a substrate; performing P-well ion implantation of a first active region; forming a first gate layer on the substrate of the first active region; forming a second gate layer on the substrate of a second active region; performing maskless N-type drain light-doped ion implantation; performing N-well ion implantation and P-type drain light-doped ion implantation of the second active region under the same mask. The N-well ion implantation and the P-type drain light-doped ion implantation share the same mask under a low-cost and high-performance platform processing; after the etching of the gate layer, the maskless N-type drain light-doped ion implantation is performed under the condition that the photoresist layer after the etching of the gate layer is reserved, so that the gate layer is prevented from being punched by the N-type light-doped ion implantation. The mask for forming the N-well and the N-type drain light-doped is saved. Under the two LDD ion implantation processes, the hot carrier effect performance of the NMOS tube is ensured, the substrate leakage current is reduced, and the reliability test is passed.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit manufacturing technology, and specifically relates to a method for forming a semiconductor device. Background Technology

[0002] For the fabrication of CMOS devices (e.g., operating at 7V), the market demands low-cost, high-performance process platforms. Maintaining the same gate size for both 7V and 5V CMOS devices while saving at least two photomasks compared to normal logic processes presents a significant challenge to wafer fabrication plants' logic processes. Summary of the Invention

[0003] The purpose of this invention is to provide a method for forming semiconductor devices. This method utilizes a low-cost, high-performance process platform, sharing the same photomask for N-well ion implantation and P-type drain light-doped ion implantation. The N-type drain light doping is achieved using maskless ion implantation, saving the need for photomasks in the two separate processes of forming the N-well and N-type drain light doping. While retaining the two LDD ion implantation processes, the hot carrier effect performance of the NMOS transistor is prioritized, significantly reducing substrate leakage current and passing reliability testing.

[0004] This invention provides a method for forming a semiconductor device, comprising:

[0005] Step S1: Provide a substrate, wherein a first active region and a second active region are defined on the substrate by shallow trench isolation;

[0006] Step S2: Perform P-trap ion implantation in the first active region;

[0007] Step S3: Forming a gate layer, a first gate oxide layer and a first gate layer are sequentially formed on the substrate of the first active region; a second gate oxide layer and a second gate layer are sequentially formed on the substrate of the second active region.

[0008] Step S4: Retain the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer; Perform maskless N-type drain light doped ion implantation under the protection of the photoresist layer to form an N-type first light doped region in the first active region and an N-type second light doped region in the second active region.

[0009] Step S5: Under the same photomask, perform N-well ion implantation and P-type drain light doped ion implantation in the second active region; in the second active region, the implanted P-type drain light doped ions neutralize the N-type second light doped region and invert to finally form the P-type light doped region.

[0010] Step S6: Perform N-type ion heavy doping implantation in the first active region to form the source and drain regions of the NMOS transistor;

[0011] Step S7: Perform P-type ion heavy doping implantation in the second active region II to form the source and drain regions of the PMOS transistor.

[0012] Furthermore, step S3 specifically includes:

[0013] A gate oxide layer and a gate material layer are formed sequentially covering the substrate;

[0014] An imaged second photoresist layer is formed on the surface of the gate material layer, the imaged second photoresist layer comprising a first region of the second photoresist layer and a second region of the second photoresist layer;

[0015] Using the second photoresist layer as a mask, the gate material layer and the gate oxide material layer are etched sequentially to form the first gate layer and the first gate oxide layer located below the first region of the second photoresist layer, and the second gate layer and the second gate oxide layer located below the second region of the second photoresist layer.

[0016] Furthermore, during the maskless N-type drain lightly doped ion implantation in step S4, the first region of the second photoresist layer and the second region of the second photoresist layer are still retained;

[0017] After the maskless N-type drain lightly doped ion implantation is completed, the first region of the second photoresist layer and the second region of the second photoresist layer are removed.

[0018] Furthermore, step S5 specifically includes:

[0019] A third photoresist layer is formed, the third photoresist layer having an opening in the second active region and covering the first active region; using the third photoresist layer as a mask, the second active region is first implanted with N-well ions to form an N-well; then the second active region is implanted with lightly doped P-type drain ions to form a lightly doped P-type region.

[0020] Furthermore, in step S5, in the second active region, the N-well ion implantation depth is greater than the P-type drain lightly doped ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped ion implantation energy.

[0021] Furthermore, in step S5, the N-trap ion implantation also penetrates the second gate layer and the second gate oxide layer into the substrate below.

[0022] Furthermore, the operating voltage of the semiconductor device includes 7V or 5V.

[0023] Furthermore, after step S5 and before step S6, the forming method further includes:

[0024] A first sidewall is formed on the substrate of the first active region, the first sidewall covering the sidewalls of the first gate oxide layer and the first gate layer; a second sidewall is formed on the substrate of the second active region, the second sidewall covering the sidewalls of the second gate oxide layer and the second gate layer.

[0025] Furthermore, after step S7, the forming method further includes:

[0026] Metal silicides are formed on the surfaces of the first gate layer and the second gate layer, and on the substrate surfaces of the first active region and the second active region.

[0027] A dielectric layer is formed, the dielectric layer covering the substrate, the first sidewall, the first gate layer, the second sidewall, and the second gate layer; a contact hole is formed in the dielectric layer;

[0028] A metal interconnect is formed, the contact hole is filled with metal, and the gate, source and drain regions of the NMOS and PMOS transistors are brought out respectively.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] This invention provides a method for forming a semiconductor device, comprising: step S1, providing a substrate, wherein a first active region and a second active region are defined on the substrate by shallow trench isolation; step S2, performing P-well ion implantation in the first active region; step S3, forming a gate layer, wherein a first gate oxide layer and a first gate layer are sequentially formed on the substrate of the first active region; and a second gate oxide layer and a second gate layer are sequentially formed on the substrate of the second active region; step S4, retaining the photoresist layer covering the first gate layer and the second gate layer formed in the step of forming the gate layer; performing maskless N-type drain lightly doped ion implantation under the protection of the photoresist layer, forming an N-type first lightly doped region in the first active region and an N-type second lightly doped region in the second active region; step S5, performing N-well ion implantation and P-type drain lightly doped ion implantation in the second active region under the same photomask; step S6, performing N-type heavy doping ion implantation in the first active region to form the source and drain regions of an NMOS transistor; and step S7, performing P-type heavy doping ion implantation in the second active region II to form the source and drain regions of a PMOS transistor.

[0031] The semiconductor device fabrication method provided by this invention is manufactured on a low-cost, high-performance process platform. It utilizes the same photomask for N-well ion implantation and P-type drain light doping (LDD) ion implantation. After gate layer etching, maskless N-type drain light doping ion implantation is performed while retaining the photoresist layer after gate layer etching, preventing the gate layer from being penetrated by N-type light doped ions. This saves the need for photomasks in the N-well and N-type drain light doping (LDD) processes. While retaining both N-type and P-type drain light doping (LDD) ion implantation processes, the hot carrier effect performance of the NMOS transistor is prioritized, significantly reducing substrate leakage current and passing reliability tests. This not only ensures the electrical performance of the semiconductor device but also achieves the goal of saving photomask costs. Attached Figure Description

[0032] Figure 1 This is a normal logic process flow diagram for a 5V CMOS device.

[0033] Figure 2 Flowchart for saving photomask logic process for 5V CMOS devices.

[0034] Figure 3 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of the semiconductor device formation method according to an embodiment of the present invention after ion implantation in the first active region P-well.

[0036] Figure 5 This is a schematic diagram of the semiconductor device formation method according to an embodiment of the present invention after performing maskless N-type drain lightly doped (LDD) ion implantation.

[0037] Figure 6 This is a schematic diagram showing the process after N-well ion implantation and P-type drain lightly doped (LDD) ion implantation in the semiconductor device formation method of this embodiment of the invention.

[0038] Figure 7 This is a flowchart illustrating a method for forming a semiconductor device according to an embodiment of the present invention.

[0039] The accompanying figure is labeled as follows:

[0040] 10-Substrate; 10a-P-well; 10b-N-well; 11-STI; I-First active region; II-Second active region; 121-First gate oxide layer; 122-Second gate oxide layer; 131-First gate layer; 132-Second gate layer; 141-N-type first lightly doped region; 142-N-type second lightly doped region; 152-P-type lightly doped region; 21-First photoresist layer; 221-Second photoresist layer first region; 222-Second photoresist layer second region; 23-Third photoresist layer. Detailed Implementation

[0041] As described in the background section, the market demands a low-cost, high-performance process platform for the fabrication of CMOS devices.

[0042] Figure 1 This is a normal logic process flow diagram for a 5V CMOS device. The inventors discovered that, to save on photomasks, in... Figure 1 Based on the existing process, directly omitting the two process steps of N-type drain light doping (LDD) and P-type drain light doping (LDD) and the corresponding two photomasks will result in poor hot carrier effect of CMOS devices and high substrate leakage current Isub, which will fail the reliability assessment.

[0043] Figure 2 This is a flowchart illustrating a mask-saving logic process for 5V CMOS devices. 7V CMOS devices utilize... Figure 2 The same process, in Figure 1 Based on the normal logic process of 5V CMOS devices, the same photomask is used for both the lightly doped N-type drain (LDD) and heavily doped N-type ions, and the same photomask is used for both the lightly doped P-type drain (LDD) and heavily doped P-type ions. This saves two photomasks: one for the N-type lightly doped drain (LDD) and one for the P-type lightly doped drain (LDD). However, in actual testing, it was found that the substrate leakage current Isub is still very high under the application voltage of 7V CMOS devices, failing to meet reliability standards. Therefore, for a low-cost, high-performance process platform for 7V CMOS devices, a new process method is urgently needed that can save photomask costs while ensuring device performance, especially the electrical performance of NMOS transistors.

[0044] Based on the above research, the present invention provides a method for forming a semiconductor device. The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0045] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.

[0046] This invention provides a method for forming a semiconductor device, such as... Figure 3 As shown, it includes:

[0047] Step S1: Provide a substrate, on which a first active region and a second active region are defined by shallow trench isolation;

[0048] Step S2: Perform P-trap ion implantation in the first active region;

[0049] Step S3: Forming a gate layer: A first gate oxide layer and a first gate layer are sequentially formed on the substrate of the first active region; a second gate oxide layer and a second gate layer are sequentially formed on the substrate of the second active region.

[0050] Step S4: Retain the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer; perform maskless N-type drain light doped ion implantation under the protection of the photoresist layer to form an N-type first light doped region in the first active region and an N-type second light doped region in the second active region.

[0051] Step S5: Under the same photomask, perform N-well ion implantation and P-type drain light doped ion implantation in the second active region; in the second active region, the implanted P-type drain light doped ions neutralize the N-type second light doped region and invert to finally form the P-type light doped region.

[0052] Step S6: Perform N-type ion heavy doping implantation in the first active region to form the source and drain regions of the NMOS transistor;

[0053] Step S7: Perform P-type ion heavy doping implantation in the second active region II to form the source and drain regions of the PMOS transistor.

[0054] The following is combined with Figures 4 to 7 The steps of the method for forming a semiconductor device according to embodiments of the present invention are described in detail.

[0055] Step S1, as follows Figure 4 As shown, a substrate 10 is provided, on which a first active region I and a second active region II are defined by shallow trench isolation (STI) 11. The substrate 10 may include semiconductor materials and may be a single-layer structure or a multilayer structure. The substrate 10 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors; it may also include a layered substrate such as silicon-on-insulator (SOI) or silicon-germanium-on-insulator. This embodiment illustrates the formation of an NMOS using the first active region I and a PMOS using the second active region II. In other embodiments, the first active region I may be used to form a PMOS and the second active region II may be used to form an NMOS.

[0056] Step S2, as follows Figure 4 As shown, P-well ion implantation is performed on the first active region I. Specifically, a first photoresist layer 21 is formed, which has an opening in the first active region I, exposing the first active region I and covering the second active region II. Using the first photoresist layer 21 as a mask, P-well ion implantation is performed on the first active region I to form P-well 10a.

[0057] Step S3, as follows Figure 5 As shown, a gate layer is formed by sequentially forming a first gate oxide layer 121 and a first gate layer 131 on the substrate of the first active region I; and sequentially forming a second gate oxide layer 122 and a second gate layer 132 on the substrate of the second active region II. Specifically, the material layers of the first gate oxide layer 121 and the second gate oxide layer 122 can be grown using a thermal oxidation growth process, with the temperature of the thermal oxidation growth process being, for example, 900°C to 1150°C. The material layers of the first gate layer 131 and the second gate layer 132 can be formed using any one of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or metal-organic chemical vapor deposition (MOCVD), as well as other suitable processes.

[0058] Using the first region 221 and the second region 222 of the second photoresist layer as masks, a first gate layer 131 and a second gate layer 132, as well as a first gate oxide layer 121 and a second gate oxide layer 122, are formed through the same etching process. The ends of the first gate layer 131 and the second gate layer 132 can be connected together. The ends of the first gate oxide layer 121 and the second gate oxide layer 122 can also be connected together.

[0059] Step S4, as follows Figure 5As shown, the photoresist layer covering the first and second gate layers is retained during the gate layer formation step. Maskless N-type drain lightly doped (LDD) ion implantation is performed under the protection of the photoresist layer. In the first active region I, N-type first lightly doped regions 141 are formed on the shallow surface of the substrate located on both sides of the first gate layer 131, and in the second active region II, N-type second lightly doped regions 142 are formed on the shallow surface of the substrate located on both sides of the second gate layer 132. In this step, after etching to form the first gate layer 131 and the second gate layer 132, the first region 221 and the second region 222 of the second photoresist layer are retained to prevent maskless LDD ion implantation into the substrate 10 directly below the first gate layer 131 and the second gate layer 132. After the maskless LDD ion implantation step is completed, the first region 221 and the second region 222 of the second photoresist layer are removed.

[0060] Step S5, as follows Figure 6 As shown, N-well ion implantation and P-type drain lightly doped (LDD) ion implantation are performed in the second active region II. Specifically, a third photoresist layer 23 is formed, which has an opening in the second active region II, exposing the second active region II and covering the first active region I. Using the third photoresist layer 23 as a mask, N-well ion implantation is first performed in the second active region II to form an N-well 10b; the N-well ion implantation also penetrates the second gate layer 132 into the substrate directly below it. Using the third photoresist layer 23 as a mask, P-type drain lightly doped (LDD) ion implantation is then performed in the second active region II to form a P-type lightly doped region 152. The N-well ion implantation depth is greater than the P-type drain lightly doped (LDD) ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped (LDD) ion implantation energy. It should be understood that in step S4, an N-type second lightly doped region 142 is formed in the shallow surface source and drain regions of the substrate on both sides of the second gate layer 132 in the second active region II. In step S5, more P-type drain lightly doped (LDD) ions need to be implanted into the shallow surface source and drain regions of the substrate in the second active region II to neutralize the previous N-type second lightly doped region 142 and invert to finally form a P-type lightly doped region 152. By performing drain light doping (LDD), the short-channel effect and hot carrier effect are suppressed, the concentration gradient at the junction of the channel and the drain / source is reduced, and the electric field strength of the source and drain is reduced to a certain extent. By performing drain light doping (LDD), the lightly doped drain region has a lighter doping in the overlap region with the gate layer, which can increase the penetration voltage of the LDD junction, improve the channel penetration characteristics of the device, reduce the hot carrier effect, and improve the reliability of the device.

[0061] Next, the third photoresist layer 23 is removed. A first sidewall (not shown) is formed on the substrate of the first active region I, the first sidewall covering the sidewalls of the first gate oxide layer 121 and the first gate layer 131; a second sidewall is formed on the substrate of the second active region II, the second sidewall covering the sidewalls of the second gate oxide layer 122 and the second gate layer 132.

[0062] Next, N-type ion heavy doping implantation is performed on the first active region I. Specifically, a fourth photoresist layer (not shown) is formed. The fourth photoresist layer has an opening in the first active region I, exposing the first active region I and covering the second active region II. Using the fourth photoresist layer as a mask, N-type ion heavy doping implantation is performed on the first active region I. Source and drain regions are formed in the substrates on both sides of the first sidewall, respectively, forming an NMOS in the first active region I.

[0063] Next, P-type ion heavy doping implantation is performed in the second active region II. Specifically, a fifth photoresist layer (not shown) is formed. The fifth photoresist layer has an opening in the second active region II, exposing the second active region II and covering the first active region I. Using the fifth photoresist layer as a mask, P-type ion heavy doping implantation is performed in the second active region II, forming the source and drain regions in the substrate on both sides of the second sidewall, respectively, thus forming a PMOS in the second active region II. The order of N-type ion heavy doping implantation in the first active region I and P-type ion heavy doping implantation in the second active region II can be interchanged.

[0064] Next, metal silicides are formed by depositing a metal layer (e.g., Ti, Co, and NiPt) on the first gate layer 131, the second gate layer 132, and the first active region I and the second active region II using physical vapor deposition. Then, rapid thermal annealing and selective wet etching are performed to ultimately form metal silicides on the surfaces of the first gate layer 131 and the second gate layer 132, as well as on the substrate surfaces of the first active region I and the second active region II. Metal silicides include thin films such as TiSi2, CoSi2, and NiPtSi. Metals Ti, Co, or NiPt do not react with the dielectric material to form metal silicides; they only react with the directly contacting polysilicon and the substrate silicon of the active regions to form metal silicides. This reduces sheet resistance and contact resistance, resulting in lower series resistance, reduced RC delay, and increased circuit speed.

[0065] Next, metal interconnects are formed; specifically, a dielectric layer is deposited, covering the substrate, first sidewall, first gate layer, second sidewall, and second gate layer. Chemical mechanical polishing (CMP) is used to planarize the dielectric layer, followed by dry etching to fabricate device contact holes. Tungsten sputtering and tungsten chemical mechanical planarization are then used to fill the device contact holes. The gate, source, and drain regions can be led out through the contact holes. A metal film is sputtered, and metal interconnect etching is completed.

[0066] Combination Figure 7 As shown, the semiconductor device fabrication method provided by this invention is manufactured on a low-cost, high-performance process platform. It uses the same photomask for both N-well ion implantation and P-type drain light doping (LDD) ion implantation. The N-type drain light doping (LDD) employs maskless ion implantation, saving the need for photomasks in the two processes of forming both the N-well and N-type drain light doping (LDD). While retaining the two LDD ion implantation processes (N-type and P-type drain light doping (LDD)), the hot carrier effect performance of the NMOS transistor is prioritized, significantly reducing substrate leakage current and passing reliability testing. This not only ensures the hot carrier effect performance of the semiconductor device but also achieves the goal of saving photomask costs.

[0067] Hot carrier injection in high-voltage NMOS transistors is worse than in PMOS transistors. The majority carriers in NMOS transistors are electrons, which have a higher mobility than holes in PMOS transistors. Therefore, under the same electric field, hot carrier injection in NMOS transistors is significantly worse. This invention prioritizes NMOS transistor performance by prioritizing P-well ion implantation and maskless lightly doped (LDD) ion implantation to maximize NMOS transistor performance.

[0068] For example, the semiconductor device in this embodiment can be a CMOS device, with an operating voltage of, for example, 7V. That is, the transistor is fully turned on when both the gate and drain voltages are 7V. Actual testing shows that the substrate leakage current Isub of the NMOS transistor in the 7V CMOS device formed using the semiconductor device formation method of this invention is significantly better than that formed using... Figure 2 The improved 5V CMOS device significantly reduces the photomask logic process, and the substrate leakage current Isub is reduced to 1 / 4 of the previous level, which is only 0.6% of the saturation current Idsat.

[0069] In summary, the present invention provides a method for forming a semiconductor device, comprising: step S1, providing a substrate, wherein a first active region and a second active region are defined on the substrate by shallow trench isolation; step S2, performing P-well ion implantation on the first active region; step S3, forming a gate layer, wherein a first gate oxide layer and a first gate layer are sequentially formed on the substrate of the first active region; and a second gate oxide layer and a second gate layer are sequentially formed on the substrate of the second active region; and step S4, retaining the layers covering the first and second gate layers formed in the gate layer forming step. A photoresist layer is used. Under the protection of the photoresist layer, maskless N-type drain lightly doped ion implantation is performed to form an N-type first lightly doped region in the first active region and an N-type second lightly doped region in the second active region. Step S5: Under the same photomask, N-well ion implantation and P-type drain lightly doped ion implantation are performed in the second active region. Step S6: N-type ion heavy doping implantation is performed in the first active region to form the source and drain regions of the NMOS transistor. Step S7: P-type ion heavy doping implantation is performed in the second active region II to form the source and drain regions of the PMOS transistor.

[0070] The semiconductor device fabrication method provided by this invention is manufactured on a low-cost, high-performance process platform. It utilizes the same photomask for N-well ion implantation and P-type drain lightly doped (LDD) ion implantation. After gate layer etching, maskless N-type drain lightly doped ion implantation is performed while retaining the photoresist layer after gate layer etching, preventing the gate layer from being penetrated by N-type lightly doped ions. This saves the need for photomasks in the N-well and N-type drain lightly doped (LDD) processes. While retaining both N-type and P-type drain lightly doped (LDD) ion implantation processes, the hot carrier effect performance of the NMOS transistor is prioritized, significantly reducing substrate leakage current and passing reliability tests. This not only ensures the electrical performance of the semiconductor device but also achieves the goal of saving photomask costs.

[0071] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, include: Step S1: Provide a substrate, wherein a first active region and a second active region are defined on the substrate by shallow trench isolation; Step S2: Perform P-trap ion implantation in the first active region; Step S3: Forming a gate layer, a first gate oxide layer and a first gate layer are sequentially formed on the substrate of the first active region; a second gate oxide layer and a second gate layer are sequentially formed on the substrate of the second active region. Step S4: Retain the photoresist layer covering the first gate layer and the second gate layer in the step of forming the gate layer; Under the protection of the photoresist layer, maskless N-type drain lightly doped ion implantation is performed to form an N-type first lightly doped region in the first active region and an N-type second lightly doped region in the second active region. Step S5: Under the same photomask, perform N-well ion implantation and P-type drain light doped ion implantation in the second active region; in the second active region, the implanted P-type drain light doped ions neutralize the N-type second light doped region and invert to finally form the P-type light doped region. Step S6: Perform N-type ion heavy doping implantation in the first active region to form the source and drain regions of the NMOS transistor; Step S7: Perform P-type ion heavy doping implantation in the second active region to form the source and drain regions of the PMOS transistor.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, Step S3 specifically includes: A gate oxide layer and a gate material layer are formed sequentially covering the substrate; An imaged second photoresist layer is formed on the surface of the gate material layer, the imaged second photoresist layer comprising a first region of the second photoresist layer and a second region of the second photoresist layer; Using the second photoresist layer as a mask, the gate material layer and the gate oxide material layer are etched sequentially to form the first gate layer and the first gate oxide layer located below the first region of the second photoresist layer, and the second gate layer and the second gate oxide layer located below the second region of the second photoresist layer.

3. The method for forming a semiconductor device as described in claim 2, characterized in that, When performing the maskless N-type drain lightly doped ion implantation in step S4, the first region of the second photoresist layer and the second region of the second photoresist layer are still retained; After the maskless N-type drain lightly doped ion implantation is completed, the first region of the second photoresist layer and the second region of the second photoresist layer are removed.

4. The method for forming a semiconductor device as described in claim 1, characterized in that, Step S5 specifically includes: A third photoresist layer is formed, the third photoresist layer having an opening in the second active region and covering the first active region; using the third photoresist layer as a mask, the second active region is first implanted with N-well ions to form an N-well; then the second active region is implanted with lightly doped P-type drain ions to form a lightly doped P-type region.

5. The method for forming a semiconductor device as described in claim 4, characterized in that, In step S5, in the second active region, the N-well ion implantation depth is greater than the P-type drain lightly doped ion implantation depth, and the N-well ion implantation energy is greater than the P-type drain lightly doped ion implantation energy.

6. The method for forming a semiconductor device as described in claim 4, characterized in that, In step S5, the N-trap ion implantation also penetrates the second gate layer and the second gate oxide layer into the substrate below.

7. The method for forming a semiconductor device according to any one of claims 1 to 6, characterized in that, The operating voltage of the semiconductor device includes 7V or 5V.

8. The method for forming a semiconductor device as described in claim 1, characterized in that, After step S5 and before step S6, the forming method further includes: A first sidewall is formed on the substrate of the first active region, the first sidewall covering the sidewalls of the first gate oxide layer and the first gate layer; a second sidewall is formed on the substrate of the second active region, the second sidewall covering the sidewalls of the second gate oxide layer and the second gate layer.

9. The method for forming a semiconductor device as described in claim 8, characterized in that, After step S7, the forming method further includes: Metal silicides are formed on the surfaces of the first gate layer and the second gate layer, and on the substrate surfaces of the first active region and the second active region. A dielectric layer is formed, the dielectric layer covering the substrate, the first sidewall, the first gate layer, the second sidewall, and the second gate layer; a contact hole is formed in the dielectric layer; A metal interconnect is formed, the contact hole is filled with metal, and the gate, source and drain regions of the NMOS and PMOS transistors are brought out respectively.

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