Back contact solar cell and preparation method thereof

Abstract

The invention provides a back contact solar cell and a preparation method thereof, and relates to the technical field of back contact solar cells. The preparation method of the back contact solar cell comprises the steps that an isolation area, a P area and an N area are arranged on the back face of a silicon wafer, and the isolation area is located between the P area and the N area; forming a silicon dioxide mask layer only on the isolation region; after a silicon dioxide mask layer is formed on the isolation region, a P-type polycrystalline silicon layer is formed in the P region; after a silicon dioxide mask layer is formed on the isolation region, an N-type polycrystalline silicon layer is formed in the N region; and removing the silicon dioxide mask layer after the P-type polycrystalline silicon layer and the N-type polycrystalline silicon layer are formed. According to the scheme, high-temperature diffusion of impurity atoms can be blocked, and the problem that the photoelectric conversion efficiency of the battery is reduced due to the fact that boron and phosphorus impurity atoms exist at the junction of the P region and the N region at the same time is effectively solved.

Description

Technical Field

[0001] The present application relates to the technical field of back-contact solar cells, and in particular to a back-contact solar cell and a method for preparing the same. Background Art

[0002] Back contact solar cells are solar cells that have all metal contacts on the back of the cell. The main advantage of back contact solar cells is that they can maximize the illumination area on the front of the cell, thereby improving the photoelectric conversion efficiency. The PN junction and metal contacts of back contact solar cells are on the back of the cell, and the P and N regions are alternately arranged in a fork shape. If the P and N regions are not isolated, leakage problems are likely to occur.

[0003] The commonly used method for isolating the P region and the N region is to perform laser etching and grooving isolation at the junction of the P region and the N region after forming the P and N polysilicon passivation layers. Under this method, the P region and the N region are not isolated when the polysilicon is diffused, resulting in the presence of two impurity atoms, boron and phosphorus, at the junction, which in turn affects the photovoltaic conversion efficiency of the battery.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present application is to provide a back-contact solar cell and a method for preparing the same. Before diffusion to form polycrystalline silicon, a silicon dioxide mask layer is prepared on the isolation area. The silicon dioxide mask layer in the isolation area blocks the high-temperature diffusion of impurity atoms, thereby effectively alleviating the problem of decreased photoelectric conversion efficiency of the cell caused by the simultaneous presence of boron and phosphorus impurity atoms at the junction of the P region and the N region.

[0006] To achieve the above objectives, this application adopts the following technical solutions: A method for preparing a back-contact solar cell, comprising: An isolation region, a P region and an N region are provided on the back side of the silicon wafer, wherein the isolation region is between the P region and the N region; forming a silicon dioxide mask layer only on the isolation region; After forming the silicon dioxide mask layer on the isolation region, forming a P-type polysilicon layer in the P region; After forming the silicon dioxide mask layer on the isolation region, forming an N-type polysilicon layer in the N region; After forming the P-type polysilicon layer and the N-type polysilicon layer, the silicon dioxide mask layer is removed.

[0007] In some embodiments, the step of forming a silicon dioxide mask layer only on the isolation region includes: forming a silicon dioxide mask layer on the back side of the silicon wafer; Printing paraffin wax on the silicon dioxide mask layer located in the isolation area to form a first paraffin wax layer; Using an acid etching method, the silicon dioxide mask layer located in the P region and the N region is removed, and the silicon dioxide mask layer located in the isolation region is retained; The first wax layer is removed to expose the silicon dioxide mask layer located in the isolation region.

[0008] In some embodiments, forming a P-type polysilicon layer in the P region includes: forming a first polysilicon layer on the back side of the silicon wafer having the silicon dioxide mask layer; Performing boron diffusion treatment on the first polysilicon layer to form a P-type polysilicon layer; Printing paraffin wax on the P-type polysilicon layer located in the P region to form a second paraffin wax layer; Using an alkaline etching method, removing the P-type polysilicon layer located in the N region and the isolation region, and retaining the P-type polysilicon layer located in the P region; The second wax layer is removed to expose the P-type polysilicon layer located in the P region.

[0009] In some embodiments, before forming the first polysilicon layer, a first tunneling layer is formed on the back side of the silicon wafer having the silicon dioxide mask layer; After removing the P-type polysilicon layer located in the N region and the isolation region, using an acid etching method to remove the first tunneling layer located in the N region and the isolation region, and retaining the first tunneling layer located in the P region; Wherein, the thickness of the first tunneling layer is less than the thickness of the silicon dioxide mask layer.

[0010] In some embodiments, forming an N-type polysilicon layer in the N region includes: forming a second polysilicon layer on the back side of the silicon wafer having the silicon dioxide mask layer; performing phosphorus diffusion treatment on the second polysilicon layer to form an N-type polysilicon layer; Printing paraffin wax on the N-type polysilicon layer located in the N region to form a third paraffin wax layer; Using an alkaline etching method, removing the N-type polysilicon layer located in the P region and the isolation region, and retaining the N-type polysilicon layer located in the N region; The third wax layer is removed to expose the N-type polysilicon layer located in the N region.

[0011] In some embodiments, it also includes: Before forming the second polysilicon layer, forming a second tunneling layer on the back side of the silicon wafer having the silicon dioxide mask layer; After removing the N-type polysilicon layer located in the P region and the isolation region, using an acid etching method to remove the second tunneling layer located in the P region and the isolation region, and retaining the second tunneling layer located in the N region; Wherein, the thickness of the second tunneling layer is less than the thickness of the silicon dioxide mask layer.

[0012] In some embodiments, after removing the silicon dioxide mask layer, the method further comprises: forming an anti-reflection film on the front side of the silicon wafer; forming a passivation film on the back side of the silicon wafer; A P-region metal electrode and an N-region metal electrode are formed on the P-region and the N-region, respectively.

[0013] In some embodiments, the thickness of the silicon dioxide mask layer is 50-60 nm.

[0014] In some embodiments, forming a silicon dioxide mask layer on the back side of the silicon wafer includes: preparing the silicon dioxide mask layer by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 580~650°C, the pressure is controlled at 60~80kPa, and the deposition time is controlled at 40~80min.

[0015] The present application also provides a back-contact solar cell, which is prepared by the above method.

[0016] In some embodiments, the back contact solar cell satisfies at least one of the following characteristics: (1) The width of the P region is 300~400μm; (2) The width of the N region is 360~460μm; (3) The width of the isolation area is 40~70μm; (4) The etching depth of the N region is 1.5~2.5μm; (5) The isolation area is a polished surface.

[0017] In the technical solution of the present application, a silicon dioxide mask layer is prepared on the isolation area before diffusion to form polysilicon. The silicon dioxide mask layer in the isolation area blocks the high-temperature diffusion of impurity atoms, effectively alleviating the problem of decreased photoelectric conversion efficiency of the battery caused by the coexistence of boron and phosphorus impurity atoms at the junction of the P region and the N region. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application. Figure 1 A diagram showing changes in the cell structure during the preparation of a back-contact solar cell in an embodiment of the present application. DETAILED DESCRIPTION

[0019] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0020] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0021] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0024] The embodiment of the present application aims to provide a back-contact solar cell and a method for preparing the same. In the technical solution of the present application, a silicon dioxide mask layer is prepared on the isolation region before diffusion to form polysilicon. The silicon dioxide mask layer in the isolation region blocks the high-temperature diffusion of impurity atoms, effectively alleviating the problem of reduced photovoltaic conversion efficiency of the cell caused by the coexistence of two impurity atoms, boron and phosphorus, at the junction of the P region and the N region. In addition, the technical solution of the present application prepares a silicon dioxide mask layer on the isolation region, and does not prepare a polysilicon layer in the isolation region, so there is no need for alkaline solution etching, thereby avoiding damage to the silicon substrate and improving the stability of the battery.

[0025] The present application provides a method for preparing a back-contact solar cell, comprising: An isolation region, a P region and an N region are provided on the back side of the silicon wafer, wherein the isolation region is between the P region and the N region; forming a silicon dioxide mask layer only on the isolation region; After forming the silicon dioxide mask layer on the isolation region, forming a P-type polysilicon layer in the P region; After forming the silicon dioxide mask layer on the isolation region, forming an N-type polysilicon layer in the N region; After forming the P-type polysilicon layer and the N-type polysilicon layer, the silicon dioxide mask layer is removed.

[0026] In the embodiment of the present application, a boron diffusion process can be used to form a P-type polysilicon layer in the P region; a phosphorus diffusion process can be used to form an N-type polysilicon layer in the N region; the preparation process of the N-type polysilicon layer and the P-type polysilicon layer can be selected according to actual needs. It should be noted that after forming a silicon dioxide mask layer on the isolation region, a P-type polysilicon layer can be formed in the P region first, and then an N-type polysilicon layer can be formed in the N region; an N-type polysilicon layer can be formed in the N region first, and then a P-type polysilicon layer can be formed in the P region; the preparation order of the N-type polysilicon layer and the P-type polysilicon layer can be set according to actual needs. Similarly, each function on the P region can be prepared first, and then each function on the N region; each function on the N region can also be prepared first, and then each function on the P region.

[0027] In an embodiment of the present application, the width of the isolation region may be 10 to 90 μm (e.g., 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm). The thickness of the P-type polysilicon layer may be 50 to 500 nm (e.g., 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm). The thickness of the N-type polysilicon layer may be 50 to 500 nm (e.g., 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm). The thickness of the silicon dioxide mask layer can be 20~100nm (for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm). It should be noted that the thickness of each layer can be set according to actual needs, and the width of the isolation region can also be set according to actual needs. In the embodiment of the present application, a silicon dioxide mask layer is prepared on the isolation region, and then each functional layer is prepared in the P region and the N region respectively, which can prevent the functional layers in the P region and the functional layers in the N region from affecting each other during the preparation process. It should be noted that the thickness of the silicon dioxide mask layer is greater than the thickness of the first tunneling layer and the second tunneling layer.

[0028] In the embodiments of the present application, the preparation methods of the silicon dioxide mask layer can be selected from one or more of wet oxidation, plasma enhanced chemical vapor deposition, and electrochemical anodization. The preparation methods of the first polysilicon layer and the second polysilicon layer can be selected from one or more of plasma enhanced chemical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, and physical vapor deposition.

[0029] In the embodiment of the present application, before the diffusion forms polysilicon (N-type polysilicon layer and P-type polysilicon layer), a silicon dioxide mask layer is prepared on the isolation area. The silicon dioxide mask layer in the isolation area blocks the high-temperature diffusion of impurity atoms, effectively alleviating the problem of reduced photoelectric conversion efficiency of the battery caused by the coexistence of two impurity atoms, boron and phosphorus, at the junction of the P area and the N area. In addition, the technical solution of the present application prepares a silicon dioxide mask layer on the isolation area, and does not prepare a polysilicon layer in the isolation area, so there is no need for alkaline etching, thereby avoiding damage to the silicon substrate and improving the stability of the battery.

[0030] In an optional embodiment, the step of forming a silicon dioxide mask layer only on the isolation region includes: forming a silicon dioxide mask layer on the back side of the silicon wafer; Printing paraffin wax on the silicon dioxide mask layer located in the isolation area to form a first paraffin wax layer; Using an acid etching method, the silicon dioxide mask layer located in the P region and the N region is removed, and the silicon dioxide mask layer located in the isolation region is retained; The first wax layer is removed to expose the silicon dioxide mask layer located in the isolation region.

[0031] In the embodiment of the present application, the thickness of the silicon dioxide mask layer can be 20~100nm (for example, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm). In the embodiment of the present application, a paraffin layer is used to assist in preparing the silicon dioxide mask layer in the isolation area without laser damage, which can improve the short-circuit current and open-circuit voltage of the battery, thereby improving the photoelectric conversion efficiency of the battery. In the embodiment of the present application, a silicon dioxide mask layer is prepared on the isolation area, and then each functional layer is prepared in the P area and the N area respectively, which can prevent the functional layers in the P area and the functional layers in the N area from affecting each other during the preparation process.

[0032] In an optional embodiment, forming a P-type polysilicon layer in the P region includes: forming a first polysilicon layer on the back side of the silicon wafer having the silicon dioxide mask layer; Performing boron diffusion treatment on the first polysilicon layer to form a P-type polysilicon layer; Printing paraffin wax on the P-type polysilicon layer located in the P region to form a second paraffin wax layer; Using an alkaline etching method, removing the P-type polysilicon layer located in the N region and the isolation region, and retaining the P-type polysilicon layer located in the P region; The second wax layer is removed to expose the P-type polysilicon layer located in the P region.

[0033] In the embodiment of the present application, before diffusion to form polysilicon (N-type polysilicon layer and P-type polysilicon layer), a silicon dioxide mask layer is prepared on the isolation area. The silicon dioxide mask layer in the isolation area blocks the high-temperature diffusion of impurity atoms, thereby effectively alleviating the problem of decreased photoelectric conversion efficiency of the battery caused by the coexistence of boron and phosphorus impurity atoms at the junction of the P region and the N region.

[0034] In the embodiment of the present application, the thickness of the first polysilicon layer can be 250-350 nm (for example, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm). In the embodiment of the present application, optimizing the thickness of the first polysilicon layer can improve the stability and passivation effect of the interface, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0035] In the embodiment of the present application, a paraffin layer is used to assist in preparing the P-type polysilicon layer in the P region without laser damage, which can increase the short-circuit current and open-circuit voltage of the battery, thereby improving the photoelectric conversion efficiency of the battery.

[0036] In an optional embodiment, before forming the first polysilicon layer, a first tunneling layer is formed on the back side of the silicon wafer having the silicon dioxide mask layer; After removing the P-type polysilicon layer located in the N region and the isolation region, using an acid etching method to remove the first tunneling layer located in the N region and the isolation region, and retaining the first tunneling layer located in the P region; Wherein, the thickness of the first tunneling layer is less than the thickness of the silicon dioxide mask layer.

[0037] In the embodiment of the present application, the thickness of the first tunneling layer may be 1 to 30 nm (for example, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm); the thickness of the first tunneling layer may be set according to actual needs.

[0038] In an optional embodiment, the forming of an N-type polysilicon layer in the N region includes: forming a second polysilicon layer on the back side of the silicon wafer having the silicon dioxide mask layer; performing phosphorus diffusion treatment on the second polysilicon layer to form an N-type polysilicon layer; Printing paraffin wax on the N-type polysilicon layer located in the N region to form a third paraffin wax layer; Using an alkaline etching method, removing the N-type polysilicon layer located in the P region and the isolation region, and retaining the N-type polysilicon layer located in the N region; The third wax layer is removed to expose the N-type polysilicon layer located in the N region.

[0039] In the embodiment of the present application, before diffusion to form polysilicon (N-type polysilicon layer and P-type polysilicon layer), a silicon dioxide mask layer is prepared on the isolation area. The silicon dioxide mask layer in the isolation area blocks the high-temperature diffusion of impurity atoms, thereby effectively alleviating the problem of decreased photoelectric conversion efficiency of the battery caused by the coexistence of boron and phosphorus impurity atoms at the junction of the P region and the N region.

[0040] In the embodiment of the present application, the thickness of the second polysilicon layer can be 180-250 nm (for example, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm). In the embodiment of the present application, optimizing the thickness of the second polysilicon layer can improve the stability and passivation effect of the interface, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0041] In the embodiment of the present application, a paraffin layer is used to assist in preparing the N-type polysilicon layer in the N region without laser damage, which can increase the short-circuit current and open-circuit voltage of the battery, thereby improving the photoelectric conversion efficiency of the battery.

[0042] In an optional embodiment, it also includes: Before forming the second polysilicon layer, forming a second tunneling layer on the back side of the silicon wafer having the silicon dioxide mask layer; After removing the N-type polysilicon layer located in the P region and the isolation region, using an acid etching method to remove the second tunneling layer located in the P region and the isolation region, and retaining the second tunneling layer located in the N region; Wherein, the thickness of the second tunneling layer is less than the thickness of the silicon dioxide mask layer.

[0043] In the embodiment of the present application, the thickness of the second tunneling layer may be 1 to 30 nm (for example, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm); the thickness of the second tunneling layer may be set according to actual needs.

[0044] In an optional embodiment, after removing the silicon dioxide mask layer, the method further includes: forming an anti-reflection film on the front side of the silicon wafer; forming a passivation film on the back side of the silicon wafer; A P-region metal electrode and an N-region metal electrode are formed on the P-region and the N-region, respectively.

[0045] In an optional embodiment, the thickness of the silicon dioxide mask layer is 50-60 nm (for example, 50 nm, 51 nm, 52 nm, 53 nm, 54 nm, 55 nm, 56 nm, 57 nm, 58 nm, 59 nm, 60 nm).

[0046] In the embodiment of the present application, optimizing the thickness of the silicon dioxide mask layer is beneficial to blocking the diffusion of impurity atoms at the junction, and can effectively alleviate the problem of decreased photoelectric conversion efficiency of the battery caused by the coexistence of boron and phosphorus impurity atoms at the junction of the P region and the N region, thereby improving the photoelectric conversion efficiency of the battery.

[0047] In an optional embodiment, forming a silicon dioxide mask layer on the back side of the silicon wafer includes: preparing the silicon dioxide mask layer by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 580~650°C (for example, 580°C, 590°C, 600°C, 610°C, 620°C, 630°C, 640°C, 650°C), the pressure is controlled at 60~80kPa (for example, 60kPa, 65kPa, 70kPa, 75kPa, 80kPa), and the deposition time is controlled at 40~80min (for example, 40min, 45min, 50min, 55min, 60min, 65min, 70min, 75min, 80min).

[0048] In the embodiment of the present application, the preparation method of the silicon dioxide mask layer is optimized, which can improve the deposition quality of the silicon dioxide mask layer, is beneficial to blocking the diffusion of impurity atoms at the junction, and can effectively alleviate the problem of decreased photoelectric conversion efficiency of the battery caused by the coexistence of boron and phosphorus impurity atoms at the junction of the P region and the N region, thereby improving the photoelectric conversion efficiency of the battery.

[0049] The present application also provides a back-contact solar cell, which is prepared by the above method.

[0050] In an optional embodiment, the back contact solar cell satisfies at least one of the following characteristics: (1) The width of the P region is 300~400μm (for example, 300μm, 310μm, 320μm, 330μm, 340μm, 350μm, 360μm, 370μm, 380μm, 390μm, 400μm); (2) The width of the N region is 360 to 460 μm (for example, 360 μm, 370 μm, 380 μm, 390 μm, 400 μm, 410 μm, 420 μm, 430 μm, 440 μm, 450 μm, 460 μm); (3) The width of the isolation region is 40 to 70 μm (e.g., 40 μm, 50 μm, 60 μm, 70 μm); (4) The etching depth of the N region is 1.5~2.5μm (for example, 1.5μm, 1.7μm, 1.9μm, 2.1μm, 2.3μm, 2.5μm); (5) The isolation area is a polished surface.

[0051] In the embodiment of the present application, the parameters of each region are limited, that is, the back surface of the silicon wafer is patterned, which can enhance the light absorption capacity of the silicon wafer, thereby generating current gain, and further improving the photoelectric conversion efficiency of the solar cell. In the embodiment of the present application, the isolation region is a polished surface rather than a velvet groove, which can increase the back reflectivity and thus improve the photoelectric conversion efficiency of the cell.

[0052] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application.

[0053] Example 1 A method for preparing a back-contact solar cell, comprising: (1) Double-sided texturing is performed on the silicon wafer to form a pyramid light trapping structure on the front and back sides of the silicon wafer to obtain the first target silicon wafer; see Figure 1 Step.1; (2) thermally oxidizing the front surface of the first target silicon wafer to generate a first silicon oxide layer with a thickness of 50 nm, and thermally oxidizing the back surface of the first target silicon wafer to generate a silicon oxide layer with a thickness of 50 nm, to obtain a second target silicon wafer; Figure 1 Step.2; (3) removing the silicon oxide layer, and then polishing the back of the second target silicon wafer to form a flat polished surface; and then preparing a silicon dioxide mask layer with a thickness of 50 nm on the polished surface to obtain a third target silicon wafer; the method for preparing the silicon dioxide mask layer comprises: taking the second target silicon wafer, and preparing a silicon dioxide mask layer on the polished surface by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 580°C, the pressure is controlled at 60 kPa, and the deposition time is controlled at 40 min; see Figure 1 Step.3; (4) using paraffin to print an isolation area on the back side of the third target silicon wafer to form a first paraffin mask area and a first non-paraffin mask area, and then using chain HF to remove the silicon dioxide mask layer in the first non-paraffin mask area to obtain a fourth target silicon wafer; see Figure 1 Step.4; (5) Using low pressure chemical vapor deposition (LPCVD), a first tunneling layer with a thickness of 1 nm and a first polysilicon layer with a thickness of 250 nm are sequentially deposited on the back side of the fourth target silicon wafer, and then the first polysilicon layer is subjected to high temperature boron diffusion treatment to form a P-type polysilicon layer and a BSG layer, thereby obtaining a fifth target silicon wafer; the isolation region is protected by a silicon dioxide mask layer with a thickness of about 50 nm, which can effectively block the diffusion of impurity atoms; see Figure 1 Step.5; (6) Printing a P region pattern on the back side of the fifth target silicon wafer with paraffin to form a second paraffin mask area and a second non-paraffin mask area, and then removing the BSG layer of the second non-paraffin mask area with chain HF to obtain a sixth target silicon wafer; see Figure 1 Step.6; (7) removing the paraffin layer on the second paraffin mask area to obtain a seventh target silicon wafer; Figure 1 Step.7; (8) using an alkaline etching method to clean and etch away the exposed P-type polysilicon layer of the seventh target silicon wafer, and then removing the exposed first tunneling layer to obtain an eighth target silicon wafer; Figure 1 Step.8; (9) on the back side of the eighth target silicon wafer, a second tunneling layer with a thickness of 1 nm and a second polysilicon layer with a thickness of 180 nm are sequentially prepared, and the second polysilicon layer is subjected to a high temperature phosphorus diffusion treatment to form an N-type polysilicon layer and a PSG layer, thereby obtaining a ninth target silicon wafer; Figure 1 Step.9; (10) Printing an N-region pattern on the back side of the ninth target silicon wafer with paraffin to form a third paraffin mask region and a third non-paraffin mask region, thereby obtaining a tenth target silicon wafer; Figure 1 Step.10; (11) removing the PSG layer on the third non-paraffin mask area by chain HF to obtain an eleventh target silicon wafer; Figure 1 Step.11; (12) removing the wax layer on the third wax mask area, then cleaning and etching the exposed N-type polysilicon layer of the eleventh target silicon wafer by an alkaline etching method, and then removing the exposed second tunneling layer to obtain a twelfth target silicon wafer; Figure 1 Step.12; (13) removing the first silicon oxide layer, the BSG layer and the PSG layer of the twelfth target silicon wafer to obtain a thirteenth target silicon wafer; Figure 1 Step.13; (14) preparing an anti-reflection film on the front side of the thirteenth target silicon wafer and preparing a passivation film on the back side of the thirteenth target silicon wafer to obtain a fourteenth target silicon wafer; Figure 1 Step.14; (15) Print the P-region metal electrode and the N-region metal electrode on the back of the fourteenth target silicon wafer, and then sinter them. The back contact solar cell meets the following requirements: the width of the P-region is 300 μm, the width of the N-region is 360 μm, the width of the isolation region is 40 μm, and the etching depth of the N-region is 1.5 μm. The changes in the cell structure during the preparation of the back contact solar cell are as follows: Figure 1More specifically, in the embodiment of the present application, the etching depth of the N region refers to the etching depth of the N region caused when the P-type polysilicon layer exposed by the seventh target silicon wafer is cleaned and etched away, and then the exposed first tunneling layer is removed. Figure 1 Step 15. The back-contact solar cell is prepared by the process of step (1) to step (15), and the separation of the P region and the N region can be completed without the aid of laser etching, without laser damage, thereby further improving the short-circuit current and open-circuit voltage of the battery, thereby improving the photoelectric conversion efficiency of the battery.

[0054] Example 2 A method for preparing a back-contact solar cell, comprising: (1) Performing double-sided texturing on a silicon wafer to form pyramid light-trapping structures on the front and back sides of the silicon wafer, respectively, to obtain a first target silicon wafer; (2) thermally oxidizing the front side of the first target silicon wafer to generate a first silicon oxide layer with a thickness of 60 nm, and thermally oxidizing the back side of the first target silicon wafer to generate a silicon oxide layer with a thickness of 60 nm, thereby obtaining a second target silicon wafer; (3) removing the silicon oxide layer, and then polishing the back side of the second target silicon wafer to form a flat polished surface; and then preparing a silicon dioxide mask layer with a thickness of 60 nm on the polished surface to obtain a third target silicon wafer; the method for preparing the silicon dioxide mask layer comprises: taking the second target silicon wafer, and preparing a silicon dioxide mask layer on the polished surface by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 650°C, the pressure is controlled at 80 kPa, and the deposition time is controlled at 80 min; (4) printing an isolation area on the back side of the third target silicon wafer with paraffin wax to form a first paraffin wax mask area and a first non-paraffin wax mask area, and then removing the silicon dioxide mask layer in the first non-paraffin wax mask area with chain HF to obtain a fourth target silicon wafer; (5) using a low pressure chemical vapor deposition (LPCVD) method, depositing a first tunneling layer with a thickness of 30 nm and a first polysilicon layer with a thickness of 350 nm on the back side of the fourth target silicon wafer in sequence, and then performing a high temperature boron diffusion treatment on the first polysilicon layer to form a P-type polysilicon layer and a BSG layer, thereby obtaining a fifth target silicon wafer; (6) printing a P region pattern on the back side of the fifth target silicon wafer with paraffin wax to form a second paraffin wax mask region and a second non-paraffin wax mask region, and then removing the BSG layer of the second non-paraffin wax mask region with chain HF to obtain a sixth target silicon wafer; (7) removing the paraffin layer on the second paraffin mask area to obtain a seventh target silicon wafer; (8) using an alkaline etching method to clean and etch away the exposed P-type polysilicon layer of the seventh target silicon wafer, and then removing the exposed first tunneling layer to obtain an eighth target silicon wafer; (9) sequentially preparing a second tunneling layer with a thickness of 30 nm and a second polysilicon layer with a thickness of 250 nm on the back side of the eighth target silicon wafer, and performing a high-temperature phosphorus diffusion treatment on the second polysilicon layer to form an N-type polysilicon layer and a PSG layer, thereby obtaining a ninth target silicon wafer; (10) Printing an N-region pattern on the back side of the ninth target silicon wafer using paraffin wax to form a third paraffin wax masking region and a third non-paraffin wax masking region, thereby obtaining a tenth target silicon wafer; (11) removing the PSG layer on the third non-paraffin mask area by chain HF to obtain an eleventh target silicon wafer; (12) removing the wax layer on the third wax mask area, then cleaning and etching the exposed N-type polysilicon layer of the eleventh target silicon wafer using an alkaline etching method, and then removing the exposed second tunneling layer to obtain a twelfth target silicon wafer; (13) removing the first silicon oxide layer, the BSG layer, and the PSG layer of the twelfth target silicon wafer to obtain a thirteenth target silicon wafer; (14) preparing an anti-reflection film on the front side of the thirteenth target silicon wafer and preparing a passivation film on the back side of the thirteenth target silicon wafer to obtain a fourteenth target silicon wafer; (15) Printing a P-region metal electrode and an N-region metal electrode on the back of the fourteenth target silicon wafer respectively and sintering them. The back contact solar cell satisfies: the width of the P-region is 400 μm, the width of the N-region is 460 μm, the width of the isolation region is 70 μm, and the etching depth of the N-region is 2.5 μm.

[0055] Example 3 The back contact solar cell of Example 3 was prepared by referring to the preparation method of Example 1, except that: Step (2) in Example 3 is: thermally oxidize the front side of the first target silicon wafer to generate a first silicon oxide layer with a thickness of 40 nm, and thermally oxidize the back side of the first target silicon wafer to generate a silicon oxide layer with a thickness of 40 nm, to obtain a second target silicon wafer.

[0056] Example 4 The back contact solar cell of Example 4 was prepared by referring to the preparation method of Example 1, except that: Step (2) in Example 4 is: thermally oxidize the front side of the first target silicon wafer to generate a first silicon oxide layer with a thickness of 70 nm, and thermally oxidize the back side of the first target silicon wafer to generate a silicon oxide layer with a thickness of 70 nm, to obtain a second target silicon wafer.

[0057] Example 5 The back contact solar cell of Example 5 was prepared by referring to the preparation method of Example 1, except that: Step (3) in Example 5 is: removing the silicon oxide layer, and then polishing the back side of the second target silicon wafer to form a flat polished surface; and then preparing a silicon dioxide mask layer with a thickness of 40 nm on the polished surface to obtain a third target silicon wafer; the method for preparing the silicon dioxide mask layer comprises: taking the second target silicon wafer, and preparing a silicon dioxide mask layer on the polished surface by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 580° C., the pressure is controlled at 60 kPa, and the deposition time is controlled at 40 min.

[0058] Example 6 The back contact solar cell of Example 6 was prepared by referring to the preparation method of Example 1, except that: Step (3) in Example 6 is: removing the silicon oxide layer, and then polishing the back side of the second target silicon wafer to form a flat polished surface; and then preparing a silicon dioxide mask layer with a thickness of 70 nm on the polished surface to obtain a third target silicon wafer; the method for preparing the silicon dioxide mask layer comprises: taking the second target silicon wafer, and preparing a silicon dioxide mask layer on the polished surface by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 580° C., the pressure is controlled at 60 kPa, and the deposition time is controlled at 40 min.

[0059] Example 7 The back contact solar cell of Example 7 was prepared by referring to the preparation method of Example 1, except that: Step (3) in Example 7 is: removing the silicon oxide layer, and then polishing the back side of the second target silicon wafer to form a flat polished surface; and then preparing a silicon dioxide mask layer with a thickness of 50 nm on the polished surface to obtain a third target silicon wafer; the method for preparing the silicon dioxide mask layer comprises: taking the second target silicon wafer, and preparing a silicon dioxide mask layer on the polished surface by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 550° C., the pressure is controlled at 50 kPa, and the deposition time is controlled at 30 min.

[0060] Example 8 The back contact solar cell of Example 8 was prepared by referring to the preparation method of Example 1, except that: Step (3) in Example 8 is: removing the silicon oxide layer, and then polishing the back side of the second target silicon wafer to form a flat polished surface; and then preparing a silicon dioxide mask layer with a thickness of 50 nm on the polished surface to obtain a third target silicon wafer; the method for preparing the silicon dioxide mask layer comprises: taking the second target silicon wafer, and preparing a silicon dioxide mask layer on the polished surface by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 700° C., the pressure is controlled at 90 kPa, and the deposition time is controlled at 90 min.

[0061] Example 9 The back contact solar cell of Example 9 was prepared by referring to the preparation method of Example 1, except that: Step (3) in Example 9 is: removing the silicon oxide layer, and then polishing the back side of the second target silicon wafer to form a flat polished surface; and then preparing a silicon dioxide mask layer with a thickness of 50 nm on the polished surface to obtain a third target silicon wafer; the method for preparing the silicon dioxide mask layer comprises: taking the second target silicon wafer, and preparing a silicon dioxide mask layer on the polished surface by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 580° C., the pressure is one atmosphere, and the deposition time is controlled at 40 minutes.

[0062] Example 10 The back contact solar cell of Example 10 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 10 is: using low pressure chemical vapor deposition (LPCVD) to deposit a first tunneling layer with a thickness of 1 nm and a first polysilicon layer with a thickness of 200 nm on the back side of the fourth target silicon wafer, and then performing high temperature boron diffusion treatment on the first polysilicon layer to form a P-type polysilicon layer and a BSG layer, thereby obtaining a fifth target silicon wafer.

[0063] Embodiment 11 The back contact solar cell of Example 11 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 11 is: using low pressure chemical vapor deposition (LPCVD) to deposit a first tunneling layer with a thickness of 1 nm and a first polysilicon layer with a thickness of 400 nm on the back side of the fourth target silicon wafer, and then performing high temperature boron diffusion treatment on the first polysilicon layer to form a P-type polysilicon layer and a BSG layer, thereby obtaining a fifth target silicon wafer.

[0064] Example 12 The back contact solar cell of Example 12 was prepared by referring to the preparation method of Example 1, except that: Step (9) in Example 12 is: on the back side of the eighth target silicon wafer, a second tunneling layer with a thickness of 1 nm and a second polysilicon layer with a thickness of 150 nm are sequentially prepared, and the second polysilicon layer is subjected to a high-temperature phosphorus diffusion treatment to form an N-type polysilicon layer and a PSG layer, thereby obtaining a ninth target silicon wafer.

[0065] Embodiment 13 The back contact solar cell of Example 13 was prepared by referring to the preparation method of Example 1, except that: Step (9) in Example 13 is: preparing a second tunneling layer with a thickness of 1 nm and a second polysilicon layer with a thickness of 300 nm on the back side of the eighth target silicon wafer in sequence, and performing a high-temperature phosphorus diffusion treatment on the second polysilicon layer to form an N-type polysilicon layer and a PSG layer, thereby obtaining a ninth target silicon wafer.

[0066] Embodiment 14 The back contact solar cell of Example 14 was prepared by referring to the preparation method of Example 1, except that: The back-contact solar cell in Example 14 satisfies the following conditions: the width of the P region is 280 μm, the width of the N region is 350 μm, the width of the isolation region is 30 μm, and the etching depth of the N region is 1.3 μm.

[0067] Embodiment 15 The back contact solar cell of Example 15 was prepared by referring to the preparation method of Example 1, except that: The back-contact solar cell in Example 15 satisfies the following requirements: the width of the P region is 430 μm, the width of the N region is 480 μm, the width of the isolation region is 80 μm, and the etching depth of the N region is 2.8 μm.

[0068] Comparative Example 1 A method for preparing a back-contact solar cell comprises depositing a tunneling layer and a polysilicon layer on the back of a silicon wafer in sequence, performing high-temperature boron diffusion treatment and high-temperature phosphorus diffusion treatment, and after forming P and N polysilicon passivation layers, laser etching and grooving isolation are performed at the junction of the P region and the N region; then the front and back of the cell are passivated, and finally, the P region metal electrode and the N region metal electrode are printed on the back of the cell respectively, and sintered.

[0069] Photoelectric tests were performed on the back-contact solar cells prepared in the above embodiments and comparative examples. The test results are shown in Table 1 below.

[0070] Table 1

[0071] Referring to the detection data of the above-mentioned embodiments 1-15, it can be known that before diffusion to form polysilicon, a silicon dioxide mask layer is prepared on the isolation area. The silicon dioxide mask layer in the isolation area blocks the high-temperature diffusion of impurity atoms, effectively alleviating the problem of decreased photoelectric conversion efficiency of the battery caused by the coexistence of two impurity atoms, boron and phosphorus, at the junction of the P region and the N region; and there is no laser damage, which can increase the short-circuit current and open-circuit voltage of the battery, thereby improving the photoelectric conversion efficiency of the battery.

[0072] Referring to the test data of the above-mentioned Example 1 and Examples 5-6, it can be seen that optimizing the thickness of the silicon dioxide mask layer is beneficial to blocking the diffusion of impurity atoms at the junction, and can effectively alleviate the problem of decreased photoelectric conversion efficiency of the battery caused by the coexistence of boron and phosphorus impurity atoms at the junction of the P region and the N region, thereby improving the photoelectric conversion efficiency of the battery.

[0073] With reference to the detection data of the above-mentioned Example 1 and Examples 7-9, it can be seen that optimizing the preparation method of the silicon dioxide mask layer can improve the deposition quality of the silicon dioxide mask layer, which is beneficial to blocking the diffusion of impurity atoms at the junction, and can effectively alleviate the problem of decreased photoelectric conversion efficiency of the battery caused by the simultaneous presence of boron and phosphorus impurity atoms at the junction of the P region and the N region, thereby improving the photoelectric conversion efficiency of the battery.

[0074] It can be seen from the test data of the above-mentioned embodiment 1 and embodiments 10-11 that optimizing the thickness of the first polysilicon layer can improve the stability and passivation effect of the interface, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0075] Referring to the test data of the above-mentioned embodiment 1 and embodiments 12-13, it can be known that optimizing the thickness of the second polysilicon layer can improve the stability and passivation effect of the interface, thereby further improving the photoelectric conversion efficiency of the solar cell.

[0076] Referring to the detection data of the above-mentioned Example 1 and Examples 14-15, it can be known that limiting the parameters of each area, that is, patterning the back side of the silicon wafer, can enhance the light absorption capacity of the silicon wafer, thereby generating current gain, and further improving the photoelectric conversion efficiency of the solar cell.

[0077] The above-mentioned embodiments 1-15 are optimized manufacturing process routes of back-contact solar cells, which have the characteristics of high process stability. It should be noted that the manufacturing process route of back-contact solar cells can also be other process routes, and it is only necessary to prepare a silicon dioxide mask layer on the isolation area before diffusion to form polysilicon to block the high-temperature diffusion of impurity atoms.

[0078] In summary, before the diffusion to form polysilicon, the present application prepares a silicon dioxide mask layer on the isolation area. The silicon dioxide mask layer in the isolation area blocks the high-temperature diffusion of impurity atoms, effectively alleviating the problem of decreased photoelectric conversion efficiency of the battery caused by the simultaneous presence of boron and phosphorus impurity atoms at the junction of the P region and the N region.

[0079] The present application can provide a back-contact solar cell (not shown), which is prepared by the above method.

[0080] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0081] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0082] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for preparing a back contact solar cell, characterized in that: include: An isolation region, a P region and an N region are provided on the back side of the silicon wafer, wherein the isolation region is between the P region and the N region; forming a silicon dioxide mask layer only on the isolation region; After forming the silicon dioxide mask layer on the isolation region, forming a P-type polysilicon layer in the P region; After forming the silicon dioxide mask layer on the isolation region, forming an N-type polysilicon layer in the N region; After forming the P-type polysilicon layer and the N-type polysilicon layer, the silicon dioxide mask layer is removed.

2. The method according to claim 1, characterized in that The step of forming a silicon dioxide mask layer only on the isolation region comprises: forming a silicon dioxide mask layer on the back side of the silicon wafer; Printing paraffin wax on the silicon dioxide mask layer located in the isolation area to form a first paraffin wax layer; Using an acid etching method, the silicon dioxide mask layer located in the P region and the N region is removed, and the silicon dioxide mask layer located in the isolation region is retained; The first wax layer is removed to expose the silicon dioxide mask layer located in the isolation region.

3. The method according to claim 1, characterized in that The forming of a P-type polysilicon layer in the P region comprises: forming a first polysilicon layer on the back side of the silicon wafer having the silicon dioxide mask layer; Performing boron diffusion treatment on the first polysilicon layer to form a P-type polysilicon layer; Printing paraffin wax on the P-type polysilicon layer located in the P region to form a second paraffin wax layer; Using an alkaline etching method, removing the P-type polysilicon layer located in the N region and the isolation region, and retaining the P-type polysilicon layer located in the P region; The second wax layer is removed to expose the P-type polysilicon layer located in the P region.

4. The method according to claim 3, characterized in that Also includes: Before forming the first polysilicon layer, forming a first tunneling layer on the back side of the silicon wafer having the silicon dioxide mask layer; After removing the P-type polysilicon layer located in the N region and the isolation region, using an acid etching method to remove the first tunneling layer located in the N region and the isolation region, and retaining the first tunneling layer located in the P region; Wherein, the thickness of the first tunneling layer is less than the thickness of the silicon dioxide mask layer.

5. The method according to claim 1, characterized in that The forming of an N-type polysilicon layer in the N region comprises: forming a second polysilicon layer on the back side of the silicon wafer having the silicon dioxide mask layer; performing phosphorus diffusion treatment on the second polysilicon layer to form an N-type polysilicon layer; Printing paraffin wax on the N-type polysilicon layer located in the N region to form a third paraffin wax layer; Using an alkaline etching method, removing the N-type polysilicon layer located in the P region and the isolation region, and retaining the N-type polysilicon layer located in the N region; The third wax layer is removed to expose the N-type polysilicon layer located in the N region.

6. The method according to claim 5, characterized in that Also includes: Before forming the second polysilicon layer, forming a second tunneling layer on the back side of the silicon wafer having the silicon dioxide mask layer; After removing the N-type polysilicon layer located in the P region and the isolation region, using an acid etching method to remove the second tunneling layer located in the P region and the isolation region, and retaining the second tunneling layer located in the N region; Wherein, the thickness of the second tunneling layer is less than the thickness of the silicon dioxide mask layer.

7. The method according to claim 1, characterized in that After removing the silicon dioxide mask layer, the method further comprises: forming an anti-reflection film on the front side of the silicon wafer; forming a passivation film on the back side of the silicon wafer; A P-region metal electrode and an N-region metal electrode are formed on the P-region and the N-region, respectively.

8. The method according to claim 1, characterized in that The thickness of the silicon dioxide mask layer is 50-60 nm.

9. The method according to claim 2, characterized in that: The forming of the silicon dioxide mask layer on the back side of the silicon wafer comprises: preparing the silicon dioxide mask layer by low-pressure chemical vapor deposition; during the deposition of the silicon dioxide mask layer, the temperature is controlled at 580-650° C., the pressure is controlled at 60-80 kPa, and the deposition time is controlled at 40-80 min.

10. A back contact solar cell, characterized in that: The method is prepared by any one of claims 1 to 9.

11. The back contact solar cell according to claim 10, characterized in that: The back contact solar cell meets at least one of the following characteristics: (1) The width of the P region is 300~400μm; (2) The width of the N region is 360~460μm; (3) The width of the isolation area is 40~70μm; (4) The etching depth of the N region is 1.5~2.5μm; (5) The isolation area is a polished surface.

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