Light-emitting diode and light-emitting diode preparation method

Abstract

The invention provides a light emitting diode and a light emitting diode preparation method. The light emitting diode comprises a patterned substrate, an epitaxial structure, an insulating structure, an electrode structure and a flat layer. The epitaxial structure is located on the patterned substrate, the epitaxial structure is provided with a step structure, and a step surface of the step structure is located in the epitaxial structure; the epitaxial structure is also provided with an isolation groove, and the bottom of the isolation groove is located on the surface of the patterned substrate. The flat layer is located at the bottom of the isolation groove; the insulation structure covers the flat layer and the step structure at the bottom of the isolation groove; the electrode structure passes through the insulating structure and is connected with the epitaxial structure. The flat layer is arranged at the bottom of the isolation groove, so that the convex structure on the surface of the patterned substrate is isolated by the flat layer, the insulating layer formed on the flat layer does not have bulges, the reflection performance is better, and the luminous efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for preparing the light-emitting diode. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor device that can emit light. It has the advantages of energy saving, high brightness, high durability, long life and light weight. It has been widely used in fields such as lighting and display.

[0003] The related art provides a light emitting diode, the structure of which includes a patterned substrate, an epitaxial structure, an insulating structure and an electrode structure.

[0004] However, the light emitting diode of the above structure may have light extraction efficiency problems and needs further optimization. Summary of the invention

[0005] The embodiments of the present disclosure provide a light emitting diode and a method for manufacturing a light emitting diode, which can significantly improve the problem that the insulating structure formed on the patterned substrate in the isolation groove is uneven, resulting in poor reflection effect of the insulating structure. The technical solution is as follows:

[0006] In one aspect, a light emitting diode is provided, comprising: a patterned substrate, an epitaxial structure, an insulating structure, an electrode structure and a planarization layer.

[0007] The epitaxial structure is located on the patterned substrate, and is provided with a step structure, the step surface of which is located inside the epitaxial structure; the epitaxial structure is also provided with an isolation groove, the bottom of which is located on the surface of the patterned substrate; the flat layer is located at the bottom of the isolation groove; the insulating structure covers the flat layer and the step structure at the bottom of the isolation groove; the electrode structure passes through the insulating structure and is connected to the epitaxial structure.

[0008] Optionally, the epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer, and the first semiconductor layer, the active layer and the second semiconductor layer are stacked in sequence on the patterned substrate; the step surface of the step structure is located in the first semiconductor layer; the thickness of the flat layer is the same as the thickness of the first semiconductor layer at the step surface.

[0009] Optionally, the planar layer is the first semiconductor layer processed by an ion implantation process.

[0010] Optionally, the planarization layer is an organic insulating material layer.

[0011] Optionally, the insulating structure includes a first insulating layer and a second insulating layer, and the first insulating layer and the second insulating layer are DBR layers.

[0012] In another aspect, a method for preparing a light emitting diode is provided, the method comprising:

[0013] forming an epitaxial structure on a patterned substrate;

[0014] Performing a patterning process on the epitaxial structure to form a step structure and an isolation groove, wherein the step surface of the step structure is located in the epitaxial structure, the bottom of the isolation groove is located in the epitaxial structure, and a flat layer is formed at the bottom of the isolation groove;

[0015] Manufacturing an insulating structure, wherein the insulating structure covers the flat layer and the step structure at the bottom of the isolation groove;

[0016] An electrode structure is manufactured, wherein the electrode structure passes through the insulating structure and is connected to the epitaxial structure.

[0017] Optionally, the epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked on the patterned substrate;

[0018] The step of patterning the epitaxial structure to form a step structure and an isolation groove includes:

[0019] Performing patterning on the epitaxial structure to form the step structure with the step surface located at the first semiconductor layer and the etching groove with the bottom located at the first semiconductor layer;

[0020] forming a photoresist mask to expose the etching groove;

[0021] The first semiconductor layer at the etching groove is subjected to ion implantation to modify the first semiconductor layer to form the insulating flat layer, and the bottom of the etching groove is extended to the surface of the patterned substrate to form the isolation groove. Optionally, the first semiconductor layer at the etching groove is subjected to ion implantation, including:

[0022] An ion implanter is used to implant ions of one element selected from the group consisting of He, Ar, N, C, B, and Si into the first semiconductor layer at the etched groove.

[0023] Optionally, the epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer, and the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked on the patterned substrate;

[0024] The step of patterning the epitaxial structure to form a step structure and an isolation groove includes:

[0025] Performing patterning on the epitaxial structure to form the step structure with the step surface located at the first semiconductor layer and the isolation groove with the bottom located at the patterned substrate;

[0026] Deposition of planarization films;

[0027] The planarization film is patterned to obtain the planarization layer.

[0028] Optionally, the thickness of the planar layer is the same as the thickness of the first semiconductor layer at the step surface.

[0029] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0030] A flat layer is arranged at the bottom of the isolation groove so that the protruding structure on the surface of the patterned substrate is isolated by the flat layer. In this way, the insulating layer formed on the flat layer has no protrusions, has better reflective performance, and can improve the luminous efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 It is a structural schematic diagram of a light emitting diode provided by the related technology;

[0033] Figure 2 It is a schematic diagram of a structural cross section of a light emitting diode provided by the related technology;

[0034] Figure 3 is a structural schematic diagram of a light emitting diode provided by an embodiment of the present disclosure;

[0035] Figure 4 is a schematic structural diagram of another light emitting diode provided by an embodiment of the present disclosure;

[0036] Figure 5 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0037] Figure 6 This is a flow chart of another method for preparing a light emitting diode provided in an embodiment of the present disclosure.

[0038] The reference numerals are as follows:

[0039] 10: epitaxial structure; 30: insulation structure; 40: electrode structure

[0040] 101: patterned substrate; 102: first semiconductor layer; 103: active layer; 104: second semiconductor layer; 105: current blocking layer; 106: transparent conductive layer; 107: first electrode; 108: first electrode pad; 109: first insulating layer; 110: second insulating layer; 111: second electrode; 112: second electrode pad; 113: first insulating layer through hole; 114: second insulating layer through hole; 116: isolation groove; 117: step structure; 118: flat layer. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0042] Figure 1 A schematic diagram of the structure of a light emitting diode provided for related technology. Figure 1 , patterning substrate 101, epitaxial structure 10, insulating structure 30 and electrode structure 40.

[0043] The epitaxial structure 10 is located on the patterned substrate 101, and a step structure 117 is provided on the epitaxial structure 10, and the step surface of the step structure 117 is located inside the epitaxial structure 10; the epitaxial structure 10 is also provided with an isolation groove 116, and the bottom of the isolation groove 116 is located on the surface of the patterned substrate 101; the insulating structure 30 covers the isolation groove 116 and the step structure 117; the electrode structure 40 passes through the insulating structure 30 and is connected to the epitaxial structure 10.

[0044] Exemplarily, the epitaxial structure 10 includes a first semiconductor layer 102 , an active layer 103 and a second semiconductor layer 104 .

[0045] Exemplarily, the insulating structure 30 includes a first insulating layer 109 and a second insulating layer 110 .

[0046] Exemplarily, the electrode structure 40 includes a first electrode 107 , a first electrode pad 108 , a second electrode 111 and a second electrode pad 112 .

[0047] The first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 are sequentially stacked on the patterned substrate 101. The first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 have a step structure 117 extending to the first semiconductor layer 102, that is, the step surface is located in the first semiconductor layer 102.

[0048] The first insulating layer 109 covers the second semiconductor layer 104, the isolation groove 116 and the step structure 117. The first insulating layer 109 respectively opens a first insulating layer through hole 113 at the second semiconductor layer 104 and the step structure 117. The first electrode 107 is connected to the second semiconductor layer 104 through the first insulating layer through hole 113 at the second semiconductor layer 104. The second electrode 111 is connected to the first semiconductor layer 102 through the first insulating layer through hole 113 at the step structure 117.

[0049] The second insulating layer 110 covers the first electrode 107, the second electrode 111 and the first insulating layer 109. The second insulating layer 110 has second insulating layer through holes 114 at the first electrode 107 and the second electrode 111 respectively. The first electrode pad 108 is connected to the first electrode 107 via the second insulating layer through hole 114 at the first electrode 107. The second electrode pad 112 is connected to the second electrode 111 via the second insulating layer through hole 114 at the second electrode 111.

[0050] In the related art, due to the unevenness of the surface of the patterned substrate, the insulating structure formed on the patterned substrate in the isolation groove also has the problem of unevenness, such as Figure 2 As shown, the reflection effect of the insulating structure is poor, which is not conducive to the light extraction efficiency of the light emitting diode.

[0051] Figure 3 A schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 3 The light emitting diode includes: a patterned substrate 101 , an epitaxial structure 10 , an insulating structure 30 , an electrode structure 40 and a planar layer 118 .

[0052] The epitaxial structure 10 is located on the patterned substrate 101, and a step structure 117 is provided on the epitaxial structure 10, and the step surface of the step structure 117 is located inside the epitaxial structure 10; the epitaxial structure 10 is also provided with an isolation groove 116, and the bottom of the isolation groove 116 is located on the surface of the patterned substrate 101; the flat layer 118 is located at the bottom of the isolation groove 116; the insulating structure 30 covers the flat layer 118 and the step structure 117 at the bottom of the isolation groove 116; the electrode structure 40 passes through the insulating structure 30 and is connected to the epitaxial structure 10.

[0053] In the disclosed embodiment, a flat layer is provided at the bottom of the isolation groove so that the protruding structure on the surface of the patterned substrate 101 is isolated by the flat layer. Thus, the insulating layer formed on the flat layer has no protrusions and has better reflective performance, thereby improving the luminous efficiency.

[0054] Exemplarily, the patterned substrate 101 is a sapphire patterned substrate.

[0055] Exemplarily, the epitaxial structure 10 includes a first semiconductor layer 102 , an active layer 103 , and a second semiconductor layer 104 . Exemplarily, the insulating structure 30 includes a first insulating layer 109 and a second insulating layer 110 .

[0056] Exemplarily, the electrode structure 40 includes a first electrode 107 , a first electrode pad 108 , a second electrode 111 and a second electrode pad 112 .

[0057] The first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 are sequentially stacked on the patterned substrate 101. The first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 have a step structure 117 extending to the first semiconductor layer 102, that is, the step surface is located in the first semiconductor layer 102.

[0058] The first insulating layer 109 covers the second semiconductor layer 104, the flat layer 118 at the bottom of the isolation groove 116 and the step structure 117. The first insulating layer 109 respectively opens first insulating layer through holes 113 at the second semiconductor layer 104 and the step structure 117. The first electrode 107 is connected to the second semiconductor layer 104 through the first insulating layer through hole 113 at the second semiconductor layer 104. The second electrode 111 is connected to the first semiconductor layer 102 through the first insulating layer through hole 113 at the step structure 117.

[0059] The second insulating layer 110 covers the first electrode 107, the second electrode 111 and the first insulating layer 109. The second insulating layer 110 has second insulating layer through holes 114 at the first electrode 107 and the second electrode 111 respectively. The first electrode pad 108 is connected to the first electrode 107 via the second insulating layer through hole 114 at the first electrode 107. The second electrode pad 112 is connected to the second electrode 111 via the second insulating layer through hole 114 at the second electrode 111.

[0060] In the embodiment of the present disclosure, the first semiconductor layer 102 may be an N-type semiconductor layer, and the second semiconductor layer 104 may be a P-type semiconductor layer.

[0061] For example, the first semiconductor layer 102 may be made of N-type GaN material, and the second semiconductor layer 104 may be made of P-type GaN material.

[0062] In other embodiments, the first semiconductor layer 102 may be a P-type semiconductor layer, and the second semiconductor layer 104 may be an N-type semiconductor layer.

[0063] In the embodiment of the present disclosure, the active layer 103 may be a multi-quantum well layer.

[0064] In the embodiment of the present disclosure, the first insulating layer 109 and the second insulating layer 110 may be a distributed Bragg reflector (DBR) layer or a SiO 2 layer, and the DBR layer is a stacked layer formed by SiO 2 and Ti 3 O 5 .

[0065] Generally, in the embodiments of the present disclosure, the first insulating layer 109 and the second insulating layer 110 are DBR layers. Changing the flatness of the DBR layer after growth in the above manner is beneficial to improving the reflection performance.

[0066] In the embodiment of the present disclosure, the first electrode 107 and the second electrode 111 may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt and Au.

[0067] Exemplarily, the first electrode 107 and the second electrode 111 are stacked layers of Cr, Al, AlCu, Ti, Ni, Pt, and Au.

[0068] In the embodiment of the present disclosure, the first electrode pad 108 and the second electrode pad 112 may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt, Au, and AuSn.

[0069] Exemplarily, the first electrode pad 108 and the second electrode pad 112 are stacked layers of Cr, Al, AlCu, Ti, Ni, Pt, Au, and AuSn.

[0070] In one implementation, the planar layer 118 may be a first semiconductor layer processed by an ion implantation process.

[0071] In this implementation, the first semiconductor layer is processed by ion implantation to form a flat layer, forming a side self-coating, and the process is simple and easy to implement. In addition, in this method, when etching the isolation groove, only the first semiconductor layer needs to be etched, and the etching process is simpler.

[0072] In this case, the thickness of the planarization layer 118 is the same as the thickness of the first semiconductor layer 102 at the step surface.

[0073] By way of example, the planar layer 118 may be a first semiconductor layer modified by implanting ions of elements such as He, Ar, N, C, B, and Si.

[0074] In this implementation, implanting the first semiconductor layer using the above example can form an insulating flat layer to prevent a short circuit between the electrode structure and the epitaxial structure.

[0075] In another implementation, the planarization layer 118 may be a film layer formed of other planarization insulating materials, for example, an organic insulating material layer, such as a planarization layer of an organic resin.

[0076] In this implementation, the planar layer formed by other planarization insulating materials has more options and can make the manufacturing process more flexible.

[0077] In this case, the thickness of the planar layer 118 may be the same as the thickness of the first semiconductor layer 102 at the step surface, or may be greater than or less than the thickness of the first semiconductor layer 102 at the step surface.

[0078] Exemplarily, the thickness of the flat layer is the same as the thickness of the first semiconductor layer at the step surface. By using a flat layer with the same thickness as the first semiconductor layer at the step surface, the insulating structure can cover the epitaxial structure and ensure the reflective performance of the insulating structure while ensuring the flatness of the insulating structure.

[0079] It is worth noting that in the embodiments of the present disclosure, structures may be selectively increased or decreased based on the structure of the above-mentioned light emitting diode, and the present disclosure does not impose any limitation on this.

[0080] Figure 4 This is a schematic diagram of the structure of another light emitting diode provided by an embodiment of the present disclosure. Figure 4 The light emitting diode further includes: a current blocking layer 105 and a transparent conductive layer 106 .

[0081] The current blocking layer 105 and the transparent conductive layer 106 are sequentially stacked on the second semiconductor layer 104 , and the transparent conductive layer wraps the current blocking layer; the insulating structure 30 covers the transparent conductive layer 106 , the flat layer 118 at the bottom of the isolation groove 116 , and the step structure 117 .

[0082] The first insulating layer 109 covers the transparent conductive layer 106, the flat layer 118 at the bottom of the isolation groove 116 and the step structure 117. The first insulating layer 109 respectively opens a first insulating layer through hole 113 at the transparent conductive layer 106 and the step structure 117. The first electrode 107 is connected to the transparent conductive layer 106 through the first insulating layer through hole 113 at the transparent conductive layer 106. The second electrode 111 is connected to the first semiconductor layer 102 through the first insulating layer through hole 113 at the step structure 117.

[0083] In the embodiment of the present disclosure, the current blocking layer 105 may be a SiO2 layer. SiO2 has good insulation properties and can effectively block the flow of electrons.

[0084] In the embodiment of the present disclosure, the transparent conductive layer 106 may be an indium tin oxide (ITO) layer. ITO has good transparency and conductivity. It allows light to pass through while conducting current to form an electrical connection.

[0085] Figure 5A flow chart of a method for preparing a light emitting diode provided in an embodiment of the present disclosure. Figure 5 The method steps include:

[0086] S11. Forming an epitaxial structure on a patterned substrate.

[0087] S12, performing patterning on the epitaxial structure to form a step structure and an isolation groove, wherein the step surface of the step structure is located in the epitaxial structure, the bottom of the isolation groove is located on the patterned substrate surface, and a flat layer is formed at the bottom of the isolation groove.

[0088] S13. Make an insulating structure, where the insulating structure covers the flat layer and the step structure at the bottom of the isolation groove.

[0089] S14, manufacturing an electrode structure, wherein the electrode structure passes through the insulating structure and is connected to the epitaxial structure.

[0090] In the disclosed embodiment, a flat layer is provided at the bottom of the isolation groove so that the raised structure on the surface of the patterned substrate is isolated by the flat layer. Thus, the insulating layer formed on the flat layer has no raised structure and better reflective performance, thereby improving the luminous efficiency.

[0091] Figure 6 is a flow chart of another method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 6 The method steps include:

[0092] S21, forming a first semiconductor layer, an active layer, and a second semiconductor layer in sequence on a patterned substrate, wherein the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.

[0093] The patterned substrate may be a sapphire patterned substrate.

[0094] In one example, step S21 includes:

[0095] The first step is to make the first semiconductor layer.

[0096] In the embodiment of the present disclosure, the first semiconductor layer is N-type GaN.

[0097] The second step is to make the active layer.

[0098] In the embodiment of the present disclosure, the active layer is a multi-quantum well layer.

[0099] The third step is to make the second semiconductor layer.

[0100] In the embodiment of the present disclosure, the second semiconductor layer is P-type GaN.

[0101] In the embodiment of the present disclosure, the first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked on the patterned substrate.

[0102] S22, performing patterning on the epitaxial structure to form a step structure and an isolation groove, wherein the step surface of the step structure is located in the epitaxial structure, the bottom of the isolation groove is located on the surface of the patterned substrate, and a flat layer is formed at the bottom of the isolation groove.

[0103] In the embodiment of the present disclosure, the first semiconductor layer, the active layer, and the second semiconductor layer are provided with a step structure extending to the first semiconductor layer, that is, the step surface is located in the first semiconductor layer.

[0104] In one example, the planar layer may be the first semiconductor layer after ion implantation. Accordingly, step S22 may include:

[0105] In the first step, the epitaxial structure is patterned to form a step structure with a step surface located at the first semiconductor layer and an etching groove with a bottom located at the first semiconductor layer.

[0106] In the second step, a photoresist mask is formed to expose the etching groove.

[0107] The photoresist mask covers the epitaxial structure and the step structure, exposing the etched groove.

[0108] The third step is to perform ion implantation on the first semiconductor layer at the etched groove to modify the first semiconductor layer to form an insulating flat layer, and to extend the bottom of the etched groove to the surface of the patterned substrate to form an isolation groove.

[0109] It should be noted that the bottom of the etched groove here refers to the isolation groove cutting the epitaxial structure. Since the modified part of the first semiconductor layer is no longer an epitaxial structure, the bottom of the isolation groove can be considered to be located on the surface of the patterned substrate. However, the bottom of the etched groove here extends to the surface of the patterned substrate to form an isolation groove, which is not achieved through patterning.

[0110] In this implementation, the first semiconductor layer is processed by ion implantation to form a flat layer, forming a side self-coating, and the process is simple and easy to implement. In addition, in this method, when etching the isolation groove, only the first semiconductor layer needs to be etched, and the etching process is simpler.

[0111] The method also includes removing the photoresist mask after the ion implantation is completed.

[0112] The third step may include: using an ion implanter to implant an element ion of He, Ar, N, C, B, and Si into the first semiconductor layer at the etching groove.

[0113] It should be noted that an insulating flat layer can be obtained without annealing after ion implantation.

[0114] In this case, the thickness of the planar layer is the same as the thickness of the first semiconductor layer at the step surface.

[0115] In this implementation, implanting the first semiconductor layer using the above example can form an insulating flat layer to prevent a short circuit between the electrode structure and the epitaxial structure.

[0116] In another implementation, the planarization layer may be a film layer formed by other planarization insulating materials, such as an organic insulating material layer, such as a planarization layer of an organic resin. Accordingly, step S22 may include:

[0117] In the first step, the epitaxial structure is patterned to form a step structure with a step surface located at the first semiconductor layer and an isolation groove with a bottom located at the patterned substrate.

[0118] The second step is to deposit a planarization film.

[0119] Among them, the planarization film can cover the epitaxial structure, the step structure and the isolation groove.

[0120] The third step is to perform graphic processing on the planarized film to obtain a planar layer.

[0121] In this implementation, the planarization film in the epitaxial structure, step structure and other regions is removed by graphical processing, leaving the planarization film in the isolation groove to obtain a planarization layer.

[0122] In this implementation, the planar layer formed by other planarization insulating materials has more options and can make the manufacturing process more flexible.

[0123] In this case, the thickness of the planar layer may be the same as the thickness of the first semiconductor layer at the step surface, or may be greater than or less than the thickness of the first semiconductor layer at the step surface.

[0124] Exemplarily, the thickness of the flat layer is the same as the thickness of the first semiconductor layer at the step surface. By using a flat layer with the same thickness as the first semiconductor layer at the step surface, the insulating structure can cover the epitaxial structure and ensure the reflective performance of the insulating structure while ensuring the flatness of the insulating structure.

[0125] S23, forming a current blocking layer and a transparent conductive layer in sequence on the surface of the epitaxial structure.

[0126] In the embodiment of the present disclosure, the current blocking layer and the transparent conductive layer are sequentially stacked on the second semiconductor layer, and the transparent conductive layer wraps the current blocking layer.

[0127] In the embodiment of the present disclosure, the current blocking layer may be a SiO2 layer. SiO2 has good insulation properties and can effectively block the flow of electrons.

[0128] In the embodiment of the present disclosure, the transparent conductive layer may be an ITO layer. ITO has excellent transparency and conductivity. It allows light to pass through while conducting current to form an electrical connection.

[0129] S24, manufacturing an insulating structure and an electrode structure, wherein the insulating structure covers the transparent conductive layer, the flat layer at the bottom of the isolation groove and the step structure, and the electrode structure passes through the insulating structure to connect with the epitaxial structure.

[0130] In one example, step S24 includes:

[0131] The first step is to make the first insulating layer.

[0132] The first insulating layer may be a DBR layer or a SiO2 layer, the DBR layer is a stacked layer formed by SiO2 and Ti3O5, and the first insulating layer covers the transparent conductive layer, the flat layer at the bottom of the isolation groove and the step structure.

[0133] The second step is to perform patterning on the first insulating layer to form a first insulating layer through hole.

[0134] The first insulating layer has first insulating layer through holes at the transparent conductive layer and the step structure respectively, the first electrode is connected to the transparent conductive layer through the first insulating layer through holes at the transparent conductive layer, and the second electrode is connected to the first semiconductor layer through the first insulating layer through holes at the step structure.

[0135] The third step is to make the first electrode and the second electrode.

[0136] The first electrode is connected to the transparent conductive layer through a through hole in the first insulating layer at the transparent conductive layer, and the second electrode is connected to the first semiconductor layer through a through hole in the first insulating layer at the step structure.

[0137] In the embodiment of the present disclosure, the first electrode and the second electrode may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt and Au.

[0138] Exemplarily, the first electrode and the second electrode are stacked layers of Cr, Al, AlCu, Ti, Ni, Pt and Au.

[0139] The fourth step is to make the second insulating layer.

[0140] The second insulating layer may be a DBR layer or a SiO2 layer, the DBR layer is a stacked layer formed by SiO2 and Ti3O5, and the second insulating layer covers the first electrode, the second electrode and the first insulating layer.

[0141] Generally, in the embodiments of the present disclosure, the first insulating layer and the second insulating layer are DBR layers. Changing the flatness of the DBR layer after growth in the above manner is beneficial to improving the reflection performance.

[0142] The fifth step is to perform patterning on the second insulating layer to form a second insulating layer through hole.

[0143] The second insulating layer has second insulating layer through holes respectively at the first electrode and the second electrode.

[0144] Step 6: Make a first electrode pad and a second electrode pad.

[0145] The first electrode pad is connected to the first electrode through a through hole in the second insulating layer at the first electrode, and the second electrode pad is connected to the second electrode through a through hole in the second insulating layer at the second electrode.

[0146] In the embodiment of the present disclosure, the first electrode pad and the second electrode pad may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt, Au and AuSn.

[0147] Exemplarily, the first electrode pad and the second electrode pad are stacked layers of Cr, Al, AlCu, Ti, Ni, Pt, Au, and AuSn.

[0148] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises: a patterned substrate (101), an epitaxial structure (10), an insulating structure (30), an electrode structure (40) and a flat layer (118); The epitaxial structure (10) is located on the patterned substrate (101), and the epitaxial structure (10) is provided with a step structure (117), and the step surface of the step structure (117) is located in the epitaxial structure (10); the epitaxial structure (10) is also provided with an isolation groove (116), and the bottom of the isolation groove (116) is located on the surface of the patterned substrate (101); the flat layer (118) is located at the bottom of the isolation groove (116); the insulating structure (30) covers the flat layer (118) and the step structure (117) at the bottom of the isolation groove (116); and the electrode structure (40) passes through the insulating structure (30) and is connected to the epitaxial structure (10).

2. The light emitting diode according to claim 1, characterized in that: The epitaxial structure (10) comprises a first semiconductor layer (102), an active layer (103) and a second semiconductor layer (104); the first semiconductor layer (102), the active layer (103) and the second semiconductor layer (104) are sequentially stacked on the patterned substrate (101); the step surface of the step structure (117) is located on the first semiconductor layer (102); the thickness of the flat layer (118) is the same as the thickness of the first semiconductor layer (102) at the step surface.

3. The light emitting diode according to claim 2, characterized in that: The flat layer (118) is the first semiconductor layer (102) processed by an ion implantation process.

4. The light emitting diode according to claim 1 or 2, characterized in that: The flat layer (118) is an organic insulating material layer.

5. The light emitting diode according to claim 1 or 2, characterized in that: The insulating structure (30) comprises a first insulating layer (109) and a second insulating layer (110), wherein the first insulating layer (109) and the second insulating layer (110) are DBR layers.

6. A method for preparing a light emitting diode, characterized in that: The method comprises: forming an epitaxial structure on the patterned substrate; Performing patterning on the epitaxial structure to form a step structure and an isolation groove, wherein the step surface of the step structure is located in the epitaxial structure, the bottom of the isolation groove is located on the surface of the patterned substrate, and a flat layer is formed at the bottom of the isolation groove; Manufacturing an insulating structure, wherein the insulating structure covers the flat layer and the step structure at the bottom of the isolation groove; An electrode structure is manufactured, wherein the electrode structure passes through the insulating structure and is connected to the epitaxial structure.

7. The method for preparing a light emitting diode according to claim 6, characterized in that: The epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer, wherein the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked on the patterned substrate; The step of patterning the epitaxial structure to form a step structure and an isolation groove includes: Performing patterning on the epitaxial structure to form the step structure with the step surface located at the first semiconductor layer and the etching groove with the bottom located at the first semiconductor layer; forming a photoresist mask to expose the etching groove; The first semiconductor layer at the etching groove is subjected to ion implantation treatment to modify the first semiconductor layer to form the insulating flat layer, and the bottom of the etching groove is extended to the surface of the patterned substrate to form the isolation groove.

8. The method for preparing a light emitting diode according to claim 7, characterized in that: The step of performing ion implantation on the first semiconductor layer at the etching groove comprises: An ion implanter is used to implant ions of one element selected from the group consisting of He, Ar, N, C, B, and Si into the first semiconductor layer at the etched groove.

9. The method for preparing a light emitting diode according to claim 6, characterized in that: The epitaxial structure comprises a first semiconductor layer, an active layer and a second semiconductor layer, wherein the first semiconductor layer, the active layer and the second semiconductor layer are sequentially stacked on the patterned substrate; The step of patterning the epitaxial structure to form a step structure and an isolation groove includes: Performing patterning on the epitaxial structure to form the step structure with the step surface located at the first semiconductor layer and the isolation groove with the bottom located at the patterned substrate; Deposition of planarization films; The planarization film is patterned to obtain the planarization layer.

10. The method for preparing a light emitting diode according to any one of claims 7 to 9, characterized in that: The thickness of the planar layer is the same as the thickness of the first semiconductor layer at the step surface.

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