Deep ultraviolet micro-led array chip and preparation method

Abstract

The application discloses a deep ultraviolet Micro-LED array chip and a preparation method thereof, and belongs to the technical field of semiconductors. The deep ultraviolet Micro-LED array chip comprises an electron supply layer, a plurality of array units, an array unit comprising a multiple quantum well active layer, an electron blocking layer and a hole supply layer which are sequentially stacked on the electron supply layer in the longitudinal direction, a through hole in the array unit which longitudinally penetrates the array unit, and the transverse sections of the array unit and the through hole being hexagonal, respectively, a plurality of first electrodes which are located on the corresponding array units and are connected with the hole supply layers in the corresponding array units, a plurality of second electrodes which are located in the through holes of the corresponding array units and are connected with the electron supply layer, the transverse section of the second electrode being hexagonal, the first electrode being arranged around the corresponding second electrode, a first interconnection layer connected with the plurality of first electrodes, and a second interconnection layer connected with the plurality of second electrodes. The application can reduce absorption loss, improve light extraction efficiency and improve chip reliability.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductors, and particularly relates to a deep ultraviolet Micro-LED array chip and a preparation method. BACKGROUND

[0002] AlGaN-based deep ultraviolet light-emitting diodes (LEDs) are considered to be a new generation of deep ultraviolet light sources due to their non-toxicity, low power consumption, small size, and long service life. Deep ultraviolet LEDs have potential application value in the fields of sterilization and disinfection, sewage treatment, solar-blind communication, and medical phototherapy.

[0003] Currently, the external quantum efficiency and the electro-optical conversion efficiency of deep ultraviolet LEDs are low, which limits their wide application. The deep ultraviolet LED epitaxial layer has a reabsorption effect on deep ultraviolet emission light, and a large number of laterally propagating photons are absorbed before being extracted out of the chip, which not only limits the light output power of the deep ultraviolet LED chip, but also causes the chip temperature to rise due to the heat energy converted by the absorbed photons, thereby reducing the reliability of the chip. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides a deep ultraviolet Micro-LED array chip and a preparation method, which can reduce absorption loss, improve light extraction efficiency, and improve chip reliability.

[0005] In a first aspect, the present application provides a deep ultraviolet Micro-LED array chip, comprising:

[0006] an electron-providing layer;

[0007] a plurality of array units spaced apart in an array, the array units comprising a multi-quantum well active layer, an electron-blocking layer, and a hole-providing layer stacked in sequence along a longitudinal direction on the electron-providing layer, the array units having a through hole penetrating through the array units in the longitudinal direction, the array units and the through hole each having a hexagonal transverse cross section;

[0008] a plurality of first electrodes corresponding one-to-one to the plurality of array units, the first electrodes being located on the corresponding array units and connected to the hole-providing layers in the corresponding array units;

[0009] a plurality of second electrodes corresponding one-to-one to the plurality of array units, the second electrodes being located in the through holes of the corresponding array units and connected to the electron-providing layer, the second electrodes each having a hexagonal transverse cross section, and the first electrodes being arranged around the corresponding second electrodes;

[0010] a first interconnection layer located between the plurality of array units and connected to the plurality of first electrodes;

[0011] A second interconnection layer is located on the side of the second electrode away from the electron supply layer and is connected with the plurality of second electrodes.

[0012] According to the deep ultraviolet Micro-LED array chip, the chip is pixelated into a plurality of array units spaced in an array, and the lateral section of the array unit is hexagonal, thereby reducing the absorption of the epitaxial material to the lateral deep ultraviolet light, reducing the absorption loss, improving the light extraction efficiency, arranging the second electrode in the array unit to form the array distributed second electrode, and the lateral section of the second electrode is hexagonal, thereby relieving the current aggregation effect, improving the current distribution performance, and improving the chip reliability.

[0013] According to an embodiment of the present application, the deep ultraviolet Micro-LED array chip further comprises:

[0014] A reflector is located on the sidewall of the through hole and the sidewall of the array unit.

[0015] According to an embodiment of the present application, the reflector comprises a plurality of refractive layers stacked, the plurality of refractive layers comprising first refractive layers and second refractive layers alternately distributed, the refractive index of the first refractive layer being different from that of the second refractive layer.

[0016] According to an embodiment of the present application, the thickness of the refractive layer is wherein λ is the central wavelength of the excitation light, and n is the refractive index of the refractive layer.

[0017] According to an embodiment of the present application, the deep ultraviolet Micro-LED array chip further comprises:

[0018] A first insulating layer covers the first interconnection layer and the plurality of second electrodes, and the second interconnection layer is located on the first insulating layer and longitudinally penetrates the first insulating layer to connect with the second electrode.

[0019] A second insulating layer covers the second interconnection layer and the first insulating layer.

[0020] A first pad longitudinally penetrates the first insulating layer and the second insulating layer and is connected with the first interconnection layer.

[0021] A second pad longitudinally penetrates the second insulating layer and is connected with the second interconnection layer.

[0022] According to an embodiment of the present application, the spacing between adjacent array units is less than the lateral dimension of the array unit.

[0023] According to an embodiment of the present application, the lateral dimension of the array unit is 110-210 μm; and / or,

[0024] A lateral dimension of the through hole is 20-40 μm; and / or,

[0025] An angle between a side wall of the array unit and an upper surface of the electron-providing layer is 40-50°, the upper surface of the electron-providing layer is parallel to the lateral direction and perpendicular to the longitudinal direction; and / or,

[0026] An angle between a side wall of the through hole and an upper surface of the electron-providing layer is 40-50°.

[0027] In a second aspect, the present application provides a preparation method of a deep ultraviolet Micro-LED array chip, comprising:

[0028] Providing an epitaxial structure, the epitaxial structure comprising an electron-providing layer, a multi-quantum well active layer, an electron-blocking layer and a hole-providing layer which are sequentially stacked along a longitudinal direction;

[0029] Forming a plurality of array units which are spaced apart in an array in the epitaxial structure, the array unit comprising the multi-quantum well active layer, the electron-blocking layer and the hole-providing layer, the array unit having a through hole which longitudinally penetrates the array unit, and a lateral cross section of the array unit and the through hole being hexagonal respectively;

[0030] Forming a first electrode connected with the hole-providing layer on the array unit, and forming a second electrode connected with the electron-providing layer in the through hole; a lateral cross section of the second electrode is hexagonal, and the first electrode is arranged around the corresponding second electrode;

[0031] Forming a first interconnection layer between the plurality of array units, and the first interconnection layer is connected with the first electrode on the plurality of array units;

[0032] Forming a second interconnection layer on a side of the second electrode away from the electron-providing layer, and the second interconnection layer is connected with the second electrode in the plurality of array units.

[0033] According to an embodiment of the present application, before the forming a first electrode connected with the hole-providing layer on the array unit, and forming a second electrode connected with the electron-providing layer in the through hole, the method further comprises:

[0034] Forming a reflector on an outer surface of the array unit and an inner surface of the through hole, the first electrode is located on a side of the reflector away from the array unit and is connected with the hole-providing layer longitudinally penetrating the reflector, and the second electrode is located in the through hole and is connected with the electron-providing layer longitudinally penetrating the reflector.

[0035] According to one embodiment of the present application, before the second interconnection layer is formed on the side of the second electrode away from the electron supply layer, the method further comprises:

[0036] A first insulating layer covering the first interconnection layer and the second electrode is formed, and the second interconnection layer is located on the first insulating layer and longitudinally penetrates the first insulating layer to connect the second electrode in the plurality of array units;

[0037] The method further comprises:

[0038] A second insulating layer covering the second interconnection layer and the first insulating layer is formed;

[0039] A first pad longitudinally penetrating the first insulating layer and the second insulating layer and connected to the first interconnection layer is formed, and a second pad longitudinally penetrating the second insulating layer and connected to the second interconnection layer is formed.

[0040] The one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0041] By pixelating the chip into a plurality of array units spaced apart in an array, and the lateral cross section of the array unit being a hexagon, the absorption of the epitaxial material to the lateral deep ultraviolet light is reduced, the absorption loss is reduced, the light extraction efficiency is improved, the second electrode is arranged in the array unit, the array-distributed second electrode is formed, and the lateral cross section of the second electrode is a hexagon, the current concentration effect is alleviated, the current distribution performance is improved, and the chip reliability is improved;

[0042] The mirror is formed on the sidewall of the array unit and the sidewall of the via hole, the laterally propagating deep ultraviolet light is redirected to the top of the chip by the mirror, the light extraction efficiency of the deep ultraviolet Micro-LED array chip is further improved, and the mirror can also act as a passivation layer to suppress the leakage current and non-radiative recombination phenomenon caused by sidewall etching damage, and improve the performance stability and reliability of the device.

[0043] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter in the description of embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0044] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the description of embodiments of the present application, taken in conjunction with the following drawings in which:

[0045] Figure 1 is a flowchart of a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0046] Figure 2is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0047] Figure 3 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0048] Figure 4 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0049] Figure 5 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0050] Figure 6 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0051] Figure 7 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0052] Figure 8 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0053] Figure 9 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0054] Figure 10 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0055] Figure 11 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0056] Figure 12 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0057] Figure 13 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0058] Figure 14 is one of structural schematic diagrams in a preparation method of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0059] Figure 15 is a structural schematic diagram of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0060] Figure 16 is one of microscope diagrams of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0061] Figure 17 is another of microscope diagrams of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0062] Figure 18 is a third of microscope diagrams of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0063] Figure 19 is a fourth of microscope diagrams of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0064] Figure 20 is a fifth of microscope diagrams of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0065] Figure 21 is a sixth of microscope diagrams of a deep ultraviolet Micro-LED array chip provided by an embodiment of the present application;

[0066] Figure 22 is a comparison diagram of light output power of a deep ultraviolet Micro-LED array chip and related technology provided by an embodiment of the present application.

[0067] Legend of reference signs:

[0068] 101, substrate; 102, buffer layer; 103, electron supply layer; 104, multi-quantum well active layer; 105, electron blocking layer; 106, hole supply layer; 107, via hole; 108, trench; 109, mirror; 110, second electrode; 111, first electrode; 112, first interconnection layer; 113, first insulating layer; 114, third opening; 115, second interconnection layer; 116, second insulating layer; 117, first contact hole; 118, second contact hole; 119, first pad; 120, second pad; 11, epitaxial structure; 12, array unit; 13a, first refractive layer; 13b, second refractive layer; 14, first opening; 15, second opening. DETAILED DESCRIPTION

[0069] Embodiments of the present application are described below in detail with reference to the accompanying drawings, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0070] A deep ultraviolet Micro-LED array chip and a preparation method thereof are provided in the embodiments of the present application.

[0071] Figure 1 A flowchart of the preparation method of the deep ultraviolet Micro-LED array chip provided in the embodiments of the present application.

[0072] As shown in Figure 1 The preparation method of the deep ultraviolet Micro-LED array chip provided in the embodiments of the present application includes steps 110 to 150.

[0073] Step 110, providing an epitaxial structure, the epitaxial structure including an electron-providing layer, a multi-quantum well active layer, an electron-blocking layer and a hole-providing layer which are sequentially stacked along a longitudinal direction.

[0074] In combination with Figure 2 As shown in the drawings, the epitaxial structure 11 can be formed on the substrate 101. In some embodiments, the substrate 101 is provided first, and then the epitaxial structure 11 is formed on the substrate 101. The substrate 101 can include a sapphire substrate, etc.

[0075] The epitaxial structure 11 includes an electron-providing layer 103, a multi-quantum well active layer 104, an electron-blocking layer 105 and a hole-providing layer 106 which are sequentially stacked along a longitudinal direction X. In some embodiments, the epitaxial structure 11 can further include a buffer layer 102, which is located between the substrate 101 and the electron-providing layer 103.

[0076] First, a thin film deposition process is used to form the buffer layer 102 on the substrate 101. The thin film deposition process includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, etc. Then, a thin film deposition process is used to form the electron-providing layer 103 on the buffer layer 102, the multi-quantum well active layer 104 on the electron-providing layer 103, the electron-blocking layer 105 on the multi-quantum well active layer 104, and the hole-providing layer 106 on the electron-blocking layer 105.

[0077] The buffer layer 102 can include AlN, etc., the electron-providing layer 103 can include n-AlGaN, etc., the multi-quantum well active layer 104 can include AlGaN, etc., the electron-blocking layer 105 can include p-AlGaN, etc., and the hole-providing layer 106 can include p-GaN, etc.

[0078] Step 120: Form multiple array units in an array-spaced distribution in the epitaxial structure. Each array unit includes a multi-quantum well active layer, an electron blocking layer, and a hole providing layer. Each array unit has a through-hole that runs longitudinally through the array unit. The transverse cross-sections of the array unit and the through-hole are hexagonal, respectively.

[0079] Combination Figure 3 As shown, photolithography and etching processes are used to etch the epitaxial structure 11 until the electron providing layer 103 is exposed, forming multiple vias 107. Specifically, the vias 107 penetrate the hole providing layer 106, the electron blocking layer 105, and the multi-quantum-well active layer 104 in a vertical X direction. The etching process includes inductively coupled plasma etching (ICP etching).

[0080] Figure 4 This is a top view of the epitaxial structure 11 and the through hole 107. (Combined) Figure 4 As shown, multiple through holes 107 are arranged in an array with spacing. The transverse Y-section of the through hole 107 is hexagonal, which can be a regular hexagon. In some embodiments, the transverse Y dimension of the through hole 107 is 20-40 μm. The transverse Y dimension of the through hole 107 refers to the distance between two opposite vertices of the transverse Y-section (hexagon) of the through hole 107, that is, the diameter of the circumcircle of the hexagon.

[0081] In some embodiments, the longitudinal X-section of the through-hole 107 is an inverted trapezoid, meaning the sidewall of the through-hole 107 is inclined away from the center of the through-hole 107. The angle between the sidewall of the through-hole 107 and the upper surface of the electron providing layer 103 (the surface of the electron providing layer 103 near the array unit 12) is 40°-50°. The upper surface of the electron providing layer 103 is parallel to the transverse Y-direction and perpendicular to the longitudinal X-direction.

[0082] Combination Figure 5 As shown, an etching process is used to etch the epitaxial structure 11 between multiple vias 107 until the electron providing layer 103 is exposed, forming a trench 108. That is, the trench 108 penetrates the hole providing layer 106, the electron blocking layer 105, and the multi-quantum well active layer 104 in the longitudinal direction X. The epitaxial structure 11 is divided into multiple array units 12 arranged in an array by the trench 108. That is, the array unit 12 includes the multi-quantum well active layer 104, the electron blocking layer 105, and the hole providing layer 106, which are sequentially stacked on the electron providing layer 103 in the longitudinal direction X.

[0083] Figure 6 This is a top view of the array unit 12, the through-hole 107, and the trench 108. (Combined with...) Figure 6As shown, the plurality of through holes 107 are located in the plurality of array units 12 one by one in a one-to-one correspondence, and the through hole 107 is located at the center of the corresponding array unit 12. The transverse Y section of the array unit 12 is a hexagon, which can be a regular hexagon. The six sides of the transverse Y section of the array unit 12 and the six sides of the transverse Y section of the through hole 107 can be arranged in parallel one by one. In some embodiments, the transverse Y dimension of the array unit 12 is 110-210 μm. The transverse Y dimension of the array unit 12 refers to the distance between the two opposite vertices of the transverse Y section (hexagon) of the array unit 12, that is, the diameter of the circumscribed circle of the hexagon.

[0084] In some embodiments, the longitudinal X section of the array unit 12 is a regular trapezoid, that is, the side wall of the array unit 12 is inclined toward the center of the array unit 12. The angle between the side wall of the array unit 12 and the upper surface of the electron-providing layer 103 (the surface of the electron-providing layer 103 close to the side of the array unit 12) is 40-50°.

[0085] In some embodiments, the spacing between adjacent array units 12 is less than the transverse dimension of the array unit 12, so as to avoid that the spacing of the array unit 12 is too large and affects the light-emitting effect of the chip.

[0086] It should be noted that the formation sequence of the through hole 107 and the groove 108 is not specifically limited, that is, the through hole 107 can be formed in the epitaxial structure 11 first and then the groove 108 is formed, or the groove 108 can be formed in the epitaxial structure 11 first and then the through hole 107 is formed, or the through hole 107 and the groove 108 can be formed in the epitaxial structure 11 at the same time.

[0087] In some embodiments, before the first electrode connected with the hole-providing layer and the second electrode connected with the electron-providing layer are formed on the array unit and in the through hole in step 130, the method further comprises:

[0088] A mirror is formed on the outer surface of the array unit and the inner surface of the through hole, the first electrode is located on the side of the mirror away from the array unit and is connected with the hole-providing layer longitudinally through the mirror, and the second electrode is located in the through hole and is connected with the electron-providing layer longitudinally through the mirror.

[0089] In combination with Figure 7 As shown, a thin film deposition process (such as plasma enhanced chemical vapor deposition (PECVD)) is used to form a mirror 109 on the outer surface of the array unit 12 and the inner surface of the through hole 107, that is, the mirror 109 is located on the side wall and the upper surface of the array unit 12 and the side wall and the bottom surface of the through hole 107. The mirror 109 is also located on the electron-providing layer 103 between the plurality of array units 12, that is, the mirror 109 is also located on the bottom surface of the groove 108. The mirror 109 can be a distributed Bragg reflector (DBR).

[0090] In some embodiments, combined with Figure 8 As shown, the reflector 109 includes multiple refractive layers stacked together. These refractive layers include alternating first refractive layers 13a and second refractive layers 13b, with different refractive indices. For example, the refractive index of the first refractive layer 13a is greater than that of the second refractive layer 13b. The bottom refractive layer of the reflector 109 can be the first refractive layer 13a, and the top refractive layer can be the second refractive layer 13b. The first refractive layer 13a may include MgF2 or HfO2, etc., and the second refractive layer 13b may include Al2O3, HfO2, or SiO2, etc. For example, the reflector 109 may include MgF2 / Al2O3, MgF2 / HfO2, HfO2 / SiO2, or HfO2 / SiO2, etc. It should be noted that the materials of different first refractive layers 13a can be the same or different. The materials of different second refractive layers 13b can be the same or different.

[0091] In some embodiments, the thickness of the refractive layer is determined by... The determination is made by considering the following: where d is the thickness of the refractive layer, λ is the center wavelength of the emitted deep ultraviolet light, and n is the refractive index of the refractive layer. For example, the reflector 109 is composed of four 25nm thick HfO2 refractive layers and four 46nm thick SiO2 refractive layers stacked alternately.

[0092] Then, combine Figure 9 As shown, an etching process is used to etch the reflector 109 to form a plurality of first openings 14 and a plurality of second openings 15 in the reflector 109. The plurality of first openings 14 are arranged one-to-one with a plurality of array units 12, and the first opening 14 is located above the corresponding array unit 12, penetrating the reflector 109 longitudinally (X) and exposing the hole-providing layer 106 in the corresponding array unit 12. The plurality of second openings 15 are arranged one-to-one with a via 107 of the plurality of array units 12, and the second opening 15 is located at the bottom of the corresponding via 107 and is connected to the corresponding via 107. The second opening 15 penetrates the reflector 109 longitudinally (X), exposing the electron-providing layer 103 at the bottom of the via 107. The transverse (Y) cross-section of the second opening 15 is hexagonal, and the first openings 14 are arranged around the corresponding second opening 15.

[0093] In this embodiment, reflectors 109 are formed on the sidewalls of the array unit 12 and the via 107. Laterally propagating deep ultraviolet light is reflected and redirected to the top of the chip by the reflectors, further improving the light extraction efficiency of the deep ultraviolet Micro-LED array chip. Moreover, the reflectors 109 can also serve as a passivation layer to suppress leakage current and non-radiative recombination caused by sidewall etching damage, thereby improving the performance stability and reliability of the device.

[0094] Step 130, forming a first electrode connected with the hole-providing layer on the array unit, and forming a second electrode connected with the electron-providing layer in the through hole; the lateral section of the second electrode is hexagonal, and the first electrode is arranged around the corresponding second electrode.

[0095] In combination Figure 10 As shown, a plurality of first electrodes 111 and a plurality of second electrodes 110 are formed by using a thin film deposition process. The plurality of first electrodes 111 are arranged one-to-one corresponding to the plurality of array units 12 and arranged one-to-one corresponding to the plurality of first openings 14. The first electrode 111 is filled in the corresponding first opening 14 and connected with the exposed hole-providing layer 106 (i.e. the hole-providing layer 106 in the corresponding array unit 12) of the corresponding first opening 14. The second electrode 110 is arranged one-to-one corresponding to the through hole 107 of the plurality of array units 12 and arranged one-to-one corresponding to the plurality of second openings 15. The second electrode 110 is filled in the corresponding through hole 107 and the corresponding second opening 15, and connected with the exposed electron-providing layer 103 (i.e. the electron-providing layer 103 in the corresponding array unit 12) of the corresponding second opening 15. After the first electrode 111 and the second electrode 110 are formed, high-temperature annealing is performed to form an ohmic contact.

[0096] Each array unit 12 corresponds to a first electrode 111 and a second electrode 110. The second electrode 110 is located at the center of the corresponding array unit 12, and the lateral Y section of the second electrode 110 is hexagonal, and the longitudinal X section of the second electrode 110 can be inverted trapezoidal. The first electrode 111 is arranged around the corresponding second electrode 110, and the first electrode 111 is arranged spaced apart from the second electrode 110. Among them, the first electrode 111 can be a p-electrode, and the second electrode 110 can be an n-electrode.

[0097] In this embodiment, the LED chip is pixelated into a suitable size hexagonal array unit 12, which reduces the absorption of the epitaxial material to the lateral deep ultraviolet light, reduces the absorption damage, and improves the light extraction efficiency.

[0098] Step 140, forming a first interconnection layer between the plurality of array units, and the first interconnection layer is connected with the first electrode on the plurality of array units.

[0099] In combination Figure 11 As shown, a first interconnection layer 112 is formed between the plurality of array units 12 by using a thin film deposition process. The first interconnection layer 112 covers the mirror 109 (i.e. the mirror 109 on the side wall and the bottom of the groove 108) between the plurality of array units 12 and the first electrode 111 on the plurality of array units 12, so that all the first electrodes 111 are connected through the first interconnection layer 112. Among them, the first interconnection layer 112 can be a p-interconnection layer.

[0100] In some embodiments, before forming the second interconnection layer on the side of the second electrode away from the electron-providing layer in step 150, the method further comprises:

[0101] forming a first insulating layer covering the first interconnection layer and the second electrode.

[0102] In combination Figure 12 As shown, a thin film deposition process is adopted to form the first insulating layer 113 covering the first interconnection layer 112 and the second electrode 110. The first insulating layer 113 fills the trench 108, and the upper surface of the first insulating layer 113 (i.e. the surface on the side of the first insulating layer 113 away from the electron-providing layer 103) is planar.

[0103] Then, an etching process is adopted to form a plurality of third openings 114 in the first insulating layer 113 in an array distribution. The plurality of third openings 114 are arranged one-to-one corresponding to the plurality of second electrodes 110, and the third openings 114 longitudinally extend through the first insulating layer 113 to expose the corresponding second electrodes 110.

[0104] In step 150, the second interconnection layer is formed on the side of the second electrode away from the electron-providing layer, and the second interconnection layer is connected with the second electrode in the plurality of array units.

[0105] With the first insulating layer 113 formed, the second interconnection layer is located on the first insulating layer and longitudinally extends through the first insulating layer to be connected with the second electrode in the plurality of array units.

[0106] In combination Figure 13 As shown, a thin film deposition process is adopted to form the second interconnection layer 115 on the first insulating layer 113, and the second interconnection layer 115 fills the plurality of third openings 114 to be connected with the plurality of second electrodes 110. All the second electrodes 110 are connected through the second interconnection layer 115. The second interconnection layer 115 can be an n-interconnection layer.

[0107] It should be noted that the second interconnection layer 115 does not completely cover the first insulating layer 113, i.e. the second interconnection layer 115 covers part of the first insulating layer 113. For example, the edge region of the first insulating layer 113 is not covered by the second interconnection layer 115, and the other regions of the first insulating layer 113 are covered by the second interconnection layer 115.

[0108] In some embodiments, the method further comprises:

[0109] forming a second insulating layer covering the second interconnection layer and the first insulating layer;

[0110] forming a first pad longitudinally extending through the first insulating layer and the second insulating layer and connected with the first interconnection layer, and forming a second pad longitudinally extending through the second insulating layer and connected with the second interconnection layer.

[0111] In combinationFigure 14 As shown, a second insulating layer 116 is formed using a thin-film deposition process. The second insulating layer 116 covers the second interconnect layer 115 and a portion of the first insulating layer 113 (i.e., the portion of the first insulating layer 113 not covered by the second interconnect layer 115). The surface of the second insulating layer 116 facing away from the electron providing layer 103 is planar.

[0112] Combination Figure 14 As shown, an etching process is used to form a first contact hole 117 and a second contact hole 118. The first contact hole 117 penetrates the second insulating layer 116 and the first insulating layer 113 longitudinally (X) to expose the first interconnect layer 112. The second contact hole 118 penetrates the second insulating layer 116 longitudinally (X) to expose the second interconnect layer 115. The number of first contact holes 117 and second contact holes 118 can be one or more.

[0113] Then, combine Figure 15 As shown, a first pad 119 and a second pad 120 are formed on the second insulating layer 116 using a thin-film deposition process. The first pad 119 fills the first contact hole 117 and is connected to the first interconnect layer 112. The first pad 119 is connected to all the first electrodes 111 through the first interconnect layer 112. The second pad 120 fills the second contact hole 118 and is connected to the second interconnect layer 115. The second pad 120 is connected to all the second electrodes 110 through the second interconnect layer 112. The first pad 119 can be a p-pad, and the second pad 120 can be an n-pad.

[0114] The output power of the LED chips in this embodiment and those in related technologies was tested. The LED chips in related technologies did not have array units or reflectors. The lateral dimensions of the array units 12 of the LED chip in this embodiment are 130 μm (Embodiment 1), 110 μm (Embodiment 2), 150 μm (Embodiment 3), 170 μm (Embodiment 4), 190 μm (Embodiment 5), and 210 μm (Embodiment 6), respectively. Microscopic images of the LED chips in Examples 1 to 6 are shown below. Figure 16 to Figure 21 As shown. The output power test results of related technologies and Examples 1 to 6 are as follows. Figure 22 As shown, it can be seen that, compared with related technologies, embodiments 1 to 6 can effectively improve the optical output power. Moreover, by reasonably setting the lateral dimension of the array unit 12, more laterally transmitted photons are redirected to the top of the chip by the reflector, and embodiment 1 (the lateral dimension of the array unit 12 is 130μm) exhibits the maximum optical output power.

[0115] In summary, according to the preparation method of the deep ultraviolet Micro-LED array chip provided in the embodiments of the present application, the chip is pixelated into a plurality of array units 12 arranged in an array at intervals, and the lateral cross section of the array unit 12 is hexagonal, thereby reducing the absorption of the epitaxial material to the lateral deep ultraviolet light, reducing the absorption loss, improving the light extraction efficiency, arranging the second electrode 110 in the array unit 12, forming the second electrode 110 arranged in an array, and the lateral cross section of the second electrode 110 is hexagonal, thereby relieving the current concentration effect, improving the current distribution performance, and improving the chip reliability. The mirror 109 is arranged on the sidewall of the via hole 107 and the sidewall of the array unit 12, thereby further enhancing the light extraction efficiency and improving the sidewall damage.

[0116] Correspondingly, the embodiments of the present application also provide a deep ultraviolet Micro-LED array chip, which can be prepared by the preparation method of the deep ultraviolet Micro-LED array chip described above.

[0117] Figure 15 A structural schematic diagram of the deep ultraviolet Micro-LED array chip provided in the embodiments of the present application is shown.

[0118] As Figure 15 shown, the deep ultraviolet Micro-LED array chip provided in the embodiments of the present application includes an electron-providing layer 103, a plurality of array units 11, a plurality of first electrodes 111, a plurality of second electrodes 110, a first interconnection layer, and a second interconnection layer.

[0119] The electron-providing layer 103 is used to provide electrons. The electron-providing layer 103 can include n-AlGaN and the like.

[0120] In some embodiments, the deep ultraviolet Micro-LED array chip further includes a buffer layer 102, and the electron-providing layer 103 is located on the buffer layer 102. The buffer layer 102 can include AlN and the like.

[0121] In some embodiments, the deep ultraviolet Micro-LED array chip further includes a substrate 101, and the buffer layer 102 is located between the substrate 101 and the electron-providing layer 103. The substrate 101 can include a sapphire substrate and the like.

[0122] The plurality of array units 11 are arranged in an array at intervals, and the array unit 11 includes a multi-quantum well active layer 104, an electron blocking layer 105, and a hole-providing layer 106 which are sequentially stacked on the electron-providing layer 103 along the longitudinal direction X. The multi-quantum well active layer 104 can include AlGaN and the like, the electron blocking layer 105 can include p-AlGaN and the like, and the hole-providing layer 106 can include p-GaN and the like.

[0123] The array unit 11 has a through hole 107 longitudinally X through the array unit 11, that is, the through hole 107 longitudinally X through the cavity providing layer 106, the electron blocking layer 105 and the multi-quantum well active layer 104. The through hole 107 is located at the center of the corresponding array unit 12. The through holes 107 in the plurality of array units 11, that is, the plurality of through holes 107, are arranged in an array.

[0124] The lateral Y section of the array unit 12 is a hexagon, which can be a regular hexagon. In some embodiments, the lateral Y dimension of the array unit 12 is 110-210 μm. The lateral Y dimension of the array unit 12 refers to the distance between two opposite vertices of the lateral Y section (hexagon) of the array unit 12, that is, the diameter of the circumscribed circle of the hexagon.

[0125] In some embodiments, the longitudinal X section of the array unit 12 is a regular trapezoid, that is, the sidewall of the array unit 12 is inclined toward the direction of the center of the array unit 12. The angle between the sidewall of the array unit 12 and the upper surface of the electron providing layer 103 (the surface of the electron providing layer 103 close to one side of the array unit 12) is 40-50°.

[0126] In some embodiments, the spacing between adjacent array units 12 is smaller than the lateral dimension of the array unit 12, so as to avoid that the spacing of the array units 12 is too large and affects the light emitting effect of the chip.

[0127] The lateral Y section of the through hole 107 is a hexagon, which can be a regular hexagon. The six sides of the lateral Y section of the array unit 12 and the six sides of the lateral Y section of the through hole 107 can be arranged in parallel one by one. In some embodiments, the lateral Y dimension of the through hole 107 is 20-40 μm. The lateral Y dimension of the through hole 107 refers to the distance between two opposite vertices of the lateral Y section (hexagon) of the through hole 107, that is, the diameter of the circumscribed circle of the hexagon.

[0128] In some embodiments, the longitudinal X section of the through hole 107 is an inverted trapezoid, that is, the sidewall of the through hole 107 is inclined away from the center of the through hole 107. The angle between the sidewall of the through hole 107 and the upper surface of the electron providing layer 103 (the surface of the electron providing layer 103 close to one side of the array unit 12) is 40-50°. The upper surface of the electron providing layer 103 is parallel to the lateral Y and perpendicular to the longitudinal X.

[0129] The plurality of first electrodes 111 are arranged one by one with the plurality of array units 12, and the first electrode 111 is located on the corresponding array unit 12 and connected with the cavity providing layer 106 in the corresponding array unit 12. The first electrode 111 can be a p-electrode.

[0130] The plurality of second electrodes 110 are arranged one-to-one with the plurality of array units 12, and the second electrode 110 is located in the through hole 107 of the corresponding array unit 12 and is connected with the electron-providing layer 103. The second electrode 110 can be an n-electrode.

[0131] The second electrode 110 is located at the center of the corresponding array unit 12, the transverse Y section of the second electrode 110 is a hexagon, and the longitudinal X section of the second electrode 110 can be an inverted trapezoid. The first electrode 111 is arranged around the corresponding second electrode 110, and the first electrode 111 is arranged in a spaced manner with the second electrode 110.

[0132] In this embodiment, the LED chip is pixelated into a suitable size hexagonal array unit 12, which reduces the absorption of the epitaxial material to the transverse deep ultraviolet light, reduces the absorption damage, and improves the light extraction efficiency.

[0133] The first interconnection layer 112 is located between the plurality of array units 12 and is connected with the plurality of first electrodes 111. The first interconnection layer 112 is located between the plurality of array units 12 and extends along the sidewall of the array unit 12 to the upper surface of the first electrode 111 to connect with the first electrode 111. All the first electrodes 111 are connected through the first interconnection layer 112. The first interconnection layer 112 can be a p-interconnection layer.

[0134] The second interconnection layer 115 is located on the side of the second electrode 110 away from the electron-providing layer 103 and is connected with the plurality of second electrodes 110. All the second electrodes 110 are connected through the second interconnection layer 115. The second interconnection layer 115 can be an n-interconnection layer.

[0135] In some embodiments, the deep ultraviolet Micro-LED array chip further comprises a mirror 109 located on the sidewall of the through hole 107 and the sidewall of the array unit 12. The mirror 109 can also be located on the electron-providing layer 103 between the plurality of array units 12. The first interconnection layer 112 covers the mirror 109 between the plurality of array units 12 and covers the mirror 109 on the sidewall of the array unit 12. The mirror 109 can be a distributed Bragg reflector (DBR).

[0136] In combination Figure 8As shown, the mirror 109 includes a plurality of refractive layers stacked, the plurality of refractive layers include first refractive layers 13a and second refractive layers 13b alternately distributed, and the refractive indexes of the first refractive layers 13a and the second refractive layers 13b are different. For example, the refractive index of the first refractive layer 13a is greater than the refractive index of the second refractive layer 13b. The refractive layer at the bottom layer of the mirror 109 can be the first refractive layer 13a, and the refractive layer at the top layer can be the second refractive layer 13b. The first refractive layer 13a can include MgF2 or HfO2, etc., and the second refractive layer 13b can include Al2O3, HfO2 or SiO2, etc. For example, the mirror 109 can include MgF2 / Al2O3, MgF2 / HfO2, HfO2 / SiO2 or HfO2 / SiO2, etc. It should be noted that the materials of different first refractive layers 13a can be the same or different. The materials of different second refractive layers 13b can be the same or different.

[0137] In some embodiments, the thickness of the refractive layer is determined by wherein d is the thickness of the refractive layer, λ is the central wavelength of the emitted deep ultraviolet light, and n is the refractive index of the refractive layer. For example, the mirror 109 is formed by alternately stacking four layers of 25 nm thick HfO2 refractive layers and four layers of 46 nm thick SiO2 refractive layers.

[0138] In this embodiment, the mirror 109 is arranged on the sidewall of the array unit 12 and the sidewall of the via 107, the laterally propagating deep ultraviolet light is redirected to the top of the chip by reflection of the mirror, further improving the light extraction efficiency of the deep ultraviolet Micro-LED array chip. Moreover, the mirror 109 can also act as a passivation layer to suppress the leakage current and non-radiative recombination phenomenon caused by sidewall etching damage, and improve the performance stability and reliability of the device.

[0139] In some embodiments, the deep ultraviolet Micro-LED array chip further includes a first insulating layer 113, a second insulating layer 116, a first pad 119 and a second pad 120.

[0140] The first insulating layer 113 covers the first interconnection layer 112 and the plurality of second electrodes 110, and the upper surface of the first insulating layer 113 (i.e. the surface on the side of the first insulating layer 113 away from the electron supply layer 103) is planar. The second interconnection layer 112 is located on the first insulating layer 113 and longitudinally penetrates the first insulating layer 113 to connect with the second electrode 110. The second interconnection layer 115 does not completely cover the first insulating layer 113, i.e. the second interconnection layer 115 covers part of the first insulating layer 113, for example, the edge region of the first insulating layer 113 is not covered by the second interconnection layer 115, and the other regions of the first insulating layer 113 are covered by the second interconnection layer 115.

[0141] The second insulating layer 116 covers the second interconnection layer 115 and the first insulating layer 113. The surface of the second insulating layer 116 away from the electron supply layer 103 is planar.

[0142] The first pad 119 longitudinally extends through the first insulating layer 113 and the second insulating layer 116, and is connected with the first interconnection layer 112. The first pad 119 is connected with all the first electrodes 111 through the first interconnection layer 112. The first pad 119 can be a p-pad.

[0143] The second pad 120 longitudinally extends through the second insulating layer 116, and is connected with the second interconnection layer 115. The second pad 120 is connected with all the second electrodes 110 through the second interconnection layer 112. The second pad 120 can be an n-pad.

[0144] In summary, according to the deep ultraviolet Micro-LED array chip provided by the embodiment of the present application, the chip is pixelated into a plurality of array units 12 distributed in an array, and the lateral cross section of the array unit 12 is hexagonal, thereby reducing the absorption of the epitaxial material to the lateral deep ultraviolet light, reducing the absorption loss, and improving the light extraction efficiency. The second electrode 110 is arranged in the array unit 12, and the second electrode 110 is arranged in an array, and the lateral cross section of the second electrode 110 is hexagonal, thereby relieving the current crowding effect, improving the current distribution performance, and improving the chip reliability. The mirror 109 is arranged on the sidewall of the via hole 107 and the sidewall of the array unit 12, thereby further enhancing the light extraction efficiency and improving the sidewall damage.

[0145] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more.

[0146] In the description of the present application, the meaning of "a plurality of" is two or more.

[0147] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0148] While the embodiments of the application have been shown and described, it is to be understood that the embodiments can be varied, modified, substituted and changed by those skilled in the art without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

Claims

1. A deep ultraviolet Micro-LED array chip, characterized in that, The deep ultraviolet Micro-LED array chip comprises: an electron-providing layer; a plurality of array units arranged in an array, the array units comprising a multiple quantum well active layer, an electron-blocking layer and a hole-providing layer arranged in sequence along a longitudinal direction on the electron-providing layer, the array units having a through hole longitudinally penetrating the array units, the array units and the through hole each having a hexagonal transverse cross section; a plurality of first electrodes corresponding to the plurality of array units, the first electrodes being arranged on the corresponding array units and connected with the hole-providing layers in the corresponding array units; a plurality of second electrodes corresponding to the plurality of array units, the second electrodes being arranged in the through holes of the corresponding array units and connected with the electron-providing layer, the second electrodes each having a hexagonal transverse cross section, and the first electrodes being arranged around the corresponding second electrodes; a first interconnection layer arranged between the plurality of array units and connected with the plurality of first electrodes; a second interconnection layer arranged on a side of the second electrodes away from the electron-providing layer and connected with the plurality of second electrodes; a mirror arranged on side walls of the through holes and side walls of the array units, the mirror also serving as a passivation layer; an angle between the side walls of the array units and an upper surface of the electron-providing layer is 40°-50°, the upper surface of the electron-providing layer being parallel to the transverse direction and perpendicular to the longitudinal direction; an angle between the side walls of the through holes and the upper surface of the electron-providing layer is 40°-50°.

2. The DUV Micro-LED array chip of claim 1, wherein, The mirror comprises a plurality of refractive layers arranged in layers, the plurality of refractive layers comprising first refractive layers and second refractive layers arranged alternately, the first refractive layers and the second refractive layers having different refractive indexes.

3. The DUV Micro-LED array chip of claim 2, wherein, the thickness of the refractive layer wherein, The deep ultraviolet Micro-LED array chip further comprises: is the center wavelength of the excitation light, n is the refractive index of the refractive layer.

4. The DUV Micro-LED array chip of claim 1, wherein, a first insulating layer covering the first interconnection layer and the plurality of second electrodes, the second interconnection layer being arranged on the first insulating layer and connected with the second electrodes longitudinally penetrating the first insulating layer; a second insulating layer covering the second interconnection layer and the first insulating layer; a first bonding pad longitudinally penetrating the first insulating layer and the second insulating layer and connected with the first interconnection layer; a second bonding pad longitudinally penetrating the second insulating layer and connected with the second interconnection layer. A spacing between adjacent array units is less than a transverse dimension of the array units.

5. The DUV Micro-LED array chip of claim 1, wherein, The transverse dimension of the array units is 110-210 μm; and / or 6. The DUV Micro-LED array chip of any of claims 1-5, wherein, A transverse dimension of the through hole is 20-40 μm. The deep ultraviolet Micro-LED array chip comprises: 7.A method for manufacturing a deep ultraviolet Micro-LED array chip, characterized in that, providing an epitaxial structure comprising an electron-providing layer, a multiple quantum well active layer, an electron-blocking layer and a hole-providing layer arranged in sequence along a longitudinal direction; forming a plurality of array units arranged in an array in the epitaxial structure, the array units comprising the multiple quantum well active layer, the electron-blocking layer and the hole-providing layer, the array units having a through hole longitudinally penetrating the array units, the array units and the through hole each having a hexagonal transverse cross section; ​ forming a first electrode connected with the hole providing layer on the array unit, and forming a second electrode connected with the electron providing layer in the through hole; the second electrode has a hexagonal lateral cross section, and the first electrode is arranged around the corresponding second electrode; forming a first interconnection layer between the array units, and the first interconnection layer is connected with the first electrode on the array units; forming a second interconnection layer on the side of the second electrode away from the electron providing layer, and the second interconnection layer is connected with the second electrode in the array units; the angle between the sidewall of the array unit and the upper surface of the electron providing layer is 40°-50°, the upper surface of the electron providing layer is parallel to the lateral direction and perpendicular to the longitudinal direction; the angle between the sidewall of the through hole and the upper surface of the electron providing layer is 40°-50°; before the step of forming a first electrode connected with the hole providing layer on the array unit, and forming a second electrode connected with the electron providing layer in the through hole, the method further comprises: forming a mirror on the outer surface of the array unit and the inner surface of the through hole, the mirror also serves as a passivation layer, the first electrode is located on the side of the mirror away from the array unit and is connected with the hole providing layer longitudinally through the mirror, and the second electrode is located in the through hole and is connected with the electron providing layer longitudinally through the mirror.

8. The method of claim 7, wherein the method further comprises: before the step of forming a second interconnection layer on the side of the second electrode away from the electron providing layer, the method further comprises: forming a first insulating layer covering the first interconnection layer and the second electrode, the second interconnection layer is located on the first insulating layer and is connected with the second electrode in the array units longitudinally through the first insulating layer; the method further comprises: forming a second insulating layer covering the second interconnection layer and the first insulating layer; forming a first pad connected with the first interconnection layer longitudinally through the first insulating layer and the second insulating layer, and forming a second pad connected with the second interconnection layer longitudinally through the second insulating layer.

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