Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and electronic equipment. The semiconductor structure includes a first electrode, a second electrode disposed opposite the first electrode, a dielectric layer disposed between the first electrode and the second electrode, and a first crystallization promoting layer disposed between the dielectric layer and the first electrode. The dielectric layer is made of lead zirconate titanate, the first crystallization promoting layer is in contact with the dielectric layer and is used for promoting crystallization of the dielectric layer, and the first crystallization promoting layer is made of a perovskite structure. The dielectric layer in the semiconductor structure can form a film at a low temperature.

Description

Technical Field

[0001] The present application relates to semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof, and electronic equipment. Background Art

[0002] With the development of semiconductor technology, semiconductor structures are increasingly widely used. For example, non-volatile memories and MEMS (Micro Electro Mechanical System) sensors (such as pressure sensors) often require various semiconductor structures.

[0003] The semiconductor structure includes a first electrode and a second electrode arranged opposite to each other, and a dielectric layer arranged between the first electrode and the second electrode. As required, the material of the dielectric layer can be a ferroelectric material or a piezoelectric material, for example, the material of the dielectric layer is lead zirconate titanate with a high dielectric constant. However, it is difficult to form the dielectric layer at a relatively low temperature, and production is limited. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, and an electronic device, so as to realize film formation of a dielectric layer at a relatively low temperature.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor structure, including:

[0006] a first electrode;

[0007] a second electrode, arranged opposite to the first electrode;

[0008] A dielectric layer, disposed between the first electrode and the second electrode, wherein the material of the dielectric layer comprises lead zirconate titanate;

[0009] The first crystallization promoting layer is arranged between the dielectric layer and the first electrode and contacts the dielectric layer, and is used to promote crystallization of the dielectric layer. The material of the first crystallization promoting layer is a perovskite structure.

[0010] In some possible implementations, the semiconductor structure further includes a second crystallization promoting layer, which is disposed on a side of the first electrode away from the second electrode and is used to promote crystallization of the first electrode.

[0011] In some possible implementations, the material of the second crystallization promoting layer includes at least one of zirconium oxide and perovskite.

[0012] In some possible implementations, the thickness of the first crystallization promoting layer is 20 nm-200 nm; and / or the thickness of the second crystallization promoting layer is 10 nm-1000 nm.

[0013] In some possible implementations, the semiconductor structure further includes an adhesion layer, and the adhesion layer is disposed between the second crystallization promoting layer and the first electrode.

[0014] In some possible implementations, the material of the adhesion layer includes at least one of titanium, zirconium oxide, iridium oxide, and chromium.

[0015] In some possible implementations, the material of the first crystallization promoting layer includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate.

[0016] In some possible implementations, the lead zirconate titanate is pure lead zirconate titanate or lead zirconate titanate containing a dopant;

[0017] The dopant includes at least one of niobium, calcium, magnesium, barium, scandium, tin, hafnium, bismuth, lanthanum, tungsten, potassium, and iron.

[0018] In some possible implementations, at least one of the first electrode, the second electrode, the dielectric layer, and the first crystallization promoting layer is formed by sputtering deposition, and the sputtering deposition uses a DC bias of 150V-500V or an AC bias of 50W-400W.

[0019] In some possible implementations, the semiconductor structure further includes a diffusion barrier layer, and the diffusion barrier layer is disposed between the dielectric layer and the second electrode.

[0020] The semiconductor structure in the embodiment of the present application includes a first electrode, a second electrode, a dielectric layer and a first crystallization promoting layer. The second electrode is arranged opposite to the first electrode, the dielectric layer is arranged between the first electrode and the second electrode, and the material of the dielectric layer includes lead zirconate titanate. The first crystallization promoting layer is arranged between the dielectric layer and the first electrode and in contact with the dielectric layer, and is used to promote the crystallization of the dielectric layer. The material of the first crystallization promoting layer is a perovskite structure. The first crystallization promoting layer has the same or similar crystal structure as the dielectric layer. The first crystallization promoting layer can promote the crystal growth of the dielectric layer, so that the dielectric layer can be crystallized at a lower temperature, and the film forming quality is better, so as to improve the performance of the entire semiconductor structure.

[0021] In a second aspect, the present application also provides an electronic device including the semiconductor structure described above. The electronic device includes the semiconductor structure described above, and thus has at least the advantage that the dielectric layer can be formed at a lower temperature and the film quality is better. For details, please refer to the above and will not be repeated here.

[0022] In a third aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, comprising:

[0023] forming a first electrode;

[0024] forming a first crystallization promoting layer on the first electrode, wherein the material of the first crystallization promoting layer is a perovskite structure;

[0025] forming a dielectric layer on the first crystallization promoting layer, wherein the material of the dielectric layer includes lead zirconate titanate;

[0026] A second electrode is formed, the second electrode being opposite to the first electrode.

[0027] In some possible implementations, at least one of the first electrode, the second electrode, the dielectric layer, and the first crystallization promoting layer is formed by sputtering deposition, and the sputtering deposition uses a DC bias of 150V-500V or an AC bias of 50W-400W.

[0028] In some possible implementations, before forming the first electrode, the method further includes:

[0029] providing a substrate;

[0030] A second crystallization promoting layer is formed on the substrate, and the second crystallization promoting layer is used to promote crystallization of the first electrode.

[0031] In some possible implementations, after forming the second crystallization promoting layer on the substrate, the method further includes: forming an adhesion layer on the second crystallization promoting layer.

[0032] In some possible implementations, before forming the second electrode, the method further includes: forming a diffusion barrier layer on the dielectric layer.

[0033] In the method for manufacturing a semiconductor structure provided in an embodiment of the present application, a first electrode, a first crystallization promoting layer, a dielectric layer, and a second electrode are formed. The material of the first crystallization promoting layer is a perovskite structure, and the dielectric layer is formed on the first crystallization promoting layer. The material of the dielectric layer includes lead zirconate titanate, which has the same or similar crystal structure as the first crystallization promoting layer. The first crystallization promoting layer can promote the crystal growth of the dielectric layer, so that the dielectric layer can be crystallized at a lower temperature and has better performance, so as to improve the performance of the entire semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0035] Figure 1 is a schematic diagram of a semiconductor structure in the related art;

[0036] Figure 2 A first schematic diagram of a semiconductor structure in an embodiment of the present application;

[0037] Figure 3 A second schematic diagram of a semiconductor structure in an embodiment of the present application;

[0038] Figure 4 A third schematic diagram of a semiconductor structure in an embodiment of the present application;

[0039] Figure 5 A fourth schematic diagram of a semiconductor structure in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of a conventional structure in an embodiment of the present application;

[0041] Figure 7 is a schematic diagram of a semiconductor structure 1 in an embodiment of the present application;

[0042] Figure 8 is a schematic diagram of a semiconductor structure 2 in an embodiment of the present application;

[0043] Fig. 9 Flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present application.

[0044] Description of reference numerals:

[0045] 10-substrate;

[0046] 20- second crystallization promoting layer;

[0047] 30-Dense layer;

[0048] 40- a first electrode;

[0049] 50-first crystallization promoting layer;

[0050] 60-dielectric layer;

[0051] 70- diffusion barrier layer;

[0052] 80- a second electrode;

[0053] 90-Isolation layer. DETAILED DESCRIPTION

[0054] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0055] See also Figure 1The semiconductor structure includes a first electrode 40 and a second electrode 80 disposed opposite to each other, and a dielectric layer 60 disposed between the first electrode 40 and the second electrode 80. The dielectric layer 60 is usually formed by sputtering. In order to promote the crystal growth of the dielectric layer 60 and improve the performance of the dielectric layer, it is often necessary to heat the substrate 10 to 500°C-600°C or even higher. The crystal growth of the dielectric layer 60 is limited by the material of the substrate 10 and its own manufacturing process. It is difficult to form a film at a lower temperature and it is also difficult to ensure the film quality.

[0056] To this end, the embodiment of the present application provides a semiconductor structure, by setting a first crystallization promoting layer under the dielectric layer, the first crystallization promoting layer is in contact with the dielectric layer and has the same or similar lattice structure. In this way, when the dielectric layer is formed, the dielectric layer is used as the outer edge of the first crystallization promoting layer for crystal growth, so that the dielectric layer can grow crystals at a lower temperature and has better performance, thereby improving the performance of the entire semiconductor structure.

[0057] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0058] The embodiment of the present application provides an electronic device, which may include a mobile phone, a computer, a television, a smart watch, a smart bracelet, a virtual reality (VR) device, an augmented reality (AR) device, a personal digital assistant (PDA), a vehicle-mounted device, etc. The embodiment of the present application does not limit the specific form of the electronic device, and the electronic device may also include household appliances, etc.

[0059] The electronic device may have a memory device or a pressure sensor, and at least one of these devices may have a semiconductor structure applied therein. The memory device may include, for example, a ferroelectric random access memory (FRAM), and the semiconductor structure may be a capacitor. The pressure sensor may include, for example, a MEMS pressure sensor, and the semiconductor structure may be a capacitor.

[0060] See also Figure 2The semiconductor structure includes a first electrode 40, a second electrode 80, a dielectric layer 60 and a first crystallization promoting layer 50. The second electrode 80 is arranged opposite to the first electrode 40, the dielectric layer 60 is arranged between the first electrode 40 and the second electrode 80, and the material of the dielectric layer 60 includes lead zirconate titanate. The first crystallization promoting layer 50 is arranged between the dielectric layer 60 and the first electrode 40, the first crystallization promoting layer 50 is in contact with the dielectric layer 60, and is used to promote the crystallization of the dielectric layer 60, and the material of the first crystallization promoting layer 50 is a perovskite structure.

[0061] Specifically, the first electrode 40 and the second electrode 80 are arranged opposite to each other, for example, the first electrode 40 is a bottom electrode, and the second electrode 80 is a top electrode, and the first electrode 40 and the second electrode 80 generate an electric field. The first electrode 40 can be a single layer or a stacked layer. The thickness of the first electrode 40 is 100nm-1500nm, and the material of the first electrode 40 includes metal, for example, the material of the first electrode 40 includes at least one of platinum, ruthenium, iridium, and rhenium.

[0062] The first electrode 40 can be formed by deposition (eg, sputtering deposition), and the first electrode 40 is sputtered using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The first electrode 40 can be formed in a vacuum device at a temperature of 200°C-350°C.

[0063] The second electrode 80 may be a single layer or a stacked layer. The thickness of the second electrode 80 is 100 nm-1500 nm. The second electrode 80 includes a metal, for example, the material of the second electrode 80 includes at least one of platinum, ruthenium, iridium, and rhenium. The material of the second electrode 80 and the material of the first electrode 40 may be the same or different.

[0064] The second electrode 80 can be formed by deposition (e.g., sputtering deposition), and the second electrode 80 is sputtered using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The second electrode 80 can be formed in a vacuum device at a temperature of 200°C-350°C.

[0065] The dielectric layer 60 is disposed between the first electrode 40 and the second electrode 80. The material of the dielectric layer 60 includes lead zirconate titanate, which has the advantages of high dielectric constant, good rectangularity of hysteresis loop, large residual polarization strength, and good piezoelectric properties. Lead zirconate titanate has a perovskite structure (ABO3 oxide), such as PbZrO3, PbTiO3, etc. The perovskite structure is a superstructure with a ReO3-type framework, which is composed of A ions merging into BO6 regular octahedrons.

[0066] In some possible examples, lead zirconate titanate is pure lead zirconate titanate (PZT) or lead zirconate titanate containing dopants (PNZT), and the dopants include at least one of niobium, calcium, magnesium, barium, scandium, tin, hafnium, bismuth, lanthanum, tungsten, potassium, and iron. Among them, PZT is a continuous solid solution of PbZrO3 and PbTiO3, and the performance parameters of the material can be changed by adjusting the ratio of the two. PNZT introduces dopants, which can directly affect the content of charge defects in the PZT lattice. Using different dopants can change the performance parameters of the material in a wider range.

[0067] The dielectric layer 60 can be formed by deposition, such as sputtering deposition. A bias voltage is used to deposit the dielectric layer 60, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The dielectric layer 60 can be formed in a vacuum device, and the dielectric layer 60 is formed at a temperature of 200°C-350°C. The deposition carrier gas is adjusted according to the purpose of the dielectric layer 60, and is usually argon, argon and oxygen, or argon and nitrogen.

[0068] The first crystallization promoting layer 50 is disposed between the dielectric layer 60 and the first electrode 40 and is in contact with the dielectric layer 60. Specifically, the first crystallization promoting layer 50 is disposed on the surface of the dielectric layer 60 facing the first electrode 40. Figure 2 As shown, the first crystallization promoting layer 50 is disposed on the bottom surface of the dielectric layer 60, and the top surface of the first crystallization promoting layer 50 is in contact with the bottom surface of the dielectric layer 60. The material of the first crystallization promoting layer 50 is a perovskite structure, and illustratively, the material of the first crystallization promoting layer 50 includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate, which can better promote the crystallization of the dielectric layer 60.

[0069] By setting the first crystallization promoting layer 50, the material of the first crystallization promoting layer 50 is a perovskite structure, and the first crystallization promoting layer 50 and the dielectric layer 60 have the same or similar crystal structure (for example, the lattice constant is the same or similar). The first crystallization promoting layer 50 is also in contact with the dielectric layer 60. In this way, in the process of forming the dielectric layer 60, the dielectric layer 60 grows directly on the first crystallization promoting layer 50. The dielectric layer 60 serves as the epitaxy of the first crystallization promoting layer 50. The first crystallization promoting layer 50 can promote the dielectric layer 60 to form a perovskite structure, so that the dielectric layer 60 can grow crystals at a lower temperature (for example, 200°C-350°C) and have better performance, so as to improve the performance of the entire semiconductor structure.

[0070] The first crystallization promoting layer 50 is also in contact with the first electrode 40. Figure 2As shown, the first crystallization promoting layer 50 is arranged on the top surface of the first electrode 40, and the first electrode 40, the first crystallization promoting layer 50 and the dielectric layer 60 are stacked in sequence. The thickness of the first crystallization promoting layer 50 is 10nm-500nm, and the thickness of the first crystallization promoting layer 50 is also less than the thickness of the dielectric layer 60. If the thickness of the first crystallization promoting layer 50 is too thin, the crystallization promoting effect on the dielectric layer 60 is poor, and if the thickness of the first crystallization promoting layer 50 is too thick, the dielectric properties of the entire semiconductor structure are affected.

[0071] In some possible examples, the first crystallization promoting layer 50 can be formed by deposition, such as sputtering deposition. The first crystallization promoting layer 50 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The first crystallization promoting layer 50 can be formed in a vacuum device at a temperature of 200°C-350°C.

[0072] See also Figure 3 and Figure 4 The semiconductor structure further includes a second crystallization promoting layer 20, which is disposed on a side of the first electrode 40 away from the second electrode 80 and is used to promote crystallization of the first electrode 40. Figure 3 and Figure 4 As shown, the second crystallization promoting layer 20 is disposed below the first electrode 40 , and may or may not be in contact with the bottom surface of the first electrode 40 .

[0073] The second crystallization promoting layer 20 has the same or similar crystal structure as the first electrode 40. For example, the material of the first electrode 40 includes metal, and the material of the second crystallization promoting layer 20 includes at least one of zirconium oxide and perovskite. In this way, in the process of forming the first electrode 40, the second crystallization promoting layer 20 can promote the crystal growth of the first electrode 40, so that the first electrode 40 can be crystallized at a lower temperature (for example, 200°C-350°C) and has better performance, so as to improve the performance of the entire semiconductor structure.

[0074] Continue reading Figure 3 and Figure 4 , the second crystallization promoting layer 20 is located on the substrate 10, for example, Figure 3 As shown, the substrate 10, the second crystallization promoting layer 20, the first electrode 40, the first crystallization promoting layer 50, and the dielectric layer 60 are stacked in sequence. The material of the substrate 10 is a semiconductor material, which may include but is not limited to any one or more of silicon, silicon germanium compounds, gallium arsenic compounds, gallium phosphorus compounds, gallium sulfur compounds, etc., or other materials known to those skilled in the art. The material of the substrate 10 may also be quartz, which is not limited in the embodiments of the present application.

[0075] The second crystallization promoting layer 20 is located between the substrate 10 and the first electrode 40, and can also isolate the substrate 10 and the first electrode 40, preventing the first electrode 40 from reacting with the substrate 10 when the first electrode 40 and the film layer thereon are formed, that is, preventing the first electrode 40 and the substrate 10 from alloying, and ensuring the performance of the first electrode 40 and the substrate 10. The thickness of the second crystallization promoting layer 20 is 10nm-1000nm. If the thickness of the second crystallization promoting layer 20 is too thin, the crystallization promoting effect on the first electrode 40 is poor. If the thickness of the second crystallization promoting layer 20 is too thick, the overall performance of the semiconductor structure is affected.

[0076] The second crystallization promoting layer 20 can be formed by deposition, such as sputtering deposition. The second crystallization promoting layer 20 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The second crystallization promoting layer 20 can be formed in a vacuum device at a temperature of 200°C-700°C.

[0077] See also Figure 4 The semiconductor structure further includes an adhesion layer 30, which is disposed between the second crystallization promoting layer 20 and the first electrode 40. For example, the second crystallization promoting layer 20, the adhesion layer 30 and the first electrode 40 are stacked in sequence. The adhesion layer 30, as a transition layer between the second crystallization promoting layer 20 and the first electrode 40, can make the connection between the second crystallization promoting layer 20 and the first electrode 40 more compact, and ensure that the first electrode 40 adheres to the second crystallization promoting layer 20.

[0078] The material of the adhesion layer 30 includes at least one of titanium, zirconium oxide, iridium oxide, and chromium, which can improve the adhesion effect between the ceramic such as lead zirconate titanate and the metal. The thickness of the adhesion layer 30 is 30nm-200nm to avoid the adhesion layer 30 being too thick and weakening the crystallization promoting effect of the second crystallization promoting layer 20 on the first electrode 40.

[0079] The adhesion layer 30 can be formed by deposition, such as sputtering deposition. The adhesion layer 30 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The adhesion layer 30 can be formed in a vacuum device at a temperature of 200°C-350°C.

[0080] See also Figure 4 The semiconductor structure further includes a diffusion barrier layer 70, which is disposed between the dielectric layer 60 and the second electrode 80. Figure 4As shown, the dielectric layer 60, the diffusion barrier layer 70 and the second electrode 80 are stacked in sequence. The diffusion barrier layer 70 can prevent the metal in the second electrode 80 from diffusing into the dielectric layer 60, that is, the diffusion barrier layer 70 can prevent the metal from escaping from the second electrode 80, thereby ensuring the performance of the dielectric layer 60 and the second electrode 80.

[0081] The material of the diffusion barrier layer 70 is a perovskite structure, for example, the material of the diffusion barrier layer 70 includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate. The material of the diffusion barrier layer 70 and the first crystallization promoting layer 50 can be the same or different. The thickness of the diffusion barrier layer 70 is 30nm-150nm.

[0082] The diffusion barrier layer 70 can be formed by deposition, such as sputtering deposition. The diffusion barrier layer 70 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The diffusion barrier layer 70 can be formed in a vacuum device at a temperature of 200°C-350°C.

[0083] Some possible examples include Figure 4 As shown, the semiconductor structure includes a second crystallization promoting layer 20, an adhesion layer 30, a first electrode 40, a first crystallization promoting layer 50, a dielectric layer 60, a diffusion barrier layer 70, and a second electrode 80 stacked in sequence. The second crystallization promoting layer 20 can promote the crystal growth of the first electrode 40, and the first crystallization promoting layer 50 can promote the crystal growth of the dielectric layer 60, so that the first electrode 40 and the dielectric layer 60 are crystallized at a lower temperature with better performance, thereby improving the performance of the semiconductor structure.

[0084] The second crystallization promoting layer 20, the adhesion layer 30, the first electrode 40, the first crystallization promoting layer 50, the dielectric layer 60, the diffusion barrier layer 70 and the second electrode 80 can be formed in one vacuum device or separately. For example, the second crystallization promoting layer 20, the adhesion layer 30 and the first electrode 40 can be formed in one vacuum device, the first crystallization promoting layer 50 and the dielectric layer 60 can be formed in one vacuum device, and the diffusion barrier layer 70 and the second electrode 80 can be formed in one vacuum device.

[0085] In the embodiment of the present application, the structure and performance of the conventional structure, semiconductor structure 1 and semiconductor structure 2 are measured and analyzed. The crystallization performance is analyzed by X-ray diffraction (XRD), the morphology and microstructure are analyzed by scanning electron microscopy (SEM), and the electrical performance is analyzed by residual polarization intensity and antimagnetic force.

[0086] Among them, Figure 6The conventional structure includes an isolation layer 90 (SiO2), an adhesion layer 30 (Ti), a first electrode 40 (Pt), a dielectric layer 60 (PZT), an adhesion layer 30 (Ti), and a second electrode 80 (Pt) stacked in sequence.

[0087] like Figure 7 As shown, the semiconductor structure 1 includes a second crystallization promoting layer 20 (ZrO2 / CaTiO3), an adhesion layer 30 (Ti), a first electrode 40 (Pt), a dielectric layer 60 (PZT), an adhesion layer 30 (Ti), and a second electrode 80 (Pt) which are stacked in sequence.

[0088] like Figure 8 As shown, the semiconductor structure 2 includes a second crystallization promoting layer 20 (ZrO2 / CaTiO3), an adhesion layer 30 (Ti), a first electrode 40 (Pt), a first crystallization promoting layer 50 (BaTiO3 / SrZrO3 / SrFeO3 / SrRuO3), a dielectric layer 60 (PZT), an adhesion layer 30 (Ti), and a second electrode 80 (Pt) which are stacked in sequence.

[0089] By comparing the conventional structure, semiconductor structure 1 and semiconductor structure 2, it can be found that the performance of semiconductor structure 2 is better than that of semiconductor structure 1, and the performance of semiconductor structure 1 is better than that of the conventional structure. The second crystallization promoting layer 20 of ZrO2 and CaTiO3 has the same effect on the crystallization promoting of the first electrode 40, and the first crystallization promoting layer 50 of BaTiO3, SrZrO3, SrFeO3 has a slightly better effect on the crystallization promoting of the dielectric layer 60 than the first crystallization promoting layer 50 of SrRuO3, but the difference is not big.

[0090] The semiconductor structure in the embodiment of the present application includes a first electrode 40, a second electrode 80, a dielectric layer 60 and a first crystallization promoting layer 50. The second electrode 80 is arranged opposite to the first electrode 40, and the dielectric layer 60 is arranged between the first electrode 40 and the second electrode 80. The material of the dielectric layer 60 includes lead zirconate titanate. The first crystallization promoting layer 50 is arranged between the dielectric layer 60 and the first electrode 40, and is in contact with the dielectric layer 60, and is used to promote the crystallization of the dielectric layer 60. The material of the first crystallization promoting layer 50 is a perovskite structure. The first crystallization promoting layer 50 has the same or similar crystal structure as the dielectric layer 60. The first crystallization promoting layer 50 can promote the crystal growth of the dielectric layer 60, so that the dielectric layer 60 can be crystallized at a lower temperature and has better performance, so as to improve the performance of the entire semiconductor structure.

[0091] The present application also provides a method for manufacturing a semiconductor structure. Fig. 9 , the preparation method specifically comprises the following steps:

[0092] Step S100: forming a first electrode.

[0093] See also Figure 5 The first electrode 40 may be formed by deposition (e.g., sputtering deposition), and the first electrode 40 may be sputtered using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The first electrode 40 may be formed in a vacuum device at a temperature of 200°C-350°C.

[0094] The first electrode 40 may be a single layer or a stacked layer. The thickness of the first electrode 40 is 100 nm-1500 nm. The material of the first electrode 40 includes metal, for example, the material of the first electrode 40 includes at least one of platinum, ruthenium, iridium, and rhenium.

[0095] Step S200: forming a first crystallization promoting layer on the first electrode, wherein the material of the first crystallization promoting layer is a perovskite structure.

[0096] See also Figure 5 The first crystallization promoting layer 50 is located on the top surface of the first electrode 40, and can be formed by deposition, such as sputtering deposition. The first crystallization promoting layer 50 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The first crystallization promoting layer 50 can be formed in a vacuum device, and the first crystallization promoting layer 50 is formed at a temperature of 200°C-350°C.

[0097] The thickness of the first crystallization promoting layer 50 is 10nm-500nm. If the thickness of the first crystallization promoting layer 50 is too thin, the crystallization promoting effect on the dielectric layer 60 is poor. If the thickness of the first crystallization promoting layer 50 is too thick, the dielectric properties of the entire semiconductor structure are affected. The material of the first crystallization promoting layer 50 is a perovskite structure. For example, the material of the first crystallization promoting layer 50 includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate, which can better promote the crystallization of the film layer above it.

[0098] Step S300: forming a dielectric layer on the first crystallization promoting layer, wherein the material of the dielectric layer includes lead zirconate titanate.

[0099] See also Figure 5 The material of the dielectric layer 60 includes lead zirconate titanate, which has the advantages of high dielectric constant, good rectangularity of hysteresis loop, large residual polarization strength, and good piezoelectric properties. Lead zirconate titanate has a perovskite structure (ABO3 oxide), such as PbZrO3, PbTiO3, etc. The perovskite structure is a superstructure with a ReO3-type framework, which is composed of A ions merging into BO6 regular octahedrons.

[0100] In some possible examples, lead zirconate titanate is pure lead zirconate titanate (PZT) or lead zirconate titanate containing dopants (PNZT), and the dopants include at least one of niobium, calcium, magnesium, barium, scandium, tin, hafnium, bismuth, lanthanum, tungsten, potassium, and iron. Among them, PZT is a continuous solid solution of PbZrO3 and PbTiO3, and the performance parameters of the material can be changed by adjusting the ratio of the two. PNZT introduces dopants, which can directly affect the content of charge defects in the PZT lattice. Using different dopants can change the performance parameters of the material in a wider range.

[0101] The dielectric layer 60 can be formed by deposition, such as sputtering deposition. The dielectric layer 60 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The dielectric layer 60 can be formed in a vacuum device. The deposition carrier gas is adjusted according to the purpose of the dielectric layer 60, and is usually argon, argon and oxygen, or argon and nitrogen.

[0102] Specifically, the dielectric layer 60 is deposited on the first crystallization promoting layer 50, and the first crystallization promoting layer 50 has the same or similar crystal structure as the dielectric layer 60. In this way, the dielectric layer 60 is directly grown on the first crystallization promoting layer 50. The dielectric layer 60 is used as the epitaxial layer of the first crystallization promoting layer 50, and the first crystallization promoting layer 50 can promote the dielectric layer 60 to form a perovskite structure, so that the dielectric layer 60 can grow crystals at a relatively low temperature (e.g., 200°C-350°C) with better performance, thereby improving the performance of the entire semiconductor structure.

[0103] Step S400: forming a second electrode, the second electrode being opposite to the first electrode.

[0104] See also Figure 5 The second electrode 80 is opposite to the first electrode 40 to generate an electric field. The second electrode 80 can be a single layer or a stacked layer. The thickness of the second electrode 80 is 100nm-1500nm. The second electrode 80 includes a metal. For example, the material of the second electrode 80 includes at least one of platinum, ruthenium, iridium, and rhenium. The material of the second electrode 80 and the material of the first electrode 40 can be the same or different.

[0105] The second electrode 80 can be formed by deposition (e.g., sputtering deposition), and the second electrode 80 is sputtered using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The second electrode 80 can be formed in a vacuum device, and the second electrode 80 is formed at a temperature of 200°C-350°C. After the second electrode 80 is formed, it is removed from the film forming chamber of the vacuum device, returned to the original card box, and then the next process is performed.

[0106] In some possible implementations, before forming the first electrode 40 (step S100 ), the method further includes: providing a substrate 10 ; and forming a second crystallization promoting layer 20 on the substrate 10 , wherein the second crystallization promoting layer 20 is used to promote crystallization of the first electrode 40 .

[0107] The material of the substrate 10 is a semiconductor material, which may include but is not limited to any one or more of silicon, silicon germanium compounds, gallium arsenic compounds, gallium phosphorus compounds, gallium sulfur compounds, etc. The material of the substrate 10 may also be quartz, which is not limited in the present embodiment.

[0108] When the material of the substrate 10 is silicon, the substrate 10 is subjected to SC-1 cleaning and SC-2 cleaning. The solution used in the SC-1 cleaning is NH4OH, H2O2 and H2O; the solvent used in the SC-2 cleaning is HCl, H2O2 and H2O. When the material of the substrate 10 is quartz, after the initial cleaning, H2SO4 and H2O2 cleaning are performed. After the substrate 10 is dried, it is placed in a vacuum device.

[0109] The second crystallization promoting layer 20 can be formed by deposition, for example, by sputtering deposition. The second crystallization promoting layer 20 is deposited using a bias voltage, for example, a DC bias of 150V-500V or an AC bias of 50W-400W, for example, by applying the above bias voltage to the substrate 10. The second crystallization promoting layer 20 can be formed in a vacuum device, and the second crystallization promoting layer 20 is formed at a temperature of 200°C-700°C, for example, by heating the substrate 10 to 200°C-700°C.

[0110] The second crystallization promoting layer 20 is located below the first electrode 40, and may or may not be in contact with the bottom surface of the first electrode 40. The second crystallization promoting layer 20 has the same or similar crystal structure as the first electrode 40. For example, the material of the first electrode 40 includes metal, and the material of the second crystallization promoting layer 20 includes at least one of zirconium oxide and perovskite. In this way, in the process of forming the first electrode 40, the second crystallization promoting layer 20 can promote the crystal growth of the first electrode 40, so that the first electrode 40 can be crystallized at a lower temperature (e.g., 200°C-350°C) and has better performance, so as to improve the performance of the entire semiconductor structure.

[0111] The second crystallization promoting layer 20 can also isolate the substrate 10 and the first electrode 40, and prevent the first electrode 40 from reacting with the substrate 10 when the first electrode 40 and the film layer thereon are formed, that is, it can prevent the first electrode 40 and the substrate 10 from alloying, and ensure the performance of the first electrode 40 and the substrate 10. The thickness of the second crystallization promoting layer 20 is 10nm-1000nm. If the thickness of the second crystallization promoting layer 20 is too thin, the crystallization promoting effect on the first electrode 40 is poor. If the thickness of the second crystallization promoting layer 20 is too thick, the overall performance of the semiconductor structure is affected.

[0112] In some possible implementations, after forming the second crystallization promoting layer 20 on the substrate 10, the method further includes: forming an adhesion layer 30 on the second crystallization promoting layer 20. The adhesion layer 30 serves as a transition layer between the second crystallization promoting layer 20 and the first electrode 40, and can make the connection between the second crystallization promoting layer 20 and the first electrode 40 more compact, thereby ensuring that the first electrode 40 adheres to the second crystallization promoting layer 20.

[0113] The adhesion layer 30 can be formed by deposition, such as sputtering deposition. The adhesion layer 30 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The adhesion layer 30 can be formed in a vacuum device at a temperature of 200°C-350°C.

[0114] The material of the adhesion layer 30 includes at least one of titanium, zirconium oxide, iridium oxide, and chromium, which can improve the adhesion effect between the ceramic such as lead zirconate titanate and the metal. The thickness of the adhesion layer 30 is 30nm-200nm to avoid the adhesion layer 30 being too thick and weakening the crystallization promoting effect of the second crystallization promoting layer 20 on the first electrode 40.

[0115] In some possible implementations, before forming the second electrode 80 (step S400), the method further includes: forming a diffusion barrier layer 70 on the dielectric layer 60. The diffusion barrier layer 70 can prevent the metal in the second electrode 80 from diffusing into the dielectric layer 60, that is, the diffusion barrier layer 70 can prevent the metal from escaping from the second electrode 80, thereby ensuring the performance of the dielectric layer 60 and the second electrode 80.

[0116] The diffusion barrier layer 70 can be formed by deposition, such as sputtering deposition. The diffusion barrier layer 70 is deposited using a bias voltage, such as a DC bias of 150V-500V or an AC bias of 50W-400W. The diffusion barrier layer 70 can be formed in a vacuum device at a temperature of 200°C-350°C.

[0117] The material of the diffusion barrier layer 70 is a perovskite structure, for example, the material of the diffusion barrier layer 70 includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate. The material of the diffusion barrier layer 70 and the first crystallization promoting layer 50 can be the same or different. The thickness of the diffusion barrier layer 70 is 30nm-150nm.

[0118] The second crystallization promoting layer 20, the adhesion layer 30, the first electrode 40, the first crystallization promoting layer 50, the dielectric layer 60, the diffusion barrier layer 70 and the second electrode 80 can be formed in one vacuum device or separately. For example, the second crystallization promoting layer 20, the adhesion layer 30 and the first electrode 40 can be formed in one vacuum device, the first crystallization promoting layer 50 and the dielectric layer 60 can be formed in one vacuum device, and the diffusion barrier layer 70 and the second electrode 80 can be formed in one vacuum device.

[0119] In the method for manufacturing the semiconductor structure in the embodiment of the present application, a first electrode 40, a first crystallization promoting layer 50, a dielectric layer 60 and a second electrode 80 are formed. The material of the first crystallization promoting layer 50 is a perovskite structure, and the dielectric layer 60 is formed on the first crystallization promoting layer 50. The material of the dielectric layer 60 includes lead zirconate titanate, which has the same or similar crystal structure as the first crystallization promoting layer 50. The first crystallization promoting layer 50 can promote the crystal growth of the dielectric layer 60, so that the dielectric layer 60 can be crystallized at a lower temperature and has better performance, so as to improve the performance of the entire semiconductor structure.

[0120] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application, are not limited to the precise structures described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: a first electrode; a second electrode, arranged opposite to the first electrode; A dielectric layer, disposed between the first electrode and the second electrode, wherein the material of the dielectric layer comprises lead zirconate titanate; The first crystallization promoting layer is arranged between the dielectric layer and the first electrode and contacts the dielectric layer, and is used to promote crystallization of the dielectric layer. The material of the first crystallization promoting layer is a perovskite structure.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a second crystallization promoting layer, which is disposed on a side of the first electrode away from the second electrode and is used to promote crystallization of the first electrode.

3. The semiconductor structure according to claim 2, characterized in that: The material of the second crystallization promoting layer includes at least one of zirconium oxide and perovskite.

4. The semiconductor structure according to claim 2, characterized in that: The thickness of the first crystallization promoting layer is 20nm-200nm; and / or the thickness of the second crystallization promoting layer is 10nm-1000nm.

5. The semiconductor structure according to claim 2, characterized in that: The semiconductor structure further includes an adhesion layer disposed between the second crystallization promoting layer and the first electrode.

6. The semiconductor structure according to claim 5, characterized in that: The material of the adhesion layer includes at least one of titanium, zirconium oxide, iridium oxide and chromium.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The material of the first crystallization promoting layer includes at least one of barium titanate, strontium zirconate, strontium ferrite and strontium ruthenate.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The lead zirconate titanate is pure lead zirconate titanate or lead zirconate titanate containing a dopant; The dopant includes at least one of niobium, calcium, magnesium, barium, scandium, tin, hafnium, bismuth, lanthanum, tungsten, potassium, and iron.

9. The semiconductor structure according to any one of claims 1 to 6, characterized in that: At least one of the first electrode, the second electrode, the dielectric layer and the first crystallization promoting layer is formed by sputtering deposition, and the sputtering deposition adopts a DC bias of 150V-500V or an AC bias of 50W-400W.

10. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The semiconductor structure further includes a diffusion barrier layer disposed between the dielectric layer and the second electrode.

11. An electronic device, characterized in that: A semiconductor structure comprising any one of claims 1 to 10.

12. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first electrode; forming a first crystallization promoting layer on the first electrode, wherein the material of the first crystallization promoting layer is a perovskite structure; forming a dielectric layer on the first crystallization promoting layer, wherein the material of the dielectric layer includes lead zirconate titanate; A second electrode is formed, the second electrode being opposite to the first electrode.

13. The manufacturing method according to claim 12, characterized in that: At least one of the first electrode, the second electrode, the dielectric layer and the first crystallization promoting layer is formed by sputtering deposition, and the sputtering deposition adopts a DC bias of 150V-500V or an AC bias of 50W-400W.

14. The production method according to claim 12 or 13, characterized in that: Before forming the first electrode, the method further includes: providing a substrate; A second crystallization promoting layer is formed on the substrate, and the second crystallization promoting layer is used to promote crystallization of the first electrode.

15. The manufacturing method according to claim 14, characterized in that: After forming a second crystallization promoting layer on the substrate, the method further includes: forming an adhesion layer on the second crystallization promoting layer.

16. The method according to claim 12 or 13, characterized in that: Before forming the second electrode, the method further includes: forming a diffusion barrier layer on the dielectric layer.

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