A method for determining failure position of array capacitor

Abstract

The present application provides a method for determining a failure position of an array capacitor, comprising: sequentially connecting only each row of upper plate blocks located in a first direction on an upper plate of the array, and providing a first level to a first target end of each row of upper plate blocks located in the first direction and providing a second level to a lower plate; detecting a first conduction condition between each row of upper plate blocks located in the first direction and the lower plate, and determining whether there is a failure position in the array capacitor; if it is determined that there is a failure position in the array capacitor, removing the connection relationship between each row of upper plate blocks located in the first direction, and sequentially connecting only each row of upper plate blocks located in a second direction on the upper plate of the array, and providing a first level to a second target end of each row of upper plate blocks located in the second direction and providing a second level to the lower plate; detecting a second conduction condition between each row of upper plate blocks located in the second direction and the lower plate, and determining the failure position in combination with the first conduction condition and the second conduction condition.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for determining a failure position of an array capacitor. Background Art

[0002] MIM capacitors (metal insulator metal) are usually composed of two upper and lower metal plates and a dielectric layer between them. Among them, defects in the dielectric layer will cause the MIM capacitor to fail. In the prior art, the capacitor plates are metal layers with larger specifications and thicker thickness. Furthermore, an EFA (electrical failure analysis) machine is used to perform electrical failure analysis, bombard the metal layer with electron beams and locate the failure point by detecting electrons flowing through the metal layer, but the metal layer will block the electron beam. Alternatively, laser scanning is performed by an OBRICH (Optical Beam Induced Resistance Change) machine to determine the resistance change, so as to find the failure location, but the metal layer will affect the penetration of the laser. Alternatively, thermal radiation is performed to the capacitor by a Thermal machine, so as to analyze the failure location by capacitor thermal imaging, but the metal layer will affect the thermal conductivity. Therefore, due to the influence of the metal layer, it is difficult to determine the failure location of the MIM capacitor and the accuracy of determining the failure location is affected. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide at least a method for determining the failure position of an array capacitor, by sequentially connecting each row of upper plate blocks of the array upper plates of the array capacitor in the first direction, detecting the conductivity of each row of upper plate blocks and the lower plate in the first direction, and removing the connection relationship of each row of upper plate blocks in the first direction, and then sequentially connecting each row of upper plate blocks in the second direction, detecting the conductivity of each row of upper plate blocks and the lower plate in the second direction, and combining the two detected conductivity conditions to determine the failure position of the array capacitor, thereby solving the technical problem of difficulty in determining the specific failure position of the capacitor in the prior art and achieving the technical effect of accurately determining the failure position.

[0004] This application mainly includes the following aspects:

[0005] In a first aspect, an embodiment of the present application provides a method for determining a failure position of an array capacitor, wherein the array capacitor includes an array upper plate, a lower plate, and a dielectric layer located between the upper plate and the lower plate, wherein the array upper plate includes a plurality of upper plate blocks arranged in an array, and the upper plate blocks do not contact each other, wherein the method includes: sequentially connecting only each row of upper plate blocks located in a first direction on the array upper plate, and providing a first level to a first target end of each row of upper plate blocks located in the first direction and providing a second level to the lower plate; detecting a voltage between each row of upper plate blocks located in the first direction and the lower plate; The method comprises the steps of: detecting a first conduction condition between each row of upper plate blocks in the first direction to determine whether there is a failure position of the array capacitor; when determining that there is a failure position of the array capacitor, removing the connection relationship between each row of upper plate blocks in the first direction, only connecting each row of upper plate blocks in the second direction on the array upper plate in sequence, providing a first level to the second target end of each row of upper plate blocks in the second direction and providing a second level to the lower plate; detecting a second conduction condition between each row of upper plate blocks in the second direction and the lower plate, and determining the failure position of the array capacitor by combining the first conduction condition and the second conduction condition.

[0006] Optionally, each row of upper plate blocks located in the first direction is one of the upper plate blocks in each row and the upper plate blocks in each column in the array upper plate, and each row of upper plate blocks located in the second direction is another of the upper plate blocks in each row and the upper plate blocks in each column in the array upper plate.

[0007] Optionally, each row of upper plate blocks is connected in sequence by: connecting adjacent upper plate blocks in the row according to the row direction of the upper plate blocks in the row; and / or, each column of upper plate blocks is connected in sequence by: connecting adjacent upper plate blocks in the column according to the column direction of the upper plate blocks in the column.

[0008] Optionally, the first target end is one end or the other end of each row of upper plate blocks located in the first direction after being connected in sequence, and the second target end is one end or the other end of each row of upper plate blocks located in the second direction after being connected in sequence.

[0009] Optionally, the detecting a first conduction condition between each row of upper plate blocks located in the first direction and the lower plate to determine whether the array capacitor has a failure position comprises: when it is detected that conduction is found between any row of upper plate blocks located in the first direction and the lower plate, it is determined that the array capacitor has a failure position; when it is detected that no conduction is found between each row of upper plate blocks located in the first direction and the lower plate, it is determined that the array capacitor does not have a failure position.

[0010] Optionally, the failure position of the array capacitor is determined in the following manner: based on the first conduction condition, a first target row of conduction is determined in each row of upper plate blocks located in the first direction; based on the second conduction condition, a second target row of conduction is determined in each row of upper plate blocks located in the second direction; based on the intersection position of the first target row and the second target row, the failure position of the array capacitor is determined.

[0011] Optionally, the first target row includes one and / or the second target row includes one, wherein the failure position of the array capacitor is determined in the following manner: the position corresponding to at least one target upper plate block corresponding to the intersection position is determined as the failure position.

[0012] Optionally, the first target row includes multiple and the second target row includes multiple, wherein the failure position of the array capacitor is determined by: removing the connection relationship between each row of upper electrode plate blocks; providing a first level to the lower electrode plate and providing a second level to multiple target upper electrode plate blocks corresponding to the intersection position, and determining the conduction status between each target upper electrode plate block and the lower electrode plate; determining the position corresponding to the target upper electrode plate block that is conductive with the lower electrode plate as the failure position of the array capacitor.

[0013] Optionally, the conduction status is determined by: determining whether each row of upper plate blocks and the lower plate are conductive by detecting the current value between each row of upper plate blocks and the lower plate; or, providing a diode for each row of upper plate blocks, and determining whether each row of upper plate blocks and the lower plate are conductive by detecting whether the diode corresponding to each row of upper plate blocks is lit.

[0014] Optionally, diodes are set for each row of upper plate blocks in the following manner: one end of each row of upper plate blocks located in the first direction is connected to one end of a first diode, and the other end of the first diode corresponding to each row of upper plate blocks located in the first direction is connected as a first receiving point, and the first receiving point is used to connect the first level; one end of each row of upper plate blocks located in the second direction is connected to one end of a second diode, and the other end of the second diode corresponding to each row of upper plate blocks located in the second direction is connected as a second receiving point, wherein the first receiving point and the second receiving point are both used to connect the first level.

[0015] The present application provides a method for determining a failure position of an array capacitor, wherein the array capacitor includes an array upper plate, a lower plate, and a dielectric layer located between the upper plate and the lower plate, wherein the array upper plate includes a plurality of upper plate blocks arranged in an array, and the upper plate blocks are not in contact with each other, wherein the method includes: sequentially connecting only each row of upper plate blocks located in a first direction on the array upper plate, and providing a first level to a first target end of each row of upper plate blocks located in the first direction and providing a second level to the lower plate; detecting a first voltage between each row of upper plate blocks located in the first direction and the lower plate; A conduction condition is used to determine whether there is a failure position of the array capacitor; when it is determined that there is a failure position of the array capacitor, the connection relationship between each row of upper plate blocks located in the first direction is removed, and only each row of upper plate blocks located in the second direction on the array upper plate are connected in sequence, and a first level is provided to the second target end of each row of upper plate blocks located in the second direction and a second level is provided to the lower plate; a second conduction condition between each row of upper plate blocks located in the second direction and the lower plate is detected, and the failure position of the array capacitor is determined by combining the first conduction condition and the second conduction condition. After sequentially connecting each row of upper plate blocks of the array capacitor in the first direction, detecting the conduction condition between each row of upper plate blocks and the lower plate in the first direction, and removing the connection relationship between each row of upper plate blocks in the first direction, sequentially connecting each row of upper plate blocks in the second direction, detecting the conduction condition between each row of upper plate blocks and the lower plate in the second direction, and combining the two detected conduction conditions to determine the failure position of the array capacitor, the technical problem of difficulty in determining the specific failure position of the capacitor in the prior art is solved, and the technical effect of accurately determining the failure position is achieved.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of an array capacitor provided in an embodiment of the present application is shown.

[0019] Figure 2 A flow chart of a method for determining a failure position of an array capacitor provided in an embodiment of the present application is shown.

[0020] Figure 3 A schematic diagram showing a method for determining a failure position of an array capacitor provided in an embodiment of the present application is shown. Figure 1 .

[0021] Figure 4 A schematic diagram showing a method for determining a failure position of an array capacitor provided in an embodiment of the present application is shown. Figure 2 .

[0022] Figure 5 A schematic diagram of another method for determining the failure position of an array capacitor provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0023] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art, under the guidance of the content of the present application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0024] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0025] In the prior art, when determining the failure position of a metal-insulator-metal capacitor, it is necessary to determine the electrons fed back by each position of the capacitor by impacting the capacitor with an electron beam, so as to determine whether there is an electron beam at each position of the capacitor to determine whether there is a failure position of the capacitor; or, determine the resistance fed back by each position of the capacitor by impacting the capacitor with a laser beam, so as to determine whether there is a failure position of the capacitor by determining the resistance at each position of the capacitor; or, determine the heat energy fed back by each position of the capacitor by thermal radiation, so as to determine whether there is a failure position of the capacitor by determining the heat energy at each position of the capacitor. However, due to the certain thickness of the metal layer, the metal layer will block the electron beam, laser beam or heat conduction, so that the result fed back by the machine is difficult to accurately know whether there is a failure position of the capacitor, and it is difficult to accurately determine the specific failure position of the capacitor.

[0026] Based on this, a method for determining the failure position of an array capacitor is provided. After sequentially connecting each row of upper plate blocks of the array upper plate of the array capacitor in the first direction, the conduction condition of each row of upper plate blocks and the lower plate in the first direction is detected, and the connection relationship of each row of upper plate blocks in the first direction is removed. Then, each row of upper plate blocks in the second direction is sequentially connected, and the conduction condition of each row of upper plate blocks and the lower plate in the second direction is detected. The failure position of the array capacitor is determined by combining the two detected conduction conditions, which solves the technical problem that it is difficult to determine the specific failure position of the capacitor in the prior art, and achieves the technical effect of accurately determining the failure position, which is specifically as follows:

[0027] For example, see Figure 1 , Figure 1 Schematic diagram of an array capacitor provided in an embodiment of the present application. Figure 1 As shown, the array capacitor includes an array upper plate Mn+1, a lower plate Mn, and a dielectric layer 201 located between the upper plate and the lower plate of the array. The array upper plate includes Mn+1 and multiple upper plate blocks arranged in an array, and the upper plate blocks are not in contact.

[0028] like Figure 1 As shown, the array upper plate Mn+1 includes an upper plate block 101, an upper plate block 102, an upper plate block 103 and an upper plate block 104, and the upper plate block 101, the upper plate block 102, the upper plate block 103 and the upper plate block 104 are not in contact with each other, that is, each upper plate block is placed on the dielectric layer and there is no electrical connection line between them.

[0029] Exemplarily, each row of upper plate blocks in the array upper plate is used as an upper plate block arranged in the x-axis direction, and then, upper plate block 101 and upper plate block 102 are in one row, and upper plate block 103 and upper plate block 104 are in another row. Each column of upper plate blocks in the array upper plate is used as an upper plate block arranged in the y-axis direction, and then, upper plate block 101 and upper plate block 103 are in one column, and upper plate block 102 and upper plate block 104 are in another column.

[0030] Exemplarily, when there is no failure position in the array capacitor, it can be considered that there are no pores or connected positions in the dielectric layer. Furthermore, for each upper plate block, a voltage with a potential difference is provided to the upper plate block and the lower plate, that is, the upper plate block and the lower plate are respectively connected to different voltages. If there is a failure position in the dielectric layer corresponding to the upper plate block, current flows between the upper plate block and the lower plate. If there is no failure position in the dielectric layer corresponding to the upper plate block, no current flows between the upper plate block and the lower plate.

[0031] See also Figure 2 , Figure 2 A flowchart for determining the failure position of an array capacitor provided in an embodiment of the present application. Figure 2 As shown, the method for determining the failure position of an array capacitor provided in an embodiment of the present application includes the following steps:

[0032] S101: sequentially connecting only each row of upper plate blocks located in a first direction on the array upper plate, and providing a first level to a first target end of each row of upper plate blocks located in the first direction and providing a second level to the lower plate.

[0033] Each row of upper plate blocks located in the first direction is one of each row of upper plate blocks and each column of upper plate blocks in the array upper plate.

[0034] Each row of upper plate blocks is connected in sequence by: connecting adjacent upper plate blocks in the row according to the row direction of the upper plate blocks in the row; and / or, each column of upper plate blocks is connected in sequence by: connecting adjacent upper plate blocks in the column according to the column direction of the upper plate blocks in the column.

[0035] That is, the first direction refers to the direction of the upper plate blocks of each row or each column in the array upper plate, and the second direction refers to the direction except the first direction in the directions corresponding to the upper plate blocks of each row and each column. That is, when the first direction is the direction of the upper plate blocks of each row, the second direction is the direction of the upper plate blocks of each column; when the first direction is the direction of the upper plate blocks of each column, the second direction is the direction of the upper plate blocks of each row.

[0036] Furthermore, only connecting each row of upper plate blocks located in the first direction on the array upper plate in sequence includes: when the first direction is the row direction where the upper plate blocks in each row are located, then for each row of upper plate blocks, only the upper plate blocks in this row are electrically connected to the adjacent upper plate blocks in the row direction in sequence, so that the upper plate blocks in this row are connected in the row direction, and then, only the upper plate blocks in each row of the array upper plate are connected in their respective row directions, and the upper plate blocks in each row are not connected to each other in the column direction; when the first direction is the column direction where the upper plate blocks in each column are located, then for each column of upper plate blocks, the upper plate blocks in this column are electrically connected to the adjacent upper plate blocks in the column direction in sequence, so that the upper plate blocks in this column are connected in the column direction, and then, the upper plate blocks in each column are connected in the column direction, and the upper plate blocks in each column are not connected to each other in the row direction.

[0037] The first target end is one end or the other end of each row of upper plate blocks located in the first direction after being sequentially connected. That is to say, for each row of upper plate blocks located in the first direction, one end or the other end of the row of upper plate blocks after being sequentially connected in the first direction is used as the first target end of the row of upper plate blocks.

[0038] Among them, the first target end of each row of upper plate blocks located in the first direction can be a different end, and it is only necessary to provide the first level to one end or the other end of each row of upper plate blocks located in the first direction, and there is a potential difference between the first level and the second level, so that when there is a failure position corresponding to any row of upper plate blocks in the first direction, a conductive loop can be formed through the first level and the second level.

[0039] Exemplarily, the first level is one of a high level and a low level, and the second level is the other of the high level and the low level.

[0040] See also Figure 3 , Figure 3 A schematic diagram of determining the failure position of an array capacitor provided in an embodiment of the present application Figure 1 .like Figure 3As shown, if the first direction in the array upper plate is the direction where the x-axis is located, then each row of upper plate blocks located in the first direction includes: a row of upper plate blocks where upper plate blocks 101 and upper plate blocks 102 are located, and another row of upper plate blocks where upper plate blocks 103 and upper plate blocks 104 are located. The lower plate is connected to voltage V, and the solid line indicates that the upper plate block 101 and the upper plate block 102 are connected in the x-axis direction, and one end of the connected upper plate block 101 and the upper plate block 102 are grounded GND; the solid line indicates that the upper plate block 103 and the upper plate block 104 are connected in the x-axis direction, and one end of the connected upper plate block 103 and the upper plate block 104 are grounded GND. At this time, each column of the upper plate blocks in the array upper plate is not connected in the y-axis direction, that is, only each row of the upper plate blocks in the control array upper plate is connected in the x-axis direction.

[0041] like Figure 3 As shown, if the first direction in the array upper plate is the direction where the y-axis is located, then each row of upper plate blocks located in the first direction includes: a column of upper plate blocks where upper plate blocks 101 and upper plate blocks 103 are located, and another column of upper plate blocks where upper plate blocks 102 and upper plate blocks 104 are located. The lower plate is connected to voltage V, and the dotted line indicates that the upper plate block 101 and the upper plate block 103 are connected in the y-axis direction, and one end of the connected upper plate block 101 and the upper plate block 103 are grounded GND; the dotted line indicates that the upper plate block 102 and the upper plate block 104 are connected in the y-axis direction, and one end of the connected upper plate block 102 and the upper plate block 104 are grounded GND. At this time, each row of upper plate blocks in the array upper plate is not connected in the x-axis direction, that is, only each column of upper plate blocks in the control array upper plate is connected in the y-axis direction.

[0042] return Figure 2 , S102; detecting a first conduction condition between each row of upper plate blocks and the lower plate in a first direction to determine whether there is a failure position in the array capacitor.

[0043] Specifically, the detecting of a first conduction condition between each row of upper plate blocks located in the first direction and the lower plate to determine whether the array capacitor has a failure position includes: when it is detected that conduction is found between any row of upper plate blocks located in the first direction and the lower plate, it is determined that the array capacitor has a failure position; and when it is detected that no conduction is found between each row of upper plate blocks located in the first direction and the lower plate, it is determined that the array capacitor does not have a failure position.

[0044] Furthermore, when it is determined that there is no failure position in the array capacitor, there is no need to perform subsequent steps. It is only necessary to remove the connection relationship formed by sequentially connecting each row of upper plate blocks located in the first direction to obtain the array capacitor with the failure position verified.

[0045] That is to say, it is determined whether each row of upper plate blocks and the lower plate in the first direction are conductive; when any row of upper plate blocks and the lower plate are conductive, it is considered that there is a failure position in the array capacitor, that is, there is a failure position in the dielectric layer, which causes current to flow between the upper plate block and the lower plate and cause conduction; when each row of upper plate blocks is not conductive to the lower plate, it is considered that there is no failure position in the array capacitor, that is, the dielectric layer has insulation ability, so that no current will flow between the upper plate block and the lower plate, that is, conduction is impossible.

[0046] Specifically, the conduction status is determined in the following manner: by detecting the current value between each row of upper plate blocks and the lower plate, determining whether each row of upper plate blocks and the lower plate are conductive; or, providing a diode for each row of upper plate blocks, and determining whether each row of upper plate blocks and the lower plate are conductive by detecting whether the diode corresponding to each row of upper plate blocks is lit.

[0047] Among them, the first conduction condition between each row of upper electrode plate blocks and the lower electrode plate located in the first direction is determined in the following manner: for each row of upper electrode plate blocks located in the first direction, by detecting the current value between the row of upper electrode plate blocks and the lower electrode plate, when the current value belongs to the preset conduction current interval, it is considered that the row of upper electrode plate blocks and the lower electrode plate are conductive, and when the current value does not belong to the preset conduction current interval, it is considered that the row of upper electrode plate blocks and the lower electrode plate are not conductive.

[0048] Exemplarily, for each row of upper plate blocks located in the first direction, the current value between the first target end of the row of upper plate blocks and the lower plate can be used as the current value between the row of upper plate blocks and the lower plate. The preset conduction current interval refers to a preset current interval corresponding to when there is a failure position in the dielectric layer and the upper and lower plates of the array capacitor are turned on.

[0049] For example, return Figure 3If the first direction in the array upper plate is the direction of the x-axis, detect the first row of current values ​​of the upper plate blocks in a row where the upper plate blocks 101 and 102 are located, and detect the second row of current values ​​of the upper plate blocks in a row where the upper plate blocks 103 and 104 are located. Furthermore, if the first row of current values ​​and the second row of current values ​​are both infinite, it is considered that there is no failure position in the array capacitor; if the first row of current values ​​and / or the second row of current values ​​belong to the preset conduction current interval, it is considered that there is a failure position in the array capacitor. Among them, when only the first row of current values ​​belongs to the preset conduction current interval, the position corresponding to at least one of the upper plate block 101 and the upper plate block 102 is considered to be a failure position; when only the second row of current values ​​belongs to the preset conduction current interval, the position corresponding to at least one of the upper plate block 103 and the upper plate block 104 is considered to be a failure position; when both the first row of current values ​​and the second row of current values ​​belong to the preset conduction current interval, the positions corresponding to at least one of the upper plate block 101 and the upper plate block 102 and at least one of the upper plate block 103 and the upper plate block 104 are failure positions.

[0050] Among them, Figure 3 As shown, if the first direction in the array upper plate is the direction of the y-axis, the first column of current values ​​of a column of upper plate blocks where upper plate blocks 101 and upper plate blocks 103 are located are detected, and the second column of current values ​​of a column of upper plate blocks where upper plate blocks 102 and upper plate blocks 104 are located are detected. Furthermore, if the first column of current values ​​and the second column of current values ​​are both infinite, it is considered that there is no failure position in the array capacitor; if the first column of current values ​​and / or the second column of current values ​​belong to the preset conduction current range, it is considered that there is a failure position in the array capacitor. Among them, when only the first column of current values ​​belongs to the preset conduction current interval, the position corresponding to at least one of the upper plate block 101 and the upper plate block 103 is considered to be a failure position; when only the second column of current values ​​belongs to the preset conduction current interval, the position corresponding to at least one of the upper plate block 102 and the upper plate block 104 is considered to be a failure position; when both the first column of current values ​​and the second column of current values ​​belong to the preset conduction current interval, the positions corresponding to at least one of the upper plate block 101 and the upper plate block 103 and at least one of the upper plate block 103 and the upper plate block 104 are failure positions.

[0051] Alternatively, the first conduction condition between each row of upper plate blocks and the lower plate located in the first direction is determined in the following manner: a first diode is set for each row of upper plate blocks located in the first direction, and whether the first diode corresponding to each row of upper plate blocks located in the first direction is lit is detected to determine whether each row of upper plate blocks located in the first direction is conductive to the lower plate.

[0052] Among them, a first diode is set for each row of upper plate blocks located in the first direction in the following manner: one end of each row of upper plate blocks located in the first direction is connected to one end of the first diode, and the other end of the first diode corresponding to each row of upper plate blocks located in the first direction is connected as a first receiving point, and the first receiving point is used to connect to the first level.

[0053] That is to say, for each row of upper plate blocks located in the first direction, one end of the row of upper plate blocks is connected to one end of the first diode, and the other end of the first diode is connected to the first level and the lower plate is connected to the second level. Then, when the first diode corresponding to the row of upper plate blocks is lit, it is considered that there is a failure position at the position where the upper plate block corresponding to the row of upper plate blocks is located.

[0054] See also Figure 4 , Figure 4 A schematic diagram of determining the failure position of an array capacitor provided in an embodiment of the present application Figure 2 .like Figure 4 As shown, if the first direction in the array upper plate is the direction where the x-axis is located, the solid lines indicate that each row of upper plate blocks in the first direction are connected in sequence, one end of the upper plate block in a row where the upper plate block 101 and the upper plate block 102 are located corresponds to one end of the first diode D1 connected, and one end of the upper plate block in a row where the upper plate block 103 and the upper plate block 104 are located corresponds to one end of the first diode D2 connected, and the other end of the first diode D1 and the other end of the first diode D2 are both grounded GND, and the lower plate is connected to the voltage V, and the voltage V should be greater than the diode conduction voltage. Furthermore, if the first diode D1 and the first diode D2 are not lit, it is considered that there is no failure position in the array capacitor; if the first diode D1 and / or the first diode D2 are lit, it is considered that there is a failure position in the array capacitor. Among them, when only the first diode D1 is lit, the position corresponding to at least one of the upper plate block 101 and the upper plate block 102 is considered to be a failure position; when only the first diode D2 is lit, the position corresponding to at least one of the upper plate block 103 and the upper plate block 104 is considered to be a failure position; when the first diode D1 and the first diode D2 are both lit, the positions corresponding to at least one of the upper plate block 101 and the upper plate block 102 and at least one of the upper plate block 103 and the upper plate block 104 are failure positions.

[0055] like Figure 4As shown, if the first direction in the array upper plate is the direction where the y-axis is located, the dotted lines indicate that each row of upper plate blocks in the first direction are connected in sequence, one end of a column of upper plate blocks where upper plate blocks 101 and upper plate blocks 103 are located corresponds to one end of the first diode D3 connected, and one end of a column of upper plate blocks where upper plate blocks 102 and upper plate blocks 104 are located corresponds to one end of the first diode D4 connected, and the other end of the first diode D3 and the other end of the first diode D4 are both grounded GND, and the lower plate is connected to the voltage V. Furthermore, if the first diode D3 and the first diode D4 are not lit, it is considered that there is no failure position in the array capacitor; if the first diode D3 and / or the first diode D4 are lit, it is considered that there is a failure position in the array capacitor. Among them, when only the first diode D3 is lit, the position corresponding to at least one of the upper plate block 101 and the upper plate block 103 is considered to be a failure position; when only the first diode D4 is lit, the position corresponding to at least one of the upper plate block 102 and the upper plate block 104 is considered to be a failure position; when the first diode D3 and the first diode D4 are both lit, the positions corresponding to at least one of the upper plate block 101 and the upper plate block 103 and at least one of the upper plate block 102 and the upper plate block 104 are failure positions.

[0056] return Figure 2 , S103: remove the connection relationship between each row of upper plate blocks located in the first direction, and only connect each row of upper plate blocks located in the second direction on the array upper plate in sequence, and provide a first level to the second target end of each row of upper plate blocks located in the second direction and provide a second level to the lower plate.

[0057] When it is determined that there is a failure position in the array capacitor, the connection relationship between each row of upper plate blocks located in the first direction is removed, and only each row of upper plate blocks located in the second direction on the array upper plate are connected in sequence, and a first level is provided to the second target end of each row of upper plate blocks located in the second direction and a second level is provided to the lower plate.

[0058] That is to say, when it is determined that there is a failure position in the array capacitor, the wires between the adjacent upper plate blocks in each row of upper plate blocks in the first direction are cut off, so that the upper plate blocks in the array upper plate of the array capacitor are still not in contact with each other. In this case, each row of upper plate blocks in the second direction on the array upper plate are connected in sequence, and the second target end of each row of upper plate blocks in the second direction is connected to the first level, and the lower plate is connected to the second level.

[0059] Wherein, each row of upper plate blocks located in the second direction is the other of each row of upper plate blocks and each column of upper plate blocks in the array upper plate. That is to say, when each row of upper plate blocks located in the first direction is each row of upper plate blocks, each row of upper plate blocks located in the second direction is each column of upper plate blocks; when each row of upper plate blocks located in the first direction is each column of upper plate blocks, each row of upper plate blocks located in the second direction is each row of upper plate blocks.

[0060] Furthermore, only connecting each row of upper plate blocks located in the second direction on the upper plate of the array in sequence includes: when the first direction is the row direction where the upper plate blocks in each row are located, the second direction is the column direction where the upper plate blocks in each column are located, and the electrical connection relationship of the upper plate blocks in each row in the first direction is removed to achieve that the adjacent upper plate blocks in each row of upper plate blocks are not connected in the row direction, and then, for each column of upper plate blocks, the upper plate blocks in the column are electrically connected to the adjacent upper plate blocks in the column direction in sequence, so that the upper plate blocks in the column are connected in the column direction, and then, only achieving The upper plate blocks in each column are connected in their respective column directions; when the first direction is the column direction of the upper plate blocks in each column, the second direction is the row direction of the upper plate blocks in each row, and the electrical connection relationship between the upper plate blocks in each column in the first direction is removed to achieve that the adjacent upper plate blocks in each column are not connected in the column direction, and then, for the upper plate blocks in each row, the upper plate blocks in the row are electrically connected to the adjacent upper plate blocks in the row direction in sequence, so that the upper plate blocks in the row are connected in the row direction, and then, only the upper plate blocks in each row are connected in their respective row directions.

[0061] The second target end is one end or the other end of each row of upper plate blocks located in the second direction after being sequentially connected. That is to say, for each row of upper plate blocks located in the second direction, one end or the other end of the row of upper plate blocks after being sequentially connected in the second direction is used as the second target end of the row of upper plate blocks.

[0062] The second target ends of each row of upper plate blocks located in the second direction may be different ends, and it is only necessary to provide the first level to one end or the other end of each row of upper plate blocks located in the second direction.

[0063] That is to say, if each row of upper plate blocks located in the first direction is each row of upper plate blocks, then after determining whether each row of upper plate blocks is conductive with the lower plate, the connecting wires between adjacent upper plate blocks in each row of upper plate blocks are cleared, and then the adjacent upper plate blocks on each column of upper plate blocks are connected in sequence, so as to connect the first level to the second target end of each column of upper plate blocks and connect the lower plate to the second level, so as to determine whether each column of upper plate blocks is conductive with the lower plate.

[0064] return Figure 2 , S104: Detect a second conduction condition between each row of upper plate blocks and the lower plate in the second direction, and determine a failure position of the array capacitor by combining the first conduction condition and the second conduction condition.

[0065] Among them, the second conduction condition between each row of upper electrode plate blocks and the lower electrode plate located in the second direction is determined in the following manner: for each row of upper electrode plate blocks located in the second direction, by detecting the current value between the row of upper electrode plate blocks and the lower electrode plate, when the current value belongs to the preset conduction current interval, it is considered that the row of upper electrode plate blocks and the lower electrode plate are conductive, and when the current value does not belong to the preset conduction current interval, it is considered that the row of upper electrode plate blocks and the lower electrode plate are not conductive.

[0066] return Figure 3 , if the first direction in the array upper plate is the direction of the x-axis, and the second direction in the array upper plate is the direction of the y-axis, the solid lines indicate that each row of upper plate blocks in the first direction are connected in sequence, then the first row current value of the upper plate blocks in a row where upper plate blocks 101 and upper plate blocks 102 are located is detected, and the second row current value of the upper plate blocks in a row where upper plate blocks 103 and upper plate blocks 104 are located is detected to determine the first conduction condition; then the wires represented by the solid lines that connect each row of upper plate blocks in sequence are removed, that is, the electrical connection lines between adjacent upper plate blocks in each row of upper plate blocks represented by the solid lines are removed, and then each column of upper plate blocks in the second direction are connected in sequence and indicated by dotted lines. At this time, the first column current value of the column where the upper plate blocks 101 and 103 are located is detected, and the second column current value of the column where the upper plate blocks 102 and 104 are located is detected to determine the second conduction condition.

[0067] That is to say, each row of upper plate blocks in the first direction and each row of upper plate blocks in the second direction are controlled not to be connected in sequence at the same time to avoid electrical connection between the upper plate blocks. This will result in that when the corresponding position of at least one upper plate block is a failure position, current will be controlled to flow through each row of upper plate blocks corresponding to the first direction and the second direction, respectively, making it impossible to determine which specific row or column corresponds to the failure position.

[0068] Alternatively, the second conduction condition between each row of upper plate blocks and the lower plate located in the second direction is determined in the following manner: a second diode is set for each row of upper plate blocks located in the second direction, and whether the second diode corresponding to each row of upper plate blocks located in the second direction is lit is detected to determine whether each row of upper plate blocks located in the second direction is conductive to the lower plate.

[0069] Wherein, a second diode is set for each row of upper plate blocks located in the second direction in the following manner: one end of each row of upper plate blocks located in the second direction is connected to one end of the second diode, and the other end of the second diode corresponding to each row of upper plate blocks located in the second direction is connected as a second receiving point, wherein the second receiving point is used to connect to the first level.

[0070] The second diode can be arranged in different directions on the same plane as the first diode, such as Figure 4 As shown, if the first direction in the array upper plate is the direction where the x-axis is located, and the second direction in the array upper plate is the direction where the y-axis is located, then after a first diode is correspondingly set at one end of each row of upper plate blocks in the first direction and each first diode is detected to be lit, the wires connected in sequence to each row of upper plate blocks are removed, and then each column of upper plate blocks are connected in sequence and a second diode is correspondingly set at one end of each column of upper plate blocks, and the second diode corresponding to each column of upper plate blocks is connected to the first level, and the lower plate is connected to the second level. Then, it is determined whether the second diode corresponding to each column of upper plate blocks is lit, so as to obtain the second conduction condition.

[0071] Exemplarily, the second diode can be set in different directions on different planes from the first diode. Furthermore, after determining whether there is a failure position in each row of upper plate blocks in the first direction through the first diode, it is necessary to remove the wires that connect the adjacent upper plate blocks in each row of upper plate blocks in the first direction, and then set an upper conductive electrode plate for each upper plate block, connect the conductive electrode plates of each column of upper plate blocks in sequence in the second direction, and connect the second diode to one end of the conductive electrode plate of each column of upper plate blocks, so as to determine the specific failure position by whether the second diode is lit. In other words, the first diode and the second diode are not limited to being set on the same plane. It is only necessary to ensure that the first diode and the second diode correspond to the upper plate blocks in different directions of the array upper plate, and the first diode and the second diode are not turned on at the same time, so as to achieve the determination of the failure position.

[0072] For example, see Figure 5 , Figure 5 A schematic diagram of another method for determining the failure position of an array capacitor provided in an embodiment of the present application. Figure 5As shown, if the first direction in the array upper plate is the direction of the x-axis, and the second direction in the array upper plate is the direction of the y-axis, the solid lines indicate that each row of upper plate blocks in the first direction are connected in sequence, one end of an upper plate block in a row where upper plate block 101 and upper plate block 102 are located corresponds to one end of the first diode D1 connected, and one end of an upper plate block in a row where upper plate block 103 and upper plate block 104 are located corresponds to one end of the first diode D2 connected, the other end of the first diode D1 and the other end of the first diode D2 are both grounded GND, and the lower plate is connected to voltage V, so as to determine whether the first diode D1 and the first diode D2 are lit. The wires connected in sequence between each row of upper plate blocks represented by the solid line are removed, and a conductive through hole 300 is correspondingly set in each upper plate block in the direction above the upper plate, and the conductive through hole corresponding to each upper plate block is connected to a top plate, wherein the upper plate block 101 is connected to the top plate 301 through its corresponding conductive through hole, the upper plate block 102 is connected to the top plate 302 through its corresponding conductive through hole, the upper plate block 103 is connected to the top plate 303 through its corresponding conductive through hole, and the upper plate block 10 The top plate 304 is connected through its corresponding conductive through hole, and each column of top plates in the second direction is connected in sequence and represented by dotted lines, one end of a column of top plates corresponding to the upper plate block 101 and the upper plate block 103 is connected to one end of the second diode D3, and one end of another column of top plates corresponding to the upper plate block 102 and the upper plate block 104 is connected to one end of the second diode D4, the other end of the second diode D3 and the other end of the second diode D4 are both grounded GND, and the lower plate is connected to the voltage V. Further, the second conduction condition is obtained by whether the second diode D3 and the second diode D4 are lit.

[0073] That is to say, the first diode corresponding to each row of the upper plate block and the second diode corresponding to each column of the upper plate block are controlled not to be connected in the array upper plate at the same time. If the first diode corresponding to each row of the upper plate block and the second diode corresponding to each column of the upper plate block are connected at the same time, each diode will be lit, so it is impossible to determine which specific row or column corresponds to the failure position.

[0074] Specifically, the failure position of the array capacitor is determined in the following manner: based on the first conduction condition, a first target row of conduction is determined in each row of upper plate blocks located in the first direction; based on the second conduction condition, a second target row of conduction is determined in each row of upper plate blocks located in the second direction; based on the intersection position of the first target row and the second target row, the failure position of the array capacitor is determined.

[0075] The first target row includes one and / or the second target row includes one, wherein the failure position of the array capacitor is determined in the following manner: positions corresponding to at least one target upper plate block corresponding to the cross position are determined as failure positions.

[0076] That is to say, Figure 4 As shown, if the first target row is a row of upper plate blocks where upper plate blocks 101 and upper plate blocks 102 are located, and the second target row is a column of upper plate blocks where upper plate blocks 101 and upper plate blocks 103 are located, then the intersection of the first target row and the second target row is upper plate block 101, which means that the dielectric layer position corresponding to upper plate block 101 is a failure position. If the first target row is a row of upper plate blocks where upper plate blocks 101 and upper plate blocks 102 are located, and the second target row is a column of upper plate blocks where upper plate blocks 101 and upper plate blocks 103 are located, and a column of upper plate blocks where upper plate blocks 102 and upper plate blocks 104 are located, then the intersection of the first target row and the second target row is upper plate blocks 101 and upper plate blocks 102, which means that the dielectric layer positions corresponding to upper plate blocks 101 and upper plate blocks 102 are both failure positions.

[0077] The first target row includes a plurality of blocks and the second target row includes a plurality of blocks, wherein the failure position of the array capacitor is determined by: removing the connection relationship between the upper plate blocks in each row; providing a first level to the lower plate and providing a second level to the plurality of target upper plate blocks corresponding to the intersection position, and determining the conduction condition between each target upper plate block and the lower plate; and determining the position corresponding to the target upper plate block that is conductive with the lower plate as the failure position of the array capacitor.

[0078] That is to say, Figure 4As shown, if the first target row is a row of upper plate blocks where upper plate blocks 101 and upper plate blocks 102 are located, and a row of upper plate blocks where upper plate blocks 103 and upper plate blocks 104 are located, and the second target row is a column of upper plate blocks where upper plate blocks 101 and upper plate blocks 103 are located, and a column of upper plate blocks where upper plate blocks 102 and upper plate blocks 104 are located, then the intersection of the first target row and the second target row is upper plate blocks 101, upper plate blocks 102, upper plate blocks 103, and upper plate blocks 104, which means that the failure positions in upper plate blocks 101, upper plate blocks 102, upper plate blocks 103, and upper plate blocks 104 are not in the same row. , possible situations include the following: upper plate block 101 and upper plate block 104 are both failure positions, upper plate block 102 and upper plate block 103 are both failure positions, upper plate block 101, upper plate block 102 and upper plate block 103 are all failure positions, upper plate block 101, upper plate block 102 and upper plate block 104 are all failure positions, upper plate block 102, upper plate block 103 and upper plate block 104 are all failure positions, upper plate block 101, upper plate block 103 and upper plate block 104 are all failure positions, upper plate block 101, upper plate block 102, upper plate block 103 and upper plate block 104 are all failure positions.

[0079] That is to say, when the first target row includes multiple and the second target row includes multiple, the failure position of the unique solution cannot be determined according to the cross position, and then, it is necessary to detect each upper plate block corresponding to the cross position separately. It is necessary to remove each row of upper plate blocks located in the first direction and each row of upper plate intervals located in the second direction. Since when this step is executed, there is only a connection relationship between each row of upper plate intervals located in the second direction, then the connecting wires between each row of upper plate intervals in the second direction can be removed. In addition, the first level is provided to the lower plate and the second level is provided to the multiple target upper plate blocks at the cross position. Since each target upper plate block is isolated from each other at this time, then, the second level can be provided to each target upper plate block at the same time, and then, the conduction of each target upper plate block can be determined by determining whether there is current passing between each target upper plate block and the lower plate, that is, when there is current passing between the target upper plate block and the lower plate, the position corresponding to the target upper plate block is considered to be a failure position.

[0080] Exemplarily, a diode may be provided for each target upper plate block and connected to the second level, and whether the target upper plate block and the lower plate are conductive may be determined by determining whether the diode is lit. When the diode corresponding to the target upper plate block is lit, the position corresponding to the target upper plate block is considered to be a failure position.

[0081] Exemplarily, the present application places the array capacitor in an EMMI (Emission Microscope), and connects the first diode and the second diode to the array capacitor according to the aforementioned steps and applies corresponding levels, so as to determine whether the first diode and the second diode are lit respectively through EMMI. When the diode is forward-conducted, it will cause electrons and holes to recombine at the PN junction and emit light, which can be monitored by EMMI. Furthermore, EMMI is used to determine which position of the diode is forward-conducted, so as to determine the specific failure location. EMMI is an instrument that uses light emission microscopy technology to achieve high-resolution microscopic defect positioning, which can quickly and accurately locate device failure defects in a large range, and is therefore widely used in device failure analysis. In semiconductor devices with hot carrier effects, breakdown, and leakage, the failure point produces a luminescence phenomenon due to the electroluminescence process. These photon streams are collected and enhanced, and then go through CCD (charge-coupled device) photoelectric conversion and image processing to obtain a luminous image. By superimposing the luminous image and the surface optical reflection image, failure points and defects can be located.

[0082] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0083] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0084] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0085] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0086] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for determining a failure position of an array capacitor, characterized in that: The array capacitor includes an array upper plate, a lower plate, and a dielectric layer located between the array upper plate and the lower plate. The array upper plate includes a plurality of upper plate blocks arranged in an array, and the upper plate blocks are not in contact with each other. Wherein, the method comprises: Only each row of upper plate blocks on the array upper plate located in the first direction are connected in sequence, and a first level is provided to a first target end of each row of upper plate blocks located in the first direction and a second level is provided to the lower plate; Detecting a first conduction condition between each row of upper plate blocks and the lower plate in a first direction to determine whether there is a failure position in the array capacitor; When it is determined that the array capacitor has a failure position, the connection relationship between each row of upper plate blocks in the first direction is removed, and only each row of upper plate blocks in the second direction on the array upper plate are sequentially connected, and the first level is provided to the second target end of each row of upper plate blocks in the second direction and the second level is provided to the lower plate, wherein each row of upper plate blocks in the first direction and each row of upper plate blocks in the second direction are not sequentially connected at the same time; Detecting a second conduction condition between each row of upper plate blocks and the lower plate in a second direction, and determining a failure position of the array capacitor by combining the first conduction condition and the second conduction condition; The conduction status is determined by the following methods: by detecting the current value between each row of upper plate blocks and the lower plate, determining whether each row of upper plate blocks and the lower plate are conductive; or, by providing a diode for each row of upper plate blocks, and by detecting whether the diode corresponding to each row of upper plate blocks is lit, determining whether each row of upper plate blocks and the lower plate are conductive.

2. The method according to claim 1, characterized in that Each row of upper plate blocks located in the first direction is one of the upper plate blocks in each row and the upper plate blocks in each column of the array upper plate, and each row of upper plate blocks located in the second direction is another of the upper plate blocks in each row and the upper plate blocks in each column of the array upper plate.

3. The method according to claim 2, characterized in that Each row of upper plate blocks is connected sequentially in the following way: Connecting adjacent upper plate blocks in the row of upper plate blocks according to the row direction of the upper plate blocks in the row; and / or, Each column of upper plate blocks is connected sequentially in the following way: Adjacent upper plate blocks in the column of upper plate blocks are connected according to the column direction of the upper plate blocks in the column.

4. The method according to claim 2 or 3, characterized in that: The first target end is one end or the other end of each row of upper plate blocks located in the first direction after being connected in sequence. The second target end is one end or the other end of each row of upper plate blocks located in the second direction after being connected in sequence.

5. The method according to claim 1, characterized in that The detecting a first conduction condition between each row of upper plate blocks and the lower plate in the first direction to determine whether there is a failure position in the array capacitor includes: When it is detected that any row of upper plate blocks in the first direction is connected to the lower plate, it is determined that there is a failure position in the array capacitor. When it is detected that each row of upper plate blocks located in the first direction is not connected to the lower plate, it is determined that there is no failure position in the array capacitor.

6. The method according to claim 1, characterized in that The failure position of the array capacitor is determined by: According to the first conduction condition, determining a first target row of conduction in each row of upper plate blocks located in the first direction; According to the second conduction condition, determining a second target row of conduction in each row of upper plate blocks located in the second direction; The failure position of the array capacitor is determined according to the intersection position of the first target row and the second target row.

7. The method according to claim 6, characterized in that The first target row comprises one and / or the second target row comprises one, The failure position of the array capacitor is determined by: The positions corresponding to at least one target upper plate block corresponding to the intersection position are determined as failure positions.

8. The method according to claim 6, characterized in that The first target row includes a plurality of and the second target row includes a plurality of, The failure position of the array capacitor is determined by: Remove the connection between each row of upper plate blocks; Providing a first level to the lower electrode plate and providing a second level to a plurality of target upper electrode plate blocks corresponding to the intersection positions, and determining the conduction status between each target upper electrode plate block and the lower electrode plate; The position corresponding to the target upper plate block that is conductive between the lower plates is determined as the failure position of the array capacitor.

9. The method according to claim 1, characterized in that: The diodes are set for each row of top plate blocks in the following manner: Connect one end of each row of upper plate blocks in the first direction to one end of a first diode, and connect the other end of the first diode corresponding to each row of upper plate blocks in the first direction as a first receiving point, wherein the first receiving point is used to connect a first level, Connect one end of each row of upper plate blocks in the second direction to one end of a second diode, and connect the other end of the second diode corresponding to each row of upper plate blocks in the second direction as a second receiving point, The first receiving point and the second receiving point are both used to connect to a first level.

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