A test circuit and test method for driving chip anti-noise

Abstract

The present invention relates to the technical field of high-voltage integrated circuits, and provides a test circuit and a test method for the anti-noise of a driver chip, which are used to test the driver chip, and include: a DC power supply, a first capacitor, a first oscilloscope, a first signal generator, a first transistor, an isolated power supply, a noise stress generator, a first inductor, a second transistor, and a second signal generator; a VCC port, a HIN port, a LIN port, a ground terminal, a HO port, a VB port, a VS port, and a LO port are provided on the driver chip; the negative output terminal of the isolated power supply is respectively connected to the VS port and the first end of the noise stress generator, the LO port is suspended, and the second end of the noise stress generator is respectively connected to the source of the first transistor, the drain of the second transistor, and the first end of the first inductor. The test circuit for the anti-noise of the driver chip of the present invention has high test accuracy for the driver chip, high product qualification rate, and good reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage integrated circuits, and in particular to a test circuit and a test method for anti-noise of a driver chip. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into IGBT driving signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, dead zone circuit, interlock circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit and other circuits. On the one hand, HVIC receives the control signal of MCU to drive the subsequent IGBT or MOS to work, and on the other hand, it sends the system status detection signal back to MCU. It is a key chip inside IPM.

[0003] With the rapid development of industry, IPM intelligent power modules are widely used in various fields. As one of the key components inside IPM, the performance of driver IC (HVIC) determines the performance of IPM. The dV / dt malfunction prevention circuit is a very important circuit inside HVIC. The function of this circuit is: during the use of HVIC, the VS terminal voltage will jump between 0V and 200V / 400V / 600V to prevent the sudden change of the voltage difference between the VS terminal level and the substrate ground level from causing the HO to malfunction, resulting in LO and HO being high at the same time, and the two IGBTs controlled by it being turned on at the same time, which will cause damage to the IGBT, unqualified products, and poor reliability. Summary of the invention

[0004] The invention provides a driver chip anti-noise test circuit, aiming to solve the problems of poor test effect, unqualified products and poor reliability of the existing driver chip.

[0005] The embodiment of the present invention provides a test circuit for anti-noise of a driver chip, which is used for testing the driver chip, and includes: a DC power supply, a first capacitor, a first oscilloscope, a first signal generator, a first transistor, an isolation power supply, a noise stress generator, a first inductor, a second transistor and a second signal generator; the driver chip is provided with a VCC port, a HIN port, a LIN port, a ground terminal, a HO port, a VB port, a VS port and a LO port;

[0006] The positive output end of the DC power supply is respectively connected to the first end of the first capacitor and the VCC port, the negative output end of the DC power supply is respectively connected to the second end of the first capacitor, the first end of the first oscilloscope, the first end of the first signal generator and the ground end and are grounded together, the second end of the first oscilloscope and the second end of the first signal generator are connected and connected to the HIN port, and the LIN port is also connected to the ground end; the second oscilloscope is used to connect the HO port, the positive output end of the isolated power supply is connected to the VB port, the negative output end of the isolated power supply is respectively connected to the VS port and the first end of the noise stress generator, the LO port is set to be suspended, the second end of the noise stress generator is respectively connected to the source of the first transistor, the drain of the second transistor and the first end of the first inductor, the source of the first transistor is also connected to the gate of the first transistor, the drain of the first transistor is connected to the second end of the first inductor and is used to connect to the high-voltage DC power supply; the source of the second transistor is grounded, and the gate of the second transistor is connected to the second signal generator.

[0007] Preferably, both the first transistor and the second transistor are PMOS transistors.

[0008] Preferably, the output voltage of the high-voltage DC power supply is greater than 600V.

[0009] In a second aspect, an embodiment of the present invention provides a method for testing the noise resistance of a driver chip. The method is implemented based on the above-mentioned test circuit for testing the noise resistance of the driver chip. The method comprises the following steps:

[0010] S1. Test starts, start the temperature control box, and set the temperature to the preset temperature;

[0011] S2, start the DC power supply and set the power supply voltage to 15V;

[0012] S3, start the first signal generator to output a 0-15V pulse input HIN;

[0013] S4, adjust the isolation power supply to 15V, adjust the high-voltage DC power supply to 400V, and the second signal generator outputs a 0-1 pulse to drive the second transistor to work;

[0014] S5, monitoring the pulse signals HIN, HO and VS through the first oscilloscope and the second oscilloscope;

[0015] S6, collect and record the voltage V1 of VS from 10% to 90% of the maximum value and the time t1 required when the HO initial state is low potential; the voltage V2 of VS from 10% to 90% of the maximum value and the time t2 required when the HO initial state is high potential;

[0016] S7. According to V1 and t1, define A<dV1 / dt1 as formula (1), where A is a preset threshold;

[0017] According to V2 and t2, define A<dV2 / dt2 as formula (2); determine whether formula (1) and formula (2) are simultaneously true; if one of the formulas is false, the test is terminated and the product is unqualified; if both formulas are true, the test is terminated and the product is qualified.

[0018] Preferably, in step S1, the preset temperature range is -45°C to 145°C.

[0019] Preferably, the preset temperature includes a first set temperature, a second set temperature and a third set temperature;

[0020] The temperature setting temperature is set to the first set temperature by starting the constant temperature control box, and steps S2-S7 are performed. If both equations are true, the temperature setting temperature is set to the second set temperature by starting the constant temperature control box, and steps S2-S7 are repeated. If both equations are true, the temperature setting temperature is set to the third set temperature by starting the constant temperature control box, and steps S2-S7 are repeated. If both equations are true, the test is completed and the product is qualified.

[0021] Preferably, the first set temperature is 25°C, the second set temperature is -40°C, and the third set temperature is 125°C.

[0022] Compared with the prior art, the beneficial effect of the present invention lies in that the positive output end of the DC power supply is respectively connected to the first end of the first capacitor and the VCC port, the negative output end of the DC power supply is respectively connected to the second end of the first capacitor, the first end of the first oscilloscope, the first end of the first signal generator and the ground terminal and are grounded together, the second end of the first oscilloscope and the second end of the first signal generator are connected and connected to the HIN port, and the LIN port is also connected to the ground terminal; the second oscilloscope is used to connect the HO port, the positive output end of the isolation power supply is connected to the VB port, the negative output end of the isolation power supply is respectively connected to the VS port and the first end of the noise stress generator, the LO port is suspended, and the second end of the noise stress generator is respectively connected to the HO port. The source of the first transistor, the drain of the second transistor and the first end of the first inductor are connected, the source of the first transistor is also connected to the gate of the first transistor, the drain of the first transistor is connected to the second end of the first inductor and is used to connect a high-voltage DC power supply; the source of the second transistor is grounded, and the gate of the second transistor is connected to the second signal generator; the HIN end is tested by inputting a pulse of 0 to 15V and a pulse of 15V to 0 at different temperatures through the test circuit to evaluate the impact of dVs / dt noise on the high and low output states of the chip, and whether there is no latch-on phenomenon at the HO end under the transient dVs / dt noise signal of AV / ns when the HO initial state is low potential. When the HO initial state is high potential, whether there is a latch-off phenomenon under the influence of the transient dVs / dt noise signal of AV / ns. In order to test whether the HVIC anti-dVs / dt ability is qualified, so as to prevent products with unqualified anti-dVs / dt ability from entering the market, the reliability is high, and the product is more competitive in the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0024] Figure 1 is a circuit diagram of a test circuit for anti-noise of a driver chip provided by an embodiment of the present invention;

[0025] Figure 2 is a flow chart of a method for testing the anti-noise performance of a driver chip provided by an embodiment of the present invention;

[0026] Figure 3 This is a waveform diagram when the HO initial state is a low potential provided by an embodiment of the present invention;

[0027] Figure 4 It is a waveform diagram when the initial state of HO provided by the embodiment of the present invention is a high potential. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Embodiment 1

[0029] Combined with Figure 1-Figure 4 As shown, an embodiment of the present invention provides a test circuit for anti-noise of a driver chip, which is used to test a driver chip 0201, including: a DC power supply 0202, a first capacitor 0203, a first oscilloscope 0204, a first signal generator 0205, a first transistor Q1, an isolation power supply 0208, a noise stress generator 0209, a first inductor L1, a second transistor Q2 and a second signal generator 0207; the driver chip 0201 is provided with a VCC port, a HIN port, a LIN port, a ground terminal, a HO port, a VB port, a VS port and a LO port.

[0030] Among them, the driver chip 0201 is a HVIC chip. Figure 1 This is a simplified diagram of the HVIC chip under test, which only draws one bridge arm input port HIN1, LIN1, VB1, VS1, output ports HO1, LO1, power supply VCC and ground GND.

[0031] The maximum output voltage of the DC power supply 0202 is >20V; the maximum output current is >0.5A, the positive output terminal is connected to the VCC of the HVIC under test, and the negative output terminal is connected to GND.

[0032] The first capacitor 0203 is a filter capacitor of the power pin, which is 1uF, with one end connected to the VCC of the HVIC under test and the other end connected to GND; the first oscilloscope 0204 and the second oscilloscope 0206 are two common probes of the oscilloscope to measure the voltage difference between the low-voltage side output and the low voltage; the first signal generator 0205 and the second signal generator 0207 are the two output ports PWM1 and PWM2 of the signal generator; the isolated power supply 0208 (isolated from other power supplies) has a maximum output voltage of >20V; the DC power supply has a maximum output current of >0.5A, the positive output terminal is connected to VB1 of the HVIC under test, and the negative output terminal is connected to VS1;

[0033] The D pole of the first transistor Q1 and one end of the inductor L1 are connected to a high-voltage DC power supply (maximum output voltage>600V; maximum output current>1A); the S and G poles of the first transistor Q1, the other end of the inductor L1, and the D pole of the switch tube of Q2 are connected to VS1 of the HVIC under test.

[0034] The G pole of the second transistor Q2 is connected to the output port 0207 of the signal generator to drive Q2 to work; the S pole of the first transistor Q1, LIN1 of the tested HVIC, and GND are grounded.

[0035] The noise stress generator 0209 is a dVs / dt stress generator, and a driving signal is provided to the dVs / dt stress generator through an isolated power supply 0208, a high voltage direct current, a first transistor Q1, a second transistor Q2, and a first inductor L1.

[0036] Working principle of dVs / dt stress generator: using a bridge structure composed of two switching devices and inductance to generate high voltage stress, when the second transistor Q2 is turned on, the first inductor L1 stores energy, and when the second transistor Q2 is turned off, the current on the first inductor L1 flows through the first transistor Q1, causing the VS terminal voltage to rise instantly.

[0037] Specifically, the positive output end of the DC power supply 0202 is respectively connected to the first end of the first capacitor 0203 and the VCC port, the negative output end of the DC power supply 0202 is respectively connected to the second end of the first capacitor 0203, the first end of the first oscilloscope 0204, the first end of the first signal generator 0205 and the grounding end and are grounded together, the second end of the first oscilloscope 0204 and the second end of the first signal generator 0205 are connected and connected to the HIN port, and the LIN port is also connected to the grounding end; the second oscilloscope 0206 is used to connect to the HO port, and the positive output end of the isolated power supply 0208 is connected The VB port and the negative output end of the isolated power supply 0208 are respectively connected to the VS port and the first end of the noise stress generator 0209, the LO port is suspended, the second end of the noise stress generator 0209 is respectively connected to the source of the first transistor Q1, the drain of the second transistor Q2 and the first end of the first inductor L1, the source of the first transistor Q1 is also connected to the gate of the first transistor Q1, the drain of the first transistor Q1 is connected to the second end of the first inductor L1 and is used to connect to a high-voltage DC power supply; the source of the second transistor Q2 is grounded, and the gate of the second transistor Q2 is connected to the second signal generator 0207. The test circuit is used to input a pulse of 0 to 15V and a pulse of 15V to 0 at the HIN end at different temperatures to evaluate the impact of dVs / dt noise on the high and low states of the chip output, and whether the HO end has no latch-on phenomenon under the transient dVs / dt noise signal condition of AV / ns when the HO initial state is low potential. When the HO initial state is high potential, whether the latch-off phenomenon occurs under the influence of the transient dVs / dt noise signal of AV / ns. This is to test whether the HVIC anti-dVs / dt capability is qualified, so as to prevent products with unqualified anti-dVs / dt capability from entering the market, with high reliability, making the product more competitive in the market.

[0038] In this embodiment, the first transistor Q1 and the second transistor Q2 are both PMOS transistors, which are high-voltage switch tubes (such as FS7M18A) that can withstand a conduction current of more than 1A.

[0039] In this embodiment, the output voltage of the high-voltage direct current power supply is greater than 600 V. The maximum output voltage is >600 V; and the maximum output current is >1 A.

[0040] In this embodiment, the first signal generator 0205 and the second signal generator 0207 have a Vp-p voltage of >10V, a current output capability of >0.5A, and a frequency bandwidth of >500MHz.

[0041] The first oscilloscope 0204 and the second oscilloscope 0206 have four-way inputs; a bandwidth of frequency > 500MHz; and are equipped with high-voltage test leads (> 500V) and differential test leads. Embodiment 2

[0042] The embodiment of the present invention provides a method for testing the anti-noise performance of a driver chip 0201. The method is implemented based on the anti-noise performance testing circuit of the driver chip 0201 in the first embodiment. The method comprises the following steps:

[0043] S1. Test starts, start the temperature control box, and set the temperature to the preset temperature;

[0044] S2, start the DC power supply 0202 and set the power supply voltage to 15V;

[0045] S3, start the first signal generator 0205 to output a 0-15V pulse input HIN;

[0046] S4, adjust the isolation power supply 0208 to 15V, adjust the high-voltage DC power supply to 400V, and the second signal generator 0207 outputs a 0-1 pulse to drive the second transistor Q2 to work;

[0047] S5, monitoring the pulse signals HIN, HO and VS through the first oscilloscope 0204 and the second oscilloscope 0206;

[0048] S6, collect and record the voltage V1 of VS from 10% to 90% of the maximum value and the time t1 required when the HO initial state is low potential; the voltage V2 of VS from 10% to 90% of the maximum value and the time t2 required when the HO initial state is high potential;

[0049] S7. According to V1 and t1, define A<dV1 / dt1 as formula (1), where A is a preset threshold;

[0050] According to V2 and t2, define A<dV2 / dt2 as formula (2); determine whether formula (1) and formula (2) are simultaneously true; if one of the formulas is false, the test is terminated and the product is unqualified; if both formulas are true, the test is terminated and the product is qualified.

[0051] In this embodiment, in step S1, the preset temperature range is -45°C to 145°C.

[0052] In this embodiment, the preset temperature includes a first set temperature, a second set temperature and a third set temperature;

[0053] The temperature setting temperature is set to the first set temperature by starting the constant temperature control box, and steps S2-S7 are performed. If both equations are true, the temperature setting temperature is set to the second set temperature by starting the constant temperature control box, and steps S2-S7 are repeated. If both equations are true, the temperature setting temperature is set to the third set temperature by starting the constant temperature control box, and steps S2-S7 are repeated. If both equations are true, the test is completed and the product is qualified.

[0054] In this embodiment, the first set temperature is 25°C, the second set temperature is -40°C, and the third set temperature is 125°C.

[0055] In this embodiment, the test steps are as follows:

[0056] 1. Power on: Power on each power supply in the following order to test whether each circuit is working properly.

[0057] ① Start HVIC: adjust the DC power supply 0202 to make its voltage to 15V. Start the first signal generator 0205 to output a 0-15V pulse input HIN, and use an oscilloscope to observe the waveforms of HIN and HO.

[0058] ② Start the dV / dt generating circuit: adjust the isolated power supply 0208 to 15V, so that its voltage to VS is 15V. The high-voltage DC power supply is adjusted to 400V, and the second signal generator 0207 outputs a 0-1 pulse to drive the second transistor Q2. The oscilloscope uses a differential probe to observe the waveform of VS.

[0059] ③ Test HVIC's dV / dt resistance:

[0060] When the HO initial state is low, under the condition of AV / ns transient dVs / dt noise signal, does the HO terminal have no latch-on phenomenon? When the HO initial state is high, under the influence of AV / ns transient dVs / dt noise signal, does the HO terminal have latch-off phenomenon?

[0061] Figure 3 When the initial state of HO is low potential, Figure 3 From the enlarged graph in the figure, we can see that the voltage of VS rises by BV in 2.4ns. After conversion, we know that the dVs / dt stress reaches (B / 2.4)V / ns, (B / 2.4)V / ns>AV / ns, and there is no latch-on phenomenon at the HO end, which meets the design requirements. The latch-on phenomenon at the HO end does not meet the design requirements.

[0062] Figure 4 When the initial state of HO is high potential, Figure 3From the enlarged graph, we can see that the voltage of VS rises by CV in 2.8ns. After conversion, we know that the dVs / dt stress reaches (C / 2.8)V / ns, (C / 2.8)V / ns>AV / ns, and there is no latch-oFF phenomenon at the HO end, which meets the design requirements. The latch-oFF phenomenon at the HO end does not meet the design requirements.

[0063] In this way, the HIN terminal is tested with pulses of 0 to 15V and 15V to 0 at different temperatures to evaluate the impact of dVs / dt noise on the chip output being high and low. When the HO initial state is low, under the condition of the transient dVs / dt noise signal of AV / ns, whether there is no latch-on phenomenon at the HO terminal. When the HO initial state is high, whether there is a latch-off phenomenon under the influence of the transient dVs / dt noise signal of AV / ns. This is to test whether the HVIC anti-dVs / dt capability is qualified, so as to prevent products with unqualified anti-dVs / dt capability from entering the market, with high reliability, making the product more competitive in the market.

[0064] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0065] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A driver chip anti-noise test circuit, used for testing the driver chip, characterized in that: include: A DC power supply, a first capacitor, a first oscilloscope, a first signal generator, a first transistor, an isolation power supply, a noise stress generator, a first inductor, a second transistor and a second signal generator; the driver chip is provided with a VCC port, a HIN port, a LIN port, a ground terminal, a HO port, a VB port, a VS port and a LO port; The positive output end of the DC power supply is respectively connected to the first end of the first capacitor and the VCC port, the negative output end of the DC power supply is respectively connected to the second end of the first capacitor, the first end of the first oscilloscope, the first end of the first signal generator and the ground end and are grounded together, the second end of the first oscilloscope and the second end of the first signal generator are connected and connected to the HIN port, and the LIN port is also connected to the ground end; the second oscilloscope is used to connect the HO port, the positive output end of the isolated power supply is connected to the VB port, the negative output end of the isolated power supply is respectively connected to the VS port and the first end of the noise stress generator, the LO port is set to be suspended, the second end of the noise stress generator is respectively connected to the source of the first transistor, the drain of the second transistor and the first end of the first inductor, the source of the first transistor is also connected to the gate of the first transistor, the drain of the first transistor is connected to the second end of the first inductor and is used to connect to the high-voltage DC power supply; the source of the second transistor is grounded, and the gate of the second transistor is connected to the second signal generator.

2. The driver chip anti-noise test circuit according to claim 1, characterized in that: The first transistor and the second transistor are both PMOS transistors.

3. The driver chip anti-noise test circuit according to claim 1, characterized in that: The output voltage of the high-voltage direct current power supply is greater than 600V.

4. A method for testing the anti-noise performance of a driver chip, characterized in that: The test method is implemented based on the test circuit for anti-noise of the driver chip according to any one of claims 1 to 3, and the test method comprises the following steps: S1. Test starts, start the temperature control box, and set the temperature to the preset temperature; S2, start the DC power supply and set the power supply voltage to 15V; S3, start the first signal generator to output a 0-15V pulse input HIN; S4, adjust the isolation power supply to 15V, adjust the high-voltage DC power supply to 400V, and the second signal generator outputs a 0-1 pulse to drive the second transistor to work; S5, monitoring the pulse signals HIN, HO and VS through the first oscilloscope and the second oscilloscope; S6, collect and record the voltage V1 of VS from 10% to 90% of the maximum value and the time t1 required when the HO initial state is low potential; the voltage V2 of VS from 10% to 90% of the maximum value and the time t2 required when the HO initial state is high potential; S7. Based on V1 and t1, define A<dV1 / dt1 as formula (1), where A is the preset threshold; According to V2 and t2, define A<dV2 / dt2 as formula (2); determine whether formula (1) and formula (2) are simultaneously true; if one of the formulas is false, the test is terminated and the product is unqualified; if both formulas are true, the test is terminated and the product is qualified.

5. The method for testing the anti-noise performance of a driver chip as claimed in claim 4, wherein: In step S1, the preset temperature range is -45°C to 145°C.

6. The method for testing the anti-noise performance of a driver chip according to claim 5, wherein: The preset temperatures include a first set temperature, a second set temperature and a third set temperature; The temperature setting temperature is set to the first set temperature by starting the constant temperature control box, and steps S2-S7 are performed. If both equations are true, the temperature setting temperature is set to the second set temperature by starting the constant temperature control box, and steps S2-S7 are repeated. If both equations are true, the temperature setting temperature is set to the third set temperature by starting the constant temperature control box, and steps S2-S7 are repeated. If both equations are true, the test is completed and the product is qualified.

7. The method for testing the anti-noise performance of a driver chip according to claim 6, wherein: The first set temperature is 25°C, the second set temperature is -40°C, and the third set temperature is 125°C.

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