Power consumption mode switching system, power consumption mode switching method and processor

Abstract

The present application discloses a power consumption mode switching system, a power consumption mode switching method and a system on chip. The system includes: a task core for generating an entry request for a preset power consumption mode; a power consumption management core for configuring the switching timing of the preset power consumption mode; a power consumption controller connected to the task core and the power consumption management core for receiving an entry request or generating an exit request for the preset power consumption mode according to a received wake-up request; a power consumption mode controller connected to the power consumption controller for executing a switching timing according to an entry request or an exit request to generate a control signal; and a plurality of hardware control devices respectively connected to the power consumption mode controller for entering or exiting the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types. The present application solves the technical problem of poor switching effect of power consumption modes in the related art.

Description

Technical Field

[0001] The present application relates to the field of system on chip, and in particular to a power consumption mode switching system, a power consumption mode switching method and a system on chip. Background Art

[0002] Currently, power mode switching is primarily achieved through two methods: software control and hardware control. While software control offers high flexibility and can customize the timing and strategy for power mode switching for different task scenarios, it suffers from significant latency and high software design complexity. In scenarios requiring rapid response, software control latency can impact user experience and even system performance and stability. Hardware control can significantly reduce latency and increase power mode switching speeds, but due to its fixed nature, it lacks sufficient flexibility and is difficult to adapt to most task scenarios. When special needs arise during user use, the hardware control method may not be able to make corresponding adjustments.

[0003] These two traditional control methods each have limitations. Software control, while flexible, suffers from high latency, while hardware control, while fast, lacks flexibility. Consequently, the industry faces the challenge of maintaining low latency while providing sufficient flexibility to address a variety of mission scenarios. This issue is particularly acute in power mode switching, as incorrect power mode timing or control strategies can lead to serious consequences such as functional failure and ineffective power reduction, impacting system reliability, performance, and user experience.

[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0005] The embodiments of the present application provide a power consumption mode switching system, a power consumption mode switching method, and a processor to at least solve the technical problem of poor power consumption mode switching effect in related technologies.

[0006] According to one aspect of an embodiment of the present application, a power consumption mode switching system is provided, including: a task core, for generating an entry request for a preset power consumption mode; a power consumption management core, for configuring a switching timing of the preset power consumption mode; a power consumption controller, connected to the task core and the power consumption management core, for receiving an entry request, or generating an exit request of the preset power consumption mode based on a received wake-up request; a power consumption mode controller, connected to the power consumption controller, for executing a switching timing based on the entry request or the exit request to generate a control signal; and multiple hardware control devices, respectively connected to the power consumption mode controller, for entering a preset power consumption mode or exiting a preset power consumption mode based on the control signal, wherein different hardware control devices have different control types.

[0007] According to one aspect of an embodiment of the present application, a power consumption mode switching method is provided, including: a task core, used to generate an entry request for a preset power consumption mode; a power consumption management core, used to configure the switching timing of the preset power consumption mode; a power consumption controller, connected to the task core and the power consumption management core, for receiving an entry request, or generating an exit request for the preset power consumption mode based on a received wake-up request; a power consumption mode controller, connected to the power consumption controller, for executing the switching timing based on the entry request or the exit request to generate a control signal; a plurality of hardware control devices, respectively connected to the power consumption mode controller, for entering the preset power consumption mode or exiting the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

[0008] According to another aspect of the embodiments of the present application, a system on chip is provided, including: any one of the systems in the above embodiments.

[0009] According to another aspect of an embodiment of the present application, a computing device is further provided, including: a memory storing an executable program; and a processor for running the program, wherein the program executes any one of the methods in the above embodiments when running.

[0010] According to another aspect of an embodiment of the present application, a computer-readable storage medium is also provided, which includes a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in various embodiments of the present application.

[0011] According to another aspect of the embodiments of the present application, a computer program product is further provided, including a computer program, which implements the methods in various embodiments of the present application when executed by a processor.

[0012] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0013] According to another aspect of the embodiments of the present application, a computer program is further provided, which implements the methods in various embodiments of the present application when executed by a processor.

[0014] In an embodiment of the present application, a task core is used to generate an entry request to a preset power consumption mode; a power management core is used to configure the switching timing of the preset power consumption mode; a power controller is connected to the task core and the power management core and is used to receive an entry request or generate an exit request of the preset power consumption mode based on a received wake-up request; a power consumption mode controller is connected to the power consumption controller and is used to execute the switching timing according to the entry request or exit request to generate a control signal; a plurality of hardware control devices are respectively connected to the power consumption mode controller and are used to enter or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types, thereby achieving an improved power consumption mode switching effect. It is easy to notice that when the system load decreases or enters a specific standby state, the task core detects this change and generates a request to enter the preset power consumption mode accordingly. The generation of this request is immediate and direct, avoiding the delay of software scheduling, thereby being able to quickly respond to load changes. The power consumption management core can ensure that before entering the preset power consumption mode, the system can adjust the power consumption control timing of each module according to specific needs. By properly configuring the timing, hardware function failures caused by improper control sequences can be avoided. After receiving an entry request or exit request from the power management controller, the power mode controller executes according to the configured switching timing and generates corresponding control signals. By controlling multiple hardware control devices through control signals, the delay of power mode switching can be reduced and the switching speed can be improved. Since each hardware control device is responsible for a different type of control, this division of labor and cooperation model ensures the comprehensiveness and efficiency of the system when switching power modes, avoiding the singleness and complexity of software control. Through the immediate request generation of the task core, the flexible timing configuration of the power management core, the hardware control signal generation of the power mode controller, and the division of labor and cooperation of multiple hardware control devices, the switching efficiency of the power mode can be improved, thereby solving the technical problem of poor power mode switching effect in related technologies.

[0015] It is easy to notice that the above general description and the following detailed description are merely for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 This is a hardware structure block diagram of a RISC-V system for implementing a power consumption mode switching method according to an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a system on a chip according to an embodiment of the present application;

[0019] Figure 3 is a schematic diagram of a power consumption mode switching system according to embodiment 1 of the present application;

[0020] Figure 4 is a structural diagram of a low-power control system according to an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of a power consumption mode controller according to an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of a power consumption mode switching state machine according to an embodiment of the present application;

[0023] Figure 7 This is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application;

[0024] Figure 8 is a schematic diagram of a low-power software controller according to an embodiment of the present application;

[0025] Figure 9 This is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application;

[0026] Figure 10 This is a schematic diagram of a process for collaboratively controlling power consumption mode switching using software and hardware according to an embodiment of the present application;

[0027] Figure 11 is a flow chart of a power consumption mode switching method according to an embodiment of the present application;

[0028] Figure 12 is a schematic diagram of a power consumption mode switching device according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following interpretations:

[0032] Phase-Locked Loop (PLL): A PLL is a closed-loop feedback control system that generates an output signal that is frequency-locked to a reference signal. In electronic devices, PLLs are commonly used for signal generation, frequency synthesis, and clock signal generation and recovery. For example, in applications requiring stable, precise frequency control, such as communications systems, computer clocks, and audio and video processing circuits.

[0033] Double Data Rate Synchronous Dynamic Random Access Memory (DDR): Double Data Rate Synchronous Dynamic Random Access Memory is a high-speed memory technology. DDR doubles the data transfer rate by transferring data on both the rising and falling edges of each clock cycle.

[0034] A power management integrated circuit (PMIC) is a chip used to manage the power supply functions in electronic devices. PMICs can integrate multiple power management functions, such as voltage conversion, battery charging, power sequencing, voltage regulation, and monitoring. They are often used in complex systems to improve battery efficiency, provide power protection, and ensure stable performance under varying load conditions.

[0035] An input / output controller (I / O controller) is a controller used to manage the input and output devices of a computer system. An I / O controller handles data transmission between the computer system and external devices, including interface protocol conversion, data caching, and data transmission control.

[0036] Currently, chip power consumption is closely related to performance, reliability, heat dissipation, cost, and battery life. Therefore, adjusting the chip's power consumption mode in real time based on the chip's operating status and load is a common technical approach in the industry to reduce power consumption. For example, a laptop will automatically enter sleep mode after being idle for a long time. When the laptop is in sleep mode, a user tapping a key will instantly wake it from sleep. Behind the laptop's state transition is the switching of the chip's power consumption mode.

[0037] As chip size continues to increase and design complexity continues to rise, chip power mode control is becoming increasingly complex. Relying on software to sequentially configure the status of each module in the system to complete power mode switching not only increases the complexity of software design, but also results in high power mode switching latency, resulting in a poor user experience. Using power mode hardware switching circuits to switch the status of each module in the system can effectively improve the speed of power mode switching, but at the same time, the flexibility and robustness of the system must be considered. If a power switching sequence error occurs, the chip function will fail. Therefore, research on how to achieve both low latency and high reliability in chip power mode switching is very important and meaningful.

[0038] According to an embodiment of the present application, a power consumption mode switching method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0039] The method embodiment provided in the first embodiment of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 1 FIG is a hardware structure diagram of a RISC-V system for implementing a power consumption mode switching method according to an embodiment of the present application. Figure 1As shown, the RISC-V system 100 can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system 100 also includes a tool chain 107 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0040] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including a basic instruction set and an extended instruction set. The basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0041] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0042] The operating system layer 104 sits above the hardware and provides a hardware abstraction layer and management mechanism, enabling applications to interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0043] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communication and graphical user interfaces.

[0044] The application layer 106 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0045] The tool chain 107 is a key component that connects the underlying hardware to the upper-level software. Various tools in the tool chain 107 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0046] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0047] In an optional embodiment, Figure 2 Shown using the above Figure 1 Schematic diagram of the RISC-V architecture system on chip (SOC). Figure 2 is a schematic diagram of a system on chip according to an embodiment of the present application, such as Figure 2 As shown, the SOC contains at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to ROM 206 (Read-Only Memory), RAM 208 (Random Access Memory), timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0048] Under the above operating environment, this application provides Figure 3 The power mode switching system is shown. Figure 3 Schematic diagram of a power consumption mode switching system according to embodiment 1 of the present application. Figure 3 As shown, the system 300 includes: a task core 302 , a power management core 304 , a power controller 306 , a power mode controller 308 , and multiple hardware control devices 310 .

[0049] Among them, the task core is used to generate an entry request for a preset power consumption mode; the power consumption management core is used to configure the switching timing of the preset power consumption mode; the power consumption controller is connected to the task core and the power consumption management core, and is used to receive an entry request, or generate an exit request for the preset power consumption mode based on the received wake-up request; the power consumption mode controller is connected to the power consumption controller, and is used to execute the switching timing according to the entry request or exit request to generate a control signal; multiple hardware control devices are respectively connected to the power consumption mode controller, and are used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

[0050] The above-mentioned power consumption controller may include a power consumption controller of a task core and a power consumption controller of a power consumption management core. When entering the low power consumption process, the power consumption controller of the task core controls the task core to enter low power consumption and then initiates a request to enter low power consumption to the power consumption mode controller. When entering the low power consumption process, the power consumption controller of the power consumption management core controls the power consumption management core to enter low power consumption after receiving a power consumption mode switching completion indication from the power consumption mode controller. When exiting the low power consumption process, the power consumption controller of the task core controls the task core to exit low power consumption after receiving a power consumption mode switching completion indication from the power consumption mode controller. When exiting the low power consumption process, the power consumption controller of the power consumption management core receives a system wake-up signal, controls the power consumption management core to exit low power consumption and then initiates a request to exit low power consumption to the power consumption mode controller.

[0051] Furthermore, the power consumption software controller can be connected to the power consumption mode controller via a control interface, receiving control signals from the power consumption mode controller. It generates a low-power request interrupt and sends it to the power management core. It receives low-power entry and exit completion feedback signals written to registers by the power management core and then sends the feedback signals to the power consumption mode controller. It counts the control signals and stores the count value in a register.

[0052] The task core described above can be a processor or core responsible for handling specific tasks. It can also be a processor or microprocessor responsible for application-level processing. The task core is the primary computing unit in a system-on-chip (SoC), and its operating state is closely linked to the system's performance and power consumption. When the system is in low load or standby mode, power consumption can be significantly reduced by lowering the task core's operating frequency or voltage or disabling unnecessary functional modules. Conversely, when the system requires high performance or to handle sudden tasks, the task core must quickly return to normal power consumption mode to ensure sufficient computing power and responsiveness. The task core can detect its own operating status and load. When it detects that the system is under low load, it can proactively request to enter low-power mode to conserve power.

[0053] The aforementioned power mode controller is a device used to manage system power mode switching. It receives power control requests from the power controllers corresponding to the task core and the power management core, and generates corresponding control signals based on these requests, thereby achieving power mode switching. The function of the power mode controller is to adjust the power consumption mode of the device in real time based on the requests of the power controllers corresponding to the task core and the power management core, so as to achieve better power management and performance under different workloads. By responding to requests from the task core and the power management core in a timely manner, the power mode controller can effectively reduce the power consumption of the device, extend the battery life of the device, and improve the performance of the device. The power mode controller can effectively balance the relationship between power consumption and performance, improve the energy efficiency of the device, and enhance the user experience.

[0054] The power management core mentioned above may be a core for processing power control strategies and execution. The power management core is responsible for configuring the switching timing of power modes and cooperating with the power mode controller to complete the power mode switching controlled by software and hardware in a coordinated manner.

[0055] The power consumption mode controller can be used to receive a request for entering or exiting a power consumption mode from a task core or a power consumption management core corresponding to the power consumption controller, and generate a control signal according to a preset switching sequence and send it to the hardware control device.

[0056] The aforementioned hardware control device can be a hardware controller that directly controls the power consumption state of each device in the system, such as a Phase Locked Loop Controller (PLL controller), a Double Data Rate Synchronous Dynamic Random Access Memory Controller (DDR controller), or an Input / Output Controller (I / O controller). The power consumption mode of each managed hardware controller can be adjusted based on control signals sent by the power mode controller.

[0057] The aforementioned preset power consumption mode may be a low power consumption mode or any other predefined power consumption mode, which is used to reduce the power consumption of the system under specific conditions (such as sleep, standby).

[0058] The switching sequence mentioned above can refer to the order and timing of the control actions of various parts of the system when entering or exiting a preset power consumption mode. It can also refer to the order and timing of the specific control actions performed by various hardware modules when the chip switches from one power consumption mode to another. In low-power design, when the system enters a low-power mode such as sleep, hibernation, or standby, or wakes up from these modes and returns to normal operating mode, different hardware modules need to be controlled in a specific order and timing to ensure system stability and optimal power consumption.

[0059] For example, when a system needs to enter a low-power mode, the switching sequence may include the following steps:

[0060] Step 1: Turn off unnecessary clock signals (clock generators).

[0061] Step 2: Turn off the power supply of the power management chip (PMIC) to non-critical hardware modules.

[0062] Step 3: precharge the dynamic random access memory (DDR) or enter a self-refresh mode.

[0063] Step 4: Turn off the phase-locked loop (PLL) to reduce power consumption associated with frequency generation.

[0064] Step 5: Reset some hardware modules (reset generator).

[0065] Step 6: Wait for confirmation feedback that all modules have entered the low power state.

[0066] During the wake-up process, the switching sequence can be configured to ensure that hardware modules are activated in the correct order, such as restoring the clock signal first and then gradually activating other hardware resources. The switching sequence can be executed by the hardware circuit, that is, the power mode controller mentioned above, and the power management core can be used to configure the switching sequence of preset power modes. This ensures low latency while also providing flexibility and robustness, ensuring efficient and safe power mode switching.

[0067] When the task core detects that the system needs to enter a preset power consumption mode (such as low power consumption mode), the task core can generate an entry request. The power consumption controller of the task core receives the entry request initiated by the task core, controls the task core to enter low power consumption, and then initiates an entry request to the power consumption mode controller. The power management core is responsible for configuring the timing of the entire switching process, and when the system needs to exit the preset power consumption mode, it cooperates with the power consumption mode controller to complete the power consumption mode switching controlled by software and hardware in collaboration. The power consumption controller of the power management core receives the system wake-up request, controls the power management core to exit low power consumption, and then initiates an exit request to the power consumption mode controller. Based on the received request, the power consumption mode controller controls multiple hardware control devices to switch the power consumption mode according to the preset timing, that is, from normal mode to low power consumption mode, or from low power consumption mode to normal mode. Low latency of power consumption mode switching can be guaranteed through hardware control, and flexibility can be provided by configuring the switching timing of preset power consumption modes according to different task requirements and special scenarios through the power management core.

[0068] For example, when an electronic device is not in use, the task core detects the system idle state and triggers a request to enter low-power mode. Upon receiving the request, the power management core configures the system power mode and hardware switching sequence to minimize latency and power consumption. For example, it first disables non-essential PLLs, then controls the DDR to enter self-refresh mode, and finally disables some I / O interfaces. The power mode controller generates control signals according to a preset sequence and sends them sequentially to the PLL controller, DDR controller, and I / O controller, causing these hardware modules to enter a low-power state. When the user resumes using the electronic device, the power management core receives a system wake-up request, such as a system interrupt or a request received through an I / O interface. It controls the power management core to exit low-power mode and controls the system power mode switcher to perform a mode switch, first restoring the I / O interfaces, then the DDR, and finally the PLL, quickly restoring the system to full functionality. This ensures the integrity of power mode switching, avoids potential omissions in the hardware-fixed switching process, and ensures system reliability and user satisfaction. This approach enables the system to not only quickly respond to power mode switches but also flexibly adapt to various task requirements and special scenarios, thereby improving the overall system power management performance and user experience.

[0069] In the above embodiment of the present application, the hardware control device includes: a first control interface, connected to the power consumption mode controller, for receiving a control signal; a hardware controller, correspondingly connected to the first control interface, for entering a preset power consumption mode or exiting a preset power consumption mode according to the control signal, and feeding back the control status of the preset power consumption mode to the power consumption mode controller, wherein the control status is used to indicate whether the hardware controller has successfully entered the preset power consumption mode or successfully exited the preset power consumption mode.

[0070] The first control interface can be a communication bridge between the hardware control device and the power consumption mode controller. The first control interface can be an interface directly connected to the hardware controller, such as an interface for connecting to a PLL controller, a DDR controller, etc.

[0071] The control signal mentioned above may be a signal for instructing the hardware to perform a specific operation. The control signal refers to an instruction issued by the power consumption mode controller, which is used to instruct the hardware control device to enter or exit a preset power consumption mode.

[0072] The aforementioned hardware controller may be a circuit that directly controls the state of a certain hardware module, such as a PLL controller for controlling the working mode of a phase-locked loop, or a DDR controller for controlling the power consumption state of a DDR memory.

[0073] The control state mentioned above refers to the status feedback of whether the hardware controller successfully enters or exits the preset power mode after executing the power mode switching operation. This state is used by the power mode controller to determine whether the power mode switching is completed.

[0074] The hardware control device receives control signals from the power mode controller via a first control interface. Based on the received control signals, the hardware controller adjusts the hardware modules it controls to enter or exit low-power mode and provides feedback on its control status to the power mode controller to confirm whether the power mode switching operation was successful. Through the collaboration between the hardware control device and the power mode controller, fast and reliable low-power mode switching is achieved. Compared to relying entirely on software control, this approach significantly reduces the latency of power mode switching and improves its efficiency.

[0075] For example, when a smartwatch detects that it has not been used for an extended period, the task core (the smartwatch's operating system) requests the smartwatch to enter low-power mode through the power mode controller. Upon receiving the request, the power mode controller sends a control signal to the hardware controller via the first control interface. For example, it first sends a control signal to the DDR controller, requesting it to enter low-power mode. The first control interface receives the control signal and transmits it to the DDR controller. The DDR controller receives the control signal, adjusts the DDR memory it controls to enter low-power mode, and sends control status feedback to the power mode controller to confirm that the DDR memory has successfully entered low-power mode. The power mode controller then sequentially controls other hardware controllers, such as the PLL controller and PMIC controller, via the first control interface according to a preset timing sequence, to enter low-power mode. Throughout this process, the interaction between the hardware control device and the power mode controller enables the smartwatch to enter low-power mode in a very short time, extending battery life while ensuring the correctness and stability of system functionality. Even if some hardware controllers fail to respond, such as the PMIC controller, the system can promptly adjust its strategy based on the feedback control status to avoid power mode switching failures and ensure system reliability.

[0076] In the above embodiment of the present application, the power consumption mode controller includes: a control circuit, which is used to generate a one-hot code according to an entry request or an exit request, wherein the one-hot code is used to represent the encoding method of the switching timing; a state machine, which is connected to the control circuit, and is used to generate a control signal according to the one-hot code and the timing judgment condition, wherein the timing judgment condition is used to indicate whether the currently executed timing in the switching timing is the last valid timing.

[0077] The one-hot code may be generated in the control circuit according to a request and a timing configuration register, wherein the request may be an entry request or an exit request.

[0078] The above-mentioned control circuit can be a hardware logic circuit for processing input signals and generating corresponding control signals. In this application, the main responsibility of the control circuit is to convert the request signal for power mode switching into a one-hot code for easy recognition by the state machine, and generate a control signal based on the state signal fed back by the state machine and output it to the hardware controller.

[0079] The control circuitry processes requests to switch power modes and generates a one-hot code to instruct the state machine to execute a specific switching sequence. A one-hot code is a binary encoding method that represents the currently active state among multiple states, with only one bit set to 1 and all other bits set to 0. This encoding method clearly indicates the specific state the system is currently in.

[0080] For example, when a task core sends a request to the system to enter or exit a low-power mode, the control circuit first parses the request and, based on the pre-configured power mode and information in the switch timing register, generates a one-hot code. This one-hot code corresponds to a specific step or sequence in the power mode switching process.

[0081] During the one-hot code generation process, the control circuit also needs to generate a timing judgment condition. This condition is used to inform the state machine whether the power mode switch sequence currently being executed is the last valid sequence in the entire switch process. This judgment condition is used to ensure the integrity and certainty of the power mode switch. It helps the state machine understand when the power mode switch will be completed, so that it can take appropriate subsequent actions, such as sending a mode switch completion indication or entering the wait state.

[0082] The control circuit not only generates one-hot codes and timing judgment conditions, but also receives feedback signals from various hardware controllers and combines them to generate an overall timing completion feedback signal, which notifies the state machine whether the current timing switch has successfully completed. Furthermore, the control circuit transparently transmits the power mode information in the power mode register to each control interface to control the corresponding module to enter or exit a low-power state.

[0083] The control circuit can convert software requests into one-hot codes that can be understood by the hardware, instructing the state machine to execute power mode switching according to a specific timing. It can also process feedback from each hardware controller to ensure the accuracy and reliability of power mode switching, effectively combining the flexibility of software and the efficiency of hardware.

[0084] The one-hot code mentioned above is a coding method in which each state is represented by only one bit, and all other bits are in the opposite state (usually zero). In power mode switching, the one-hot code is used to indicate the timing that should be executed currently. The one-hot code can be used to control the timing of power mode switching. By converting the timing configuration into a one-hot code, it is possible to precisely control which operation the state machine performs in each timing, and at the same time clearly identify whether the current operation is the last operation, thereby achieving flexible and efficient power mode switching.

[0085] The state machine can be a hardware-based transition between states, executing a series of predefined rules or operations until a final state is reached. The state machine is used to parse one-hot codes and generate sequential transition states based on timing judgment conditions.

[0086] The above timing judgment condition is a logic signal used to judge whether the currently executed power consumption mode switching timing is the last valid timing in the entire sequence.

[0087] Upon receiving a low-power entry or exit request, the control circuit converts the request into a one-hot code and generates a timing judgment condition to determine whether the current sequence is the last in a valid sequence. The state machine generates a timing transition state based on the received one-hot code and the timing judgment condition. Based on the timing transition state, the control circuit generates a control signal to control the corresponding hardware controller to enter or exit a low-power state. The control circuit also receives feedback signals from the hardware controller to confirm whether the timing control signals have been correctly executed. After the last valid sequence completes, the control circuit generates a mode switch completion indication to notify the state machine and the processor's power controller. Based on the mode switch completion indication, the processor's power controller controls the power management core to enter a low-power state or controls the task core to exit a low-power state.

[0088] By using one-hot codes and timing judgment conditions, the power mode controller achieves fast, reliable, and flexible switching between low-power modes. The one-hot codes allow the state machine to clearly identify the sequence to be processed, avoiding the delays associated with complex software scheduling. The timing judgment conditions ensure that the hardware correctly completes the mode switch after executing a valid sequence, enhancing system robustness and reliability. This hardware control approach not only reduces power mode switching latency but also increases flexibility through software-configurable timing, enabling the system to adapt to various task requirements and avoiding the potential risks associated with fixed hardware timing.

[0089] For example, assume a computing device equipped with a RISC-V processor triggers sleep mode after a prolonged period of inactivity. The laptop's power mode controller must control multiple modules, including the CPU, DDR memory, PLL, and I / O interfaces, into a low-power state. The control circuit converts timing information into a one-hot code based on the timing registers configured by the power management core. For example, sequence 1 is set to control the DDR memory to enter low power, with the one-hot code being 7'b0000100'. Based on the one-hot code and timing judgment conditions, the state machine begins executing the sequence that controls the DDR memory to enter low power. Upon receiving the low-power control signal, the DDR controller enters a low-power state and sends a completion signal back to the control circuit. The control circuit confirms the completion of sequence 1 based on the feedback signal and proceeds to the next sequence control. This process repeats until the state machine detects that the current sequence is the last valid sequence and has completed. The control circuit then generates a mode switch completion indication and notifies the power management core controller. The power management core controller then controls the power management core to enter low power, officially entering low-power mode. It should be noted that the above numerical values ​​are only for illustration and are not intended to be specific limitations.

[0090] Through the above control process, not only does hardware control reduce the delay of power mode switching, but the arbitrary timing switching method configured by the power management core also enhances the flexibility and reliability of the system, enabling the chip to more effectively respond to different task scenarios and user needs, and achieve a balance between power consumption control and system performance.

[0091] In the above embodiment of the present application, the power consumption mode switching system further includes: a timing configuration register connected to the power consumption management core, for storing the switching timing after receiving the switching timing configured by the power consumption management core.

[0092] Timing configuration registers are hardware registers used to store control signal sequences. Based on system configuration requirements, they record the order and time intervals of each module's actions during specific operations (such as power mode switching). These registers are key components for implementing hardware circuit timing control and can be dynamically adjusted based on software configuration to adapt to varying system states and load requirements.

[0093] The above-mentioned timing configuration registers may include but are not limited to low-power entry timing configuration registers, low-power exit timing configuration registers, and power mode registers of each control object. These three groups of registers determine the entire low-power entry and exit mode switching timing and the low-power mode of each module.

[0094] During the power mode switching process, the power management core first sets multiple timing configurations for different power modes based on system requirements, defining the operation sequence and time intervals for each module during the power mode switching process. When the system needs to enter a low-power mode, the power management core selects and issues a configuration based on the selected power mode. These configurations are stored in the timing configuration registers. Subsequently, at the start of the power mode switch, the power mode controller reads the information in the timing configuration registers and sequentially controls each hardware module to enter a low-power state according to a predetermined timing sequence, or to resume normal operation according to a pre-configured exit sequence upon wakeup.

[0095] In an embodiment of the present application, the timing configuration register is connected to the power management core through a bus. After the power management core configures the timing configuration register, it triggers the power mode controller to complete the power mode switching, providing the ability to dynamically adjust the power mode switching timing at the hardware level. This not only reduces the complexity of software configuration and reduces the delay of power mode switching, but also ensures the flexibility and robustness of power mode switching. Through the timing configuration register, users can flexibly set the switching order of power modes according to different task requirements and usage scenarios, avoiding the system function failure or inefficiency problems that may be caused by fixed timing, and enhancing the overall performance of the system and user experience.

[0096] For example, suppose that when the system is idle, the power management core finds through analysis that power consumption can be further reduced without affecting system responsiveness. At this time, the power management core will configure the low-power entry timing configuration register and set a low-power entry timing, such as turning off the PLL first, then letting the DDR enter the low-power state, and finally controlling the power management core to enter low power. When the user triggers the wake-up operation, the system will recover according to the pre-configured low-power mode exit timing. The power management core will be awakened first, then the DDR, and finally the PLL. In this way, not only is the delay of power mode switching significantly reduced, but the flexibility and reliability of the entire process are also enhanced. When dealing with changing task scenarios, it can manage power consumption more efficiently and intelligently, improving the overall performance of the system and user experience.

[0097] In the above embodiment of the present application, the power consumption mode switching system also includes: a second control interface, connected to the power consumption management core, for receiving a control signal; a software controller, connected to the second control interface and the first control interface, for generating a count value according to the control signal, wherein the count value is used to represent a numerical value obtained by counting the control signal; the power consumption management core is used to call the control program corresponding to the count value, and enter or exit the preset power consumption mode by executing the control program.

[0098] The first control interface is used as a communication connection structure between the power management core and the software controller.

[0099] The software controller can be a power mode switching system that, in addition to the first control interface that directly communicates with the hardware controller, includes an additional software-controllable interface circuit for inserting software control logic into the hardware switching process. The software controller can be a low-power software controller.

[0100] The software controller is composed of a control circuit and a request counting circuit, which can receive entry requests and exit requests from the power mode controller and notify the power management core through counting and interruption, so that the software can intervene in the control process.

[0101] The above-mentioned count value may be a result value obtained by counting the control signal by the request counting circuit, and is used by the software to identify the current stage of the power consumption mode switching so as to execute the corresponding control program.

[0102] A software controller is introduced into the power mode switching system to control specific timing points in the hardware switching process. During the switching process, the power mode controller sends control signals to the software controller according to the preset timing configuration, triggering counting and generating a count value. Based on the count value, the power management core calls the pre-stored control program to perform specific power mode switching operations, such as shutting down unnecessary circuits and reducing clock frequencies.

[0103] By combining hardware control and software control, the present application overcomes the problem of large delay of software control alone, as well as the shortcomings of poor flexibility and versatility of hardware control alone. The collaborative control of software and hardware improves the speed of power mode switching, while providing sufficient flexibility to adapt to the needs of different scenarios. When the system needs to quickly enter a low-power state, hardware control can quickly complete the control of most modules to reduce latency. However, if the control of a specific module is omitted in the hardware control process, or the user has new low-power control requirements during system operation, the power management core can call the corresponding software control program according to the count value through the software controller to control the omitted module or meet new control requirements, thereby ensuring the integrity and flexibility of power mode switching while maintaining the advantage of switching speed.

[0104] For example, suppose the system is using high-performance mode to perform complex calculations, and the user triggers a request for the system to enter low-power mode. The power mode switching system first starts with the task core sending a low-power request to the power mode controller, which then executes from sequence 1 according to the preset timing configuration. At sequences 2 and 6, the controller sends a low-power entry request to the software controller, triggering the counting circuit to count, generate a specific count value, and send an interrupt notification to the power management core. After reading the count value, the power management core reads and executes the pre-stored control program based on the count value. For example, at sequence 2, the control program may include adjusting the power state of the PLL, while at sequence 6, the control program may involve special power settings for the PMIC. Through such coordinated software and hardware control, the system can quickly and accurately enter low-power mode. Even if the control of certain modules may be omitted in the hardware control process, software control can ensure the integrity and reliability of the entire switching process while meeting the power consumption requirements in specific scenarios.

[0105] In the above embodiment of the present application, the software controller includes: a request counting circuit, which is used to count the control signal according to the trigger information of the control signal to obtain a count value.

[0106] The trigger information is specific data or conditions carried in the control signal, which is used to determine how the control signal is processed. The trigger information may include but is not limited to the type, quantity, frequency, or order of triggering the control signal.

[0107] In the low power mode switching process, the trigger information may be the order and number of low power request signals and wake-up request signals issued by the power mode controller. The power management core determines the low power control program to be executed based on this information.

[0108] The request counting circuit described above can be used to monitor and count the number of control signals received within a certain period of time. This circuit can be used in system designs that require counting the frequency or number of operations. The request counting circuit can be used to monitor the number of low-power request and wake-up request signals received from the power mode controller. These count values ​​are used to determine the low-power control procedure executed by the power management core.

[0109] When the request counting circuit receives a control signal, it updates an internal counter. This counter value is the count value, which reflects the receipt of the control signal. After obtaining the count value, the count value can be converted into an operation instruction set that the power management core can understand. Different count values ​​are mapped to different control programs or operation instructions through methods such as soft coding.

[0110] In an optional embodiment, a request counting circuit receives control signals from the power mode controller and counts them to generate a count value. This count value is output to a register, which the power management core reads and, through a soft-coding mechanism, determines which low-power control program should be executed. This process leverages the low latency of the hardware while retaining the flexibility and programmability of the software, allowing the system to dynamically adjust the power control strategy based on the count value (i.e., the frequency and sequence of the control signals).

[0111] Soft coding, as described above, is a coding mechanism implemented at the software level, as opposed to hard coding, which is typically implemented at the hardware level. Soft coding is primarily used in areas such as data processing, communication protocols, and control logic. It allows the coding process or coding information to be dynamically adjusted at runtime, rather than being fixed during the design or production phase. In the context of hardware-software co-design, soft coding can be used to define and control the behavior of hardware components in areas such as power management and timing control. Software can control register configuration, algorithmic decision-making, or the operation of state machines to determine the hardware's execution flow or operating mode. The flexibility of soft coding lies in its ability to adapt to changing software requirements without modifying the hardware design, thereby improving the system's programmability and adaptability.

[0112] The request counting circuit enables precise counting of control signals for power mode switching. By soft-coding the mapping between the count value and the low-power control routine, fast and flexible power mode switching is achieved. This approach avoids the limitations of fixed hardware switching sequences while reducing the latency introduced by software control, ensuring efficient power management for the chip under varying task requirements. The power management core can quickly determine and execute the appropriate low-power control strategy based on the actual control signal sequence received, improving overall system response speed and power control accuracy.

[0113] For example, if the power consumption mode controller needs to dynamically adjust the power consumption mode according to the task requirements. In the process of entering the low power consumption mode, the control signal is triggered at timing 1, timing 3, and timing 5 respectively, and the request counting circuit records that a total of 3 low power consumption requests have been triggered. After receiving the request interrupt, the power management core reads the count value (for example, 3) output by the request counting circuit to the register, and parses it through the soft coding table to find out that this represents the low power consumption mode of turning off the PLL controller, DDR controller, and PMIC controller. Therefore, the second control interface of the software controller can be combined with the hardware control as a supplementary interface for the hardware control, while also retaining the flexibility of dynamically adjusting the power consumption control process according to specific task requirements.

[0114] Figure 4 is a structural diagram of a low power consumption control system according to an embodiment of the present application, such as Figure 4 As shown, the task core can be responsible for requesting to enter the low power mode, the power management core is responsible for configuring the power mode and switching timing, the processor low power controller is responsible for controlling the processor to enter and exit low power, the power mode controller is responsible for switching the system power mode, and the controllers of each module connected to the power mode controller include but are not limited to the hardware controllers such as the PLL controller, DDR controller, IO controller, clock generator, PMIC controller, reset generator, etc. listed in this application. The controllers of each of the above modules can complete the low power control of each module in the system by receiving the request of the power mode controller. The first control interface is set between the power mode controller and the controllers of each module, and the low power software controller is connected to the power management core and the power mode controller through the first control interface and the second control interface.

[0115] Combine Figure 4 , the power mode switching process includes the following steps:

[0116] Step S401: The task core requests the system to enter low power consumption and notifies the power management core.

[0117] Step S402, the power management core configures the power consumption mode and switches the timing register;

[0118] Step S403: The processor low power consumption controller of the task core controls the task core to enter a low power consumption mode;

[0119] Step S404: the processor low power controller of the task core initiates a low power request to the power mode controller;

[0120] Step S405 , the power consumption mode controller starts power consumption mode switching, executing from sequence 1 to sequence N;

[0121] Step S406: The power consumption mode controller completes the power consumption mode switching and issues a mode switching completion indication;

[0122] Step S407: The processor low power controller of the power management core receives the power mode switching completion indication and controls the power management core to enter the low power mode;

[0123] Step S408: The power management core enters the low power mode and waits for wake-up. The low power entry process is completed.

[0124] Step S409: The low power controller of the power management core receives the wake-up request and controls the power management core to exit the low power mode;

[0125] Step S410, the power management core is awakened;

[0126] Step S411: The low power controller of the power management core initiates a wake-up request to the power mode controller;

[0127] Step S412: The power consumption mode controller starts power consumption mode switching, executing from sequence 1 to sequence N.

[0128] Step S413: The power consumption mode controller completes the power consumption mode switching and issues a mode switching completion indicator;

[0129] Step S414 , the power consumption manager of the task core receives the power consumption mode switching completion indication and controls the task core to exit low power consumption;

[0130] In step S415 , the task core is awakened, and the low power mode exit process is completed.

[0131] In the above steps S405 to S412 , the power consumption mode controller supports low power consumption mode switching at any timing.

[0132] Figure 5 is a schematic diagram of a power consumption mode controller according to an embodiment of the present application, such as Figure 5 As shown, the control circuit receives low-power entry timing configuration registers (each timing has a set of registers), low-power exit timing configuration registers (each timing has a set of registers), and power consumption mode registers of each control object (each control interface has a set of registers) from registers. These three groups of registers determine the entire low-power entry and exit mode switching timing and the low-power mode of each module.

[0133] The control circuit and state machine receive low-power entry requests from the task core's low-power controller and low-power exit requests from the power management core's low-power controller. The control circuit converts the low-power entry and exit timing configuration registers into one-hot codes and sends them to the state machine. It also generates a judgment condition for whether each timing sequence is the last valid timing sequence and sends it to the state machine. The control circuit receives low-power entry feedback signals and low-power exit feedback signals from each control interface in the module controller, generates feedback signals for each timing sequence, and sends them to the state machine. The control circuit receives status indication signals from the state machine, generates low-power entry request signals and low-power exit request signals, and sends them to the control interfaces of each module controller. It also generates a mode switch completion indication signal and sends it to the state machine and the processor's low-power controller. The control circuit also transparently transmits the input power mode registers to each control interface to control the power mode of the controlled object.

[0134] Figure 6 is a schematic diagram of a power consumption mode switching state machine according to an embodiment of the present application, such as Figure 6 As shown, the workflow of the state machine includes the following steps:

[0135] Step S601 : After receiving a low power consumption request, the low power consumption entry and wake-up control state machine switches from the “idle state” to the “enter low power consumption state”.

[0136] In step S602, the timing conversion control state machine starts to work. If the next timing is not the last valid timing, the timing conversion state machine enters "timing state 1" from "idle state".

[0137] Step S603, the timing conversion control state machine is in "timing state 1". If the next timing is the last valid timing and the current timing is completed, it directly enters the "final state"; if the current timing is invalid or the current timing is completed, it enters the next timing, and repeats this step until it enters the "final state".

[0138] In step S604, the timing transition state machine returns from the "final state" to the "idle state", and the control circuit generates a mode switching completion indication to notify the low power entry and wake-up control state machine and the processor low power controller.

[0139] Step S605 , the low power consumption entry and wake-up control state machine enters the “waiting to wake-up state”, and the low power consumption mode switch is completed.

[0140] Step S606 : The low power consumption entry and wake-up control state machine receives the wake-up request and enters the “exit low power consumption state”.

[0141] Step S607 , repeating the above steps S602 to S604 , the low power entry and wake-up control state machine returns to the “idle state”, and the low power mode exit switching is completed.

[0142] The power mode controller divides the mode switching process into N time sequences (N can be determined according to actual needs). Figure 7 This is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application. Figure 7 As shown, each timing corresponds to a set of programmable timing configuration registers, which determine the control interface of the timing operation. For example, if control interface 3 is operated at timing 1, the configuration register of timing 1 is 3'b011. If the control interface is not operated at timing 2, the configuration register of timing 2 is 3'b000. If control interface 1 is operated at timing 3, the configuration register of timing 3 is 3'b001. If control interface 4 is operated at timing 4, the configuration register of timing 4 is 3'b100. If control interface 5 is operated at timing 5, the configuration register of timing 5 is 3'b101. If control interface 2 is operated at timing 6, the configuration register of timing 6 is 3'b010. If control interface 6 is operated at timing 7, the configuration register of timing 7 is 3'b110. The specific implementation method is that the one-hot code is the one-hot code of the low-power entry timing configuration register and the low-power exit timing configuration register, and the values ​​of the low-power entry request signal and the low-power exit request signal are equivalent to the one-hot code.

[0143] Taking Table 2 as an example, in timing state 1, the low-power entry timing configuration register is configured to 3'b011, the second bit of the low-power entry request signal is output high, the one-hot code is 7'b0000100, and this bit is hard-wired to the DDR controller, thereby achieving low-power control of the DDR. In timing state 2, the low-power entry timing configuration register is configured to 3'b000, the low-power entry request signal is output to none, the one-hot code is 7'b0000000, and no control is performed. In timing state 3, the low-power entry timing configuration register is configured to 3'b001, the 0th bit of the low-power entry request signal is output high, the one-hot code is 7'b0000001, and this bit is hard-wired to the PLL controller, thereby achieving low-power control of the PLL. In timing state 4, the low-power entry timing configuration register is configured to 3'b100, the low-power entry request signal bit 3 is output high, and the one-hot code is 7'b0001000. This bit is hardwired to the IOPAD controller, thereby implementing low-power control of the IOPAD. In timing state 5, the low-power entry timing configuration register is configured to 3'b101, the low-power entry request signal bit 4 is output high, and the one-hot code is 7'b0010000. This bit is hardwired to the CLK controller, thereby implementing low-power control of CLK. In timing state 6, the low-power entry timing configuration register is configured to 3'b010, the low-power entry request signal bit 1 is output high, and the one-hot code is 7'b0000010. This bit is hardwired to the RST controller, thereby implementing low-power control of RST. In timing state 7, the low-power entry timing configuration register is configured to 3'b110, and the 5th bit of the low-power entry request signal is output high, with the one-hot code 7'b0100010. This bit is hardwired to the PMIC controller, thus implementing low-power control of the PMIC. When the timing configuration is 0, no operation is performed in this timing state, indicating an invalid timing. Therefore, by configuring the configuration register for each "timing state", power mode switching can be implemented at any timing.

[0144] Table 2

[0145]

[0146] In summary, the power mode controller implements power mode switching with arbitrary timing. Users can reasonably configure the timing configuration registers according to their needs, thereby completing the power mode switching safely and reliably and avoiding the risks brought by hardware-fixed switching timing.

[0147] This application proposes a power consumption mode hardware switching method, which designs a hardware circuit that supports arbitrarily configurable low-power control timing, making it convenient for users to reasonably configure the power consumption mode timing according to task requirements. Since it is a hardware switching circuit, the power consumption mode switching speed is improved and the complexity of software design is reduced. In addition, since the low-power control timing supports arbitrarily configurable rather than hardware-fixed, users can customize the corresponding power consumption mode timing according to the actual task scenario, thereby increasing the flexibility and reliability of the system. This power consumption mode hardware switching circuit is suitable for various systems with power consumption switching requirements and has a certain degree of versatility.

[0148] In another optional embodiment, Figure 4 On this basis, in step S405 to step S412, the power consumption mode controller controls each control interface to complete the switching of power consumption modes of arbitrary timing, wherein control interface 1 is connected to the low-power software controller, and the remaining control interfaces are connected to the hardware controllers of each module. The power consumption mode switching method of software and hardware collaborative control is realized by combining the software and hardware control interfaces.

[0149] Figure 8 is a schematic diagram of a low-power software controller according to an embodiment of the present application, such as Figure 8 As shown, the low-power software controller consists of a control circuit and a request counting circuit. The control circuit receives low-power requests and wake-up requests initiated by the power mode controller, generates a request interrupt, and notifies the power management core. The request counting circuit receives and counts low-power requests and wake-up requests initiated by the power mode controller, outputs the count value to a register, and after receiving the request interrupt, the power management core reads the counter value to determine the low-power control program to be executed (the software soft-codes the count value and the low-power control program). The control circuit receives the low-power feedback signal and wake-up feedback signal from the register and feeds them back to the power mode controller.

[0150] Figure 9 This is a schematic diagram of a timing and control interface mapping relationship according to an embodiment of the present application. Figure 9 As shown, the power mode controller divides the mode switching process into N timings (N is determined according to actual needs), and each timing corresponds to a set of programmable timing configuration registers, which determine whether the control interface of the timing operation is software control or hardware control. Figure 9The figure shows the corresponding workflow for entering low power consumption (the exit process is similar). The power controller switches from sequence 1 to sequence N. Each sequence controls a set of control interfaces, where sequences 2 and 6 control software control interfaces, and the remaining sequences control hardware control interfaces, thereby implementing a power mode switching method with cross-control between software and hardware. For example, if control interface 3 is operated at sequence 1, the configuration register of sequence 1 is 3'b011. If control interface 1 is operated at sequence 2, the configuration register of sequence 2 is 3'b001. If control interface 4 is operated at sequence 3, the configuration register of sequence 3 is 3'b100. If control interface 2 is operated at sequence 4, the configuration register of sequence 4 is 3'b010. If control interface 6 is operated at sequence 5, the configuration register of sequence 5 is 3'b110. If control interface 1 is operated at sequence 6, the configuration register of sequence 6 is 3'b001.

[0151] Figure 10 FIG. 1 is a schematic diagram of a process flow of software and hardware collaboratively controlling power consumption mode switching according to an embodiment of the present application. Figure 10 As shown in the figure, the low power software control process includes:

[0152] Step S1001: The low power software controller receives a low power entry request from the power mode controller.

[0153] Step S1002: Request the counting circuit to count and save the count to the register.

[0154] Step S1003: The control circuit generates a request interrupt.

[0155] Step S1004 : The power management core receives a request interrupt and reads a count register.

[0156] Step S1005 : The power management core clears the request interrupt.

[0157] Step S1006 : The power management core executes a corresponding low power control program according to the count value, and the specific control command is determined according to the pre-agreed soft coding.

[0158] Step S1007 : The power management core writes the low power feedback register, indicating that the software-controlled low power operation has been completed.

[0159] Step S1008 : The control circuit generates a low power consumption feedback signal.

[0160] Step S1009 : The power consumption mode controller receives the feedback signal, completes the current low power consumption control sequence, and enters the next sequence.

[0161] The power mode switching process includes:

[0162] Step S1101 : the power consumption controller switches to sequence 1 .

[0163] Step S1102: Control interface 3 to be controlled, and control the clock generator.

[0164] Step S1103 : the power consumption controller switches to sequence 2 .

[0165] Step S1104 : Controller interface 1 is controlled, and the software takes over low power consumption control.

[0166] Step S1105 : the power consumption controller switches to sequence 3 .

[0167] Step S1106: Control interface 4 to be controlled and control IO.

[0168] Step S1107 : the power consumption controller switches to sequence 4 .

[0169] Step S1108 , control interface 2 to be controlled, and control the PMIC.

[0170] Step S1109 : the power consumption controller switches to sequence 5 .

[0171] Step S1110 , the control interface 6 is controlled to control the PLL.

[0172] Step S1111 : the power consumption controller switches to sequence 6 .

[0173] Step S1112: Control interface 1 is controlled, and the software takes over low power consumption control.

[0174] This application integrates a software-controlled interface into the entire power mode hardware switching process, effectively reducing the latency of power mode switching and addressing specific scenarios. For example, if a module is not controlled during the hardware switching process, resulting in unsatisfactory power consumption, or if the user has added certain low-power control requirements, the software and hardware collaboratively control power mode switching, not only improving the speed of power mode switching but also providing users with great flexibility and versatility.

[0175] This application also designs a hardware circuit in which software and hardware can collaboratively control the low-power state of each module in the system. Hardware control effectively reduces the delay of power mode switching, and software control flexibly responds to certain special scenarios that occur during the user's use phase. For example, in the hardware switching process, a module is not controlled enough, resulting in power consumption not meeting expectations, or the user has added certain low-power control requirements. The collaborative control of power mode switching by software and hardware not only improves the speed of power mode switching, but also provides users with great flexibility. This method is applicable to various systems with power switching requirements and has a certain degree of versatility.

[0176] The present application proposes a hardware circuit that supports arbitrarily configurable low-power control timing, which facilitates users to reasonably configure the power mode switching timing according to task requirements. It reduces the complexity of software design, enhances system flexibility and reliability, and effectively improves the power mode switching speed. This method is applicable to various systems with power switching requirements and has a certain degree of versatility. Furthermore, the present application also proposes a hardware circuit in which software and hardware can collaboratively control the low-power state of each module in the system. Hardware control effectively reduces the delay of power mode switching, and software control flexibly responds to certain special scenarios that occur during the user's use phase, such as the lack of control of a module in the hardware switching process, resulting in power consumption not meeting expectations, or the user has added certain low-power control requirements. The collaborative control of power mode switching by software and hardware not only improves the power mode switching speed, but also provides users with great flexibility. This method is applicable to various systems with power switching requirements and has a certain degree of versatility.

[0177] According to an embodiment of the present application, a power consumption mode switching method is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0178] Figure 11 is a flow chart of a power consumption mode switching method according to an embodiment of the present application, such as Figure 11 As shown, the method includes:

[0179] Step S1102, in response to receiving an entry request for a preset power consumption mode sent by a power consumption controller in a power consumption mode switching system, or receiving an exit request for a preset power consumption mode sent by a power consumption controller, controlling the power consumption mode controller in the power consumption mode switching system to execute a switching sequence according to the entry request or the exit request to generate a control signal.

[0180] The switching sequence is a switching sequence of a preset power consumption mode configured by a power consumption management core in the power consumption mode switching system.

[0181] The switching timing is the switching timing of the preset power consumption mode configured by the power consumption management core.

[0182] In an optional embodiment, the power mode controller is in a standby state, waiting to receive a power mode switch request from the task core or the power management core low-power controller. When the task core detects that the system needs to enter a low-power state (for example, when the device is in standby or idle mode), it sends an entry request to the task core's low-power controller. The task core's low-power controller controls the task core to enter low power and then sends an entry request to the power mode controller. Similarly, when the power management core's low-power controller detects that the system needs to wake up from a low-power state (for example, due to user interaction or increased system load), it controls the power management core to exit the low-power mode and sends an exit request to the power mode controller. The "preset power mode" here refers to a low-power mode or high-performance mode predefined by the system based on the current operating state and load conditions, and the "switching timing" refers to the control sequence and timing of each hardware control device when entering or exiting these preset power modes. This timing is configured by the power management core based on system requirements to ensure that all hardware control devices can switch states in the appropriate order and time.

[0183] Step S1104 : controlling the plurality of hardware control devices in the power consumption mode switching system to enter or exit the preset power consumption mode according to the control signal.

[0184] Among them, different hardware control devices have different control types.

[0185] In an optional embodiment, the power consumption mode controller executes the configured switching sequence according to the received request and generates corresponding control signals. These control signals will be transmitted to multiple hardware control devices in the system. Each device will perform specific power consumption mode switching operations according to the received control signals, such as turning off or on the power supply, adjusting the clock frequency, entering or exiting a deep sleep state, etc. Since different hardware control devices have different control types, the responses and execution operations of different hardware control devices to the control signals will also be different. This ensures that the system can perform fine-grained control for different hardware characteristics during the power consumption mode switching process.

[0186] By having the hardware control device directly respond to control signals, scheduling delays at the software layer are avoided, ensuring rapid execution of power mode switching. The power management core can flexibly configure the timing of power mode switching based on current task requirements, enabling the system to adapt to a variety of usage scenarios and load conditions, improving the versatility and adaptability of power mode switching. Preset switching timing ensures coordinated and consistent power mode switching between hardware control devices, avoiding system failures caused by timing errors and enhancing system robustness and stability. Fast power mode switching reduces the device's wake-up time from sleep to active state, or the wait time from active to sleep, thereby improving device responsiveness and providing users with a smoother and more immediate user experience. By shifting some power mode switching control to the hardware layer, the burden of software design is reduced, allowing software development to focus more on upper-level application logic rather than underlying hardware state management, simplifying overall system design and maintenance. This application effectively combines the low latency of hardware with the flexibility of software to achieve efficient, flexible, and reliable control of power mode switching, which is of great significance for improving the energy efficiency and user experience of modern high-performance computing systems, IoT devices, mobile terminals, and the like.

[0187] Through the above steps, in response to receiving a request to enter a preset power mode sent by a power consumption controller in a power consumption mode switching system, or receiving a request to exit a preset power mode sent by a power consumption controller, the power consumption mode controller in the power consumption mode switching system is controlled to execute a switching sequence according to the entry request or exit request to generate a control signal, wherein the switching sequence is the switching sequence of the preset power mode configured by the power consumption management core in the power consumption mode switching system; and multiple hardware control devices in the power consumption mode switching system are controlled to enter or exit the preset power mode according to the control signal, wherein different hardware control devices have different control types, thereby achieving an improved power consumption mode switching effect. It is easy to notice that when the system load decreases or enters a specific standby state, the task core detects this change and generates a request to enter the preset power mode accordingly. The generation of this request is immediate and direct, avoiding the delay of software scheduling, thereby enabling a rapid response to load changes. The power consumption management core can ensure that before entering the preset power mode, the system can adjust the power consumption control sequence of each module according to specific needs. By properly configuring the timing, hardware function failures caused by improper control sequences can be avoided. The power mode controller receives an entry request from the task core or a system wake-up request, such as a system interrupt or a trigger signal from IO, and executes according to the configured switching timing to generate a corresponding control signal. By controlling multiple hardware control devices through control signals, the delay of power mode switching can be reduced and the switching speed can be improved. Since each hardware control device is responsible for a different type of control, this division of labor and cooperation model ensures the comprehensiveness and efficiency of the system when switching power modes, avoiding the singleness and complexity of software control. Through the immediate request generation of the task core, the flexible timing configuration of the power management core, the hardware control signal generation of the power mode controller, and the division of labor and cooperation of multiple hardware control devices, the efficiency of power mode switching can be improved, thereby solving the technical problem of poor power mode switching effect in related technologies.

[0188] In the above-mentioned embodiment of the present application, multiple hardware control devices in the power consumption mode switching system are controlled to enter a preset power consumption mode or exit a preset power consumption mode according to a control signal, including: generating a one-hot code according to an entry request or an exit request, wherein the one-hot code is used to represent the encoding method of the switching timing; generating a control signal according to the one-hot code and a timing judgment condition, wherein the timing judgment condition is used to indicate whether the currently executed timing in the switching timing is the last valid timing.

[0189] In an optional embodiment, the generation of one-hot codes and the use of timing judgment conditions are the key to achieving efficient and flexible control of the power mode switching hardware circuit. When the system receives requests to enter or exit low power consumption, these requests will be converted into one-hot codes, which is a coding method that can ensure that only one control object is activated in any timing, avoiding conflicts and unnecessary power consumption that may be caused by multiple control objects switching power modes at the same time. At the same time, through the timing judgment conditions, the circuit can determine whether the currently executed timing is the last valid timing, which enables the system to quickly issue an indication of mode switching completion after completing all necessary operations, thereby avoiding unnecessary waiting time and reducing the overall power mode switching delay.

[0190] The above steps improve the speed of power mode switching. By operating directly at the hardware level, software configuration delays and system scheduling uncertainties are avoided. Furthermore, system flexibility and robustness are maintained, allowing users to configure timing registers to adapt to different task scenarios. Because it supports arbitrary timing configuration, this solution is highly versatile and can be applied to a variety of systems requiring power mode switching, not just specific chips or devices. This provides designers with greater choice and innovation opportunities.

[0191] By combining the use of one-hot codes and timing judgment conditions, the present application achieves fast response, flexible configuration and high reliability of power consumption mode switching.

[0192] In the above embodiment of the present application, the method also includes: controlling the software controller in the power consumption mode switching system to generate a count value according to a control signal, and entering or exiting the preset power consumption mode by executing a control program corresponding to the count value.

[0193] In this application, by introducing a software control interface into the power mode switching system, collaborative control of hardware and software is achieved, enhancing the system's flexibility and versatility. Specifically, when the power mode controller controls the software controller, it can generate a count value associated with the control signal. This count value is further interpreted by the power management core to determine which set of preset low-power control programs to execute.

[0194] When the power consumption management of a key module is omitted in the hardware control process, the software control interface can dynamically intervene to ensure that all modules can enter or exit low-power mode as expected, thereby avoiding performance or power consumption issues caused by incomplete power consumption control. Secondly, this combination of software and hardware control mechanism allows users to customize the power consumption mode switching process according to actual needs. Even if new power consumption management requirements arise during the product life cycle, they can be adapted through software updates without changing the hardware design. This not only reduces design costs but also improves user experience. This application achieves the dual advantages of low latency and high flexibility in power consumption mode switching through the collaborative control of software and hardware, and is suitable for a wide range of power consumption control scenarios.

[0195] In the above embodiment of the present application, the software controller in the power consumption mode switching system is controlled to generate a count value corresponding to the control signal, including: controlling the request counting circuit in the software controller to count the control signal according to the trigger information of the control signal to obtain the count value.

[0196] In this application, by introducing a software control interface, namely a low-power software controller, into the power mode switching system, an effective supplement and flexible control of the hardware switching process is achieved. Specifically, when hardware control cannot meet the power mode switching requirements in a specific scenario, such as when the hardware switching process omits control of a key module or the user proposes new low-power control requirements during the chip's use phase, the low-power software controller can generate a count value corresponding to the control signal. This count value encodes information about the specific low-power control program to be executed. Subsequently, based on the read count value, the power management core can identify and execute the corresponding control program to accurately enter or exit the preset power mode. This combination of software and hardware control not only maintains the fast response and low latency advantages brought by hardware switching, but also gives the system high flexibility and robustness in the face of complex and changing task scenarios, ensuring the chip's efficiency and reliability in power consumption control, and effectively avoiding the problems of functional failure or inaccurate power consumption control that may be caused by fixed hardware processes. This achieves refined management of chip power consumption without affecting the user experience, improving overall system performance and user satisfaction.

[0197] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0198] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0199] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0200] According to an embodiment of the present application, a power consumption mode switching device for implementing the above power consumption mode switching method is also provided. Figure 12 is a schematic diagram of a power consumption mode switching device according to an embodiment of the present application, such as Figure 12 As shown, the device includes: a first control module 1202 and a second control module 1204.

[0201] Among them, the first control module is used to control the power consumption mode controller in the power consumption mode switching system to execute the switching timing according to the entry request or exit request in response to receiving an entry request for the preset power consumption mode sent by the power consumption controller in the power consumption mode switching system, or receiving an exit request for the preset power consumption mode sent by the power consumption controller, to generate a control signal, wherein the switching timing is the switching timing of the preset power consumption mode configured by the power consumption management core in the power consumption mode switching system; the second control module is used to control multiple hardware control devices in the power consumption mode switching system to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

[0202] It should be noted that the first control module 1302 and the second control module 1304 correspond to steps S1202 to S1204 in the above embodiment. The examples and application scenarios implemented by the two modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiment 1. It should be noted that the above modules or units can be hardware components or software components stored in a memory (e.g., memory 104) and processed by one or more processors (e.g., processors 102a, 102b, ..., 102n). The above modules can also be part of the device and can be run in the computer terminal 10 provided in the first embodiment.

[0203] It should be noted that the preferred implementation scheme involved in the above embodiments of this application is the same as the scheme provided in Example 1, as well as the application scenario and implementation process, but is not limited to the scheme provided in Example 1.

[0204] In an embodiment of the present application, a computing device may be provided, comprising: a memory storing an executable program; and a processor for running the program, wherein when the program is run, any of the methods in the above embodiments is executed. It should be noted that the computing device may be a chip, which is not limited here.

[0205] In this embodiment, the computer terminal can execute the program code in the method.

[0206] A person skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0207] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0208] Optionally, in this embodiment, the above-mentioned storage medium may be located in any one of the computing devices in the computing device group in the computer network, or in any one of the mobile terminals in the mobile terminal group.

[0209] In an embodiment of the present application, a task core is used to generate an entry request to a preset power consumption mode; a power management core is used to configure the switching timing of the preset power consumption mode; a power controller is connected to the task core and the power management core and is used to receive an entry request or generate an exit request of the preset power consumption mode based on a received wake-up request; a power consumption mode controller is connected to the power consumption controller and is used to execute the switching timing according to the entry request or exit request to generate a control signal; a plurality of hardware control devices are respectively connected to the power consumption mode controller and are used to enter or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types, thereby achieving an improved power consumption mode switching effect. It is easy to notice that when the system load decreases or enters a specific standby state, the task core detects this change and generates a request to enter the preset power consumption mode accordingly. The generation of this request is immediate and direct, avoiding the delay of software scheduling, thereby being able to quickly respond to load changes. The power consumption management core can ensure that before entering the preset power consumption mode, the system can adjust the power consumption control timing of each module according to specific needs. By properly configuring the timing, hardware function failures caused by improper control sequences can be avoided. After receiving an entry request or exit request from the power management controller, the power mode controller executes according to the configured switching timing and generates corresponding control signals. By controlling multiple hardware control devices through control signals, the delay of power mode switching can be reduced and the switching speed can be improved. Since each hardware control device is responsible for a different type of control, this division of labor and cooperation model ensures the comprehensiveness and efficiency of the system when switching power modes, avoiding the singleness and complexity of software control. Through the immediate request generation of the task core, the flexible timing configuration of the power management core, the hardware control signal generation of the power mode controller, and the division of labor and cooperation of multiple hardware control devices, the switching efficiency of the power mode can be improved, thereby solving the technical problem of poor power mode switching effect in related technologies.

[0210] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program, and when the computer program is executed by a processor, the method provided in the embodiment is implemented.

[0211] The embodiments of the present application further provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store a computer program that, when executed by a processor, implements the method provided in the embodiments above.

[0212] The embodiment of the present application further provides a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, the method provided in the above embodiment is implemented.

[0213] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0214] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0215] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0216] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0217] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware.

[0218] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0219] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A power consumption mode switching system, characterized in that: include: A task core, configured to generate an entry request to a preset power consumption mode; A power management core, configured to configure a switching sequence of the preset power consumption modes; a power consumption controller connected to the task core and the power consumption management core, and configured to receive the entry request, or generate an exit request of the preset power consumption mode according to the received wake-up request; a power consumption mode controller, connected to the power consumption controller, configured to execute the switching sequence according to the entry request or the exit request to generate a control signal; A plurality of hardware control devices are respectively connected to the power consumption mode controller and are used to enter or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

2. The power consumption mode switching system according to claim 1, wherein: The hardware control device includes: A first control interface, connected to the power consumption mode controller, for receiving a control signal; A hardware controller is connected to the first control interface, and is used to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal, and to feedback the control status of the preset power consumption mode to the power consumption mode controller, wherein the control status is used to indicate whether the hardware controller successfully enters the preset power consumption mode or successfully exits the preset power consumption mode.

3. The power consumption mode switching system according to claim 1, wherein: The power consumption mode controller includes: a control circuit, configured to generate a one-hot code according to the entry request or the exit request, wherein the one-hot code is used to represent an encoding method of the switching sequence; A state machine is connected to the control circuit and is used to generate the control signal according to the one-hot code and a timing judgment condition, wherein the timing judgment condition is used to indicate whether the currently executed timing in the switching timing is the last valid timing.

4. The power consumption mode switching system according to claim 1, wherein: The power consumption mode switching system further includes: a timing configuration register connected to the power management core via a bus, and configured to store the switching timing after receiving the switching timing configured by the power management core; The power consumption mode register is connected to the power consumption management core via a bus, and is used to store the preset power consumption mode after receiving the preset power consumption mode configured by the power consumption management core.

5. The power consumption mode switching system according to claim 2, wherein: The power consumption mode switching system further includes: A second control interface, connected to the power management core, for receiving a control signal; a software controller connected to the second control interface and the first control interface, and configured to generate a count value according to the control signal, wherein the count value is used to represent a numerical value obtained by counting the control signal; The power consumption management core is used to call the control program corresponding to the count value, and enter the preset power consumption mode or exit the preset power consumption mode by executing the control program.

6. The power consumption mode switching system according to claim 5, characterized in that: The software controller includes: The request counting circuit is used to count the control signal according to the trigger information of the control signal to obtain the count value.

7. A method for switching power consumption modes, characterized in that: include: In response to receiving an entry request for a preset power consumption mode sent by a power consumption controller in a power consumption mode switching system, or receiving an exit request for the preset power consumption mode sent by the power consumption controller, controlling the power consumption mode controller in the power consumption mode switching system to execute a switching timing according to the entry request or the exit request to generate a control signal, wherein the switching timing is a switching timing of the preset power consumption mode configured by a power consumption management core in the power consumption mode switching system; Controlling multiple hardware control devices in the power consumption mode switching system to enter or exit the preset power consumption mode according to the control signal, wherein different hardware control devices have different control types.

8. The power consumption mode switching method according to claim 7, wherein: Controlling multiple hardware control devices in the power consumption mode switching system to enter the preset power consumption mode or exit the preset power consumption mode according to the control signal includes: generating a one-hot code according to the entry request or the exit request, wherein the one-hot code is used to represent an encoding method of the switching sequence; The control signal is generated according to the one-hot code and a timing judgment condition, wherein the timing judgment condition is used to indicate whether the currently executed timing in the switching timing is the last valid timing.

9. The power consumption mode switching method according to claim 7, wherein: The method further comprises: Controlling a software controller in the power consumption mode switching system to generate a count value according to the control signal; Entering the preset power consumption mode or exiting the preset power consumption mode is performed by executing a control program corresponding to the count value.

10. The power consumption mode switching method according to claim 9, wherein: Controlling a software controller in the power consumption mode switching system to generate a count value corresponding to the control signal includes: The request counting circuit in the software controller is controlled to count the control signal according to the trigger information of the control signal to obtain the count value.

11. A system on chip, characterized in that: include: The system according to any one of claims 1 to 6.

12. A computing device, characterized in that include: a memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 7 to 10 when running.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored executable program, wherein when the executable program is run, the device where the storage medium is located is controlled to execute the method according to any one of claims 7 to 10.

14. A computer program product, characterized in that A computer program is included which, when executed by a processor, implements the method according to any one of claims 7 to 10.

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