Memory management methods and memory storage devices

Abstract

This invention provides a memory management method and a memory storage device, which can increase the lifespan of the memory storage device. The memory management method is used in a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple physical units. The memory management method includes: performing a detection operation on the multiple physical units to obtain multiple detection results corresponding to the multiple physical units; generating a physical unit bitmap based on the multiple detection results; selecting a target physical unit from the multiple physical units according to the physical unit bitmap and preset conditions, wherein the preset conditions are used to characterize that the target physical unit includes a first type of physical unit and a second type of physical unit; performing a target operation to replace the first type of physical unit or the second type of physical unit, and using the replaced first type of physical unit or the replaced second type of physical unit as a spare physical unit; and updating the physical unit bitmap.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a memory storage device. Background Technology

[0002] With the rapid evolution of flash memory technology, NAND flash memory has transitioned from two-dimensional (2D) to three-dimensional (3D), and in terms of storage cells, it has gradually evolved from single-layer cell (SLC) to three-layer (TLC) and even four-layer (QLC) storage cells. This series of technological innovations has greatly improved the storage density of NAND flash memory while reducing the cost per unit capacity. However, as the thickness of the oxide layer inside flash memory continues to decrease, the impact of erase and write operations on the storage medium becomes more significant, thus affecting the durability and reliability of flash memory.

[0003] The memory storage device can perform a self-test operation to mark the erroneous physical cells in the rewritable non-volatile memory module as bad physical cells within a certain number of programmed / erase cycles (PE cycles). Bad physical cells will no longer be used in subsequent data access operations.

[0004] Optimizing the management strategy of physical cells to improve the accuracy of marking not only helps extend the lifespan of flash memory, but also further improves the overall performance and stability of the system, ensuring that users have a smoother and more reliable user experience. Summary of the Invention

[0005] Exemplary embodiments of the present invention provide a memory management method and a memory storage device that can make full use of the storage space of the memory storage device to increase the lifespan of the memory storage device.

[0006] An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple entity units, each of which includes multiple sub-entity units. The memory management method includes: performing a detection operation on the multiple entity units to obtain multiple detection results corresponding to the multiple entity units; generating an entity unit bitmap based on the multiple detection results; selecting a target entity unit from the multiple entity units according to the entity unit bitmap and preset conditions, wherein the preset conditions are used to characterize that the target entity unit includes a first type of entity unit and a second type of entity unit; performing a target operation to replace the first type of entity unit or the second type of entity unit, and using the replaced first type of entity unit or the replaced second type of entity unit as a spare entity unit; and updating the entity unit bitmap.

[0007] In an exemplary embodiment of the present invention, the detection operation includes a first detection operation and a second detection operation, wherein the detection result corresponding to the first type of entity unit is used to characterize that the first detection operation is successful and the second detection operation is unsuccessful, and the detection result corresponding to the second type of entity unit is used to characterize that the second detection operation is successful and the first detection operation is unsuccessful.

[0008] In an exemplary embodiment of the present invention, the detection result corresponding to the third type of entity unit is used to characterize that both the first detection operation and the second detection operation are successful, and the detection result corresponding to the fourth type of entity unit is used to characterize that both the first detection operation and the second detection operation are failed.

[0009] In an exemplary embodiment of the present invention, the first detection operation is a single-level storage cell read detection operation, and the second detection operation is a three-level storage cell read detection operation.

[0010] In an exemplary embodiment of the present invention, the step of generating the entity unit bitmap based on the plurality of detection results includes: classifying each of the plurality of sub-entity units in the plurality of entity units based on the plurality of detection results to obtain a classification result, wherein the classification result includes a first type of entity unit, a second type of entity unit, a third type of entity unit, and a fourth type of entity unit; and generating the entity unit bitmap according to the classification result, wherein the entity unit bitmap is used to reflect that the plurality of sub-entity units in the plurality of entity units are respectively the first type of entity unit, the second type of entity unit, the third type of entity unit, or the fourth type of entity unit.

[0011] In an exemplary embodiment of the present invention, the step of performing the target operation to replace the first type of entity unit or the second type of entity unit includes: replacing the first type of entity unit or the second type of entity unit in the target entity unit with the third type of entity unit.

[0012] In an exemplary embodiment of the present invention, the memory management method further includes: replacing the fourth type of entity unit with the spare entity unit based on the entity unit bitmap.

[0013] In an exemplary embodiment of the present invention, the memory management method further includes: selecting a target write entity unit corresponding to a write mode of a write instruction based on the entity unit bitmap, and writing write data corresponding to the write instruction into the target write entity unit, wherein the target write entity unit is the first type of entity unit or the second type of entity unit; and performing a read verification operation on the target write entity unit after the target write entity unit is filled.

[0014] In an exemplary embodiment of the present invention, the memory management method further includes: based on the entity cell bitmap, setting a first read count threshold and a second read count threshold for the first type of entity cell and the second type of entity cell respectively, wherein the first read count threshold and the second read count threshold are both lower than the read count threshold for the third type of entity cell.

[0015] In an exemplary embodiment of the present invention, the memory management method further includes: in an idle state, performing a read verification operation on the first type of entity unit with stored data and the second type of entity unit with stored data based on the entity unit bitmap.

[0016] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes multiple physical units. Each of the multiple physical units includes multiple sub-physical units. The memory control circuit unit is used to perform detection operations on the multiple physical units to obtain multiple detection results corresponding to the multiple physical units. The memory control circuit unit is also used to generate a physical unit bitmap based on the multiple detection results. The memory control circuit unit is further used to select a target physical unit from the multiple physical units according to the physical unit bitmap and preset conditions, wherein the preset conditions are used to characterize that the target physical unit includes a first type of physical unit and a second type of physical unit. The memory control circuit unit is further used to perform a target operation to replace the first type of physical unit or the second type of physical unit, and to use the replaced first type of physical unit or the replaced second type of physical unit as a spare physical unit. The memory control circuit unit is also used to update the physical unit bitmap.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to classify each of the plurality of sub-entity units among the plurality of entity units based on the plurality of detection results to obtain a classification result, wherein the classification result includes a first type of entity unit, a second type of entity unit, a third type of entity unit, and a fourth type of entity unit. The memory control circuit unit is further configured to generate an entity unit bitmap according to the classification result, wherein the entity unit bitmap is used to reflect that the plurality of sub-entity units among the plurality of entity units are respectively the first type of entity unit, the second type of entity unit, the third type of entity unit, or the fourth type of entity unit.

[0018] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to replace the first type of entity unit or the second type of entity unit in the target entity unit with the third type of entity unit.

[0019] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to replace the fourth type of entity unit with the spare entity unit based on the entity unit bitmap.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to select a target write entity unit corresponding to a write mode of a write instruction based on the entity unit bitmap, and write write data corresponding to the write instruction into the target write entity unit, wherein the target write entity unit is either the first type of entity unit or the second type of entity unit. The memory control circuit unit is further configured to perform a read verification operation on the target write entity unit after it has been filled.

[0021] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to set a first read count threshold and a second read count threshold for the first type of entity unit and the second type of entity unit respectively based on the entity unit bitmap, wherein the first read count threshold and the second read count threshold are both lower than the read count threshold of the third type of entity unit.

[0022] In an exemplary embodiment of the present invention, in an idle state, the memory control circuit unit is further configured to perform a read verification operation on the first type of entity unit with stored data and the second type of entity unit with stored data based on the entity unit bitmap.

[0023] Based on the above, the present invention provides a memory management method and a memory storage device, which can fully utilize the storage space of the rewritable non-volatile memory module while maintaining the correctness of the data stored in the rewritable non-volatile memory module, thereby effectively improving the service life and performance of the memory storage device.

[0024] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of a system and storage device according to an exemplary embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0031] Figure 7 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention;

[0032] Figure 8 This is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0033] Figure 9 This is a schematic diagram of the structure of a solid unit bitmap according to an exemplary embodiment of the present invention;

[0034] Figure 10 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention;

[0035] Figure 11 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention;

[0036] Figure 12 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Detailed Implementation

[0037] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0038] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0039] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0040] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be coupled to a system bus 110.

[0041] In one exemplary embodiment, the host system 11 can be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0042] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0043] In one exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0044] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the host system 11 is an in-vehicle system. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0045] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0046] Please refer to Figure 3The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0047] Figure 4 This is a block diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0048] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0049] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0050] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0051] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0052] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0053] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical units. Specifically, memory cells on the same word line can form one or more physical programmable units. If each memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0054] In one exemplary embodiment, an entity programming unit is the smallest unit of programming. That is, an entity programming unit is the smallest unit for writing data. For example, an entity programming unit can be an entity page or an entity sector. If the entity programming unit is an entity page, these entity programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple entities for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 entities, and the size of one entity sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer entities, and the size of each entity sector may also be larger or smaller. On the other hand, an entity unit is the smallest unit of erasure. That is, each entity unit contains a minimum number of storage units that are erased together. For example, an entity unit is an entity block.

[0055] Figure 5 This is a block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0056] Please refer to Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0057] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0058] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware format. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are written to the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0059] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0060] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuitry is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuitry 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0061] The host interface 52 is coupled to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. In addition, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0062] The memory interface 53 is coupled to the memory management circuit 51 and used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0063] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0064] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0065] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0066] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0067] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0068] Please refer to Figure 6 The memory management circuit 51 can logically group the physical cells 610(0)~610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. A physical cell refers to a virtual block (VB). For example, a virtual block may include multiple physical programming units. For example, a virtual block may include multiple physical erase units. For example, a virtual block may contain one or more physical cells.

[0069] The physical units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 may store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0070] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0071] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped to a logical unit, it means that the data currently stored in this physical unit contains valid data. Conversely, if a physical unit is not currently mapped to any logical unit, it means that the data currently stored in this physical unit does not contain any valid data.

[0072] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logical units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logic-to-entity mapping table.

[0073] To fully utilize the storage space of the memory storage device 10 and extend its lifespan, this invention provides a memory management method. Generally, on a production line, the memory storage device 10 can perform a self-test operation to mark erroneous physical cells in the rewritable non-volatile memory module 43 within a certain number of programmed / erase cycles (PE cycles), record the erroneous physical cells in a bad block table, and then discontinue using the physical cells recorded in the bad block table in subsequent data access operations.

[0074] The physical units recorded in the bad block table may be, for example, early bad blocks inherent in the memory storage device 10 at the time of manufacture, and later bad blocks generated during self-test operations or when subsequent data access operations fail (e.g., physical units that fail to erase and / or write operations, or physical units that fail to read and verify operations).

[0075] A typical self-test operation may, for example, involve the memory management circuit 51 sequentially performing erase, write, and read detection operations on all physical cells in the rewritable non-volatile memory module 43. The read detection operation includes two types of error detection operations, such as a single-level cell (SLC) read detection operation and an X-level cell (XLC) read detection operation, where X is an integer greater than 1 and may vary depending on the specifications of the memory storage device 10. For example, the X-level cell read detection operation can be a second-level cell (MLC), a third-level cell (TLC), or a fourth-level cell (QLC) read detection operation. Alternatively, the read detection operation may include both single-level and third-level cell read detection operations. If an error occurs in the single-level and / or third-level cell read detection operations of a physical cell during the read detection operation, the physical cell is identified as a bad physical cell and recorded in the bad block table.

[0076] However, if an entity cell encounters an error only in a single-level memory cell read detection operation and not in a three-level memory cell read detection operation, then this entity cell can be successfully accessed in three-level memory cell (TLC) mode. Accordingly, the memory management method provided by this invention can increase the storage space of the rewritable non-volatile memory module 43 by including entity cells that only encountered errors in one type of read detection operation in subsequent data access operations during the self-test operation of the memory storage device 10, thereby extending the lifespan of the memory storage device 10.

[0077] Figure 7 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention; Figure 8 This is a schematic diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a solid unit bitmap according to an exemplary embodiment of the present invention. Please refer to... Figures 7 to 9 Specifically, Figure 7 The memory management method is associated with self-test operations. In one exemplary embodiment, such as Figure 8 As shown, the rewritable non-volatile memory module 43 may include, for example, physical planes P0 and P1, wherein physical planes P0 and P1 respectively include sub-physical units B(0) to B(N), and the multiple sub-physical units B(0) to B(N) in physical planes P0 and P1 are used to form multiple physical units V(0) to V(N).

[0078] In step S701, the memory management circuit 51 can perform an erase operation on multiple entity units V(0)~V(N). Specifically, the memory management circuit 51 can clear all data stored in the sub-entity units B(0)~B(N) in entity planes P0 and P1.

[0079] In step S702, the memory management circuit 51 can subsequently perform write operations on multiple physical units V(0) to V(N). Specifically, the memory management circuit 51 can write the test data of the self-test operation to multiple physical units V(0) to V(N). That is, the memory management circuit 51 can write the test data of the self-test operation to the sub-physical units B(0) to B(N) in the physical planes P0 and P1.

[0080] It should be noted that in step S701 (or step S702), if any sub-entity unit fails to erase (or write), this sub-entity unit is recorded as a fourth type of entity unit and will not be put into subsequent data access operations.

[0081] In step S703, the memory management circuit 51 can perform detection operations on multiple entity units V(0)~V(N) to obtain multiple detection results corresponding to the multiple entity units V(0)~V(N). In an exemplary embodiment, the detection operation includes a first detection operation and a second detection operation. The first detection operation may be, for example, a single-level cell (SLC) read detection operation, and the second detection operation may be, for example, a second-level cell (MLC) read detection operation, a third-level cell (TLC) read detection operation, or a fourth-level cell (QLC) read detection operation. Specifically, the memory management circuit 51 can perform SLC read verification operation and TLC read verification operation on the sub-entity units B(0)~B(N) in entity planes P0 and P1 respectively to determine whether the test data of the self-test operation was correctly written to the sub-entity units B(0)~B(N) in step S702, and generate multiple detection results corresponding to the entity units V(0)~V(N) based on the results of the SLC read verification operation and the TLC read verification operation.

[0082] Next, the memory management circuit 51 can generate an entity cell bitmap 91 based on multiple detection results. Specifically, in step S704, the memory management circuit 51 can classify each sub-entity cell B(0) to B(N) in the multiple entity cells V(0) to V(N) based on multiple detection results to obtain a classification result. Specifically, the memory management circuit 51 can classify the entity cells B(0) to B(N) in entity planes P0 and P1 respectively based on the multiple detection results generated in step S703 to obtain a classification result. In an exemplary embodiment, the classification result includes a first type of entity cell, a second type of entity cell, a third type of entity cell, and a fourth type of entity cell.

[0083] For example, the detection result corresponding to the first type of entity unit indicates that the first detection operation (i.e., the SLC read verification operation) was successful and the second detection operation (i.e., the TLC read verification operation) failed. That is, the first type of entity unit can be successfully accessed in SLC mode. Similarly, the detection result corresponding to the second type of entity unit indicates that the second detection operation was successful and the first detection operation failed. That is, the second type of entity unit can be successfully accessed in TLC mode.

[0084] For example, the detection result corresponding to the third type of entity cell (also known as a good entity cell) is used to indicate that both the first and second detection operations are successful. Accordingly, in both single-level cell (SLC) and triple-level cell (TLC) modes, the memory management circuit 51 can use the third type of entity cell to perform data access operations. For example, the detection result corresponding to the fourth type of entity cell (also known as a bad entity cell) is used to indicate that both the first and second detection operations are unsuccessful. Accordingly, in subsequent data access operations, the memory management circuit 51 no longer uses the fourth type of entity cell.

[0085] Additionally, in step S705, the memory management circuit 51 can generate an entity cell bitmap 91 based on the classification results. Specifically, the entity cell bitmap 91 can be used to reflect that the sub-entity cells B(0) to B(N) in multiple entity cells V(0) to V(N) are respectively a first type entity cell, a second type entity cell, a third type entity cell, or a fourth type entity cell.

[0086] like Figure 9As shown, sub-entity units B(0), B(1), and B(3) in entity plane P0 and sub-entity unit B(0) in entity plane P1 are first-type entity units. Sub-entity units B(3) and B(N) in entity plane P1 are second-type entity units. Sub-entity units B(2) and B(N) in entity plane P0 and sub-entity unit B(2) in entity plane P1 are third-type entity units. Sub-entity unit B(1) in entity plane P1 is a fourth-type entity unit.

[0087] Further, in step S706, the memory management circuit 51 can select a target entity unit from a plurality of entity units V(0)~(N) according to the entity unit bitmap 91 and preset conditions. In an exemplary embodiment, the preset conditions are used to characterize that the target entity unit includes both a first type of entity unit and a second type of entity unit. Specifically, as shown in the example... Figure 9 As shown, the sub-entity unit B(3) belonging to the entity plane P(0) is a first type of entity unit, and the sub-entity unit B(3) belonging to the entity plane P(1) is a second type of entity unit. Therefore, the memory management circuit 51 can select entity unit V(3) as the target entity unit.

[0088] Next, the memory management circuit 51 can perform a target operation to replace a first type of entity unit or a second type of entity unit in entity unit V(3), and use the replaced first type of entity unit or the replaced second type of entity unit as a spare entity unit. Specifically, in step S707, the memory management circuit 51 can replace a first type of entity unit or a second type of entity unit in the target entity unit (i.e., entity unit V(3)) with a third type of entity unit, and use the replaced first type of entity unit or the replaced second type of entity unit as a spare entity unit. In an exemplary embodiment, such as Figure 9 As shown, the memory management circuit 51 can replace the first type of entity unit in entity unit V(3) (i.e., the sub-entity unit B(3) in entity plane P0) with the third type of entity unit, and use the replaced sub-entity unit B(3) in entity plane P0 as a spare entity unit to complete the target operation. In another embodiment, the memory management circuit 51 can also replace the second type of entity unit in entity unit V(3) (i.e., the sub-entity unit B(3) in entity plane P1) with the third type of entity unit, and use the replaced sub-entity unit B(3) in entity plane P1 as a spare entity unit to complete the target operation.

[0089] On the other hand, in step S708, the memory management circuit 51 can replace the fourth type of entity cell with a spare entity cell based on the entity cell bitmap 91. In an exemplary embodiment, such as Figure 9As shown, the memory management circuit 51 can replace the sub-entity unit B(1) in the physical plane P0 with the sub-entity unit B(3) in the physical plane P0. In another embodiment, the memory management circuit 51 can also replace the sub-entity unit B(1) in the physical plane P0 with the sub-entity unit B(3) in the physical plane P1. Accordingly, the storage space of the memory storage device 10 can be increased.

[0090] Accordingly, in step S709, the memory management circuit 51 can update the entity cell bitmap 91. Specifically, the memory management circuit 51 can update the entity cell bitmap 91 according to the operation of replacing the first type of entity cell or the second type of entity cell (see step S707) and / or replacing the fourth type of entity cell.

[0091] Finally, in step S710, the memory management circuit 51 can set a first read count threshold and a second read count threshold for the first type of entity cell and the second type of entity cell, respectively, based on the entity cell bitmap 91. In an exemplary embodiment, the memory management circuit 51 can, for example, be configured to... Figure 9 A first read count threshold is set for the first type of entity units B(0) and B(1) of entity plane P0 and the first type of entity units B(0) and B(1) of entity plane P1, and a second read count threshold is set for the second type of entity units B(3) and B(N) of entity plane P1. Specifically, both the first and second read count thresholds are lower than the read count threshold of the third type of entity unit. The first read count threshold may be equal to or not equal to the second read count threshold, for example, and this invention does not limit this. In this way, the frequency of performing read verification operations on the first and second type of entity units can be increased to maintain the performance of the memory storage device 10.

[0092] Based on the above, the memory management method of the present invention can allocate sub-entity units where only one read detection operation fails to subsequent data access operations, thereby increasing the storage space of the rewritable non-volatile memory module 43 and thus extending the lifespan of the memory storage device 10. Furthermore, the memory management method of the present invention can also increase the frequency of read verification operations performed on the first and second type of entity units by setting a lower read count threshold for the first and second type of entity units, thereby strengthening the protection of the first and second type of entity units and maintaining the performance of the memory storage device 10.

[0093] After completion Figure 7 After associating the memory management method with the self-test operation, it can be executed. Figure 10 The memory management method shown is associated with write operations and read verification operations. Figure 10This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Please refer to... Figure 10 .

[0094] In step S1001, the memory management circuit 51 can receive write commands from the host system 11. Specifically, when data needs to be written to the memory access device 10, the user can transmit a write command to the memory storage device 10 through the host system 11.

[0095] In step S1002, the memory management circuit 51 may select a target write entity cell corresponding to the write mode of the write instruction based on the entity cell bitmap 91, and write the write data corresponding to the write instruction to the target write entity cell. In an exemplary embodiment, the memory management circuit 51 may, for example, select one or more target write entity cells corresponding to the write mode of the write instruction from the idle area 602 based on the entity cell bitmap 91 after receiving the write instruction.

[0096] In one exemplary embodiment, the write mode may be, for example, an operating mode in which the memory storage device 10 can operate, such as a single-level cell (SLC) mode, a two-level cell (MLC) mode, a three-level cell (TLC) mode, or a four-level cell (QLC) mode. Therefore, the target write entity may be, for example, a first type of entity that can be successfully accessed in SLC mode or a second type of entity that can be successfully accessed in MLC mode (or TLC mode, QLC mode).

[0097] For example, assuming the write mode corresponding to the write instruction is SLC mode, the memory management circuit 51 can select the target write entity cell corresponding to the SLC mode from the idle area 602 based on the entity cell bitmap 91. In an exemplary embodiment, a first type of entity cell in the entity cell bitmap 91 can be successfully accessed in SLC mode, and a second type of entity cell can be successfully accessed in TLC mode. The memory management circuit 51 can select a sub-entity cell B(0) of entity plane P0 as the target write entity cell based on the entity cell bitmap 91, and write the write data corresponding to the write instruction to the target write entity cell based on the SLC mode.

[0098] In step S1003, the memory management circuit 51 can perform a read verification operation on the target write entity unit after it is full. Specifically, since the target write entity unit can only be successfully accessed in a single operating mode, the probability of errors in the target write entity unit may be higher compared to the third type of entity unit. Therefore, after the target write entity unit is full, the memory management circuit 51 can perform a read verification operation on the target write entity unit to ensure that the data stored in the target write entity unit is error-free, thereby maintaining the performance of the memory storage device 10.

[0099] In this way, the memory management method of the present invention can use the management entity unit bitmap 91 to use a suitable target write entity unit to complete the write operation, and after the target write entity unit is full, a read verification operation is performed on the target write entity unit, which can increase the storage space of the memory storage device 10 while maintaining the performance of the memory storage device 10.

[0100] The memory management method of the present invention further improves the read verification operation of the memory storage device 10. Generally, the conventional read verification operation involves the memory storage device 10 periodically obtaining the number of reads of each used physical unit containing stored data, and performing read verification operations on used physical units whose read counts exceed a read count threshold, so as to ensure the correctness of the data stored in the rewritable non-volatile memory module 43.

[0101] Based on this, the memory management method of the present invention has been improved in the following ways: (1.) As mentioned above, a lower read count threshold is set for the first type of entity unit and the second type of entity unit; (2.) In the idle state, a read verification operation is directly performed on the first type of entity unit and the second type of entity unit. Specific implementation details are as follows: Figure 11 As shown. Figure 11 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Please refer to... Figure 11 .

[0102] In step S1101, the memory management circuit 51 can determine whether the memory storage device 10 is in an idle state. If yes, proceed to step S1105; if no (meaning that the memory storage device 10 is in an operating state), proceed to step S1102.

[0103] In step S1102, the memory management circuit 51 may periodically obtain the number of reads of the sub-entity unit containing stored data. In an exemplary embodiment, the memory management circuit 51 may periodically obtain the number of reads of the sub-entity unit containing stored data from the rewritable non-volatile memory module 43, wherein the sub-entity unit containing stored data may be, for example, one or more, and each sub-entity unit containing stored data may be, for example, a first type of entity unit, a second type of entity unit, or a third type of entity unit.

[0104] In step S1103, the memory management circuit 51 can determine whether the number of reads of the sub-entity unit containing stored data is greater than a read count threshold. In an exemplary embodiment, each sub-entity unit in the rewritable non-volatile memory module 43 may, for example, have a read count threshold. For example, if the sub-entity unit containing stored data is a third type of entity unit, the memory management circuit 51 can determine whether the number of reads of this third type of entity unit is greater than its read count threshold. If yes, proceed to step S1104; if no, do not perform read verification operation on this third type of entity unit, that is, end the process for this third type of entity unit. Figure 11 Memory management methods.

[0105] Additionally, it should be noted that, as mentioned earlier, after completing the following... Figure 7 After the memory management method associated with the self-test operation is implemented, the memory management circuit 51 can set a first read count threshold and a second read count threshold for the first type of entity unit and the second type of entity unit, respectively, wherein the first read count threshold and the second read count threshold are both lower than the read count threshold of the third type of entity unit.

[0106] Therefore, in an exemplary embodiment, if the sub-entity unit storing data is a first type of entity unit, the memory management circuit 51 can use a lower read count threshold (i.e., a first read count threshold) as a criterion to determine whether the read count of this first type of entity unit is greater than its first read count threshold. If yes, proceed to step S1104; if no, do not perform a read verification operation on this first type of entity unit for the time being.

[0107] Similarly, if the sub-entity unit storing data is a second type of entity unit, the memory management circuit 51 can also use a lower read count threshold (i.e., the second read count threshold) as a criterion to determine whether the read count of this second type of entity unit is greater than its second read count threshold. If yes, proceed to step S1104; if no, do not perform a read verification operation on this second type of entity unit for the time being.

[0108] Next, in step S1104, the memory management circuit 51 can perform a read verification operation. Specifically, the memory management circuit 51 can perform a read verification operation on sub-entity units with stored data whose read count exceeds a read count threshold to confirm whether the stored data is correct, thereby ensuring the correctness of the data stored in the rewritable non-volatile memory module 43.

[0109] On the other hand, when the memory storage device 10 is in an idle state, in step S1105, the memory management circuit 51 can perform a read verification operation on the first type of entity unit with stored data and the second type of entity unit with stored data based on the entity unit bitmap 91.

[0110] Specifically, in the idle state, the memory management circuit 51 can query the first type of entity cells and the second type of entity cells in the rewritable non-volatile memory module 43 based on the entity cell bitmap 91, and perform read verification operations on the first type of entity cells and / or the second type of entity cells in the rewritable non-volatile memory module 43 that have stored data, in order to confirm the correctness of the stored data.

[0111] Based on the above, since the first type of entity unit and the second type of entity unit can only be successfully accessed in a single operating mode, the probability of errors in the first type of entity unit and the second type of entity unit may be higher than that in the third type of entity unit. Therefore, the memory management method of the present invention can improve the protection of the data stored in the first type of entity unit and the second type of entity unit by (1.) setting a lower read count threshold for the first type of entity unit and the second type of entity unit; and (2.) directly performing read verification operations on the first type of entity unit and the second type of entity unit with stored data in the idle state, so as to ensure the correctness of the data stored in the rewritable non-volatile memory module 43.

[0112] Figure 12 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Please refer to... Figure 12 In step S1201, a detection operation is performed on multiple entity units V(0)~V(N) to obtain multiple detection results corresponding to the multiple entity units V(0)~V(N). In step S1202, an entity unit bitmap 91 is generated from the multiple detection results. In step S1203, a target entity unit is selected from the multiple entity units V(0)~V(N) according to the entity unit bitmap 91 and preset conditions, wherein the preset conditions are used to characterize that the target entity unit contains a first type of entity unit and a second type of entity unit. In step S1204, a target operation is performed to replace the first type of entity unit or the second type of entity unit, and the replaced first type of entity unit or the replaced second type of entity unit is used as a spare entity unit. In step S1205, the entity unit bitmap is updated.

[0113] However, Figure 12 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 12Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 12 The method can be used in conjunction with the above embodiments or alone, and the present invention does not limit it.

[0114] In summary, the memory management method and memory storage device proposed in the exemplary embodiments of the present invention can fully utilize the storage space of the rewritable non-volatile memory module while maintaining the correctness of the data stored in the rewritable non-volatile memory module, thereby effectively improving the service life and performance of the memory storage device.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, A rewritable non-volatile memory module is used, wherein the rewritable non-volatile memory module includes multiple physical units, wherein each of the multiple physical units includes multiple sub-physical units, and the memory management method includes: A detection operation is performed on the plurality of entity units to obtain a plurality of detection results corresponding to the plurality of entity units respectively; An entity unit bitmap is generated based on the multiple detection results. The entity unit bitmap is generated by performing the detection operation on the multiple sub-entity units based on the multiple detection results. A target entity unit is selected from the plurality of entity units according to the entity unit bitmap and preset conditions, wherein the preset conditions are used to characterize that the target entity unit includes a first type of entity unit and a second type of entity unit; For the target entity unit, perform a target operation to replace either the first type of entity unit or the second type of entity unit, and use the replaced first type of entity unit or the replaced second type of entity unit as a spare entity unit; and Update the entity cell bitmap. The detection operation includes a first detection operation and a second detection operation. The detection result corresponding to the first type of entity unit is used to indicate that the first detection operation is successful and the second detection operation is unsuccessful. The detection result corresponding to the second type of entity unit is used to indicate that the second detection operation is successful and the first detection operation is unsuccessful. The detection result corresponding to the third type of entity unit is used to indicate that both the first detection operation and the second detection operation are successful. The detection result corresponding to the fourth type of entity unit is used to indicate that both the first detection operation and the second detection operation are unsuccessful. The first detection operation is a single-level storage unit read detection operation, and the second detection operation is a three-level storage unit read detection operation.

2. The method according to claim 1, wherein the step of generating the entity unit bitmap based on the plurality of detection results includes: Based on the multiple detection results, each of the multiple sub-entity units in the multiple entity units is classified to obtain a classification result, wherein the classification result includes the first type of entity unit, the second type of entity unit, the third type of entity unit, and the fourth type of entity unit; and The entity unit bitmap is generated based on the classification result, wherein the entity unit bitmap is used to reflect that the multiple sub-entity units among the multiple entity units are respectively the first type of entity unit, the second type of entity unit, the third type of entity unit, or the fourth type of entity unit.

3. The memory management method according to claim 2, wherein the step of performing the target operation to replace the first type of entity unit or the second type of entity unit includes: Replace the first type of entity unit or the second type of entity unit in the target entity unit with the third type of entity unit.

4. The memory management method according to claim 2, further comprising: Based on the entity unit bitmap, the fourth type of entity unit is replaced with the spare entity unit.

5. The memory management method according to claim 1, further comprising: Based on the entity unit bitmap, a target write entity unit corresponding to the write mode of the write instruction is selected, and write data corresponding to the write instruction is written to the target write entity unit, wherein the target write entity unit is either the first type of entity unit or the second type of entity unit; and After the target write entity unit is filled, a read verification operation is performed on the target write entity unit.

6. The memory management method according to claim 1, further comprising: Based on the entity unit bitmap, a first read count threshold and a second read count threshold are set for the first type of entity unit and the second type of entity unit, respectively. Wherein, both the first read count threshold and the second read count threshold are lower than the read count threshold of the third type of entity unit.

7. The memory management method according to claim 1, further comprising: In the idle state, based on the entity unit bitmap, a read verification operation is performed on the first type of entity unit with stored data and the second type of entity unit with stored data.

8. A memory storage device, characterized in that, include: A connection interface unit for coupling to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, wherein each of the plurality of physical units comprises a plurality of sub-physical units; and The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: A detection operation is performed on the plurality of entity units to obtain multiple detection results corresponding to the plurality of entity units. An entity unit bitmap is generated based on the multiple detection results. This entity unit bitmap is generated by performing the detection operation on the multiple sub-entity units based on the multiple detection results. A target entity unit is selected from the plurality of entity units based on the entity unit bitmap and preset conditions, wherein the preset conditions are used to indicate that the target entity unit includes a first type of entity unit and a second type of entity unit. For the target entity unit, a target operation is performed to replace either the first type of entity unit or the second type of entity unit, and the replaced first type of entity unit or the replaced second type of entity unit is used as a spare entity unit. Update the entity cell bitmap. The detection operation includes a first detection operation and a second detection operation. The detection result corresponding to the first type of entity unit is used to indicate that the first detection operation is successful and the second detection operation is unsuccessful. The detection result corresponding to the second type of entity unit is used to indicate that the second detection operation is successful and the first detection operation is unsuccessful. The detection result corresponding to the third type of entity unit is used to indicate that both the first detection operation and the second detection operation are successful. The detection result corresponding to the fourth type of entity unit is used to indicate that both the first detection operation and the second detection operation are unsuccessful. The first detection operation is a single-level storage unit read detection operation, and the second detection operation is a three-level storage unit read detection operation.

9. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to classify each of the plurality of sub-entity units among the plurality of entity units based on the plurality of detection results to obtain a classification result, wherein, The classification results include the first type of entity unit, the second type of entity unit, the third type of entity unit, and the fourth type of entity unit, and The memory control circuit unit is further configured to generate the entity unit bitmap based on the classification result, wherein the entity unit bitmap is used to reflect that the multiple sub-entity units among the multiple entity units are respectively the first type of entity unit, the second type of entity unit, the third type of entity unit, or the fourth type of entity unit.

10. The memory storage device of claim 9, wherein the memory control circuit unit is further configured to replace the first type of entity unit or the second type of entity unit in the target entity unit with the third type of entity unit.

11. The memory storage device of claim 9, wherein the memory control circuit unit is further configured to replace the fourth type of entity unit with the spare entity unit based on the entity unit bitmap.

12. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to select a target write entity unit corresponding to a write mode of a write instruction based on the entity unit bitmap, and write write data corresponding to the write instruction into the target write entity unit, wherein, The target write entity unit is either the first type of entity unit or the second type of entity unit, and The memory control circuit unit is also used to perform a read verification operation on the target write entity unit after the target write entity unit is full.

13. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to set a first read count threshold and a second read count threshold for the first type of entity unit and the second type of entity unit respectively, based on the entity unit bitmap, wherein, Both the first read count threshold and the second read count threshold are lower than the read count threshold of the third type of entity unit.

14. The memory storage device according to claim 8, wherein, In the idle state, the memory control circuit unit is also used to perform read verification operations on the first type of entity unit with stored data and the second type of entity unit with stored data based on the entity unit bitmap.

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