Cache verification method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a cache verification method and device, electronic equipment and a readable storage medium. The method comprises the following steps: constructing a first subprogram; the first subprogram is used for generating a data access request; constructing a second subprogram based on the function behavior information of the to-be-verified cache; the second subprogram is used for receiving the data access request and responding to the data access request based on the functional behavior information; and generating a verification result of the to-be-verified cache based on the response result of the second subprogram. Therefore, according to the embodiment of the invention, the second subprogram is constructed based on the functional behavior information of the to-be-verified cache, hardware modeling of the to-be-verified cache can be realized, and meanwhile, the verification result is obtained by constructing the first subprogram used for generating the data access request and according to the response result of the second subprogram, so that the verification efficiency is improved. According to the method and the device, test constraint can be realized according to different data access requests, different cache verification requirements are met, and the cache verification effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a cache verification method, device, electronic device and readable storage medium. Background Art

[0002] With the development of computer technology, some integrated chips adopt multi-processor (Central Processing Unit, CPU) system, that is, multiple processor cores are used for data processing.

[0003] In a multi-core CPU, multiple cores often access and update the same shared data (such as global variables, process control blocks, etc.). In order to ensure the data consistency of each core, the cache module usually performs corresponding functional behaviors based on the cache consistency protocol. Therefore, the behavioral accuracy of the cache module is particularly important. How to verify the cache module has become an urgent problem to be solved. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a cache verification method, device, electronic device and readable storage medium to solve the problem of how to verify the cache. The specific technical solution is as follows: In a first aspect of the present invention, a cache verification method is provided, the method comprising: Constructing a first subroutine; wherein the first subroutine is used to generate a data access request; Based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data memory access request and respond to the data memory access request based on the functional behavior information; Based on the response result of the second subroutine, a verification result of the cache to be verified is generated.

[0005] Optionally, responding to the data access request based on the functional behavior information includes: Determine at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request; generating at least one data acquisition request based on the data acquisition address and outputting the data acquisition request; At least one data write request is generated based on the data write address and the data write request is output.

[0006] Optionally, the method further comprises: The second subroutine is executed cyclically to obtain a plurality of response results of the second subroutine.

[0007] Optionally, the generating the verification result of the cache to be verified based on the response result of the second subprogram includes: Generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified; Based on the response result of the second subroutine and the reference response result, a verification result of the cache to be verified is generated.

[0008] Optionally, the data memory access request includes at least a processor core identifier and a memory access address.

[0009] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0010] In a second aspect of the present invention, a cache verification device is provided, the device comprising: A first construction module is used to construct a first subprogram; the first subprogram is used to generate a data access request; A second construction module is used to construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is used to receive the data memory access request and respond to the data memory access request based on the functional behavior information; A generation module is used to generate a verification result of the cache to be verified based on the response result of the second subprogram.

[0011] Optionally, the second building block includes: A determination submodule, configured to determine at least one data acquisition address and at least one data writing address based on the functional behavior information and the data memory access request; A first request generation submodule, configured to generate at least one data acquisition request based on the data acquisition address and output the data acquisition request; The second request generation submodule is used to generate at least one data write request based on the data write address and output the data write request.

[0012] Optionally, the device further comprises: The execution module is used to execute the second subroutine in a loop to obtain multiple response results of the second subroutine.

[0013] Optionally, the generating module includes: A reference submodule, configured to generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified; The result generation submodule is used to generate the verification result of the cache to be verified based on the response result of the second subprogram and the reference response result.

[0014] Optionally, the data memory access request includes at least a processor core identifier and a memory access address.

[0015] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0016] In a third aspect of the present invention, there is also provided an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the method described in the first aspect when executing the program stored in the memory.

[0017] In a fourth aspect of the implementation of the present invention, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in the first aspect above.

[0018] In a fifth aspect of the implementation of the present invention, there is also provided a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0019] The cache verification method provided by the embodiment of the present invention is through constructing a first subroutine; the first subroutine is used to generate a data access request; based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information; based on the response result of the second subroutine, the verification result of the cache to be verified is generated. In this way, the embodiment of the present invention can realize the hardware modeling of the cache to be verified by constructing the second subroutine based on the functional behavior information of the cache to be verified. At the same time, by constructing the first subroutine for generating the data access request, the cache to be verified can be verified by the first subroutine and the second subroutine, and the verification result can be obtained according to the response result of the second subroutine. The constraints on the test can be realized according to different data access requests, different cache verification requirements can be met, and the effect of cache verification can be improved. At the same time, compared with the method of building a hardware circuit for verification, the cache verification method provided by the embodiment of the present invention only needs to construct the second subroutine according to the functional behavior information, which greatly improves the efficiency of cache verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0021] Figure 1 A flowchart of a cache verification method according to an embodiment of the present invention; Figure 2is a schematic diagram of the structure of a second subroutine in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a cache verification device in an embodiment of the present invention; Figure 4 Schematic diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0024] Figure 1 FIG. 1 is a flow chart of the steps of a cache verification method in an embodiment of the present invention. Figure 1 As shown, the method includes: Step 101: construct a first subroutine; the first subroutine is used to generate a data access request.

[0025] Step 102: construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is used to receive the data memory access request and respond to the data memory access request based on the functional behavior information.

[0026] Step 103: Generate a verification result of the cache to be verified based on the response result of the second subprogram.

[0027] With respect to the above steps 101 to 103, the embodiment of the present invention can be applied to any computer device, and the embodiment of the present invention does not limit this. It should be noted that the embodiment of the present invention can be carried out in the chip design stage to perform functional verification on the designed cache module. Of course, it can also be carried out before the chip goes into production or when there is a functional abnormality, and the embodiment of the present invention does not limit this. Among them, the above-mentioned cache to be verified refers to a cache module that has a verification requirement. Cache refers to a high-speed memory whose access speed is faster than system memory and is equivalent to the processing speed of the CPU, but the cache capacity is much smaller than the system memory. The principle based on the cache is the "local behavior of program execution and data access" in the memory, that is, within a certain program execution time and space, the accessed code and data will be concentrated in a part.

[0028] Among them, the functional behavior information is used to characterize the cache consistency protocol implemented by the cache to be verified, that is, the cache consistency protocol followed by the cache to be verified during normal operation. The cache consistency protocol refers to the cache consistency management in a multi-processor system. Because in a multi-core system, multiple cores may read and write operations on the same memory address at the same time. To manage these concurrent accesses and ensure the data consistency of each core, a protocol is required to coordinate the cache status of each core to prevent reading old data or erroneous data. Therefore, it is necessary to enable the cache module to implement corresponding functional behaviors based on the cache consistency protocol. Among them, the above-mentioned cache consistency protocol can be MESI (Modified, Exclusive, Shared, Invalid, Modified, Exclusive, Shared, Invalid), MOESI (Modified, Owned, Exclusive, Shared, Invalid, Modified, Occupied, Exclusive, Shared, Invalid), MSI (Modified, Shared, Invalid, Modified, Shared, Invalid) or CHI (Coherent Hub Interface, consistency protocol), etc., and the embodiment of the present invention is not limited to this.

[0029] Specifically, the cache is used in the processor system to receive data access requests and respond to data access requests, that is, according to the data access requests of the CPU, CPU core or other modules, read data from the corresponding address or write data. Accordingly, in order to verify the cache module, the embodiment of the present invention can construct a first subroutine, and the first subroutine is used to generate data access requests. The above-mentioned first subroutine can be understood as a test module used to provide incentives to the cache to be verified in a test environment, and different data access requests can represent different types of incentives. Specifically, the first subroutine can randomly generate data access requests, or it can generate data access requests according to preset rules, which can be set according to actual needs, and the embodiment of the present invention does not limit this. Among them, the above-mentioned preset rules can be the parameter content required to be included in the data access request, for example, it can include the access address, and it can also include the CPU core identification, etc., which can be set based on the verification requirements, and the embodiment of the present invention does not limit this.

[0030] Among them, the above-mentioned functional behavior information is also used to describe the functional behavior implemented when the cache to be verified is running. Specifically, the functional behavior implemented when the cache module is running refers to the request sent by the cache module during normal operation, that is, when the processor is simulating normal operation, the minimum condition for the normal operation of the cache module is usually provided by the hardware circuit. However, building a hardware circuit is often cumbersome, resulting in low verification efficiency. In this case, the embodiment of the present invention can construct a second subroutine based on the functional behavior information of the cache to be verified for verification, without the need to build a real hardware circuit for simulation.

[0031] Specifically, the functional behavior information is often an operation behavior that complies with the specified bus protocol rules. On this basis, the second subroutine can receive a data access request and respond to the data access request based on the specified bus protocol rules. Specifically, the response operation refers to issuing a corresponding data read and write request based on the data access request and the functional behavior information. The specified bus protocol rules can be a pre-set cache consistency protocol, which can be CHI, MSI, etc.

[0032] The above-mentioned response result refers to the data read and write request issued by the second subroutine based on each data access request. Furthermore, the embodiment of the present invention can verify the cache to be verified based on the response result output by the second subroutine. Specifically, the embodiment of the present invention can generate a reference response result for each data access request based on the specified bus protocol rule. Accordingly, the response result of each data access request and the reference response result can be compared. If the comparison is consistent, it is determined that the cache to be verified complies with the specified bus protocol rule. If the comparison is inconsistent, it is determined that the cache to be verified does not comply with the specified bus protocol rule.

[0033] Optionally, the embodiment of the present invention may also set a ratio threshold to determine the ratio of the response results that are consistent with the comparison, and when the ratio is greater than the ratio threshold, it is determined that the cache to be verified complies with the specified bus protocol rules. When the ratio is not greater than the ratio threshold, it is determined that the cache to be verified does not comply with the specified bus protocol rules.

[0034] In summary, the cache verification method provided by the embodiment of the present invention is through constructing a first subroutine; the first subroutine is used to generate a data access request; based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information; based on the response result of the second subroutine, the verification result of the cache to be verified is generated. In this way, the embodiment of the present invention can realize the hardware modeling of the cache to be verified by constructing the second subroutine based on the functional behavior information of the cache to be verified. At the same time, by constructing the first subroutine for generating a data access request, the cache to be verified can be verified by the first subroutine and the second subroutine, and the verification result can be obtained according to the response result of the second subroutine. The constraints on the test can be implemented according to different data access requests, different cache verification requirements can be met, and the effect of cache verification can be improved. At the same time, compared with the method of building a hardware circuit for verification, the cache verification method provided by the embodiment of the present invention only needs to construct the second subroutine according to the functional behavior information, which greatly improves the efficiency of cache verification.

[0035] Optionally, the operation of responding to the data access request based on the functional behavior information may specifically include: S21. Determine at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request.

[0036] S22. Generate at least one data acquisition request based on the data acquisition address and output the data acquisition request.

[0037] S23. Generate at least one data write request based on the data write address and output the data write request.

[0038] The data acquisition address and data writing address can be generated based on the data access request and the functional behavior information. Based on the access address carried by the data access request, according to the bus protocol rules corresponding to the cache to be verified, the data processing operation that needs to be executed in accordance with the bus protocol rules can be determined, and then at least one data acquisition address and at least one data writing address that comply with the bus protocol rules can be determined based on the determined data processing operation. Accordingly, a data acquisition request can be generated and output based on the data acquisition address, and a data writing request can be generated and output based on the data writing address.

[0039] Exemplarily, taking the CHI bus as an example, a data access request indicates that a unique copy of the data is desired, so that the data can be modified, otherwise other copies (if any) cannot know that their data is no longer authentic. The situation here is that when he issues the request, no cache has a valid copy, whether it is the request module of the data access request or other caches at the next level. In order to maintain the cache consistency in the CHI bus, the embodiment of the present invention can first access the access address carried by the data access request to request the current data. Then, based on the CHI rule, a data acquisition request needs to be sent to the access address in the memory. At the same time, in this example, the data at the access address does not have a new or old statement. At the same time, the message of this data acquisition request contains the node identifier of the original request, so the embodiment of the present invention can also generate a data write request to return the data to the requester. Furthermore, the embodiment of the present invention can also add a unique identifier (uniqueclean, uc) to the data acquisition request and the data write request, uc indicating that the data is a unique copy that is consistent with the memory data. The initiator of the request can then send a transaction completion identifier (comack) to indicate that the transaction has been completed.

[0040] Specifically, since the data processing operations performed by the cache are often data transfer, each data processing operation requires data acquisition and data writing. When the data memory access request is a data storage request, the above-mentioned data acquisition address can be the memory access address carried by the data storage request, and accordingly, the above-mentioned data write address can be the address to which the data needs to be written. It can be understood that in order to ensure cache consistency, the cache consistency protocol often performs cache updates so that the data in the caches of different cores remain consistent, so the above-mentioned data write address can be one or more. When the data memory access request is a data access request, the above-mentioned data acquisition address can be the memory access address carried by the data access request, and accordingly, the above-mentioned data write address can be the destination address carried by the data access request. Furthermore, since the data transfer of multiple addresses may be involved in the data processing operation, the above-mentioned data acquisition address can also be multiple.

[0041] Furthermore, by outputting a data acquisition request and a data writing request, the response result of the second subprogram can be printed, thereby facilitating timely acquisition of the response result of the second subprogram.

[0042] In the embodiment of the present invention, at least one data acquisition address and at least one data write address are determined based on the functional behavior information and the data access request; at least one data acquisition request is generated based on the data acquisition address and the data acquisition request is output; at least one data write request is generated based on the data write address and the data write request is output. In this way, the response result of the second subroutine can be obtained through the output of the second subroutine. At the same time, by generating a data acquisition request and a data write request, it can be verified whether the operation of the cache to be verified complies with the corresponding functional behavior information, thereby realizing the verification of the cache.

[0043] Optionally, the embodiment of the present invention may further include: S31. Execute the second subroutine in a loop to obtain a plurality of response results of the second subroutine.

[0044] The above loop operation can be implemented through a loop function, and the above second subroutine can be nested in a loop function (for loop function or while loop function, etc.), so that the second subroutine in the loop function can be executed cyclically according to the clock cycle.

[0045] Specifically, each cycle may include data acquisition and data submission operations, and accordingly, each cycle may output a data acquisition request and a data write request, so that the effect of data flow in the pipeline design can be achieved. Specifically, in the embodiment of the present invention, the operations of submitting, acquiring, submitting, and acquiring can be performed in sequence, so as to achieve the effect of updating data within one beat of the combinational logic.

[0046] Optionally, the second subroutine can also be used to construct a first queue and a second queue. The first queue is used to store the data access requests sent by the first subroutine in the order of reception. When the first queue is full, the first subroutine can be prepared to resend the request and store part of the information in the second queue. At the same time, when there is an idle position in the first queue, based on the part of the information of the original request stored in the second queue, the first subroutine is required to resend the corresponding request. Accordingly, the second subroutine responds to the stored data access requests in sequence according to the storage order in the first queue. In this way, the feedback queue structure of the cache module can be simulated.

[0047] Optionally, Figure 2 is a schematic diagram of the structure of a second subroutine in an embodiment of the present invention, such as Figure 2As shown, the second subroutine may specifically include a transceiver module, a cache module and a control module. The transceiver module is used to receive data access requests and output data access requests. The cache module is used to record the address of global valid data and local valid data. The control module is used to execute the above-mentioned S21~S23 operations, that is, to control the process of each transaction. Each transaction starts when the request receiving module receives the request. Among them, the transceiver module may include receiving modules and sending modules of different channels, namely: request receiving module, data receiving module, response receiving module, request sending module, data sending module and response sending module, monitoring sending module. Among them, the retransmission (Retry) queue refers to the above-mentioned second queue, which is used to store part of the requested information when the first queue is full.

[0048] Optionally, the operation of generating the verification result of the cache to be verified based on the response result of the second subprogram may specifically include: S41. Generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified.

[0049] S42: Generate a verification result of the cache to be verified based on the response result of the second subprogram and the reference response result.

[0050] Specifically, for any data access request, the reference response result may include the response operations that the cache executes in sequence when the functional behavior information is met, that is, a series of data transfer operations of the cache. Accordingly, the embodiment of the present invention may compare the request parameters and the execution order of each request included in the reference response result with the response result. If they are consistent, the cache to be verified meets the requirements. If they are inconsistent, it does not meet the requirements.

[0051] Thus, in the embodiment of the present invention, a reference response result is generated for each data access request based on the functional behavior information of the cache to be verified; and a verification result of the cache to be verified is generated based on the response result of the second subprogram and the reference response result. In this way, verification of the cache can be achieved.

[0052] Optionally, the data memory access request at least includes a processor core identifier and a memory access address.

[0053] Among them, the above-mentioned processor core identifier refers to the unique identifier of different CPU cores, which is used to characterize different processor cores. Specifically, since the cache consistency protocol (such as MESI, MOESI, MSI, etc.) used by the multi-core CPU must handle multiple cache states (such as sharing, exclusive, modification, etc.), and these protocols must minimize redundant communications. Designing a reasonable protocol can ensure data consistency without frequent delays and conflicts. This process is extremely complicated. In order to ensure the verification of cache consistency, data access requests from different CPU cores can be used for verification. Therefore, the data access requests in the embodiment of the present invention may include a processor core identifier. Furthermore, the above-mentioned processor core identifier can be generated based on the processor core contained in the system where the cache to be verified is located. It can be randomly generated according to actual needs or generated according to preset rules. The embodiment of the present invention does not limit this.

[0054] Accordingly, since the cache may perform different response operations for different memory access addresses, the data memory access request in the embodiment of the present invention may also include the memory access address, so that the second subroutine responds based on the functional behavior information and the memory access address. The above-mentioned memory access address may be a memory address, or an address of a first-level cache or a second-level cache, and may be randomly generated, and the embodiment of the present invention does not limit this.

[0055] Optionally, the data access request may be generated based on different verification requirements, for example, verification of data sharing between threads, such as a shared counter or a lock variable.

[0056] In this way, the embodiment of the present invention can verify the consistency of the cache of a multi-core CPU system by carrying the processor core identification and the data access request of the memory access address, ensure the timely propagation of cache updates between cores, and avoid calculation errors or resource competition caused by data asynchrony.

[0057] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0058] The high-level programming language refers to a high-level software development language, which is relative to a low-level programming language. They usually have a good human-computer interaction interface and powerful data abstraction capabilities. The high-level programming language can be JAVA, C, C++, python or Systemc, which can be selected according to actual needs, and the embodiment of the present invention does not limit this. Optionally, an event-driven method and a method similar to kernel scheduling can also be used to update the combination or sequential logic.

[0059] It should be noted that in related technologies, hardware description languages ​​(systemc, verilog, systemverilog, etc.) are usually used to build hardware design models. However, hardware description languages ​​are quite different from traditional software development languages, and developers need to understand concepts such as hardware timing, delay, and parallelism. For beginners, the learning cost is high, especially to understand sequential logic and circuit synchronization. Moreover, hardware description languages ​​such as Verilog and VHDL are mainly based on register transfer level (RTL), and developers need to manually define signal transmission and status, with a low level of abstraction. This low-level abstraction leads to lengthy code and difficult debugging when designing complex circuits, which reduces development efficiency.

[0060] The embodiment of the present invention is constructed using a high-level programming language, and the code can be written through high-level synthesis (HLS), which simplifies the cumbersome details of the register transfer level (RTL). With the help of Python's high-level data structures and control statements, developers can more easily describe complex circuit behaviors and data flows. Python's modular design, encapsulation characteristics of functions and classes allow hardware design codes to be more easily reused, which is conducive to building parameterized modules and functions. Developers can use object-oriented methods to build complex modules and achieve a high code reuse rate. Optionally, compared to systemc, which has a complete library, python requires a similar library to complete the timing simulation, and a scheduler to schedule the process of each component, which is convenient for the expression of hardware language. The embodiment of the present invention can obtain the python library in advance, and construct the above-mentioned first subroutine and second subroutine based on the python library.

[0061] Figure 3 FIG. 1 is a schematic diagram of a cache verification device according to an embodiment of the present invention. Figure 3 As shown, the device 20 may include: A first construction module 201 is used to construct a first subprogram; the first subprogram is used to generate a data access request; A second construction module 202 is used to construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is used to receive the data memory access request and respond to the data memory access request based on the functional behavior information; the functional behavior information is used to characterize the cache consistency protocol implemented by the cache to be verified; The generating module 203 is used to generate the verification result of the cache to be verified based on the response result of the second subprogram.

[0062] Optionally, the second building block includes: A determination submodule, configured to determine at least one data acquisition address and at least one data writing address based on the functional behavior information and the data memory access request; A first request generation submodule, configured to generate at least one data acquisition request based on the data acquisition address and output the data acquisition request; The second request generation submodule is used to generate at least one data write request based on the data write address and output the data write request.

[0063] Optionally, the device further comprises: The execution module is used for cyclically executing the second subroutine to obtain a plurality of response results of the second subroutine.

[0064] Optionally, the generating module includes: A reference submodule, configured to generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified; The result generation submodule is used to generate the verification result of the cache to be verified based on the response result of the second subprogram and the reference response result.

[0065] Optionally, the data memory access request includes at least a processor core identifier and a memory access address.

[0066] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0067] In summary, the cache verification device provided by the embodiment of the present invention constructs a first subroutine; the first subroutine is used to generate a data access request; based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information; and the verification result of the cache to be verified is generated based on the response result of the second subroutine. In this way, the embodiment of the present invention can realize hardware modeling of the cache to be verified by constructing the second subroutine based on the functional behavior information of the cache to be verified. At the same time, by constructing the first subroutine for generating a data access request, the cache to be verified can be verified by the first subroutine and the second subroutine, and the verification result can be obtained according to the response result of the second subroutine. The constraints on the test can be implemented according to different data access requests, different cache verification requirements can be met, and the effect of cache verification can be improved. At the same time, compared with the method of building a hardware circuit for verification, the cache verification method provided by the embodiment of the present invention only needs to construct the second subroutine according to the functional behavior information, which greatly improves the efficiency of cache verification.

[0068] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0069] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0070] Regarding the cache verification device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0071] An embodiment of the present invention further provides an electronic device, comprising: a processor and a memory for storing processor executable instructions, wherein the processor is configured to execute the above cache verification method.

[0072] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the cache verification method of the aforementioned embodiment.

[0073] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0074] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmble Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0075] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0076] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable ReadOnly), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0077] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The cache validation method shown.

[0078] The present invention also provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute Figure 1 The cache validation method shown.

[0079] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned cache verification method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0080] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0081] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0082] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0083] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0084] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0086] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0087] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0088] It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0089] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0090] The above is a detailed introduction to a cache verification method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A cache verification method, characterized in that: The method comprises: Constructing a first subroutine; wherein the first subroutine is used to generate a data access request; Based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data memory access request and respond to the data memory access request based on the functional behavior information; the functional behavior information is used to characterize the cache consistency protocol implemented by the cache to be verified; Based on the response result of the second subroutine, a verification result of the cache to be verified is generated.

2. The method according to claim 1, characterized in that The responding to the data access request based on the functional behavior information includes: Determine at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request; generating at least one data acquisition request based on the data acquisition address and outputting the data acquisition request; At least one data write request is generated based on the data write address and the data write request is output.

3. The method according to claim 2, characterized in that The method further comprises: The second subroutine is executed cyclically to obtain a plurality of response results of the second subroutine.

4. The method according to claim 1, characterized in that: The step of generating the verification result of the cache to be verified based on the response result of the second subprogram includes: Generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified; Based on the response result of the second subroutine and the reference response result, a verification result of the cache to be verified is generated.

5. The method according to claim 1, characterized in that: The data memory access request includes at least a processor core identifier and a memory access address.

6. The method according to any one of claims 1 to 5, characterized in that: The first subroutine and the second subroutine are both constructed based on a high-level programming language.

7. A cache verification device, characterized in that: The device comprises: A first construction module is used to construct a first subprogram; the first subprogram is used to generate a data access request; A second construction module is used to construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is used to receive the data memory access request and respond to the data memory access request based on the functional behavior information; the functional behavior information is used to characterize the cache consistency protocol implemented by the cache to be verified; A generation module is used to generate a verification result of the cache to be verified based on the response result of the second subprogram.

8. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-6 when executing a program stored in a memory.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program, characterized in that When the computer program is executed by a computer, the method according to any one of claims 1 to 6 is implemented.

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