Bus monitor for AXI-BUS read transactions

Abstract

The embodiment of the invention discloses a bus monitor for AXI-BUS read transactions. According to one specific embodiment, the master device bus monitor comprises an error signal generating device and an output gating device, the master device bus monitor is used for coupling a master device to a bus, and the bus comprises a read address channel and a read data channel; the error signal generation device is coupled to the read address channel and the read data channel, and generates a main equipment exception signal in response to obtaining a read transaction from the read address channel and not obtaining a response to the read transaction from the read data channel within a preset time period; the output gating device is coupled with the read address channel and the read data channel; the output gating device responds to the received bypass signal and outputs the read transaction; and in response to the received main equipment abnormal signal, outputting a false signal of the read transaction, so that bus transmission can be completed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to chip technology, and more particularly to a bus monitor for monitoring communications on a bus of a chip. Background Art

[0002] The bus is a public communication trunk for transmitting information between various components of an information processing device. The bus includes a read data channel, a read address channel, a write address channel, a write data channel, and a write response channel. Among them, the read data channel may refer to a data bus, which provides a channel for data transmission from a slave device to a master device. A master device may refer to a device that has bus control during bus transmission. A slave device may refer to a device that cooperates with a master device to complete data transmission during a bus transmission cycle, and a slave device usually passively accepts commands from a master device. The read address channel may refer to an address bus, which provides a channel for transmitting information such as the address and length of a read transaction. A read transaction generally refers to the operation used from requesting the bus to completing the bus, which may include request operations, arbitration operations, address transmission, data transmission, and bus release.

[0003] As the number of integrated processors and peripherals in a chip increases, the bus becomes more and more complex. At present, when an error occurs during data transmission on the bus, the bus is usually reset by restarting the system.

[0004] However, when resetting the bus in the above manner, the following technical problems usually occur:

[0005] First, the operation status of the bus cannot be monitored in time, and the error cannot be located in time, resulting in the inability to quickly reset the bus with the error, which greatly prolongs the time required for bus reset;

[0006] Second, it is impossible to complete the transmission of virtual data and response signals when an error occurs, resulting in chain errors at the upstream and downstream ends, further extending the time required for bus reset. Summary of the invention

[0007] The content of this disclosure is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this disclosure is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.

[0008] Some embodiments of the present disclosure propose bus monitors, including a master bus monitor for a master device and a slave bus monitor for a slave device, to solve one or more of the technical problems mentioned in the above background technology section.

[0009] In a first aspect, some embodiments of the present disclosure provide a master device bus monitor, which includes: an error signal generating device, wherein: the above-mentioned master device bus monitor is used to couple the master device to a bus, wherein the above-mentioned bus includes a read address channel and a read data channel; the above-mentioned error signal generating device is coupled to the above-mentioned read address channel and the above-mentioned read data channel, and generates a master device abnormal signal in response to obtaining a read transaction from the above-mentioned read address channel and not obtaining a response to the above-mentioned read transaction from the read data channel within a preset time period.

[0010] In some embodiments, the master device bus monitor further includes: a monitoring signal generating device, wherein: the monitoring signal generating device is coupled to the read address channel and the read data channel, and generates a slave device not ready signal and a master device ready signal in response to obtaining the master device abnormal signal from the error signal generating device.

[0011] In some embodiments, the master device bus monitor further includes: an output enabling device, wherein: the output enabling device is coupled to the read address channel and the read data channel, and in response to obtaining the master device abnormal signal from the error signal generating device, sends the slave device not ready signal to the master device through the read address channel, and sends the master device ready signal to the slave device through the read data channel.

[0012] In some embodiments, the error signal generating device further: performs timing in response to the number of read transactions obtained from the read address channel being greater than the number of responses to the read transactions obtained from the read data channel; performs timing reset in response to the number of read transactions obtained from the address channel being equal to the number of responses to the read transactions obtained from the read data channel or responses to the read transactions obtained from the read data channel; and outputs the master device abnormality signal in response to the timing time being greater than the length of a preset time period.

[0013] In some embodiments, the error signal generating device includes a first counter, a second counter and a timer, wherein: the first counter is used to count the number of read transactions obtained from the read address channel; the second counter is used to count the number of responses to the read transactions obtained from the read data channel; the timer performs timing in response to the number counted by the first counter being greater than the number counted by the second counter; the error signal generating device resets the timer in response to the number counted by the first counter being equal to the number counted by the second counter or obtaining a response to the read transaction from the read data channel; and generates a master device abnormal signal in response to the timing time of the timer being greater than the length of the preset time period.

[0014] In some embodiments, the error signal generating device further: identifies the occurrence of a read transaction according to a read address valid signal in the read address channel; and obtains a response to the read transaction according to an end signal in the read data channel indicating the data to be read by the read transaction.

[0015] In some embodiments, the error signal generating device further obtains a response to the read transaction according to an end signal in the read data channel indicating the data to be read by the read transaction and a read data valid signal in the read data channel.

[0016] In some embodiments, the master device bus monitor further includes: a configuration device, wherein: the configuration device is used to provide an error enable signal to the error signal generating device, provide a reset signal to the error signal generating device and the monitoring signal generating device, and provide a bypass signal to the output selection device.

[0017] In some embodiments, the error signal generating device further: generates a master device abnormality signal in response to receiving the error enable signal, and outputs the master device abnormality signal; and resets the first counter, the second counter and the timer in response to receiving the reset signal.

[0018] In some embodiments, the output selection device further: in response to receiving the bypass signal and not receiving the monitoring enable signal, outputs the read transaction; in response to not receiving the bypass signal, the monitoring enable signal and the master device abnormal signal, outputs a false signal of the read transaction.

[0019] In some embodiments, the error signal generating device further outputs the master device abnormal signal in response to obtaining multiple read transactions from the read address channel and failing to obtain a response to any of the multiple read transactions from the read data channel within a predetermined time.

[0020] In some embodiments, the error signal generating device further includes a first counter, a second counter and a timer corresponding to each of a plurality of IDs used for read transactions, wherein: the first counter counts the number of read transactions with an ID corresponding to the first counter captured from the read address channel; the second counter counts the number of responses to the read transactions with an ID corresponding to the second counter obtained from the read data channel.

[0021] In some embodiments, in response to obtaining the above-mentioned master device abnormal signal from the above-mentioned error signal generating device and the value of the first counter corresponding to the first ID is different from the value of the second counter corresponding to the above-mentioned first ID, the above-mentioned monitoring signal generating device indicates the slave device not ready signal for the above-mentioned read address channel and the identification signal of the above-mentioned first ID to the above-mentioned master device; and, the above-mentioned monitoring signal generating device indicates the master device ready signal for the above-mentioned read data channel and the identification signal of the above-mentioned first ID to the above-mentioned slave device; wherein the above-mentioned first ID is any one of the above-mentioned multiple IDs.

[0022] In a second aspect, some embodiments of the present disclosure provide a slave device bus monitor, comprising: an error signal generating device, wherein: the above-mentioned slave device bus monitor is used to couple the slave device to a bus, wherein the above-mentioned bus includes a read address channel and a read data channel; the above-mentioned error signal generating device is coupled to the above-mentioned read address channel and the above-mentioned read data channel, and generates a slave device exception signal in response to obtaining a read transaction from the above-mentioned read address channel and not obtaining a response to the above-mentioned read transaction from the above-mentioned read data channel within a preset time period.

[0023] In some embodiments, the slave device bus monitor further includes: a memory and a monitoring signal generating device, wherein: the memory stores the data length to be read for the read transaction; the monitoring signal generating device is coupled to the read address channel and the read data channel, and in response to obtaining the slave device abnormal signal from the error signal generating device, obtains the data length to be read for the read transaction from the memory, transmits data of the amount of the first difference to the master device based on the first difference between the data length to be read for the read transaction and the data length already read for the read transaction, and indicates to the master device that the read transaction transmission is complete.

[0024] In some embodiments, the slave device bus monitor further includes: an output enabling device, wherein: the output enabling device is coupled to the read address channel and the read data channel; the output enabling device transmits the data of the first difference quantity transmitted by the monitoring signal generating device to the master device to the master device through the read data channel, and transmits the signal indicating the completion of the read transaction transmission by the monitoring signal generating device to the master device to the master device through the read data channel.

[0025] In some embodiments, the monitoring signal generating device further generates a slave device not ready signal in response to obtaining the slave device abnormal signal from the error signal generating device.

[0026] In some embodiments, the output selection device further sends the slave device not ready signal to the master device through the read address channel in response to obtaining the slave device abnormal signal from the error signal generating device.

[0027] In some embodiments, the error signal generating device further: performs timing in response to the number of read transactions obtained from the read address channel being greater than the number of responses to the read transactions obtained from the read data channel; performs timing reset in response to the number of read transactions obtained from the address channel being equal to the number of responses to the read transactions obtained from the read data channel or responses to the read transactions obtained from the read data channel; and outputs the slave device abnormality signal in response to the timing time being greater than the length of a preset time period.

[0028] In some embodiments, the error signal generating device includes a first counter, a second counter and a timer, wherein: the first counter is used to count the number of read transactions obtained from the read address channel; the second counter is used to count the number of responses to the read transactions obtained from the read data channel; the timer performs timing in response to the number counted by the first counter being greater than the number counted by the second counter; the error signal generating device resets the timer in response to the number counted by the first counter being equal to the number counted by the second counter or obtaining a response to the read transaction from the read data channel; and generates a slave device abnormality signal in response to the timing time of the timer being greater than the length of the preset time period.

[0029] In some embodiments, the error signal generating device further: identifies the occurrence of a read transaction according to a read address valid signal in the read address channel; and obtains a response to the read transaction according to an end signal in the read data channel indicating the data to be read by the read transaction.

[0030] In some embodiments, the error signal generating device further obtains a response to the read transaction according to an end signal in the read data channel indicating the data to be read by the read transaction and a read data valid signal in the read data channel.

[0031] In some embodiments, the slave device bus monitor further includes: a configuration device, wherein: the configuration device is used to provide an error enable signal to the error signal generating device, provide a reset signal to the error signal generating device and the monitoring signal generating device, and provide a bypass signal to the output selection device.

[0032] In some embodiments, the error signal generating device further: generates a slave device abnormality signal in response to receiving the error enable signal, and outputs the slave device abnormality signal; and resets the first counter, the second counter and the timer in response to receiving the reset signal.

[0033] In some embodiments, the output selection device further: in response to receiving the bypass signal and not receiving the monitoring enable signal, outputs the read transaction; in response to not receiving the bypass signal, the monitoring enable signal and the slave device abnormal signal, outputs a false signal of the read transaction.

[0034] In some embodiments, the error signal generating device further outputs the slave device abnormality signal in response to obtaining multiple read transactions from the read address channel and failing to obtain a response to any of the multiple read transactions from the read data channel within a preset time period.

[0035] In some embodiments, the error signal generating device further includes a first counter, a second counter and a timer corresponding to each of a plurality of IDs for read transactions, wherein: the first counter counts the number of read transactions with an ID corresponding to the first counter captured from the read address channel; the second counter counts the number of responses to the read transactions with an ID corresponding to the second counter obtained from the read data channel.

[0036] In some embodiments, in response to obtaining the above-mentioned slave device abnormal signal from the above-mentioned error signal generating device and the value of the first counter corresponding to the first ID is different from the value of the second counter corresponding to the above-mentioned first ID, the above-mentioned monitoring signal generating device indicates the slave device not ready signal for the above-mentioned read address channel and the identification signal of the above-mentioned first ID to the above-mentioned master device; wherein the above-mentioned first ID is any one of the above-mentioned multiple IDs.

[0037] In some embodiments, the monitoring signal generating device also responds to obtaining the slave device exception signal from the error signal generating device. For each first ID of the read transaction, if the value of the first counter corresponding to the first ID is different from the value of the second counter corresponding to the first ID, the data to be read by the read transaction corresponding to the first ID is transmitted to the slave device until the value of the first counter corresponding to the first ID is the same as the value of the second counter corresponding to the first ID.

[0038] In some embodiments, the monitoring signal generating device includes a counter, and the counter of the monitoring signal generating device counts the length of data read for the read transaction captured from the read data channel, wherein the monitoring signal generating device captures the data read for the read transaction based on the read data valid signal of the read data channel and / or the slave device ready signal.

[0039] In a third aspect, some embodiments of the present disclosure provide an electronic system comprising: a master device, a slave device, a bus, a master device bus monitor and a slave device bus monitor, wherein: the above-mentioned bus provides a read data channel and a read address channel; the above-mentioned master device bus monitor couples the above-mentioned master device to the bus; the above-mentioned slave device bus monitor couples the above-mentioned slave device to the bus; the above-mentioned master device bus monitor is a bus monitor according to any one of claims 1-5; the above-mentioned slave device bus monitor is a bus monitor according to any one of claims 6-9.

[0040] In some embodiments, the electronic system further includes: a processor, wherein: in response to receiving a master device exception signal output by the master device bus monitor and / or a slave device exception signal output by the slave device bus monitor, the master device bus monitor and / or the slave device bus monitor are reset.

[0041] In some embodiments, the master device bus monitor further sends the generated master device abnormal signal to the slave device bus monitor.

[0042] In some embodiments, the error signal generating device of the slave device bus monitor further generates a slave device abnormal signal in response to receiving the master device abnormal signal.

[0043] In some embodiments, the slave device bus monitor further sends the generated slave device abnormality signal to the master device bus monitor.

[0044] In some embodiments, the error signal generating device of the master device bus monitor further generates a master device abnormal signal in response to receiving the slave device abnormal signal.

[0045] The above-mentioned embodiments of the present disclosure have the following beneficial effects: through the master device bus monitor and the slave device bus monitor of some embodiments of the present disclosure, the operation state of the bus can be monitored in time and the error can be located in time. Furthermore, the bus with an error can be quickly reset, reducing the time required for reset. Specifically, the reason for the long reset time and low reset efficiency of the bus is that the operation state of the bus cannot be monitored in time, the error cannot be located in time, and the bus with an error cannot be quickly reset. Based on this, the master device bus monitor and the slave device bus monitor of some embodiments of the present disclosure complete the monitoring of the operation state of the bus by adopting an error signal generating device. First, the master device abnormal signal can be generated by monitoring the acquisition of a read transaction from the read address channel and the failure to obtain a response to the read transaction from the read data channel within a preset time period. Thus, the monitoring of the operation state of the bus can be completed. Then, according to the read address valid signal in the above-mentioned read address channel, the occurrence of the read transaction is identified, and according to the end signal of the data to be read by the read transaction in the above-mentioned read data channel, the response of the above-mentioned read transaction is obtained. Thus, it can be determined whether the response to the read transaction is completed, thereby determining whether the bus is abnormal. Then, the error signal generating device also generates a master device abnormal signal in response to receiving the error enable signal, and outputs the master device abnormal signal, thereby facilitating the outside world to reset the bus with an error in time according to the master device abnormal signal, thus achieving the technical effect of reducing the reset time. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0047] Figure 1A is a schematic diagram showing a structure of a master device bus monitor provided by the present disclosure;

[0048] Figure 1B is another structural schematic diagram showing a master device bus monitor provided by the present disclosure;

[0049] Figure 2 is based on Figure 1B A schematic structural diagram of an error signal generating device of a disclosed master device bus monitor;

[0050] Figure 3 is based on Figure 1B A schematic structural diagram of a monitoring signal generating device of a disclosed master device bus monitor;

[0051] Figure 4 is based on Figure 1B A schematic diagram of the structure of an output gating device of a disclosed master device bus monitor;

[0052] Figure 5 is based on Figure 1A A schematic structural diagram of an error signal generating device of a disclosed master device bus monitor;

[0053] Figure 6 is based on Figure 1A A schematic structural diagram of a monitoring signal generating device of a disclosed master device bus monitor;

[0054] Fig. 7A is a schematic diagram showing a structure of a slave device bus monitor provided by the present disclosure;

[0055] Figure 7B is another structural schematic diagram showing a slave device bus monitor provided by the present disclosure;

[0056] Figure 8 is based on Fig. 7A A schematic structural diagram of an error signal generating device of a disclosed slave device bus monitor;

[0057] Fig. 9 is based on Fig. 7A A schematic structural diagram of a monitoring signal generating device of a disclosed slave device bus monitor;

[0058] Fig.10 It is a schematic diagram of the relationship between the master device and the slave device of the present invention. DETAILED DESCRIPTION

[0059] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0060] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0061] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0062] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0063] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0064] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0065] Please refer to Figure 1A , which shows a structural schematic diagram of a master device bus monitor provided by the present disclosure. Figure 1A A master monitor is shown coupled to a bus master for monitoring the bus for read transactions. Figure 1A As shown, the master device bus monitor 100 of this embodiment may include: an error signal generating device 1, a monitoring signal generating device 2, an output gating device 3 and a configuration device 4. The error signal generating device 1, the monitoring signal generating device 2 and the output gating device 3 are all coupled to the configuration device 4. The error signal generating device 1 is coupled to the monitoring signal generating device 2, and the monitoring signal generating device 2 is coupled to the output gating device 3. The error signal generating device 1, the monitoring signal generating device 2 and the output gating device 3 are all capable of receiving bus input signals. The output gating device 3 outputs signals to the bus.

[0066] refer to Figure 1B , which shows a schematic diagram of the structure of a master device bus provided by another embodiment of the present disclosure. Figure 1B A master monitor is shown coupled to a bus master for monitoring write transactions on the bus. Figure 1B As shown, the master device bus monitor 150 of this embodiment includes: an error signal generating device 5, a monitoring signal generating device 6, an output gating device 7, a configuration device 8 and a memory 9. The error signal generating device 5, the monitoring signal generating device 6 and the output gating device 7 are all coupled to the configuration device 8. The error signal generating device 5 is coupled to the monitoring signal generating device 6, and the monitoring signal generating device 6 is coupled to the output gating device 7. The monitoring signal generating device 6 and the output gating device 7 are all coupled to the FIFO controller 9. The error signal generating device 5, the monitoring signal generating device 6 and the output gating device 7 are all capable of receiving bus input signals. The output gating device 7 outputs signals to the bus.

[0067] In some embodiments, the master device bus monitor is used to couple the master device to the bus. The bus may be an internal structure, and may be a common channel for the CPU (Central Processing Unit), memory, input, and output devices to transmit information. The bus includes a read data channel, a read address channel, a write address channel, a write data channel, and a write response channel. The read data channel is a channel for transmitting data between the slave device and the master device during the processing of a read transaction; the write data channel is a channel for transmitting data between the slave device and the master device during the processing of a write transaction. Here, the master device may refer to a device with bus control during bus transmission. Here, the slave device may refer to a device that cooperates with the master device to complete data transmission during the bus transmission cycle, and the slave device usually passively accepts commands sent by the master device. The read address channel may be a channel that provides the slave device with information such as the address and length of the transmission read transaction during the processing of the read transaction. The write address channel is a channel that provides the slave device with information such as the address and length of the data related to the transmission write transaction during the processing of the write transaction. The write response channel is a channel that indicates the readiness state of data transmission during the processing of the write transaction. Here, a read transaction generally refers to the operation from the master device requesting the slave device to read data to the slave device feeding back a read response message. For details, please refer to the definition of read transactions in the AXI (Advanced eXtensible Interface) bus protocol, which will not be expanded here. In practice, please refer to Table 1 and also refer to Figure 1A , Figure 1B , showing some signal interpretations of the master bus monitor of the present disclosure:

[0068] Table 1

[0069] Logo Interpretation Logo Interpretation Axi AXI Bus Master-err Master device abnormal signal in / i enter Moniter-en Monitor enable signal aw Write Address fake-signal False Signals w Writing Data out / o Output b Write Response Error-en Error enable signal ar Read Address Clear-en Reset enable signal r Read Data Bypass-en Bypass enable signal

[0070] As an example, Figure 1AThe Axi-in shown in the figure can represent the input signal of the bus, and Axi-in includes Axi-ar-i and Axi-ri. Among them, Axi-ar-i can represent the input signal of the read address channel of the bus, and Axi-ri can represent the input signal of the read data channel of the bus; Master-err can represent the signal of the abnormal master device; Moniter-en represents the enable signal of the monitor; Axi-fake-signal can represent the false signal of the read transaction generated by the master device bus monitor; Axi-out can represent the output signal of the bus, and Axi-out includes Axi-ar-o and Axi-ro, among which Axi-ar-o can represent the output signal of the read address channel of the bus, and Axi-ro can represent the output signal of the read data channel of the bus; Error-en can represent the signal indicating the abnormal state of the master device; Clear-en can represent the reset enable signal; Bypass-en can represent the bypass enable signal.

[0071] As another example, Figure 1B The Axi-in shown in the figure can represent the input signal of the bus, and Axi-in includes: Axi-aw-i, Axi-wi and Axi-bi. Among them, Axi-aw-i can represent the input signal of the write address channel of the bus, Axi-wi can represent the input signal of the write data channel of the bus, and Axi-bi can represent the input signal of the write response channel of the bus; Master-err can represent the signal of the abnormal master device; Moniter-en represents the enable signal of the monitor; Axi-fake-signal can represent the false signal of the write transaction generated by the master device bus monitor; Axi-out can represent the output signal of the bus, and Axi-out includes Axi-aw-o, Axi-wo and Axi-bo. Among them, Axi-aw-o represents the output signal of the write address channel of the bus, Axi-wo can represent the output signal of the write data channel of the bus, and Axi-bo can represent the output signal of the write response channel of the bus; Error-en can represent the signal indicating the abnormal state of the master device; Clear-en can represent the reset enable signal; Bypass-en can represent the bypass enable signal.

[0072] Optionally, the signal in the embodiment of the present disclosure is a level signal, and the level value includes a high level and a low level. For example, the high level is "1" and the low level is "0". In some embodiments, when Error-en is at a high level, the error signal generating device 1 is informed that the master device has an abnormality; when Clear-en is at a high level, the error signal generating device 1 and the monitoring signal generating device 2 are reset / reset; when Bypass-en is at a high level, it indicates that the master device bus monitor 100 works in bypass mode. In bypass mode, the master device bus monitor 100 does not monitor the input signal of the master device / bus. Even if the master device is abnormal, it only transmits the input signal of the master device / bus; when Monitor-en is at a high level, it indicates that the master device bus monitor 100 works in supervision mode. In supervision mode, the master device bus monitor 100 monitors the input signal of the master device / bus in real time, and when the master device is abnormal or the data transmission is abnormal, it takes over the bus and generates a false signal to smoothly complete the data transmission. Optionally, Moniter-en and Bypass-en are usually not at a high level or a low level at the same time. If they are at a high level at the same time, the master device bus monitor 100 works in the supervisory mode; if they are at a low level at the same time, the master device bus monitor 100 works in the bypass mode. In another embodiment, Moniter-en and Bypass-en are at a high level or a low level at the same time, the master device bus monitor 100 works in the bypass mode. For another example, when Master-err is at a high level, it indicates to the error generating device that the current master device is abnormal.

[0073] Optionally, when Error-en is at a low level, the error signal generating device 1 is not aware of an abnormality in the master device; when Clear-en is at a low level, the error signal generating device 1 and the monitoring signal generating device 2 are not reset; when Bypass-en is at a low level, the master device bus monitor 100 is not instructed to operate in bypass mode, and the master device bus monitor 100 only monitors the input signal of the master device / bus; when Moniter-en is at a low level, the master device bus monitor 100 is not instructed to operate in supervision mode.

[0074] It can be understood that the working states of various signals in the master device bus monitor 150 at different levels can refer to the description of the master device bus monitor 100 mentioned above.

[0075] In some embodiments, the error signal generating device 1 can be coupled to the above-mentioned read address channel and the above-mentioned read data channel, and generate a master device abnormality signal in response to obtaining a read transaction from the above-mentioned read address channel and not obtaining a response to the above-mentioned read transaction from the read data channel within a preset time period. Here, the master device abnormality signal indicates that the data transmission of the bus is abnormal and the abnormality is on the master device side. Here, the preset time period can be a pre-set time period from obtaining a read transaction valid signal from the read data channel to obtaining a response signal to the read transaction valid signal. Here, the preset time period can be configured according to demand, for example, 1ms-1s. It should be understood that the above-mentioned preset time period can be a time period indicating that the response to the above-mentioned read transaction is limited, rather than a time period indicating the generation of a master device abnormality signal.

[0076] In some embodiments, the monitoring signal generating device 2 can be coupled to the above-mentioned read address channel and the above-mentioned read data channel, and generate a slave device not ready signal and a master device ready signal in response to obtaining the above-mentioned master device abnormal signal from the above-mentioned error signal generating device 1. Here, the slave device not ready signal indicates to the master device that the slave device is not ready and temporarily suspends the sending of the read transaction. Here, the master device ready signal indicates to the slave device that the master device is ready.

[0077] In some embodiments, the output selection device 3 can be coupled to the above-mentioned read address channel and the above-mentioned read data channel, and in response to obtaining the above-mentioned master device abnormal signal from the above-mentioned error signal generating device 1, the above-mentioned slave device not ready signal is sent to the above-mentioned master device through the above-mentioned read address channel, and the above-mentioned master device ready signal is sent to the slave device through the above-mentioned read data channel.

[0078] In some embodiments, the configuration device 4 can be used to provide an error enable signal to the error signal generating device 1 , provide a reset signal to the error signal generating device 1 and the monitoring signal generating device 2 , and provide a bypass signal to the output enabling device 3 .

[0079] In some embodiments, Figure 2 As shown, the error signal generating device 5 is used to generate a master device abnormality signal. In practice, the error signal generating device 5 can receive an externally input error enable signal to mark that the current master device has an abnormality, or can be judged by counting the various counters included in the error signal generating device 5. The error signal generating device 5 may include a first counter 201, a second counter 202, a third counter 203 and a timer 204. Among them, the first counter 201, the second counter 202 and the third counter 203 are all coupled to the timer 204.

[0080] In practice, the first counter 201 can be used to record the number of write transactions (write commands) received by the error generating device 5 in the write address channel of the bus. Here, in the bus protocol, when the write address signal is at a high level, it indicates that an address appears in the write address channel, and also represents the occurrence of a write transaction. For example, when the write address signal and the write address ready signal are valid at the same time, it indicates that a write command is received, and the count of the first counter 201 is increased by 1.

[0081] In practice, the second counter 202 can be used to record the number of write data transmission commands in the write data channel that have been completed by the error generating device 5. For example, when the write data signal, the write data ready signal and the last data written are valid at the same time, it indicates that a burst data transmission is completed, and the count of the second counter 202 is increased by 1.

[0082] In practice, the third counter 203 can be used to record the number of completed responses to burst data in the write response channel. For example, when the write response signal and the write response ready signal are valid at the same time, it means that a write response is completed, and the count of the third counter 203 is increased by 1.

[0083] In practice, the error signal generating device 5 also includes a first counter, a second counter, a third counter and a timer corresponding to each of the multiple IDs for write transactions, wherein: the first counter counts the number of write transactions with an ID corresponding to the first counter captured from the above-mentioned write address channel; the second counter counts the number of responses to write transactions with an ID corresponding to the second counter obtained from the above-mentioned write data channel; the third counter counts the number of responses completed to write transactions with an ID corresponding to the third counter obtained from the above-mentioned write response channel. Here, ID represents the signal identifier of the write transaction. For example, in a write transaction processing flow, the write data ID must match the write data ID, and the write response ID must also match the write data ID. In practice, the data bit width of the first counter, the second counter and the third counter can be set to indicate the outstanding number of buses (the maximum number of concurrent bus requests) to ensure that when counting, the count value of the first counter is less than the count value of the second counter and the third counter. Here, the number bit width can be used to represent the outstanding counter bit width. For example, outstanding = 7, 7 is represented as 3'b111 in binary, that is, a 3-bit binary number is required to represent it, and the bit width is 3. For example, the timer starts timing when the value counted by the first counter is equal to the value counted by the second counter and the value of the third counter is not equal to the value of the first counter, and the write response signal is determined to be invalid. For example, the timer starts timing when the value counted by the second counter is not equal to the value counted by the first counter, and the write response signal is determined to be invalid. After the timing reaches a predetermined threshold, the error signal generating device 5 generates a master device abnormality signal.

[0084] In some embodiments, Figure 3 As shown, the monitoring signal generating device 6 can be coupled to the write address channel, the write data channel and the write response channel, and in response to obtaining the master device abnormal signal from the above-mentioned error signal generating device 5, obtain the data length to be written by the write transaction from the FIFO controller 9, and transmit the data of the first difference to the above-mentioned master device according to the first difference between the transaction length to be written by the above-mentioned write transaction and the data length already written for the above-mentioned write transaction, and transmit the data of the first difference to the above-mentioned master device, and indicate to the above-mentioned master device that the above-mentioned write transaction transmission is completed. The monitoring signal generating device 6 can include a first counter 301, a second counter 302, a third counter 303, a fourth counter 304, a FIFO selector 305, a signal marker 306, a bus false signal generator 307, an output selector 308, a state machine 309 and an enable signal marker 310. Among them, the first counter 301, the second counter 302, the third counter 303 and the fourth counter 304 are all coupled to the bus false signal generator 307. The first counter 301 and the second counter 302 are both coupled to the FIFO selector 305. The output selector 308 and the state machine 309 are coupled to the bus false signal generator 307. The first counter 301, the second counter 302, the third counter 303, the fourth counter 304 and the FIFO selector 305 are coupled to the signal marker 306.

[0085] In practice, please refer to Table 2, which shows some signal interpretations of the monitoring signal generating device 6:

[0086] Table 2

[0087]

[0088]

[0089] As an example, Figure 3Axi-aw-i shown in the figure can represent the input signal of the write address channel of the bus; Axi-bi can represent the input signal of the write response channel of the bus; Axi-wi can represent the input signal of the write data channel of the bus; Master-error-en can represent the enable signal indicating the error of the master device; wr-monitor-en can represent the signal that the device is ready to receive data and allows the release of data; Axi-aw-f can represent the false signal of the write address channel of the input bus; Axi-wf can represent the false signal of the write data channel of the input bus; Axi-bf can represent the false signal of the write response channel of the input bus; w-valid-f can represent that both the write data false signal and the write select false signal can be used; w-wstrb-f can represent the false signal of the write data channel, and each bit corresponds to a byte of write data.

[0090] Understandably, Figure 3 The input of each signal in the diagram only indicates the device through which the signal passes, rather than a specific processing flow.

[0091] In practice, the first counter 301 can be used to record the number of write transactions received by the monitoring signal generating device 6. For example, when an address appears in the write address channel and indicates to the slave device that the master device is ready to receive a control signal associated with the address, indicating that a write transaction is received, the first counter 301 counts up by 1.

[0092] In practice, the second counter 302 can be used to record the number of write data transfers that the monitoring signal generating device 6 has completed. For example, when the master device abnormal signal is invalid, and the write data valid signal, the write data ready signal and the last data written in the write data channel are valid at the same time, it indicates that a data transfer is completed, and the second counter 302 counts up by 1. For example, when the monitoring signal generating device 6 has received the master device abnormal signal, the slave device is ready to receive data and the signal allowing the release of data is valid, and the write data false signal, the write data false ready signal and the last false data written are valid at the same time, it indicates that a data transfer is completed, and the second counter 302 counts up by 1.

[0093] In practice, the third counter 303 can be used to record the number of write responses that the monitoring signal generating device 6 has completed. For example, when the master device abnormal signal is invalid, and the write response signal and the write response ready signal in the write response channel are valid at the same time, it indicates that a response transmission of a write data is completed, and the third counter 303 counts plus 1. When the monitoring signal generating device 6 has received the master device abnormal signal, the slave device is ready to receive data and the signal allowing the release of data is valid, and the write response false signal and the write response false ready signal are valid at the same time, it indicates that a write response is completed, and the third counter 303 counts plus 1. In practice, the data bit width of the first counter, the second counter and the third counter can be set to the outstanding number of bit widths of the bus to ensure that when counting, the count value of the first counter is less than the count value of the second counter and the third counter.

[0094] In practice, the fourth counter 304 is used to record the number of burst data that has been sent. Here, a burst of data (burst) can include multiple data, and the number of data in the burst of data is determined by the signal length. For example, when the master device abnormal signal is invalid, and the write data valid signal and the write data ready signal are valid at the same time, it indicates that a data transmission is completed, and the fourth counter 304 counts plus 1. For example, when the write data valid signal, the write data ready signal and the last data written are valid at the same time, it indicates that a burst of data transmission is completed, and the fourth counter 304 counts zero. For example, when the master device abnormal signal is valid, and the write data false valid signal and the write data false ready signal are valid at the same time, it indicates that a data transmission is completed, and the fourth counter 304 counts plus 1; when the write data false valid signal, the write data false ready signal and the last false data written are valid at the same time, it indicates that a burst of data transmission is completed, and the fourth counter 304 counts zero.

[0095] In practice, when the master device abnormal signal is at a high level, it indicates that the master device is abnormal. At this time, the signal marker (first_handle_flag) is pulled high to mark the first command processing after the master device abnormal signal is at a high level. When the first write data false valid signal, the write data false ready signal and the last false data written are valid at the same time during the period when the signal marker is maintained at a high level, it indicates that the first write data transmission after the master device abnormal signal is at a high level is completed.

[0096] In practice, the FIFO selector 305 is a selector for selecting which FIFO memory in the FIFO memory group needs to be taken out for processing at this time. For example, when the master device does not have an abnormality, the FIFO selector 305 takes the current processing ID, that is, the write data ID when the write data valid signal and the write data ready signal are valid. When the signal marker 306 is at a high level, there are two possible situations. One is that the last burst data transmission is completed and the current burst data transmission has not yet started. At this time, the fourth counter 304 is 0. At this time, the second counter 302 and the first counter 301 are compared from ID0 to see if they are equal. If they are not equal, it proves that the ID still has commanded write data that has not been sent out. The IDs need to be processed one by one from small to large. The value of the FIFO selector 305 is the highest priority ID value to be processed; the other situation is that the current burst data transmission stage has been entered, and the fourth counter 304 is not 0. At this time, the current burst data transmission needs to be completed first. Therefore, during the signal marker 306, the FIFO selector 305 takes the memory selection value before the abnormal situation is sent. After the signal marker 306 is pulled down from high, the ID numbers are processed one by one from small to large, and the value taken by the FIFO selector 305 is the ID value with the highest priority to be processed.

[0097] In practice, the bus false signal generator 307 needs to lower the write address false ready signal during the period when the master device abnormal signal is at a high level, so as to prevent the master device from sending signals outward; at the same time, the write address ID, write address length, write address size and write address address read from the FIFO controller 9 are assigned to the corresponding false signal. For the write data channel, the write data false ID can read the write address ID from the memory; the write data false signal is assigned to 0; the output selector 308 can generate a false signal for the write data channel to ensure that each bit corresponds to a byte of write data. When the count of the fourth counter 304 is equal to the write address false length, the signal of the last false data written is pulled high; the state machine 308 can control the write data false signal and the write selection false signal. For the write response channel, the write response false signal can be set to an abnormal state, and the write response false ready signal can be continuously pulled high. Finally, when the count of the third counter of all IDs is equal to the count of the first counter, it indicates that the processing of the abnormal signal of the master device is completed, and the signal generated by the enable signal marker 310 is pulled high to indicate that the master device is ready to receive data and allow the release of data, and the reset signal of the external input is received to reset the counter, state machine and signal marker.

[0098] In some embodiments, see Figure 4The output selection device 7 can be coupled to the write address channel and the write data channel, and in response to obtaining the master device abnormal signal from the error signal generating device 5, the slave device not ready signal is sent to the master device through the write address channel, and the master device ready signal is sent to the slave device through the write data channel. The output selection device 7 also outputs the write transaction in response to receiving the bypass signal and not receiving the monitoring enable signal; and outputs the false signal of the write transaction in response to not receiving the bypass signal, the monitoring enable signal and the master device abnormal signal.

[0099] In some embodiments, the configuration device 8 can be used to provide an error enable signal to the error signal generating device 5 , provide a reset signal to the error signal generating device 5 and the monitoring signal generating device 6 , and provide a bypass signal to the output enabling device 7 .

[0100] In some embodiments, the FIFO controller 9 may include multiple FIFO memories and FIFO controllers. For example, multiple FIFO storage modules can cache the write address channel ID, write address channel size, write address channel length and write address channel address contained in the bus write transaction. The number of FIFO memories is equal to the number of IDs used by the master device, and the depth of the FIFO memory depends on the outstanding capability of each ID. The depth is set to be equal to the outstanding to ensure that the stored information does not overflow. The outstanding capability is the ability to directly initiate the next action without receiving the previous write response. For example, outstangding = 5, that is, up to 5 write responses can be directly initiated without receiving a reply, but if no reply is received, the 6th action cannot be initiated.

[0101] The above-mentioned embodiments of the present disclosure have the following beneficial effects: through the master device bus monitor of some embodiments of the present disclosure, the operation state of the bus can be monitored in time and the error can be located in time. Furthermore, the bus with an error can be quickly reset, reducing the time required for reset. Specifically, the reason for the long reset time and low reset efficiency of the bus is that the operation state of the bus cannot be monitored in time, the error cannot be located in time, and the bus with an error cannot be quickly reset. Based on this, the master device bus monitor and the slave device bus monitor of some embodiments of the present disclosure complete the monitoring of the operation state of the bus by adopting an error signal generating device. First, the master device abnormal signal can be generated by monitoring the acquisition of a read transaction from the read address channel and the failure to obtain a response to the read transaction from the read data channel within a preset time period. Thus, the monitoring of the operation state of the bus can be completed. Then, according to the read address valid signal in the above-mentioned read address channel, the occurrence of the read transaction is identified, and according to the end signal of the data to be read by the read transaction in the above-mentioned read data channel, the response of the above-mentioned read transaction is obtained. Thus, it can be determined whether the response to the read transaction is completed, thereby determining whether the bus is abnormal. Then, the error signal generating device also generates a master device abnormal signal in response to receiving the error enable signal, and outputs the master device abnormal signal, thereby facilitating the outside world to reset the bus with an error in time according to the master device abnormal signal, thus achieving the technical effect of reducing the reset time.

[0102] Continue to refer Figure 5 , which shows a structural schematic diagram of the error signal generating device 1 of the master device bus monitor provided by the present disclosure. Figure 5 As shown, the error signal generating device 1 of this embodiment may include: a first counter 501, a second counter 502, a timer 503 and an error signal generator 504. The first counter 501 and the second counter 502 are both coupled to the timer 503; the timer 503 is coupled to the error signal generator 504.

[0103] In some embodiments, the error signal generating device 1 may perform timing in response to the number of read transactions obtained from the above-mentioned read address channel being greater than the number of responses to read transactions obtained from the above-mentioned read data channel; perform timing reset in response to the number of read transactions obtained from the above-mentioned address channel being equal to the number of responses to read transactions obtained from the above-mentioned read data channel or the responses to read transactions obtained from the above-mentioned read data channel; and output the above-mentioned master device abnormality signal in response to the timing time being greater than the length of the preset time period. In practice, the preset time period can be configured as required, for example, 1ms-1s. In the bus protocol, when the read address valid signal is at a high level, it indicates that an address has appeared in the read address channel, indicating that a read transaction has occurred. It can be understood that Figure 5The input of each signal in the diagram only indicates the device through which the signal passes, rather than a specific processing flow. Specifically, Figure 5 The various signals in can be found in the description of Table 1. In practice, when the read address valid signal is at a high level, the first counter 501 counts the read transactions appearing from the above-mentioned read address channel. In practice, when the last data read and the read data valid signal are valid at the same time, the second counter 502 counts the number of responses to the read transactions appearing in the read data channel. In practice, the timer 503 starts timing when the counts of the first counter 501 and the second counter 502 are not equal; the error signal generating device 1 controls the error signal generator 504 to generate a master device abnormal signal in response to the timing time of the above-mentioned timer 503 being greater than the length of the above-mentioned preset time period. The error signal generating device 1 also resets the timing of the above-mentioned timer 503 in response to the number counted by the above-mentioned first counter 501 being equal to the number counted by the above-mentioned second counter 502 or obtaining a response to the read transaction from the above-mentioned read data channel.

[0104] In some embodiments, the error signal generating device 1 can also identify the occurrence of a read transaction based on a read address valid signal in the read address channel; and obtain a response to the read transaction based on an end signal in the read data channel indicating the data to be read by the read transaction.

[0105] In some embodiments, the error signal generating device 1 further obtains a response to the read transaction according to an end signal in the read data channel indicating the data to be read by the read transaction and a read data valid signal in the read data channel.

[0106] In some embodiments, the error signal generating device 1 also generates a master device abnormality signal in response to receiving the above-mentioned error enable signal, and outputs the above-mentioned master device abnormality signal; in response to receiving the above-mentioned reset signal, the above-mentioned first counter 501, the above-mentioned second counter 502 and the above-mentioned timer 503 are reset.

[0107] In some embodiments, the error signal generating device 1 also includes a first counter, a second counter and a timer corresponding to each of a plurality of IDs used for read transactions, wherein: the first counter counts the number of read transactions with an ID corresponding to the first counter captured from the above-mentioned read address channel; the second counter counts the number of responses to the read transactions with an ID corresponding to the second counter obtained from the above-mentioned read data channel.

[0108] In some embodiments, in response to obtaining the above-mentioned master device abnormal signal from the above-mentioned error signal generating device 1 and the value of the first counter corresponding to the first ID is different from the value of the second counter corresponding to the above-mentioned first ID, the above-mentioned monitoring signal generating device indicates the slave device not ready signal for the above-mentioned read address channel and the identification signal of the above-mentioned first ID to the above-mentioned master device; and, the above-mentioned monitoring signal generating device indicates the master device ready signal for the above-mentioned read data channel and the identification signal of the above-mentioned first ID to the above-mentioned slave device; wherein the above-mentioned first ID is any one of the above-mentioned multiple IDs.

[0109] It should be understood that the error signal generating device 1 only needs to generate a read data ready signal during transmission. After the master device read monitor takes over, it first pulls down the read address ready signal to prevent the issuance of new commands, and then directly pulls up the read data ready signal to wait for all the first counters to be equal to the second counters, indicating that all exception processing is completed.

[0110] Continue to refer Figure 6 , which shows a structural schematic diagram of a monitoring signal generating device 2 of a master device bus monitor provided by the present disclosure. Figure 6 As shown, the monitoring signal generating device 2 of this embodiment may include: a first counter 601, a second counter 602, a bus false signal generator 603 and an enable signal marker 604. The first counter 601 and the second counter 602 are both coupled to the enable signal marker 604; the second counter 602 is coupled to the bus false signal generator 603.

[0111] In some embodiments, the monitoring signal generating device 2 can be coupled to the above-mentioned read address channel and the above-mentioned read data channel, and generate a slave device not ready signal and a master device ready signal in response to obtaining the above-mentioned master device abnormal signal from the above-mentioned error signal generating device.

[0112] In practice, the first counter 601 can be used to record the number of read transactions received by the monitoring signal generating device 2. For example, when an address appears in the read address channel and a control signal indicating to the slave device that the master device is ready to receive the control signal associated with the address appears, indicating that a read transaction is received, the first counter 601 counts up by 1.

[0113] In practice, the second counter 602 can be used to record the number of read data transfers that the monitoring signal generating device 2 has completed. For example, when the master device abnormal signal is invalid, and the read data valid signal, the read data ready signal and the last data read in the read data channel are valid at the same time, it indicates that a data transfer is completed, and the second counter 602 counts up by 1. For example, when the monitoring signal generating device 2 has received the master device abnormal signal, the slave device is ready to receive data and the signal allowing the release of data is valid, and the read data false signal, the read data false ready signal and the last false data read are valid at the same time, it indicates that a data transfer is completed, and the second counter 602 counts up by 1.

[0114] It is understood that the timing of using the bus false signal generator 603 and the enable signal marker 604 can be seen in Figure 3 Description of embodiments.

[0115] Please refer to Fig. 7A , which shows a schematic diagram of the structure of the slave device bus monitor provided by the present disclosure. Fig. 7A The slave bus monitor is coupled to the bus slave device to monitor the bus read transactions. Fig. 7A As shown, the slave device bus monitor 700 of this embodiment may include: an error signal generating device 7011, a monitoring signal generating device 7012, an output gating device 7013, a configuration device 7014 and a FIFO controller 7015. The error signal generating device 7011, the monitoring signal generating device 7012 and the output gating device 7013 are all coupled to the configuration device 7014. The error signal generating device 7011 is coupled to the monitoring signal generating device 7012, and the monitoring signal generating device 7012 is coupled to the output gating device 7013. The monitoring signal generating device 7012 and the output gating device 7013 are all coupled to the FIFO controller 7015. The error signal generating device 7011, the monitoring signal generating device 7012 and the output gating device 7013 are all capable of receiving a bus input signal. The output gating device 7013 outputs an output signal of the bus.

[0116] refer to Figure 7B , which shows another structural schematic diagram of the slave device bus monitor provided by the present disclosure. Figure 7B The slave bus monitor is coupled to the slave device to monitor the write transaction of the bus. Figure 7BAs shown, the slave device bus monitor 750 of this embodiment may include: an error signal generating device 7021, a monitoring signal generating device 7022, an output gating device 7023 and a configuration device 7024. The error signal generating device 7021, the monitoring signal generating device 7022 and the output gating device 7023 are all coupled to the configuration device 7024. The error signal generating device 7021 is coupled to the monitoring signal generating device 7022, and the monitoring signal generating device 7022 is coupled to the output gating device 7013. The error signal generating device 7021, the monitoring signal generating device 7022 and the output gating device 7023 are all capable of receiving a bus input signal. The output gating device 7023 outputs an output signal of the bus.

[0117] In some embodiments, the master device bus monitor is used to couple the master device to the bus. The bus may be an internal structure, and may be a common channel for the CPU (Central Processing Unit), memory, input, and output devices to transmit information. The bus includes a read data channel, a read address channel, a write address channel, a write data channel, and a write response channel. The read data channel is a channel for transmitting data between the slave device and the master device during the processing of a read transaction; the write data channel is a channel for transmitting data between the slave device and the master device during the processing of a write transaction. Here, the master device may refer to a device with bus control during bus transmission. Here, the slave device may refer to a device that cooperates with the master device to complete data transmission during the bus transmission cycle, and the slave device usually passively accepts commands sent by the master device. The read address channel may be a channel that provides the slave device with information such as the address and length of the transmission read transaction during the processing of the read transaction. The write address channel is a channel that provides the slave device with information such as the address and length of the data related to the transmission write transaction during the processing of the write transaction. The write response channel is a channel that indicates the readiness state of data transmission during the processing of the write transaction. Here, a read transaction generally refers to an operation from a master device requesting a slave device to read data to the slave device feeding back a read response message. For details, please refer to the definition of a read transaction in the AXI (Advanced eXtensible Interface) bus protocol, which will not be expanded here. In practice, please refer to Table 3, which shows some signal interpretations of the master device bus monitor disclosed in the present invention:

[0118] Table 3

[0119] Logo Interpretation Logo Interpretation Axi bus Slave-err Abnormal signal from the device in / i enter Moniter-en Monitor enable signal aw Write Address fake-signal / f False Signals w Writing Data out / o Output b Write Response Error-en Error enable signal ar Read Address Clear-en Reset signal r Read Data Bypass-en Bypass signal

[0120] As an example, Fig. 7AThe Axi-in shown in the figure can represent the input signal of the bus, and Axi-in includes Axi-ar-i and Axi-ri. Among them, Axi-ar-i can represent the input signal of the read address channel of the bus, and Axi-ri can represent the input signal of the read data channel of the bus; Slave-err can represent the abnormal signal of the slave device; Moniter-en represents the enable signal of the monitor; Axi-fake-signal can represent the false signal of the read transaction generated by the slave device bus monitor; Axi-out can represent the output signal of the bus, and Axi-out includes Axi-ar-o and Axi-ro. Among them, Axi-ar-o can represent the output signal of the read address channel of the bus, and Axi-ro can represent the output signal of the read data channel of the bus; Error-en can represent the signal indicating the abnormal state of the slave device; Clear-en can represent the reset enable signal; Bypass-en can represent the bypass enable signal.

[0121] As another example, Figure 7B The Axi-in shown in the figure can represent the input signal of the bus, and Axi-in includes: Axi-aw-i, Axi-wi and Axi-bi. Among them, Axi-aw-i can represent the input signal of the write address channel of the bus, Axi-wi can represent the input signal of the write data channel of the bus, and Axi-bi can represent the input signal of the write response channel of the bus; Slave-err can represent the abnormal signal of the slave device; Monitor-en represents the enable signal of the monitor; Axi-fake-signal can represent the false signal of the write transaction generated by the slave device bus monitor; Axi-out can represent the output signal of the bus, and Axi-out includes Axi-aw-o, Axi-wo and Axi-bo. Among them, Axi-aw-o represents the output signal of the write address channel of the bus, Axi-wo can represent the output signal of the write data channel of the bus, and Axi-bo can represent the output signal of the write response channel of the bus; Error-en can represent the signal indicating the abnormal state of the slave device; Clear-en can represent the reset enable signal; Bypass-en can represent the bypass enable signal.

[0122] Optionally, all signals in the embodiments of the present disclosure are level signals, and the level values ​​include high level and low level. For example, the high level is "1" and the low level is "0". In some embodiments, when Error-en is at a high level, the error signal generating device 7011 learns that an abnormality has occurred in the slave device; when Clear-en is at a high level, the error signal generating device 7011 and the monitoring signal generating device 7012 are reset / reset; when Bypass-en is at a high level, it indicates that the slave device bus monitor 700 works in bypass mode. In bypass mode, the slave device bus monitor 700 does not monitor the input signal of the slave device / bus. Even if an abnormality occurs in the slave device, only the input signal of the slave device / bus is transmitted; when Monitor-en is at a high level, it indicates that the slave device bus monitor 700 works in supervision mode. In supervision mode, the slave device read monitor 701 monitors the input signal of the slave device / bus in real time, and takes over the bus when the slave device is abnormal or the data transmission is abnormal, and generates a false signal, so that the data is smoothly transmitted. Optionally, Moniter-en and Bypass-en are usually not at a high level or a low level at the same time. If they are at a high level at the same time, the slave bus monitor 700 works in a supervisory mode; if they are at a low level at the same time, the slave bus monitor 700 works in a bypass mode. In another embodiment, Moniter-en and Bypass-en are at a high level or a low level at the same time, the slave bus monitor 700 works in a bypass mode. For another example, when Slave-err is at a high level, it indicates that the error generating device has an abnormality in the current slave device.

[0123] Optionally, when Error-en is at a low level, the error signal generating device 7011 is not aware of an abnormality in the slave device; when Clear-en is at a low level, the error signal generating device 7011 and the monitoring signal generating device 7012 are not reset / reset; when Bypass-en is at a low level, the slave device bus monitor 700 is not indicated to operate in bypass mode, and the slave device bus monitor 700 only monitors the input signal of the slave device / bus; when Moniter-en is at a low level, the slave device bus monitor 700 is not indicated to operate in supervision mode.

[0124] It can be understood that the working states of the various signals in the slave device bus monitor 750 at different levels can be found in the description of the slave device bus monitor 700 above.

[0125] In some embodiments, the error signal generating device 7011 can be coupled to the above-mentioned read address channel and the above-mentioned read data channel, and generate a slave device abnormality signal in response to obtaining a read transaction from the above-mentioned read address channel and not obtaining a response to the above-mentioned read transaction from the read data channel within a preset time period. Here, the slave device abnormality signal indicates that the data transmission of the bus is abnormal and the abnormality occurs on the slave device side. Here, the preset time period can be a pre-set time period from obtaining a read transaction valid signal from the read data channel to obtaining a response signal to the read transaction valid signal. Here, the preset time period can be configured according to demand, for example, 1ms-1s. It should be understood that the above-mentioned preset time period can be a time period indicating that the response to the above-mentioned read transaction is limited, rather than a time period indicating the generation of a master device abnormality signal.

[0126] In some embodiments, the error signal generating device 7011 further: performs timing in response to the number of read transactions obtained from the above-mentioned read address channel being greater than the number of responses to the read transactions obtained from the above-mentioned read data channel; performs timing reset in response to the number of read transactions obtained from the above-mentioned address channel being equal to the number of responses to the read transactions obtained from the above-mentioned read data channel or the responses to the read transactions obtained from the above-mentioned read data channel; and outputs the above-mentioned slave device abnormality signal in response to the timing time being greater than the length of the preset time period.

[0127] In some embodiments, Figure 8 As shown, the error signal generating device 7011 includes a first counter 801, a second counter 802, a timer 803 and an error signal generator 804. The first counter 801 and the second counter 802 are both coupled to the timer 803; the timer 803 is coupled to the error signal generator 804. The first counter is used to count the number of read transactions obtained from the read address channel; the second counter is used to count the number of responses to read transactions obtained from the read data channel; the timer performs timing in response to the number counted by the first counter being greater than the number counted by the second counter; the error signal generating device resets the timer in response to the number counted by the first counter being equal to the number counted by the second counter or obtaining a response to a read transaction from the read data channel; and generates a slave device abnormality signal in response to the timing time of the timer being greater than the length of the preset time period.

[0128] In practice, the first counter 801 can be used to record the number of read transactions (read commands) received by the error generating device 7011 in the read address channel of the bus. Here, in the bus protocol, when the read address signal is at a high level, it indicates that an address has appeared in the read address channel, and also represents the occurrence of a read transaction. For example, when the read address signal and the read address ready signal are both valid, it indicates that a read command has been received, and the count of the first counter 801 is increased by 1.

[0129] In practice, the second counter 802 can be used to record the number of read data transmission commands in the read data channel that have been completed by the error generating device 7011. For example, when the read data signal, the read data ready signal and the last data read are valid at the same time, it indicates that a data transmission is completed, and the count of the second counter 802 is increased by 1.

[0130] In practice, the timer 803 starts timing when the counts of the first counter 801 and the second counter 802 are not equal; the error signal generating device 7011 generates a master device abnormality signal in response to the timing time of the timer 803 being greater than the length of the preset time period. The error signal generating device 7011 also resets the timer 803 in response to the number of counts of the first counter 801 being equal to the number of counts of the second counter 802 or obtaining a response to a read transaction from the read data channel.

[0131] In some embodiments, the error signal generating device 7011 further: identifies the occurrence of a read transaction according to a read address valid signal in the read address channel; and obtains a response to the read transaction according to an end signal in the read data channel indicating the data to be read by the read transaction.

[0132] In some embodiments, the error signal generating device 7011 further obtains a response to the read transaction according to an end signal in the read data channel indicating the data to be read by the read transaction and a read data valid signal in the read data channel.

[0133] In some embodiments, the error signal generating device 7011 also: in response to receiving the above-mentioned error enable signal, controls the error signal generator 804 to generate a slave device abnormality signal, and outputs the above-mentioned slave device abnormality signal; in response to receiving the above-mentioned reset signal, resets the above-mentioned first counter, the above-mentioned second counter and the above-mentioned timer.

[0134] In some embodiments, the error signal generating device 7011 also outputs the above-mentioned slave device abnormal signal in response to obtaining multiple read transactions from the above-mentioned read address channel and not obtaining a response to any of the above-mentioned multiple read transactions from the above-mentioned read data channel within a preset time period.

[0135] In some embodiments, the error signal generating device 7011 also includes a first counter, a second counter and a timer corresponding to each of multiple IDs used for read transactions, wherein: the first counter counts the number of read transactions with the ID corresponding to the first counter captured from the read address channel; the second counter counts the number of responses to the read transactions with the ID corresponding to the second counter obtained from the read data channel.

[0136] In some embodiments, in response to obtaining the above-mentioned slave device abnormal signal from the above-mentioned error signal generating device 7011 and the value of the first counter corresponding to the first ID is different from the value of the second counter corresponding to the above-mentioned first ID, the above-mentioned monitoring signal generating device 7012 indicates the above-mentioned master device the slave device not ready signal for the above-mentioned read address channel and the identification signal of the above-mentioned first ID; wherein the above-mentioned first ID is any one of the above-mentioned multiple IDs.

[0137] It should be understood that the error signal generating device 7011 only needs to generate a read data ready signal during transmission. After the slave device read monitor takes over, the read address ready signal is first pulled low to prevent the issuance of new commands, and then the read data ready signal is directly pulled high to wait for all first counters to be equal to the second counters, indicating that all exception processing is completed. It can be understood that some usage opportunities of the first counter 801, the second counter 802 and the timer 803 can be seen in FIG. 1 ( Figure 1A and Figure 1B )- Figure 6 Description of embodiments.

[0138] In some embodiments, the FIFO controller 7015 stores the data length to be read for the read transaction; the monitoring signal generating device 7012 is coupled to the read address channel and the read data channel, and in response to obtaining the slave device abnormal signal from the error signal generating device 7011, obtains the data length to be read for the read transaction from the memory 7015, and transmits data of the amount of the first difference to the master device according to the first difference between the data length to be read for the read transaction and the data length already read for the read transaction, and indicates to the master device that the read transaction transmission is completed.

[0139] In practice, the FIFO controller 7015 uses a set of FIFOs to cache the write address channel id, write address channel size, write address channel len and write address channel addr in the axi write command. The number of FIFOs is equal to the number of ids used by the master device, and the FIFO depth depends on the outstanding capability of each id. The depth is set to be equal to the outstanding to ensure that the stored information does not overflow. The outstanding capability is the ability to directly initiate the next action without receiving a response to the previous action. For example, outstangding = 5, which means that up to 5 read and write actions can be directly initiated without receiving a reply, but if no reply is received, the 6th action cannot be initiated. The write enable of the FIFO is determined by the write address channel of the Axi original input information. When aw-valid-i and aw-ready-i are valid, it means that Axi-cmd is valid at this time. At this time, check aw-id and write aw-id (write address id), aw-size (write address size), aw-len (write address length) and aw-addr (write address address) to the corresponding fifo. Since the FIFO is not large in size, the FIFO built with registers is used, and the data delay is set to 0cycle, then the FIFO itself forms the head-out characteristic. Delay indicates the delay between data reading and initiating the read action when reading the FIFO. If it is 0, a read action is initiated, and the data corresponding to this read has been output. If it is 1, a read is initiated, and the read data will be output one cycle after the read enable is valid. Therefore, the data of the FIFO read data port can be used directly. After use, the fifo read enable is pulled high again to read out the used data, and the next data to be used is exposed to the r-data port (i.e., the head-out characteristic). It can be considered that the FIFO has a read port and a write port. Exposing it to the read port means that as long as no new read action is initiated, the value of the FIFO read data signal remains unchanged, and this value is the value of the next data to be used. The FIFO read enable is determined by the write data channel of the monitor's axi data. When w-valid-o, w-last-o, and w-ready-_o are high at the same time, it means that the write phase of a cmd data is completed. At this time, find the FIFO corresponding to w-id-o, pull up the read enable, and read out the old data. Here, valid indicates whether the data or control information in the channel is valid. For example, valid is valid when it is at a high level; it is invalid when it is at a low level. Here, ready indicates whether the device can receive data (whether it is ready). For example, ready is valid when it is at a high level; it is invalid when it is at a low level.

[0140] In practice, the FIFO controller 7015 receives the write data (write address id, write address size, write address len and write address address) corresponding to Axi-aw-i when the write address valid signal is at a high level and the write address ready is at a high level, and the write address channel id is equal to the FIFO id and the FIFO memory is not full.

[0141] In some embodiments, the monitoring signal generating device 7012 further generates a slave device not ready signal in response to obtaining the slave device abnormal signal from the error signal generating device 7011. Here, the slave device not ready signal indicates to the master device that the slave device is not ready and suspends sending the read transaction.

[0142] In some embodiments, the monitoring signal generating device 7012 is also responsive to obtaining the above-mentioned slave device exception signal from the above-mentioned error signal generating device 7011. For each first ID of the read transaction, if the value of the first counter corresponding to the above-mentioned first ID is different from the value of the second counter corresponding to the above-mentioned first ID, the data to be read by the read transaction corresponding to the above-mentioned first ID is transmitted to the above-mentioned slave device until the value of the first counter corresponding to the above-mentioned first ID is the same as the value of the second counter corresponding to the above-mentioned first ID.

[0143] In some embodiments, the monitoring signal generating device 7012 includes a counter, and the counter of the monitoring signal generating device 7012 counts the length of the data read for the read transaction captured from the read data channel. The monitoring signal generating device 7012 identifies and captures the data read for the read transaction according to the read data valid signal of the read data channel and / or the slave device ready signal.

[0144] In practice, such as Fig. 9As shown, the monitoring signal generating device 7012 may include a first counter 901, a second counter 902, a third counter 903, a FIFO selector 904, a signal marker 905, a bus false signal generator 906, an output gate 907, a state machine 908 and an enable signal marker 909. The monitoring signal generating device 7012 may include a first counter 901, a second counter 902, a third counter 903, a FIFO selector 904, a signal marker 905, a bus false signal generator 906, an output gate 907, a state machine 908 and an enable signal marker 909. The first counter 901, the second counter 902 and the third counter 903 are all coupled to the bus false signal generator 906. The first counter 901 and the second counter 902 are both coupled to the FIFO selector 904. The output gate 907 and the state machine 9089 are both coupled to the bus false signal generator 906. The second counter 902 , the third counter 903 , and the FIFO selector 904 are all coupled to a signal marker 905 .

[0145] In practice, the first counter 901 can be used to record the number of read transactions received by the monitoring signal generating device 7012. For example, when an address appears in the read address channel and indicates to the master device that the slave device is ready to receive a control signal associated with the address, indicating that a read transaction is received, the first counter 601 counts up by 1.

[0146] In practice, the second counter 902 can be used to record the number of read data transfers that the monitoring signal generating device 7012 has completed. For example, when the slave device abnormal signal is invalid, and the read data valid signal, the read data ready signal and the last data read in the read data channel are valid at the same time, it indicates that a data transfer is completed, and the second counter 902 counts up by 1. For example, when the monitoring signal generating device 7012 has received the slave device abnormal signal, the master device is ready to receive data and the signal allowing the release of data is valid, and the read data false signal, the read data false ready signal and the last false data read are valid at the same time, it indicates that a data transfer is completed, and the second counter 902 counts up by 1.

[0147] In practice, the third counter 903 is used to record the number of burst data that has been sent. Here, a burst of data (burst) can include multiple data, and the number of data in the burst of data is determined by the signal length. For example, when the slave device abnormal signal is invalid, and the read data valid signal and the read data ready signal are valid at the same time, it indicates that a data transmission is completed, and the third counter 903 counts plus 1. For example, when the read data valid signal, the read data ready signal and the last data read are valid at the same time, it indicates that a burst of data transmission is completed, and the third counter 903 counts zero. For example, when the slave device abnormal signal is valid, and the read data false valid signal and the read data false ready signal are valid at the same time, it indicates that a data transmission is completed, and the third counter 903 counts plus 1; when the read data false valid signal, the read data false ready signal and the last false data read are valid at the same time, it indicates that a burst of data transmission is completed, and the third counter 903 counts zero.

[0148] In practice, when the slave device abnormal signal is at a high level, it indicates that the slave device is abnormal. At this time, the signal marker (first_handle_flag) is pulled high to mark the first command processing after the slave device abnormal signal is at a high level. When the first read data false valid signal, the read data false ready signal and the last false data read are valid at the same time during the period when the signal marker 905 is maintained at a high level, it indicates that the first read data transmission after the slave device abnormal signal is at a high level is completed. It can be understood that the use timing of the FIFO selector 904, the signal marker 905, the bus false signal generator 906, the output selector 907, the state machine 908 and the enable signal marker 909 can be referred to. Figure 3 Description of embodiments.

[0149] In some embodiments, the output enabling device 7013 can be coupled to the read address channel and the read data channel; the output enabling device 7013 transmits the data of the first difference quantity transmitted by the monitoring signal generating device 7012 to the master device to the master device through the read data channel, and transmits the signal indicating that the read transaction transmission is completed by the monitoring signal generating device 7012 to the master device to the master device through the read data channel.

[0150] In some embodiments, the output selection device 7013 also: in response to receiving the above-mentioned bypass signal and not receiving the monitoring enable signal, outputs the above-mentioned read transaction; in response to not receiving the above-mentioned bypass signal, the above-mentioned monitoring enable signal and the above-mentioned slave device abnormal signal, outputs a false signal of the above-mentioned read transaction.

[0151] In some embodiments, the configuration device 7014 may provide an error enable signal to the error signal generating device 7011 , provide a reset signal to the error signal generating device 7011 and the monitoring signal generating device 7012 , and provide a bypass signal to the output selection device 7013 .

[0152] It is understood that some use opportunities of the memory 7015, the error signal generating device 7021, the monitoring signal generating device 7022, the output gating device 7023 and the configuration device 7024 can be seen in FIG. Figure 6 Description of embodiments.

[0153] Through the slave device bus monitor of some embodiments of the present disclosure, the operation state of the bus can be monitored in time and the error can be located in time. Furthermore, the bus with an error can be quickly reset, reducing the time required for reset. Specifically, the reason for the long reset time and low reset efficiency of the bus is that the operation state of the bus cannot be monitored in time, the error cannot be located in time, and the bus with an error cannot be quickly reset. Based on this, the master device bus monitor and the slave device bus monitor of some embodiments of the present disclosure complete the monitoring of the operation state of the bus by adopting an error signal generating device. First, the master device abnormal signal can be generated by monitoring the acquisition of a read transaction from the read address channel and the failure to obtain a response to the read transaction from the read data channel within a preset time period. Thus, the monitoring of the operation state of the bus can be completed. Then, according to the read address valid signal in the above-mentioned read address channel, the occurrence of the read transaction is identified, and according to the end signal of the data to be read by the read transaction in the above-mentioned read data channel, the response of the above-mentioned read transaction is obtained. Thus, it can be determined whether the response to the read transaction is completed, thereby determining whether the bus is abnormal. Then, the error signal generating device also generates a master device abnormal signal in response to receiving the error enable signal, and outputs the master device abnormal signal, thereby facilitating the outside world to reset the bus with an error in time according to the master device abnormal signal, thus achieving the technical effect of reducing the reset time.

[0154] Fig.10 It is a schematic diagram of the relationship between the master device and the slave device of the present invention.

[0155] like Fig.10As shown, the electronic system provided by the present disclosure includes a master device 1001, a slave device 1002, a bus 1003, a master device bus monitor 1004 and a slave device bus monitor 1005, wherein: the bus 1003 is used to provide a read data channel (not shown in the figure) and a read address channel (not shown in the figure). The read address channel transmits information such as the address and length of the read transaction. The master device bus monitor 1004 couples the master device 1001 to the bus 1003. The slave device bus monitor 1005 couples the slave device 1002 to the bus 1003. The bus 1003 can be a common channel for the CPU (Central Processing Unit), memory, input, and output devices to transmit information. In the embodiment of the present disclosure, the master device 1001 can refer to a device with bus control rights during bus transmission, and the slave device 1002 can refer to a device (module) that cooperates with the master device 1001 to complete data transmission during the bus transmission cycle. The slave device usually passively accepts commands sent by the master device. The master device abnormality signal in the embodiment of the present disclosure indicates that the data transmission of the bus is abnormal and the abnormality occurs on the master device side. The slave device abnormality signal in the embodiment of the present disclosure indicates that the data transmission of the bus is abnormal and the abnormality occurs on the slave device side.

[0156] In some embodiments, the electronic system further includes a processor (not shown). Here, the processor may be a CPU. In response to receiving a master device abnormality signal output by the master device bus monitor or a slave device abnormality signal output by the slave device bus monitor, the processor resets the master device bus monitor, the slave device bus monitor, the corresponding master device / slave device and / or the bus.

[0157] It should be understood that Fig.10 The number of master devices, slave devices, master bus monitors and slave bus monitors in the embodiment is only illustrative. Any number of master devices, slave devices, master bus monitors and slave bus monitors may be provided according to implementation requirements.

[0158] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the above-mentioned features are replaced with the technical features with similar functions disclosed in the embodiments of the present disclosure (but not limited to) and the technical solutions formed.

Claims

1. A master device bus monitor, characterized in that: The master device bus monitor comprises: an error signal generating device and an output gating device, wherein: The master device bus monitor is used to couple the master device to a bus, wherein the bus includes a read address channel and a read data channel; The error signal generating device is coupled to the read address channel and the read data channel, and generates a master device abnormal signal in response to obtaining a read transaction from the read address channel and not obtaining a response to the read transaction from the read data channel within a preset time period; The output strobe device couples the read address channel and the read data channel; In response to receiving the bypass signal, the output selection device outputs the read transaction; in response to receiving the master device abnormal signal, the output selection device outputs a false signal of the read transaction, so that the bus transmission can be completed.

2. The master device bus monitor according to claim 1, characterized in that: The error signal generating device further outputs the master device abnormal signal in response to obtaining multiple read transactions from the read address channel and failing to obtain a response to any of the multiple read transactions from the read data channel within a predetermined time.

3. The master device bus monitor according to claim 1 or 2, characterized in that: The error signal generating device comprises a first counter, a second counter and a timer, wherein: the first counter is used to count the number of read transactions obtained from the read address channel; the second counter is used to count the number of responses to the read transactions obtained from the read data channel; the timer performs timing in response to the number counted by the first counter being greater than the number counted by the second counter; The error signal generating device generates the master device abnormality signal in response to the timing time of the timer being greater than the length of the preset time period.

4. The master device bus monitor according to any one of claims 1 to 3, characterized in that: The error signal generating device resets the timer in response to the number counted by the first counter being equal to the number counted by the second counter or obtaining a response to a read transaction from the read data channel.

5. The master device bus monitor according to any one of claims 1 to 4, characterized in that: The error signal generating device also includes a first counter, a second counter and a timer corresponding to each of a plurality of IDs for read transactions, wherein: the first counter counts the number of read transactions with an ID corresponding to the first counter captured from the read address channel; and the second counter counts the number of responses to the read transactions with an ID corresponding to the second counter obtained from the read data channel.

6. The master bus monitor according to claim 5, characterized in that: Also included is a monitoring signal generating device; The monitoring signal generating device is coupled to the read address channel and the read data channel; In response to obtaining the master device abnormal signal from the error signal generating device and the value of the first counter corresponding to the first ID is different from the value of the second counter corresponding to the first ID, the monitoring signal generating device indicates the slave device not ready signal for the read address channel and the identification signal of the first ID to the master device; and the monitoring signal generating device indicates the master device ready signal for the read data channel and the identification signal of the first ID to the slave device.

7. A slave device bus monitor, characterized in that: The slave device bus monitor comprises: an error signal generating device and an output gating device, wherein: The slave device bus monitor is used to couple the slave device to the bus, wherein the bus includes a read address channel and a read data channel; The error signal generating device is coupled to the read address channel and the read data channel, and generates a slave device abnormal signal in response to obtaining a read transaction from the read address channel and not obtaining a response to the read transaction from the read data channel within a preset time period; The output strobe device is coupled to the read address channel and the read data channel; The output selection device outputs the read transaction in response to receiving the bypass signal; and outputs a false signal of the read transaction in response to receiving the slave device abnormal signal.

8. The slave device bus monitor according to claim 7, characterized in that: The slave device bus monitor further comprises: a memory and a monitoring signal generating device, wherein: The memory stores the length of data to be read by the read transaction; The monitoring signal generating device is coupled to the read address channel and the read data channel, and in response to obtaining the slave device abnormal signal from the error signal generating device, obtains the data length to be read by the read transaction from the memory, transmits data of the amount of the first difference to the master device according to a first difference between the data length to be read by the read transaction and the data length already read for the read transaction, and indicates to the master device that the read transaction transmission is completed.

9. The slave device bus monitor according to claim 7 or 8, characterized in that: The error signal generating device includes a first counter, a second counter and a timer, wherein: the first counter is used to count the number of read transactions obtained from the read address channel; the second counter is used to count the number of responses to read transactions obtained from the read data channel; the timer performs timing in response to the number counted by the first counter being greater than the number counted by the second counter; the error signal generating device generates a slave device abnormal signal in response to the timing time of the timer being greater than the length of a preset time period.

10. An electronic system comprising: A master, a slave, a bus, a master bus monitor, and a slave bus monitor, where: The bus provides a read data channel and a read address channel; The master bus monitor couples the master device to a bus; The slave bus monitor couples the slave device to a bus; The master bus monitor is a bus monitor according to any one of claims 1 to 6; The slave bus monitor is a bus monitor according to any one of claims 7-9.

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