AHB-to-simple parallel interface conversion bridge
By designing the AHB to simple parallel interface conversion bridge, using the AHB interface to write addresses and implement indirect addressing, the problem of manual address setting in the existing technology affecting efficiency is solved, automatic address increase and continuous operation are realized, and access efficiency is improved .
Patent Information
- Application Number
- CN202411510181.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-07
AI Technical Summary
In the prior art, when the control module needs to access the peripheral registers or memory through the AHB interface, it needs to manually set the address, which affects the access efficiency.
A AHB to simple parallel interface conversion bridge is designed to write the simple parallel interface address to be accessed through the AHB interface. The registers in the conversion bridge realize indirect addressing and accessing the simple parallel interface, and the address is automatically increased after the read and write operation is completed.
It realizes continuous operation without manual address setting, improving access efficiency.
Smart Images
Figure CN119396754A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of data transmission protocol conversion, and in particular to an AHB to simple parallel interface conversion bridge. Background Art
[0002] At present, the commonly used low-speed interface inside SoC is AHB interface, which uses multiple data lines and control lines for data transmission. However, some peripheral modules have low speed and small area, and use simpler simple parallel interface to access registers and memory. When the control module needs to access the registers or memory of the peripheral through AHB, a conversion bridge is required to convert the AHB protocol into a simple parallel interface protocol. Usually, when the control module reads and writes the memory of the peripheral, it needs to read and write the continuous address space. When performing this operation in the prior art, the address needs to be set manually, which affects the access efficiency. Summary of the invention
[0003] To achieve the above-mentioned purpose and other related purposes, the present invention discloses an AHB to simple parallel interface conversion bridge, comprising:
[0004] The conversion bridge includes a set of AHB interfaces and one or more sets of simple parallel interfaces. The registers in the conversion bridge are configured by AHB to achieve indirect addressing access to the simple parallel interface.
[0005] The address of the simple parallel interface to be accessed is written to the conversion bridge through AHB, and then the conversion bridge reads or writes data to the simple parallel interface according to the address. After the read or write operation is completed, the address in the conversion bridge is automatically increased by one.
[0006] Furthermore, the timing flow of the simple parallel interface when performing a write operation includes:
[0007] Provide write address and write data;
[0008] Pull wr_en high for at least one cycle, and the simple parallel interface performs a write operation according to the write address and write data;
[0009] After the write operation is completed, ack is pulled high for at least one cycle, indicating that the next data transmission can begin.
[0010] Furthermore, the timing flow of the simple parallel interface during a read operation includes:
[0011] Provide the read address;
[0012] Pull rd_en high for at least one cycle, and the simple parallel interface performs a read operation according to the read address;
[0013] After the reading is completed, ack is pulled high for at least one cycle, indicating that the next data transmission can begin.
[0014] Furthermore, the conversion bridge is provided with 5 registers, namely r_addr, r_wdata, r_rdata, r_wr_fail and r_rd_fail, and the timing flow of the AHB interface writing data to the simple parallel interface through the conversion bridge includes:
[0015] Write the address of the simple parallel interface to be accessed to the r_addr register through the AHB interface;
[0016] After writing the data to be written to the r_wdata register through the AHB interface, the conversion bridge pulls down hready and pulls up wr_en for at least one cycle to write the data in the r_wdata register to the simple parallel interface corresponding to the address in the r_addr register;
[0017] When the write operation is completed, hready is pulled high, and the simple parallel interface address in the r_addr register is automatically increased by one. If continuous access is required, the next data to be written is directly written to the r_wdata register, and the write operation is continued according to the simple parallel interface address in the r_addr register.
[0018] Furthermore, the timing flow of the AHB interface reading the data of the simple parallel interface through the conversion bridge includes:
[0019] Write the address of the simple parallel interface to be accessed to the r_addr register through the AHB interface;
[0020] After reading the r_rdata register through the AHB interface, the conversion bridge pulls down hready and pulls up rd_en for at least one cycle, initiates a read operation to the corresponding simple parallel interface according to the address in the r_addr register, and transfers the read data to the r_rdata register, then pulls up hready, and the simple parallel interface address in the r_addr register is automatically increased by one. If continuous access is required, the read operation continues according to the address in the r_addr register.
[0021] Furthermore, if the read or write address is out of range or an illegal read or write operation occurs, the 31st bit of the r_rd_fail or r_wr_fail register is set to 1, and the value of the erroneous r_addr register is stored in bits 18:0.
[0022] By adopting the above technical solution, the conversion bridge writes the address of the simple parallel interface to be accessed, and then the AHB interface reads or writes data according to the address of the simple parallel interface. After the read operation or write operation is completed, the address of the simple parallel interface written in the conversion bridge is automatically increased by one. When continuous operation is required, there is no need to re-enter the address of the simple parallel interface, and continuous operation can be achieved, thereby improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, among which:
[0024] Figure 1 This is the timing diagram for the simple parallel interface write operation;
[0025] Figure 2 This is the timing diagram for the simple parallel interface to perform a read operation;
[0026] Figure 3 This is the timing diagram of the AHB interface writing data to the simple parallel interface through the conversion bridge;
[0027] Figure 4 This is the timing diagram for the AHB interface to read data from the simple parallel interface through the conversion bridge. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.
[0029] The embodiment of the present invention provides an AHB to simple parallel interface conversion bridge, comprising:
[0030] The conversion bridge includes a set of AHB interfaces and one or more sets of simple parallel interfaces. The registers in the conversion bridge are configured by AHB to achieve indirect addressing access to the simple parallel interface.
[0031] The address of the simple parallel interface to be accessed is written to the conversion bridge through AHB, and then the conversion bridge reads or writes data to the simple parallel interface according to the address. After the read or write operation is completed, the address in the conversion bridge is automatically increased by one.
[0032] Reference Figure 1 , the timing flow of the simple parallel interface writing operation includes:
[0033] Provide write address and write data;
[0034] Pull wr_en high for at least one cycle, and the simple parallel interface performs a write operation based on the write address and write data;
[0035] After the write operation is completed, ack is pulled high for at least one cycle, indicating that the next data transmission can begin.
[0036] Reference Figure 2 , the timing flow of the simple parallel interface reading operation includes:
[0037] Provide the read address;
[0038] Pull rd_en high for at least one cycle, and the simple parallel interface performs a read operation according to the read address;
[0039] After the reading is completed, ack is pulled high for at least one cycle, indicating that the next data transmission can begin.
[0040] The conversion bridge is provided with 5 registers, namely r_addr, r_wdata, r_rdata, r_wr_fail and r_rd_fail, as shown in Table 1.
[0041] Table 1
[0042]
[0043] Reference Figure 3 The timing process of the AHB interface writing data to the simple parallel interface through the conversion bridge includes:
[0044] Write the address of the simple parallel interface to be accessed to the r_addr register through the AHB interface;
[0045] After writing the data to be written to the r_wdata register through the AHB interface, the conversion bridge pulls down hready and pulls up wr_en for at least one cycle to write the data in the r_wdata register to the simple parallel interface corresponding to the address in the r_addr register;
[0046] When the write operation is completed, hready is pulled high, and the simple parallel interface address in the r_addr register is automatically increased by one. If continuous access is required, the next data to be written is directly written to the r_wdata register, and the write operation is continued according to the simple parallel interface address in the r_addr register.
[0047] Reference Figure 4 The timing flow of the AHB interface reading the data of the simple parallel interface through the conversion bridge includes:
[0048] Write the address of the simple parallel interface to be accessed to the r_addr register through the AHB interface;
[0049] After reading the r_rdata register through the AHB interface, the conversion bridge pulls down hready and pulls up rd_en for at least one cycle, initiates a read operation to the corresponding simple parallel interface according to the address in the r_addr register, and transfers the read data to the r_rdata register, then pulls up hready, and the simple parallel interface address in the r_addr register is automatically increased by one. If continuous access is required, the read operation continues according to the address in the r_addr register.
[0050] If the read or write address is out of range or an illegal read or write operation occurs, the 31st bit of the r_rd_fail or r_wr_fail register is set to 1, and the value of the erroneous r_addr register is stored in bits 18:0.
[0051] An embodiment of the present invention provides an AHB to simple parallel interface conversion bridge, wherein the address of a simple parallel interface to be accessed is written to the conversion bridge via the AHB, and then the conversion bridge reads or writes data to the simple parallel interface according to the address. After the read operation or write operation is completed, the address in the conversion bridge is automatically increased by one. When continuous operation is required, continuous operation can be achieved without re-entering the address of the simple parallel interface, thereby improving work efficiency.
[0052] Those skilled in the art will appreciate that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.
[0053] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.
[0054] It can be known from the description of the above implementation modes that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute the methods described in the various implementation modes of the present application or certain parts of the implementation modes.
[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. An AHB to simple parallel interface conversion bridge, characterized in that: include: The conversion bridge includes a set of AHB interfaces and one or more sets of simple parallel interfaces. The registers in the conversion bridge are configured by AHB to achieve indirect addressing access to the simple parallel interface. The address of the simple parallel interface to be accessed is written to the conversion bridge through AHB, and then the conversion bridge reads or writes data to the simple parallel interface according to the address. After the read or write operation is completed, the address in the conversion bridge is automatically increased by one.
2. The AHB to simple parallel interface conversion bridge according to claim 1, characterized in that: The timing flow of the simple parallel interface writing operation includes: Provide write address and write data; Pull wr_en high for at least one cycle, and the simple parallel interface performs a write operation based on the write address and write data; After the write operation is completed, ack is pulled high for at least one cycle, indicating that the next data transmission can begin.
3. The AHB to simple parallel interface conversion bridge according to claim 1, characterized in that: The timing flow of the simple parallel interface reading operation includes: Provide the read address; Pull rd_en high for at least one cycle, and the simple parallel interface performs a read operation according to the read address; After the reading is completed, ack is pulled high for at least one cycle, indicating that the next data transmission can begin.
4. The AHB to simple parallel interface conversion bridge according to claim 1, characterized in that: The conversion bridge is provided with 5 registers, namely r_addr, r_wdata, r_rdata, r_wr_fail and r_rd_fail. The timing flow of the AHB interface writing data to the simple parallel interface through the conversion bridge includes: Write the address of the simple parallel interface to be accessed to the r_addr register through the AHB interface; After writing the data to be written to the r_wdata register through the AHB interface, the conversion bridge pulls down hready and pulls up wr_en for at least one cycle to write the data in the r_wdata register to the simple parallel interface corresponding to the address in the r_addr register; When the write operation is completed, hready is pulled high, and the simple parallel interface address in the r_addr register is automatically increased by one. If continuous access is required, the next data to be written is directly written to the r_wdata register, and the write operation is continued according to the simple parallel interface address in the r_addr register.
5. The AHB to simple parallel interface conversion bridge according to claim 4, characterized in that: The timing flow of the AHB interface reading the data of the simple parallel interface through the conversion bridge includes: The address of the simple parallel interface to be accessed is written to the r_addr register through the AHB interface; after reading the r_rdata register through the AHB interface, the conversion bridge pulls down hready and pulls up rd_en for at least one cycle, initiates a read operation to the corresponding simple parallel interface according to the address in the r_addr register, and transfers the read data to the r_rdata register, then pulls up hready, and at the same time, the simple parallel interface address in the r_addr register is automatically increased by one. If continuous access is required, the read operation is continued according to the address in the r_addr register.
6. The AHB to simple parallel interface conversion bridge according to claim 5, characterized in that: If the read or write address is out of range or an illegal read or write operation occurs, the 31st bit of the r_rd_fail or r_wr_fail register is set to 1, and the value of the erroneous r_addr register is stored in bits 18:0.