Hardware lookup table for artificial intelligence chip, method for loading data and computing device

Abstract

The present invention provides a hardware lookup table for an artificial intelligence chip, a method for loading data, and a computing device, the device comprising: a memory group, the memory group comprising a plurality of storage units, each storage unit having a storage space corresponding to the input data of the hardware lookup table; a data distributor, for distributing the input data of the hardware lookup table to the corresponding storage unit; a readout module, for reading data from the corresponding storage unit according to the address lookup data, wherein the bit width of the input data of the hardware lookup table is the same as the data bus bit width of the artificial intelligence chip. The technical solution according to the present invention can shorten the lookup table loading time, improve the lookup table performance, and reduce power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a hardware lookup table and a lookup table group for an artificial intelligence chip, a method for loading data for an artificial intelligence chip, an artificial intelligence chip, a computer program, and a computing device. Background Art

[0002] With the rapid development of integrated circuits, the Look-Up Table (LUT) as a hardware device in integrated circuits has also become a very important technology. In essence, the look-up table is a random access memory (RAM). In actual hardware integrated circuit design, the look-up table is often used to implement some complex combinational logic functions.

[0003] The lookup table receives some inputs (usually binary data), and then searches the table for the corresponding results and outputs them according to the values ​​of these inputs. For example, in the design of chip algorithm circuits, lookup tables are often implemented using static random access memory (SRAM). In this scenario, after the LUT receives the input data, these data are connected to the lookup table as address lines. Generally speaking, all possible logical results have been pre-written in the lookup table, and according to the value of the input data, the lookup table can find the corresponding results and output them. It can be seen that the advantage of the lookup table is that it is very fast, because the lookup operation is usually implemented through data mapping, and the mapping speed is usually much faster than the calculation speed of the central processing unit (CPU). Therefore, lookup tables are often used to implement combinational logic that requires high-speed response.

[0004] Figure 1 The schematic diagram of searching in the prior art is shown.

[0005] See also Figure 1 , the figure shows the schematic diagram of the search representation in the prior art. It can be seen that the traditional hardware circuit lookup table (LUT) in the prior art is composed of memory, and can only write data according to the input data bit width (data_i[7:0]). Referring to the example in the figure, writing 256 data requires 256 clock cycles. For AI computing chips, the clock cycles required to load the LUT are too many, which greatly increases the latency and seriously affects the performance of the AI ​​chip.

[0006] Therefore, a technical solution is needed to shorten the lookup table loading time, improve the lookup table performance, and reduce power consumption. Summary of the invention

[0007] The present invention aims to provide a hardware lookup table and a lookup table group for an artificial intelligence chip and a method for loading data for an artificial intelligence chip, an artificial intelligence chip and a computer program, and a computing device, which can shorten the lookup table loading time, improve the lookup table performance, and reduce power consumption.

[0008] According to one aspect of the present invention, a hardware lookup table for an artificial intelligence chip is provided, comprising:

[0009] a memory group, the memory group comprising a plurality of storage units, each storage unit having a storage space corresponding to input data of the hardware lookup table;

[0010] A data distributor, used for distributing the input data of the hardware lookup table to corresponding storage units;

[0011] The read module is used to read data from the corresponding storage unit according to the address.

[0012] Among them, the bit width of the input data of the hardware lookup table is the same as the data bus bit width of the artificial intelligence chip.

[0013] According to some embodiments, the data distributor includes a demultiplexer, which receives input data input to the hardware lookup table and distributes the input data to corresponding storage units according to a first control signal.

[0014] According to some embodiments, the first control signal comes from a counter or a state machine, which is used to record batches of data input to the hardware lookup table and control corresponding batches of the input data to be written into the corresponding lookup table to achieve automatic loading.

[0015] According to some embodiments, the readout module comprises a first selector and a second selector, wherein:

[0016] The first selector is used to select a corresponding storage unit to output the first data according to the first part of the address lookup data;

[0017] The second selector is used to select corresponding second data as an output result from the first data output by the selected storage unit according to the second part of the address search data.

[0018] According to some embodiments, the first selector and the second selector include a first multiplexer and a second multiplexer, respectively, the first multiplexer utilizing a first portion of the address lookup data as a control signal, and the second multiplexer utilizing a second portion of the address lookup data as a control signal.

[0019] According to one aspect of the present invention, there is provided a hardware lookup table group for an artificial intelligence chip, comprising a plurality of cascaded hardware lookup tables according to any one of the above items.

[0020] According to one aspect of the present invention, a method for loading data on an artificial intelligence chip is provided, wherein the artificial intelligence chip comprises a hardware lookup table as described in any one of the above items, and the method comprises:

[0021] Configure the lookup table data that needs to be loaded into the hardware lookup table;

[0022] Configure the computational data that needs to be loaded;

[0023] The lookup table data and the operation data are stored in the same host memory address space, with the lookup table data being located at the front;

[0024] The lookup table data and the operation data in the same segment of the host memory address space are moved to the memory of the artificial intelligence chip through direct memory access.

[0025] According to one aspect of the present invention, there is provided an artificial intelligence chip, comprising: a hardware lookup table as described in any one of the above items or a hardware lookup table group as described above.

[0026] According to another aspect of the present invention, a computer program product is provided, comprising: a computer program, wherein when the computer program is executed by a processor, the method described above is implemented.

[0027] According to another aspect of the present invention, there is provided a computing device, comprising:

[0028] Processor; and

[0029] A memory storing a computer program, which, when executed by the processor, enables the processor to execute any of the methods described above.

[0030] According to another aspect of the present invention, there is provided a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, and when the instructions are executed by a processor, the processor is caused to execute any of the above methods.

[0031] According to the embodiment of the present invention, by matching the bit width of the external input data with the bus bit width, the bandwidth of the data bus is fully utilized, the waiting time during the data transmission process is reduced, so that the lookup table device achieves maximum configuration efficiency, shortens the lookup table loading time, and thus speeds up the entire data loading speed. Moreover, directly matching the data bus bit width can simplify the hardware interface design, reduce the additional logic overhead introduced due to inconsistent data width, and is suitable for application scenarios with high requirements for real-time performance and data throughput, and can significantly improve the overall performance of the device.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0034] Figure 1 The schematic diagram of searching in the prior art is shown.

[0035] Figure 2 A schematic diagram of a hardware lookup representation for an artificial intelligence chip according to an example embodiment is shown.

[0036] Figure 3 A structural diagram of a hardware lookup table for an artificial intelligence chip according to an example embodiment is shown.

[0037] Figure 4 A flow chart of a method for loading data into an artificial intelligence chip according to an example embodiment is shown.

[0038] Figure 5 A block diagram of a computing device is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0040] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0041] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0042] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0043] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0044] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0045] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0046] With the rapid development of integrated circuits, the design of look-up tables (LUTs) has become a very important technology. The advantage of a look-up table is that it is very fast, because the lookup operation is usually implemented through data mapping, and the mapping speed is usually much faster than the CPU calculation speed. Therefore, look-up tables are often used to implement combinational logic that requires high-speed response.

[0047] However, traditional LUTs are usually implemented based on static random access memory (SRAM), and their write operations need to be performed one by one according to the address, which leads to a long initialization or configuration time. For application scenarios that require fast loading of large amounts of data, such as weight loading in deep learning, approximation of activation functions, etc., this delay is unacceptable.

[0048] To this end, the present invention proposes a hardware lookup table and a lookup table group for an artificial intelligence chip, a method for loading data for an artificial intelligence chip, an artificial intelligence chip, a computer program, and a computing device, which can shorten the lookup table loading time, improve the lookup table performance, and reduce power consumption. According to an embodiment, by matching the bit width of the external input data with the bus bit width, the lookup table device achieves maximum configuration efficiency, shortens the lookup table loading time, improves the data bus utilization rate, and reduces unnecessary data batch transmission processes, thereby speeding up the entire data loading speed and significantly improving the overall performance of the device.

[0049] Before describing the embodiments of the present invention, some terms or concepts involved in the embodiments of the present invention are explained.

[0050] Direct Memory Access (DMA) is a technology that allows certain hardware subsystems to read or write data from main memory without the intervention of the central processing unit (CPU). Through DMA, the speed and efficiency of data transfer can be significantly improved while reducing the CPU load.

[0051] Static Random Access Memory (SRAM) is a type of volatile memory used in computers and other digital electronic devices.

[0052] Advanced High-performance Bus (AHB) is part of AMBA (Advanced Microcontroller Bus Architecture), developed by ARM to connect high-performance components in System-on-Chip (SoC). As a high-speed, low-latency solution, AHB is designed to support communication between high-performance modules such as CPU, DMA controller, high-speed RAM, etc.

[0053] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0054] Figure 2 A schematic diagram of a hardware lookup representation for an artificial intelligence chip according to an example embodiment is shown.

[0055] See also Figure 2 , the figure shows a hardware lookup table for an artificial intelligence chip according to an example embodiment, comprising: a memory group 01, the memory group 01 comprising a plurality of storage units, each storage unit having a storage space corresponding to the input data of the hardware lookup table; a data distributor 02, for distributing the input data of the hardware lookup table to corresponding storage units; a readout module 03, for reading data from corresponding storage units according to address lookup data, wherein the bit width of the input data of the hardware lookup table is the same as the data bus bit width of the artificial intelligence chip, so that the device achieves maximum configuration efficiency and shortens data loading time.

[0056] According to some embodiments, by making the bit width of the external input data the same as the bit width of the data bus, the bandwidth of the data bus can be maximized, thereby reducing the time of data transmission and improving the overall configuration efficiency. There are two factors that determine the bit width. On the one hand, it is the bit width of the module data bus, for example, AHB is usually 128 bits, and AXI bus is usually 512 bits, 1024 bits; On the other hand, it is the size of the LUT, for example, 256 bytes (256x8 bits), 1024 bytes (1024 x8 bits). In short, the larger the bit width of the bus, the shorter the number of cycles required to write to the LUT. By ensuring the consistency of the input data and the bit width of the data bus, due to the high utilization rate of the data bus, unnecessary data batch transmission process is reduced, thereby speeding up the speed of the entire data loading, making full use of the bandwidth of the data bus, reducing the waiting time during the data transmission process, and directly matching the data bus bit width can simplify the hardware interface design and reduce the additional logic overhead introduced due to inconsistent data width. This architecture is particularly suitable for application scenarios with high requirements for real-time performance and data throughput, such as high-performance computing, AI accelerators, etc. By optimizing the data path and processing flow, the overall performance of the device can be significantly improved.

[0057] According to some embodiments, see Figure 2 Compared with the traditional lookup table architecture, the lookup table architecture designed by the present invention expands the input data bit width (data_i[511:0]), so that the input data bit width of the LUT matches the bus bit width, achieving maximum configuration efficiency and shortening the data loading time. In the scenario of a bus bit width of 512 bits (64 bytes), the traditional SRAM LUT architecture requires 256 cycles to load 256 bytes of data due to the limitation of the input data bit width; the lookup table architecture designed by the present invention has a data bit width expanded to 512 bits, and only 4 cycles are required to complete data loading, shortening the loading time by 64 times, significantly improving the overall performance of the device.

[0058] Figure 3 A structural diagram of a hardware lookup table for an artificial intelligence chip according to an example embodiment is shown.

[0059] See also Figure 3, the figure shows a hardware search for an artificial intelligence chip according to an example embodiment, wherein the data bit width of the module bus is 512 bits (64 bytes), and data_1~data_4 in the figure are 4 data written into the LUT in 4 clock cycles respectively. The LUT size is 256 * 8 bits, and Byte 63~0 in the figure can be understood as address 0~63 caching 64 bytes of data, and so on. The input data_i[511:0] is selected to be cached in 4 512-bit registers (64 bytes) through the first control signal (addr_i[7:6]). When reading, the first part of the address search data addr_i[7:6] is selected to select the corresponding 512-bit register, and the second part of the address search data (addr_i[5:0]) is selected to select the byte in the corresponding 512-bit register to implement the function of the lookup table.

[0060] The data distributor 02 includes a demultiplexer 0201, which receives input data input to the hardware lookup table and distributes the input data to corresponding storage units according to a first control signal. The demultiplexer 0201 receives input data input to the hardware lookup table and distributes the lookup table input data to the memory group 01 according to a first control signal; the memory group 01 includes a plurality of storage units, which respectively receive and cache the lookup table input data segments distributed from the demultiplexer 0201.

[0061] According to some embodiments, the first control signal comes from a counter or a state machine, which is used to record the data batches input into the hardware lookup table, and control the input data of the corresponding batch to be written into the corresponding lookup table to achieve automatic loading, thereby ensuring the orderliness and traceability of data processing. The counter or state machine generates the first control signal according to the data batch currently being processed. If a counter is used, each time a new data batch arrives, the counter increments and generates a new control signal. If a state machine is used, the state machine generates a control signal according to a predefined state sequence to ensure the orderliness of data processing. The data distributor 02 distributes the data to the corresponding storage units in the memory group 01 according to the bit width, address information and the first control signal of the input data. Such a design can adapt to application scenarios that require efficient processing of large amounts of data, such as image processing, video encoding, deep learning acceleration, etc., and can optimize the data path and improve data processing efficiency.

[0062] According to some embodiments, the read module 03 includes a first selector 0301 and a second selector 0303, wherein the first selector 0301 is used to select a corresponding storage unit to output the first data according to the first part of the address lookup data; the second selector 0303 is used to select the corresponding second data from the first data output by the selected storage unit according to the second part of the address lookup data as the output result. The first selector 0301 and the second selector 0303 are used to select and output data in stages, so that the hardware lookup table can process and output data more finely, ensuring efficient and orderly data access. First, the first selector 0301 receives the first part (high address) of the address selection signal and selects one or more storage units as candidates. Data is read from the selected storage unit as the first data. Afterwards, the second selector 0303 receives the second part (low address) of the address selection signal, further selects a specific part of the first data as the second data, and outputs the final second data as the operation result. By selecting and outputting data in stages, the efficiency of data access is improved and the flexibility of data processing is ensured.

[0063] According to some embodiments, the first selector 0301 and the second selector 0303 may be a first multiplexer and a second multiplexer, respectively, the first multiplexer uses the first part of the address lookup data as a control signal, and the second multiplexer uses the second part of the address lookup data as a control signal. The two multiplexers use the first part and the second part of the address lookup data as control signals, respectively, to achieve accurate data selection and output. By introducing the first multiplexer and the second multiplexer, the data access capability and flexibility of the hardware lookup table are enhanced, so that the hardware lookup table can better adapt to complex real-time data processing requirements.

[0064] According to some embodiments, the demultiplexer 0201 is configured to distribute the external input data to multiple storage units of the memory group 01 according to a first control signal. According to the first control signal, the demultiplexer 0201 divides the input data into multiple parts and sends these parts to different storage units in the memory group 01 respectively.

[0065] According to some embodiments, the first selector 0301 is configured to: select a specific external input data segment as the first data to be output externally according to the first part of the address lookup data. The first selector 0301 selects the first part of the address lookup data to receive data segments from multiple storage units in the memory group 01 and selects a specific data segment as the first data to be output externally.

[0066] According to some embodiments, the second selector 0303 is configured to: select a specific first data segment as the second data to be output externally according to the second part of the address lookup data. The second selector 0303 receives the first data segment from the first selector. Select a specific first data segment as the second data to be output externally according to the second part of the address lookup data.

[0067] According to some embodiments, in the design of the solution of the present invention, the input data bit width is matched with the data bus bit width, thereby ensuring the maximum efficiency of data transmission and shortening the data loading time. Through the two-level selection mechanism, the required storage unit and specific data can be located faster, reducing the overall processing delay, and it is widely applicable to application scenarios that require efficient processing of large amounts of data, such as image processing, video encoding, deep learning acceleration, etc., and significantly improves the performance of related applications by optimizing the data path and improving data processing efficiency.

[0068] According to some embodiments, the multiple storage units are specifically implemented as multiple registers, each register is used to store multiple bytes of data, which improves the efficiency and flexibility of data reading and writing. The number of registers can be adjusted according to the size of the lookup table and the application requirements. The register has high-speed reading and writing capabilities, which is suitable for frequent access and fast data processing. Each register stores multiple bytes of data, so that a single read can obtain a large amount of data, reducing the overhead of multiple reads, and improving the data storage density per unit area, which is suitable for application scenarios requiring high-density storage.

[0069] According to some embodiments, the demultiplexer 0201 receives input data input to the hardware lookup table, and distributes the data to different storage units in the memory group 01 according to certain rules. The memory group 01 includes multiple storage units, each of which can cache data segments received from the demultiplexer 0201. Each storage unit is responsible for storing a specific part of the data, and these data segments together constitute the complete lookup table input data. After receiving the data, the storage unit caches it and then transmits it to the first selector. The first selector selects a specific data segment as output from the data segments received from each storage unit in the memory group 01 according to the address lookup data. The memory group 01 receives the first data from the first selector, that is, stores a first data segment in each storage unit, and transmits the first data segments cached in the multiple storage units to the second selector; the second selector receives multiple first data segments from the second memory group 01, and selects a specific first data segment as the second data according to the address lookup data as the output result to output externally. This selection process can be dynamically switched as needed, thereby allowing different data segments to be flexibly selected as the final output.

[0070] According to some embodiments, by using the demultiplexer 0201 and the first selector 0301 and the second selector 0303, the device can process multiple data fragments at the same time, thereby improving the speed of data processing. Such a design method optimizes the data path and improves the data throughput by reasonably arranging the data flow path, reduces unnecessary data transmission delays, and improves the overall efficiency. According to some embodiments, by introducing a second-layer storage and selection mechanism, multi-level data processing is performed on the data, so that the device can operate the data at a finer granularity, thereby improving the flexibility and accuracy of data processing. The multi-level storage and selection structure helps to disperse the data flow, reduce bottlenecks, improve the overall data throughput, more effectively utilize storage resources, and reduce unnecessary data transmission delays.

[0071] According to some embodiments, the design scheme of the present invention can also be applied to the design of a hardware lookup table group of an artificial intelligence chip, which may include a plurality of cascaded hardware lookup tables as described in any of the above items, and the functions and processing capabilities are expanded by cascading a plurality of lookup tables, so that the hardware lookup table group of the artificial intelligence chip can process data step by step, gradually realize complex logical operations and data conversion, and is suitable for applications of high-performance computing and large-scale data processing. Among them, each level of hardware lookup table can be configured differently as needed to realize complex logical operations and data conversion. The design of multi-level lookup tables can further improve the efficiency of data access and reduce delays.

[0072] Figure 4 A flow chart of a method for loading data into an artificial intelligence chip according to an example embodiment is shown.

[0073] See also Figure 4 , the figure shows a method for loading data for an artificial intelligence chip according to an example embodiment, the artificial intelligence chip includes a hardware lookup table as described in any of the above items, and the specific steps of the method are as follows:

[0074] At S401 , the lookup table data to be loaded into the hardware lookup table is configured.

[0075] According to some embodiments, the lookup table data, such as mapping relationships, conversion functions, etc., are obtained, and format conversion, bit width adjustment, etc. are performed to ensure that they meet the requirements of the hardware lookup table. Ensure that the format and size of the lookup table data are suitable for subsequent processing.

[0076] In S403, the operation data to be loaded is configured.

[0077] According to some embodiments, the external input operation data is obtained, and format conversion, bit width adjustment, etc. are performed to ensure that it meets the requirements of the hardware lookup table. Ensure that the format and size of the operation data are suitable for subsequent processing.

[0078] In S405, the lookup table data and the operation data are stored in the same segment of the host memory address space, with the lookup table data being located at the front.

[0079] According to some embodiments, a continuous address space is allocated in the host memory, and the lookup table data is placed at the front of the address space, and the operation data is placed immediately thereafter in the same address space.

[0080] In S407, the lookup table data and the operation data in the same segment of the host memory address space are moved to the memory of the artificial intelligence chip through direct memory access (DMA).

[0081] According to some embodiments, the DMA controller is configured to set the source address to the starting address in the host memory and the target address to the memory address of the artificial intelligence chip. The DMA transfer is triggered to move the lookup table data and the operation data from the host memory to the memory of the artificial intelligence chip at one time. After the DMA transfer is completed, the hardware lookup table can immediately start using these data for calculations.

[0082] According to some embodiments, DMA allows data to be transferred directly between the host memory and the memory of the artificial intelligence chip, reducing CPU intervention and improving transmission efficiency. The lookup table data is located at the front of the address space, which is convenient for quickly loading and initializing the lookup table. By applying the hardware lookup table as described above, the bit width of the entire data block is the same as the data bus bit width to achieve maximum configuration efficiency and reduce data loading time. This method design enhances the data loading capability and flexibility of the artificial intelligence chip by introducing the DMA transmission mechanism and optimizing the data path, and better adapts to complex real-time data processing requirements.

[0083] According to some embodiments, the external input data and the lookup table configuration data are stored in the same address space, wherein the lookup table configuration data is at the front end of the address space, and the lookup table input data is obtained. According to some embodiments, the original input data is converted or adjusted as necessary to ensure that the data can be properly processed by other components in the device, which may involve operations such as data formatting, standardization, and noise filtering.

[0084] According to some embodiments, these data and the lookup table configuration data are merged into the same continuous address space, simplifying the subsequent data access and processing process, because the related data are organized together for quick access and use. It is particularly noted that the lookup table configuration data is arranged to be placed at the front end. Such a layout method can quickly load and set the configuration information required for the lookup table when the device is started, thereby realizing automatic configuration of the LUT.

[0085] According to some embodiments, in the traditional mode, the CPU needs to configure the LUT before the module works, and then the DMA module needs to calculate the data, which is inefficient and cumbersome to operate. In the design scheme of the present invention, the calculation data and the LUT configuration data are pre-integrated, so that the automatic configuration of the LUT is realized during the operation of the device, see Figure 3 In the example in , LUT data and operation data are stored in the same address space, and LUT data is arranged at the front, that is, the hardware design of the first 4 64-byte data in the figure is used to load LUT (used with low-latency LUT architecture), and the following data is operation data. This design method simplifies the module configuration process, reduces the probability of software configuration errors, improves the reliability of the design, reduces DMA configuration and transfer times, reduces data transfer delays, shortens loading time, and achieves the effect of improving performance and reducing power consumption.

[0086] According to some embodiments, assuming that the module contains multiple different LUTs that need to write data, the design processing of the present invention can also be adopted. When cnt = x, the data is written to the LUT. The order of data arrangement is LUT configuration data + operation data. Assume that the AI ​​chip contains 16 LUTs, 8 of which are 256 bytes and the other 8 are 1024 bytes. When the data bit width of the bus is 64 bytes, the data bit width of the LUT is also designed to be 64 bytes, which can improve the efficiency of loading (writing) and reduce latency. At this time, it takes 8 * 256 + 8 * 1024 = 10240 bytes to configure all LUTs. The bus data bit width is 64 bytes, and the clock cycle to complete the LUT configuration is 10240 / 64 = 160 cycles. That is to say, there are 8 256-byte LUTs, and one LUT is filled every 4 cycles. When cnt=0~3&DMA dat_vld signal writes data to the first LUT. When cnt= 4~7&DMA dat_vld signal writes data into the second LUT, and so on, until cnt= 28~31&DMA dat_vld the eighth 256-byte LUT is completely written, and then 8 1024-byte LUTs are written. When cnt=32~47, data is written into the ninth LUT, and so on.

[0087] According to some embodiments, the design of the solution of the present invention can also be applied to the design and development of artificial intelligence chips, wherein the artificial intelligence chip includes a device as described in any of the above items, so that the artificial intelligence chip can quickly load the lookup table, shorten the data loading time, and improve the loading efficiency.

[0088] According to some embodiments, the design of the scheme of the present invention can also be applied to the design and development of computer program products, and the computer program products include: a computer program, which implements the above-mentioned method when executed by a processor, simplifies the configuration process of the lookup table module, reduces the probability of software configuration errors, improves the reliability of the design, reduces DMA configuration and transfer times, reduces data transfer delays, shortens loading time, and achieves the effect of improving performance and reducing power consumption.

[0089] According to some embodiments, the design of the scheme of the present invention integrates and stores the external input operation data and the lookup table configuration data, realizes automatic configuration of the lookup table during data processing, greatly simplifies the configuration process of the lookup table device, reduces the risk of software configuration errors, and improves the reliability of the design. Compared with the configuration technology in traditional technology, it reduces the DMA configuration and transfer times, reduces the delay of data transfer, shortens the lookup table loading time, and achieves the effect of improving performance and reducing power consumption.

[0090] According to some embodiments, the design of the scheme of the present invention fully utilizes the bandwidth of the data bus by matching the bit width of the external input data with the bus bit width, reduces the waiting time during the data transmission process, and enables the lookup table device to achieve maximum configuration efficiency, shorten the lookup table loading time, improve the data bus utilization rate, and reduce unnecessary data batch transmission processes, thereby speeding up the entire data loading speed. Moreover, directly matching the data bus bit width can simplify the hardware interface design, reduce the additional logic overhead introduced by inconsistent data width, and is suitable for application scenarios with high requirements for real-time performance and data throughput, and can significantly improve the overall performance of the device.

[0091] Figure 5 A block diagram of a computing device according to an example embodiment of the invention is shown.

[0092] like Figure 5 As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0093] The processor 12 may include one or more general-purpose CPUs (Central Processing Units, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0094] The memory 14 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM) and / or a cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 may read the instructions stored in the memory 14 to execute the above-mentioned method according to the embodiment of the present invention.

[0095] The computing device 30 may also communicate with one or more networks via the network interface 16. The network interface 16 may be a wireless network interface.

[0096] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0097] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0098] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when the program is executed by a processor. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0099] An embodiment of the present invention also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0100] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0101] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0102] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0103] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0104] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0105] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0106] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0107] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0108] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. A hardware lookup table for an artificial intelligence chip, characterized in that: include: a memory group, the memory group comprising a plurality of storage units, each storage unit having a storage space corresponding to input data of the hardware lookup table; A data distributor, configured to distribute input data of the hardware lookup table to different storage units of the memory group, each storage unit caching data fragments received from the data distributor, the data fragments together constituting the complete input data; The read module is used to read data from the corresponding storage unit according to the address. Wherein, the bit width of the input data of the hardware lookup table is the same as the bit width of the data bus of the artificial intelligence chip; The data distributor includes a demultiplexer, the demultiplexer receives input data input to the hardware lookup table, and distributes the input data to corresponding storage units according to a first control signal, The readout module includes a first selector and a second selector, wherein: The first selector is used for selecting a corresponding storage unit to output first data according to the first part of the address search data; The second selector is used to select corresponding second data as an output result from the first data output by the selected storage unit according to the second part of the address search data; The first selector and the second selector include a first multiplexer and a second multiplexer, respectively. The first multiplexer uses the first part of the address lookup data as a control signal, and the second multiplexer uses the second part of the address lookup data as a control signal.

2. The hardware lookup table according to claim 1, characterized in that: The first control signal comes from a counter or a state machine, and is used to record the data batches input into the hardware lookup table, and control the input data of the corresponding batches to be written into the corresponding lookup table to achieve automatic loading.

3. A hardware lookup table group for an artificial intelligence chip, characterized in that: The method comprises a plurality of hardware lookup tables according to any one of claims 1-2 connected in cascade.

4. A method for loading data into an artificial intelligence chip, characterized in that: The artificial intelligence chip includes a hardware lookup table as described in any one of claims 1-2, and the method includes: Configure the lookup table data that needs to be loaded into the hardware lookup table; Configure the computational data that needs to be loaded; The lookup table data and the operation data are stored in the same host memory address space, with the lookup table data being located at the front; The lookup table data and the operation data in the same segment of the host memory address space are moved to the memory of the artificial intelligence chip through direct memory access.

5. An artificial intelligence chip, characterized in that: include: A hardware lookup table as claimed in any one of claims 1 to 2 or a hardware lookup table group as claimed in claim 3.

6. A computer program product, characterized in that include: A computer program, which, when executed by a processor, implements the method according to claim 4.

7. A computing device, characterized in that include: processor; as well as A memory storing a computer program, which, when executed by the processor, causes the processor to perform the method according to claim 4.

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