Random test method, device and equipment

Abstract

The invention discloses a random test method, device and equipment, and relates to the technical field of chip verification. The random test method comprises the steps that a target queue corresponding to a target random test variable is acquired, N historical random values of the target random test variable are recorded in the target queue, and N is a non-negative integer; based on the target queue, generating a first random value of the target random test variable, the first random value being different from the N historical random values recorded in the target queue; and based on the first random value, carrying out random testing on the to-be-tested design chip. According to the embodiment of the invention, the purpose of effectively improving the random test efficiency can be achieved.

Description

Technical Field

[0001] The present application belongs to the field of chip verification technology, and in particular relates to a random testing method, device and equipment. Background Art

[0002] At present, when verifying and testing IC (Integrated Circuit), building a random test environment is often a very important part of the verification process. In a random test environment, whether it is module-level verification, sub-module verification or chip system verification, it is often necessary to randomly generate a large number of random test signals, and the probability of the random value generated by each signal variable is determined by the bit width of the signal. For example, if the bit width of signal variable a is 32, then if all possible values ​​of variable a are exhausted, the number of possible values ​​of signal variable a is 2. 32 = 4294967296. However, when a test environment is in a random test, before all values ​​are exhausted, the values ​​generated by subsequent random tests may be repeated with the values ​​generated by previous random tests, resulting in a decrease in random efficiency.

[0003] Based on this, the industry is still in urgent need of a new random testing solution to ensure that the random value generated in the next random test is different from the random value generated previously, thereby achieving the goal of effectively improving the random efficiency of chip verification testing. Summary of the Invention

[0004] The embodiments of the present application provide a random testing method, apparatus, and device that can effectively improve the efficiency of random testing.

[0005] In a first aspect, an embodiment of the present application provides a random testing method, the random testing method comprising:

[0006] Obtain the target queue corresponding to the target random test variable. The target queue records N historical random values ​​of the target random test variable, where N is a non-negative integer.

[0007] Based on the target queue, a first random value of the target random test variable is generated, where the first random value is different from the N historical random values ​​recorded in the target queue;

[0008] Based on the first random value, a random test is performed on the design chip to be tested.

[0009] In some possible implementations, generating a first random value of a target random test variable based on a target queue includes:

[0010] Generate candidate random values ​​for the target random test variable;

[0011] Perform traversal comparison on the candidate random value and the N historical random values ​​in the target queue to obtain the traversal comparison result of the candidate random value;

[0012] If the traversal comparison result indicates that each of the N historical random values ​​is different from the candidate random value, the candidate random value is determined as the first random value;

[0013] If the traversal comparison result indicates that the target historical random value exists in the N historical random values, jump to the step of generating a candidate random value of the target random test variable to generate a new candidate random value of the target random test variable until each of the N historical random values ​​is different from the candidate random value;

[0014] The target historical random value is the same historical random value as the candidate random value.

[0015] In some possible implementations, generating a first random value of a target random test variable based on a target queue includes:

[0016] Get M possible values ​​of the target random test variable, where M is a positive integer;

[0017] Compare the M possible values ​​with the N historical random values ​​to determine MN candidate random values ​​that have not been randomly selected;

[0018] A first random value is generated based on MN candidate random values, where the MN candidate random values ​​include the first random value.

[0019] In some possible implementations, after generating a first random value of a target random test variable based on a target queue, the random testing method further includes:

[0020] Write the first random value into the target queue.

[0021] In some possible implementations, after writing the first random value into the target queue, the random testing method further includes:

[0022] Obtain the first value quantity of the target random test variable stored in the target queue;

[0023] Compare the first value quantity with the second value quantity to obtain a comparison result, where the second value quantity is the maximum value quantity supported by the value bit width of the target random test variable;

[0024] When the comparison result indicates that the first value quantity is greater than or equal to the second value quantity, the random values ​​of the target random test variables recorded in the target queue are cleared.

[0025] In some possible implementations, after comparing the first value quantity with the second value quantity to obtain a comparison result, the random testing method further includes:

[0026] If the comparison result indicates that the first number of values ​​is less than the second number of values, generating a second random value of the target random test variable based on the target queue;

[0027] The second random value is different from the N historical random values ​​and the first random value recorded in the target queue; the second random value is used for random testing of the designed chip to be tested.

[0028] In some possible implementations, after generating a first random value of a target random test variable based on a target queue, the random testing method further includes:

[0029] The first random value is stored in a target file, and the target file is provided to the design chip to be tested, so that the design chip to be tested performs a random test based on the random value stored in the target file;

[0030] Write the first random value into the target queue, including:

[0031] The first random value is read from the target file and written into the target queue.

[0032] In some possible implementations, after comparing the first value quantity with the second value quantity to obtain a comparison result, the random testing method further includes:

[0033] When the comparison result indicates that the first value quantity is greater than or equal to the second value quantity, the random values ​​of the target random test variables stored in the target file are cleared.

[0034] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a random testing device, which includes:

[0035] The first acquisition module is used to obtain a target queue corresponding to a target random test variable, where the target queue records N historical random values ​​of the target random test variable, where N is a non-negative integer;

[0036] A first generating module is configured to generate a first random value of a target random test variable based on a target queue, where the first random value is different from the N historical random values ​​recorded in the target queue;

[0037] The first testing module is configured to perform a random test on the design chip to be tested based on a first random value.

[0038] In a third aspect, an embodiment of the present application provides a random testing device, the random testing device comprising:

[0039] a processor and a memory storing computer program instructions;

[0040] When the processor executes the computer program instructions, the random testing method provided in any one of the above embodiments of the present application is implemented.

[0041] In a fourth aspect, an embodiment of the present application provides a computer storage medium having computer program instructions stored thereon, and when the computer program instructions are executed by a processor, a random testing method as provided in any one of the above-mentioned embodiments of the present application is implemented.

[0042] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes a random testing method as provided in any one of the above-mentioned embodiments of the present application.

[0043] The present invention provides a random testing method, apparatus, and device. The method obtains a target queue corresponding to a target random test variable, which records N historical random values ​​of the target random test variable. Based on the target queue, a first random value of the target random test variable is generated. The first random value is different from the N historical random values ​​recorded in the target queue, and the first random value can be used for random testing of a design chip under test.

[0044] As can be seen from the above description, the random testing method, apparatus, and device of the present invention enable communication between a large number of random tests through a target queue. This is equivalent to using the target queue to inform the next random test that the previous random test generated certain values, thereby ensuring that the random values ​​generated by this random test are different from those generated previously. This significantly improves the random efficiency of the overall verification test of the chip under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] Figure 1 This is a flow chart of a random testing method provided in one embodiment of the present application;

[0047] Figure 2 This is a schematic diagram of the structure of a random testing device provided in one embodiment of the present application;

[0048] Figure 3 It is a structural diagram of a random testing device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0049] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0050] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0051] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned. They should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0052] As described in the background technology section, currently when a test environment is in a random test, the values ​​generated by the subsequent random test may be repeated with the values ​​generated by the previous random test before all values ​​are exhausted, resulting in a decrease in random efficiency. In order to deeply understand the root cause of the above-mentioned technical problems, the hardware description language SystemVerilog, which is commonly used in IC verification tests, is first introduced below. SystemVerilog is a hardware description language for designing and verifying digital systems. It is an extension of the Verilog language. SystemVerilog not only includes all the functions of Verilog, but also adds many features, such as enhanced data types, object-oriented programming, verification functions such as assertions and coverage, as well as interface and connection functions, making design descriptions more intuitive and modular.

[0053] The existing SystemVerilog library provides a randc modifier, but its effect is limited to a single test. If a variable is randomly modified by randc multiple times, the resulting random values ​​will be different until all cases of the variable are exhausted. However, the existing SystemVerilog library cannot resolve the correlation between multiple random tests. This means that the random value generated by one random test may be the same as the random value generated by the next test.

[0054] In SystemVerilog, random generators are primarily based on pseudo-random number generators (PRNGs). These generators use some initial value (seed value) and a specific PRNG algorithm to produce a sequence of random numbers. When generating random numbers, the pseudo-random number generator often begins with an initial value (seed). This seed can be a fixed value or dynamically generated based on the system time or other unpredictable values. Common PRNG algorithms include the Linear Congruential Generator (LCG) and the Mersenne Twister algorithm. These PRNG algorithms use the seed value to generate new random numbers and use this value as the new seed value to generate the next random number.

[0055] When building a real-world random number testing environment, due to the deterministic nature of the PRNG algorithm, the PRNG will generate identical random sequences due to factors such as the same seed value, the algorithm's periodicity (primarily manifested), and the limited output space for a random number generator with a specific bit width. For example, if the same seed value is used in different simulation runs, the PRNG will generate the same random sequence, resulting in repetitive simulation results. Furthermore, the periodicity of the PRNG means that after the operation exceeds its own period, the generated numbers will begin to repeat. Therefore, repeated random values ​​may occur during long runs or when generating large numbers of random numbers. Furthermore, for a random number generator with a specific bit width (e.g., 32 bits), the output space is limited (2^32 possible values), increasing the probability of identical values ​​when generating large numbers of random numbers.

[0056] This application is mainly aimed at solving the algorithmic periodicity drawback of the random generator in the above-mentioned prior art. Under the limitation of the algorithmic periodicity of the above-mentioned random generator, even with different random seeds, the same random value will still be generated without traversing all possible values, thereby reducing the overall random efficiency.

[0057] Based on this, the industry is still in urgent need of a new random testing solution so that the random value generated by the next random test is different from the random value generated previously, thereby effectively improving random efficiency.

[0058] In view of the above, in order to solve the problems of the prior art, the embodiments of the present application provide a random testing method, device and equipment. It should be noted that the embodiments provided in this application are not intended to limit the scope of the disclosure of this application.

[0059] The following first introduces the random testing method provided in the embodiment of the present application.

[0060] Figure 1 The flowchart of the random testing method provided by an embodiment of the present application is shown. The random testing method is applied to an electronic device, which may include a server or a user terminal. Figure 1 As shown, the random testing method includes the following steps:

[0061] S110, obtaining a target queue corresponding to a target random test variable, wherein the target queue records N historical random values ​​of the target random test variable, where N is a non-negative integer;

[0062] S120, generating a first random value of a target random test variable based on the target queue, where the first random value is different from N historical random values ​​recorded in the target queue;

[0063] S130: Perform a random test on the design chip to be tested based on the first random value.

[0064] An embodiment of the present application provides a random testing method that obtains a target queue corresponding to a target random test variable, wherein the target queue records N historical random values ​​of the target random test variable. Then, based on the target queue, a first random value of the target random test variable is generated. The first random value is different from the N historical random values ​​recorded in the target queue, and the first random value can be used for random testing of a design chip under test.

[0065] As can be seen from the above description, a random testing method according to an embodiment of the present application enables a "communication" between a large number of random tests through a target queue. This is equivalent to using the target queue to inform the next random test that the previous random test generated certain values, thereby ensuring that the random values ​​generated by this random test are different from those generated previously. This significantly improves the random efficiency of the overall verification test of the chip under test.

[0066] The specific implementation of the above steps 110 to 130 is described in detail below.

[0067] In S110 , during specific implementation, a target queue corresponding to the target random test variable is obtained, and the target queue records N historical random values ​​of the target random test variable, where N is a non-negative integer.

[0068] The target random test variable is, for example, a random variable defined in SystemVerilog. The target random test variable can directly or indirectly constitute a component of the stimulus of the design chip to be tested, thereby achieving random testing of the design chip to be tested.

[0069] The target random test variable may be set with a fixed bit width of a value, and the fixed bit width (bit) determines the possible values ​​of the target random test variable.

[0070] The target queue may be pre-defined in SystemVerilog, and the target queue may be defined to store and record the random values ​​of the target random test variable.

[0071] In S120 , during specific implementation, a first random value of a target random test variable is generated based on the target queue, and the first random value is different from the N historical random values ​​recorded in the target queue.

[0072] It should be noted that when generating the first random value of the target random test variable, the random generation of the above-mentioned first random value can be achieved by combining PRNG algorithms such as linear congruential generator and Mersenne twister algorithm, and no strict restrictions are imposed here.

[0073] According to some embodiments of the present application, optionally, in order to more reasonably implement "communication" between random tests, so that the first random value randomly generated this time is different from the random value generated previously, the above-mentioned generating the first random value of the target random test variable based on the target queue includes:

[0074] Generate candidate random values ​​for the target random test variable;

[0075] Perform traversal comparison on the candidate random value and the N historical random values ​​in the target queue to obtain the traversal comparison result of the candidate random value;

[0076] If the traversal comparison result indicates that each of the N historical random values ​​is different from the candidate random value, the candidate random value is determined as the first random value;

[0077] If the traversal comparison result indicates that the target historical random value exists in the N historical random values, jump to the step of generating a candidate random value of the target random test variable to generate a new candidate random value of the target random test variable until each of the N historical random values ​​is different from the candidate random value;

[0078] The target historical random value is the same historical random value as the candidate random value.

[0079] In a specific implementation, for example, a PRNG algorithm, such as a linear congruential generator or a Mersenne twister algorithm, can be used to generate a candidate random value for the target random test variable. After generating the candidate random value, the candidate random value is traversed and compared with N historical random values ​​in the target queue to obtain a traversal comparison result for the candidate random value.

[0080] In this way, when the traversal comparison result indicates that each of the N historical random values ​​is different from the candidate random value, it means that the candidate random value is not repeated with the aforementioned generated random value. At this time, the candidate random value can be determined as the first random value.

[0081] When the traversal comparison result indicates that the target historical random value and the candidate random value exist among the N historical random values, the corresponding PRNG algorithm can be used to continue to generate new candidate random values ​​of the target random test variable, and perform a new round of traversal comparison with the N historical random values ​​in the target queue until each of the N historical random values ​​is different from the candidate random value.

[0082] In this embodiment, a candidate random value is generated and then compared with N historical random values ​​to determine whether they overlap. This determines whether the candidate random value is the same as the previously generated random value. Only when the current candidate random value is different from all N historical random values ​​in the target queue will the candidate random value be determined as the first random value generated. In this way, the judgment of whether there is duplication between random tests can be more fully realized, so that the first random value generated this time is different from the random value generated previously, which helps to improve the overall efficiency of random testing.

[0083] According to some embodiments of the present application, optionally, for reasons similar to those in the above embodiments, in order to more reasonably implement "communication" between random tests, so that the first random value randomly generated this time is different from the random value generated previously, the above-mentioned generating the first random value of the target random test variable based on the target queue includes:

[0084] Get M possible values ​​of the target random test variable, where M is a positive integer;

[0085] Compare the M possible values ​​with the N historical random values ​​to determine MN candidate random values ​​that have not been randomly selected;

[0086] A first random value is generated based on MN candidate random values, where the MN candidate random values ​​include the first random value.

[0087] In a specific implementation, for example, if the target random test variable is random variable bit[2:0]a, the target random test variable a has 8 possible values, and the M possible values ​​of the target random test variable a are 0, 1, 2, 3, 4, 5, 6, and 7. In this case, the N historical random values ​​that have been randomly selected and recorded in the target queue are, for example, 0, 1, 3, 5, and 6.

[0088] Then, by comparing the M possible values ​​0, 1, 2, 3, 4, 5, 6, and 7 with the N historical random values ​​0, 1, 3, 5, and 6, we can obtain MN candidate random values ​​2, 4, and 7 that have not been randomly selected. After determining the above MN candidate random values, a candidate random value can be randomly selected from the MN candidate random values ​​as the above first random value.

[0089] In this way, this embodiment can also ensure that the first random value randomly generated this time is different from the random value generated previously, thereby helping to improve the overall random test efficiency.

[0090] In S130 , during specific implementation, a random test is performed on the design chip to be tested based on the first random value.

[0091] In this embodiment, each random value of the target random test variable can constitute a component of the stimulus of the design chip to be tested, providing a random test environment for the design chip to be tested, thereby effectively implementing random testing of the design chip to be tested.

[0092] According to some embodiments of the present application, optionally, in order to achieve sufficient recording of the random values ​​of the target random test variable generated by the target queue, so as to continuously ensure the exchange of random values ​​in the random test based on the target sequence, thereby effectively avoiding the generation of the same random value without traversing all possible values, after generating the first random value of the target random test variable based on the target queue, the random testing method further includes:

[0093] Write the first random value into the target queue.

[0094] According to some embodiments of the present application, optionally, considering that the number of possible values ​​of the target random test variable is limited, when all possible values ​​of the target random test variable have been randomized, the target queue can be cleared to ensure the random value exchange function of the target queue in the random test. Based on this, after writing the first random value into the target queue, the random testing method further includes:

[0095] Obtain the first value quantity of the target random test variable stored in the target queue;

[0096] Compare the first value quantity with the second value quantity to obtain a comparison result, where the second value quantity is the maximum value quantity supported by the value bit width of the target random test variable;

[0097] When the comparison result indicates that the first value quantity is greater than or equal to the second value quantity, the random values ​​of the target random test variables recorded in the target queue are cleared.

[0098] More specifically, if the comparison result indicates that the first number of values ​​is less than the second number of values, generating a second random value of the target random test variable based on the target queue;

[0099] The second random value is different from the N historical random values ​​and the first random value recorded in the target queue; the second random value is used for random testing of the designed chip to be tested.

[0100] In specific implementation, for example, the first number of values ​​of the target random test variable stored in the target queue is obtained. For example, the target queue records N historical random values ​​of the target random test variable a that have been randomized, such as 0, 1, 2, 3, 4, 5, 6, 7, then the first number of values ​​is 5.

[0101] If the target random test variable a is the random variable bit[2:0]a, the target random test variable a has 8 possible values ​​0, 1, 2, 3, 4, 5, 6, and 7, that is, the second value number is 8. In this case, the first value number is equal to the second value number, indicating that all possible values ​​of the target random test variable have been randomized.

[0102] In this case, by clearing the target queue, it is ensured that in the next round of randomness of the target random test variable a, the target queue can still fully exert its random value exchange function in the random test, thereby ensuring that the first random value generated subsequently is different from the random value generated previously, which helps to improve the overall random test efficiency.

[0103] Alternatively, in another example, the target queue records N historical random values ​​of the target random test variable a that have been randomly generated, such as 0, 1, 3, 5, and 6, and the first value quantity is 5. If the target random test variable is the random variable bit[2:0]a, the second value quantity corresponding to the target random test variable is 8, and the first value quantity is less than the second value quantity.

[0104] In this case, a second random value of the target random test variable can be generated based on the target queue for subsequent random testing of the design chip to be tested. This second random value is different from the N historical random values ​​and the first random value recorded in the target queue, thereby effectively improving random efficiency.

[0105] According to some embodiments of the present application, optionally, in combination with the actual language environment of random testing, in order to more reasonably write the first random value into the target queue so as to achieve sufficient recording of the random value of the generated target random test variable by the target queue, after generating the first random value of the target random test variable based on the target queue, the random testing method further includes:

[0106] The first random value is stored in a target file, and the target file is provided to the design chip to be tested, so that the design chip to be tested performs a random test based on the random value stored in the target file;

[0107] Write the first random value into the target queue, including:

[0108] The first random value is read from the target file and written into the target queue.

[0109] In this embodiment, the target file may be, for example, a txt file. By storing the first random value in the txt file, the first random value may be stored in the form of plain text information.

[0110] When performing random testing on a specific chip to be tested, for example, the target file can be input into a verification platform corresponding to the chip to be tested, so that the chip to be tested performs random testing based on the random values ​​stored in the target file. This is not strictly limited here.

[0111] After the first random value is stored in the target file, the first random value can be read from the target file to more reasonably record and store the first random value in the target queue. The data format conversion operations that may be involved in the reading and writing processes are not described in detail in this embodiment.

[0112] In combination with the solution provided in the above embodiment, in which when all possible values ​​of the target random test variable are randomized, the target queue is cleared to ensure the random value exchange function of the target queue in the random test, after comparing the first value quantity with the second value quantity and obtaining the comparison result, the random testing method further includes:

[0113] When the comparison result indicates that the first value quantity is greater than or equal to the second value quantity, the random values ​​of the target random test variables stored in the target file are cleared.

[0114] In this embodiment, if the comparison result indicates that the number of first values ​​is greater than or equal to the number of second values, it means that all possible values ​​of the target random test variable in the current random round have been randomly selected. In this case, the target file is cleared so that the cleared target file can continue to store new random values ​​in the next random round of the target random test variable.

[0115] To facilitate understanding of the random testing method provided by the above embodiment, the above method is described below using a specific scenario embodiment. To facilitate understanding of this embodiment, before describing the application scenario of this scenario embodiment, the transaction class in SystemVerilog is first introduced.

[0116] Specifically, the Transaction class in SystemVerilog serves as the source of stimulus generation in IC verification. It defines necessary random variables and control variables. These variables directly or indirectly form part of the stimulus, ultimately acting on the chip under test.

[0117] For example, in a transaction class in a test environment, there is a random variable bit[2:0]a. This variable a has eight possible values: 0, 1, 2, 3, 4, 5, 6, and 7. In actual random testing, it is necessary to ensure that the random values ​​of variable a are different in the first eight tests to effectively improve the efficiency of random testing and avoid the same random value being used in random testing without traversing all possible values.

[0118] This scenario embodiment may specifically include the following implementation steps:

[0119] 1. Implement a transaction class, for example, my_trans, and define a random variable named rand bit[2:0]a, which corresponds to the target random test variable in the aforementioned embodiment of the present application.

[0120] 2. Define a target queue bit[2:0]a_q[$], which is used to record the historical random values ​​of the target random test variable a.

[0121] 3. Declare the variable int a_all_posible_num, which can be used to calculate the number of possible values ​​of the target random test variable a. In this scenario, the target random test variable a has 8 possible values, that is, the value of the variable int a_all_posible_num is 8.

[0122] 4. Implement a function in the my_trans class: load_previous_avaluse(). This function opens a file called a.txt and reads the most recent random value of the target random test variable a from that file, storing it in the bit[2:0]a_q[$] queue. This a.txt file corresponds to the target file in the previous example.

[0123] 5. Implement a function in the my_trans class: check_if_clear_atxt() . This function calculates the number of possible outcomes for the target random test variable a (the second number of possible values) and then compares this number with the number of random values ​​that the target random test variable a has already obtained (the first number of possible values) in the a_q[$] queue.

[0124] When the number of random values ​​of the target random test variable a stored in the target queue is greater than or equal to the number of possible values ​​of the target random test variable a, it indicates that the target random test variable a has been exhausted as the number of random times increases. In order to ensure that the next round of randomization can proceed normally, the a.txt file needs to be cleared.

[0125] 6. Implement a function in the my_trans class: write_the_new_avalue_to_txt(int a). The purpose of this function is to save the newly generated random value of the target random test variable a to the file a.txt for subsequent random testing of the design chip under test.

[0126] 7. Implement a constraint: unique_a. The purpose of the constraint: unique_a constraint is to ensure that the random value generated by the current target random test variable a and the historical random values ​​of the target random test variable a recorded in the a_q[$] queue are not repeated.

[0127] 8. Before generating random values, in the pre_randomize() function, execute the function: load_previous_avaluse(), and then execute the function: check_if_clear_atxt(). The functions of the above two functions have been explained in items 4 and 5.

[0128] 9. After generating the random value, execute the function write_the_new_avalue_to_txt(int a) in the post_randomize() function. The purpose of this function is explained in Section 6 above.

[0129] 10. In the actual random test, instantiate my_trans and call the built-in method randomize() in SystemVerilog to generate a random value for the target random test variable a.

[0130] It should be understood that, in actual script implementation, the specific implementation order of the above steps can be flexibly modified and configured according to actual circumstances, as long as it conforms to the random test operation logic. Furthermore, the above steps can be implemented by writing a makefile script file for test operation, and this scenario embodiment does not impose strict limitations here.

[0131] In this scenario, by establishing a "communication" between random tests, the random value generated by the next random test is different from the random value generated previously. In actual test scenarios, users can customize the implementation of the above transaction. The transaction contains many random signals, and each of these random signals corresponds to a txt file that records the values ​​generated by the random test of the corresponding random signal. Before the next random test, the pre_randomize() function is used to read the latest random value from the txt file and store these values ​​in the respective queues. Then, the random value for this time is randomly generated using the above constraints. Under the influence of the constraints, the random value generated this time is different from all previously generated random values. After the current random value is generated and before the next random value is generated, the latest random value is added to the txt file in post_randomize() for reference in subsequent random tests and for queue reading.

[0132] In a real project, the above steps can all be implemented using a script. The script can be used to parse all variables with the rand and randc modifiers in the user-defined transaction class and generate their own txt files, queues, constraints, functions, etc. based on different random variables. It should be noted here that due to the large number of random variables, the generated txt files can be hidden to fully ensure the aesthetics of the verification environment file.

[0133] In summary, the embodiment of the present application uses the target queue to allow a kind of "communication" between a large number of random tests. This is equivalent to telling the next random test through the target queue that the previous random test generated certain values, so that the random values ​​generated by this random test are different from the random values ​​generated previously. This greatly improves the random efficiency of the overall verification test of the chip under test. In addition, the random testing solution provided by the embodiment of the present application has a wide range of applicability, whether it is module-level, subsystem-level, or system-level chip verification, as long as it involves a scenario that requires random testing.

[0134] Based on the random testing method provided in the above embodiment, for the same inventive concept, the present application also provides a random testing device corresponding to the above random testing method. Figure 2 A detailed introduction to the random testing device is given.

[0135] Figure 2 A schematic structural diagram of a random testing device provided in one embodiment of the present application is shown. Figure 2 The random testing apparatus 200 shown comprises:

[0136] The first acquisition module 210 is used to obtain a target queue corresponding to a target random test variable, where the target queue records N historical random values ​​of the target random test variable, where N is a non-negative integer;

[0137] A first generating module 220 is configured to generate a first random value of a target random test variable based on a target queue, where the first random value is different from the N historical random values ​​recorded in the target queue;

[0138] The first testing module 230 is configured to perform a random test on the design chip to be tested based on a first random value.

[0139] The random test device provided by the present application is configured with corresponding functional modules to obtain a target queue corresponding to a target random test variable. The target queue records N historical random values ​​of the target random test variable. Then, based on the target queue, a first random value of the target random test variable is generated. The first random value is different from the N historical random values ​​recorded in the target queue. This first random value can be used for random testing of a design chip under test.

[0140] As can be seen from the above description, a random test device according to an embodiment of the present application uses a target queue to enable "communication" between a large number of random tests. This is equivalent to using the target queue to inform the next random test that the previous random test generated certain values, thereby ensuring that the random values ​​generated by this random test are different from those generated previously. This significantly improves the random efficiency of the overall verification test of the design chip under test.

[0141] According to some embodiments of the present application, optionally, generating a first random value of a target random test variable based on a target queue includes:

[0142] A first generation submodule may be used to generate candidate random values ​​of a target random test variable;

[0143] The first traversal submodule can be used to traverse and compare the candidate random value with the N historical random values ​​in the target queue to obtain the traversal comparison result of the candidate random value;

[0144] The first determination submodule may be configured to determine the candidate random value as the first random value when the traversal comparison result indicates that each of the N historical random values ​​is different from the candidate random value;

[0145] The first loop submodule may be configured to, when the traversal comparison result indicates that the target historical random value exists in the N historical random values, jump to the step of generating a candidate random value for the target random test variable, so as to generate a new candidate random value for the target random test variable, until each of the N historical random values ​​is different from the candidate random value;

[0146] The target historical random value is the same historical random value as the candidate random value.

[0147] According to some embodiments of the present application, optionally, the first generating module 220 generates a first random value of a target random test variable based on a target queue, including:

[0148] The first acquisition submodule can be used to obtain M possible values ​​of the target random test variable, where M is a positive integer;

[0149] The second determination submodule can be used to compare the M possible values ​​with the N historical random values ​​to determine MN candidate random values ​​that have not been randomly selected;

[0150] The second generating submodule may be configured to generate a first random value based on MN candidate random values, where the MN candidate random values ​​include the first random value.

[0151] According to some embodiments of the present application, optionally, after generating the first random value of the target random test variable based on the target queue, the random testing device further includes:

[0152] The first writing module can be used to write the first random value into the target queue.

[0153] According to some embodiments of the present application, optionally, after writing the first random value into the target queue, the random testing device further includes:

[0154] The second acquisition module can be used to obtain the first value quantity of the target random test variable stored in the target queue;

[0155] A first obtaining module may be used to compare the first value quantity with the second value quantity to obtain a comparison result, where the second value quantity is the maximum value quantity supported by the value bit width of the target random test variable;

[0156] The first case module can be used to clear the random values ​​of the target random test variable recorded in the target queue when the comparison result indicates that the first value quantity is greater than or equal to the second value quantity.

[0157] According to some embodiments of the present application, optionally, after comparing the first value quantity with the second value quantity to obtain a comparison result, the random testing device further includes:

[0158] A second generating module may be configured to generate a second random value of the target random test variable based on the target queue if the comparison result indicates that the number of first values ​​is less than the number of second values;

[0159] The second random value is different from the N historical random values ​​and the first random value recorded in the target queue; the second random value is used for random testing of the designed chip to be tested.

[0160] According to some embodiments of the present application, optionally, after generating a first random value of a target random test variable based on a target queue, the random testing apparatus further includes:

[0161] The first storage module may be used to store the first random value in a target file, and the target file is used to provide the target chip to be tested so that the target chip to be tested performs a random test based on the random value stored in the target file;

[0162] The first writing module writes the first random value into the target queue, including:

[0163] The first random value is read from the target file and written into the target queue.

[0164] According to some embodiments of the present application, optionally, after comparing the first value quantity with the second value quantity to obtain a comparison result, the random testing device further includes:

[0165] The second case module can be used to clear the random values ​​of the target random test variables stored in the target file when the comparison result indicates that the first value quantity is greater than or equal to the second value quantity.

[0166] Based on the random testing method provided in the above embodiment, for the same inventive concept, the present application also provides a random testing device corresponding to the above random testing method, which is described below. Figure 3 Provide a detailed introduction to random testing equipment.

[0167] See below Figure 3 , Figure 3 It is a structural diagram of a random testing device provided in one embodiment of the present application.

[0168] The random testing device may include a processor 301 and a memory 302 storing computer program instructions.

[0169] Specifically, the processor 301 may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0170] The memory 302 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 302 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 302 may include removable or non-removable (or fixed) media. Where appropriate, the memory 302 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 302 is a non-volatile solid-state memory.

[0171] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0172] The processor 301 implements any one of the random testing methods in the above embodiments by reading and executing computer program instructions stored in the memory 302 .

[0173] In one example, the data random test device may further include a communication interface 303 and a bus 310. Figure 3As shown, the processor 301 , the memory 302 , and the communication interface 303 are connected via a bus 310 and communicate with each other.

[0174] The communication interface 303 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0175] Bus 310 comprises hardware, software or both, couples the parts of random test equipment to each other.For example, and not limitation, bus can comprise accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations.In suitable cases, bus 310 can comprise one or more buses.Although the present application embodiment describes and shows specific bus, the application considers any suitable bus or interconnection.

[0176] The random testing device executes the random testing method in the embodiment of the present application, thereby realizing the random testing method described in the embodiment of the present application.

[0177] In addition, in conjunction with the random testing method in the above embodiments, the present application embodiment may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the random testing methods in the above embodiments is implemented.

[0178] Based on the random testing method in the above embodiments, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the random testing method provided in any one of the above embodiments of the present application.

[0179] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0180] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0181] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0182] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It is also understood that each box in the block diagram and / or flowchart and the combination of the boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0183] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A random testing method, characterized in that: The method comprises: Obtain a target queue corresponding to a target random test variable, wherein the target queue records N historical random values ​​of the target random test variable, where N is a non-negative integer; Based on the target queue, generating a first random value of the target random test variable, wherein the first random value is different from the N historical random values ​​recorded in the target queue; Based on the first random value, a random test is performed on the design chip to be tested.

2. The method according to claim 1, characterized in that The step of generating a first random value of the target random test variable based on the target queue includes: generating candidate random values ​​for the target random test variable; Perform traversal comparison on the candidate random value and the N historical random values ​​in the target queue to obtain a traversal comparison result of the candidate random value; When the traversal comparison result indicates that each of the N historical random values ​​is different from the candidate random value, determining the candidate random value as the first random value; In the case where the traversal comparison result indicates that the target historical random value exists in the N historical random values, jump to the step of generating a candidate random value of the target random test variable to generate a new candidate random value of the target random test variable, until each of the N historical random values ​​is different from the candidate random value; The target historical random value is the same historical random value as the candidate random value.

3. The method according to claim 1, characterized in that The step of generating a first random value of the target random test variable based on the target queue includes: Obtain M possible values ​​of the target random test variable, where M is a positive integer; Compare the M possible values ​​with the N historical random values ​​to determine MN candidate random values ​​that have not been randomly selected; The first random value is generated based on the MN candidate random values, and the MN candidate random values ​​include the first random value.

4. The method according to claim 1, characterized in that: After generating a first random value of the target random test variable based on the target queue, the method further includes: The first random value is written into the target queue.

5. The method according to claim 4, characterized in that After writing the first random value into the target queue, the method further includes: Obtaining the first value quantity of the target random test variable stored in the target queue; Compare the first value number with the second value number to obtain a comparison result, where the second value number is the maximum value number supported by the value bit width of the target random test variable; When the comparison result indicates that the first value quantity is greater than or equal to the second value quantity, the random values ​​of the target random test variables recorded in the target queue are cleared.

6. The method according to claim 5, characterized in that After comparing the first value quantity with the second value quantity to obtain a comparison result, the method further includes: If the comparison result indicates that the first value quantity is less than the second value quantity, generating a second random value of the target random test variable based on the target queue; The second random value is different from the N historical random values ​​and the first random value recorded in the target queue; the second random value is used for random testing of the designed chip to be tested.

7. The method according to claim 5, characterized in that After generating a first random value of the target random test variable based on the target queue, the method further includes: storing the first random value in a target file, wherein the target file is provided to the design chip to be tested, so that the design chip to be tested performs a random test based on the random value stored in the target file; Writing the first random value into the target queue includes: The first random value is written into the target queue by reading the first random value in the target file.

8. The method according to claim 7, characterized in that After comparing the first value quantity with the second value quantity to obtain a comparison result, the method further includes: When the comparison result indicates that the first value quantity is greater than or equal to the second value quantity, the random value of the target random test variable stored in the target file is cleared.

9. A random testing device, characterized in that: The device comprises: A first acquisition module is used to acquire a target queue corresponding to a target random test variable, wherein the target queue records N historical random values ​​of the target random test variable, where N is a non-negative integer; A first generating module, configured to generate a first random value of the target random test variable based on the target queue, wherein the first random value is different from the N historical random values ​​recorded in the target queue; The first testing module is used to perform a random test on the design chip to be tested based on the first random value.

10. A random testing device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the random testing method according to any one of claims 1 to 8 is implemented.

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