Circuit breaker power module layout optimization method and system based on multi-chip current sharing

Abstract

The application provides a circuit breaker power module layout optimization method and system based on multi-chip current sharing, relates to the technical field of power electronics, collects parasitic parameters of a circuit breaker power module, and constructs a first switching transient circuit model according to the parasitic parameters; based on the first switching transient circuit model and conduction transient characteristics, a conduction transient process circuit is constructed; current balance is performed on the conduction transient process circuit according to a common-source inductance compensation function, so as to update the state of the conduction transient process circuit, obtain a second switching transient circuit model corresponding to the conduction transient process circuit after state updating, extract parasitic inductance parameters in the second switching transient circuit model by using an ANSYS Q3D simulation tool, and through multiple iterative optimization of the copper layer shape and copper layer size of each power tube in the second switching transient circuit model by finite element simulation according to the common-source inductance compensation function and the parasitic inductance parameters, an optimized layout scheme of the circuit breaker power module is obtained. The application is helpful to avoid the local overload problem caused by uneven current distribution, and improves the current sharing degree of devices under the multi-chip parallel connection condition.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, and particularly relates to a circuit breaker power module layout optimization method and system based on multi-chip current sharing. BACKGROUND

[0002] In recent years, with the rapid development of power electronics technology, the requirements for power devices are becoming higher and higher. SiC MOSFET has higher switching speed, lower on-state loss and higher blocking voltage than traditional Si MOSFET, and can improve system efficiency, reduce device size and improve device power density. However, due to the current process level and cost constraints under specific requirements, the current-carrying capacity of a single SiC MOSFET is limited and cannot meet the requirements of high-power applications. Therefore, multiple SiC MOSFETs are often used in parallel, and this parallel application scheme is widely used in motor control and inverter fields.

[0003] A Chinese patent with publication number CN113392552B discloses a multi-parallel switching device current sharing optimization design method based on finite element simulation. The multi-parallel switching device includes a driving module, a first switching tube device, a second switching tube device, …, and an nth switching tube device. The length of the wire between the driving module and the switching device is artificially set. According to the structural symmetry principle between the first switching tube device, the second switching tube device, …, and the nth switching tube device, the circuit board is designed through AltiumDesigner software. The target parasitic inductance value is determined. The required error is set. The width of the wire between the driving module and the switching device is calculated in combination with the target parasitic inductance value. The width of the wire between the driving module and the switching device is optimized through finite element simulation multiple times. However, the method provided in the above-mentioned application can aggravate the magnetic coupling between the multiple current loops, and is not easy to package and integrate the power module and subsequently use in parallel, resulting in a decrease in the device current sharing degree. Therefore, it is necessary to provide a circuit breaker power module layout optimization method and system based on multi-chip current sharing to improve the device current sharing degree under the multi-chip parallel condition. SUMMARY

[0004] Therefore, the present application provides a circuit breaker power module layout optimization method and system based on multi-chip current sharing. By optimizing the current balance of the on-state transient process circuit, the current sharing between multiple power devices is realized, the local overload problem caused by uneven current distribution is avoided, and the device current sharing degree under the multi-chip parallel condition is improved.

[0005] The present application provides a circuit breaker power module layout optimization method based on multi-chip current sharing, which comprises:

[0006] Collecting a parasitic parameter of a circuit breaker power module, and constructing a first switch transient circuit model according to the parasitic parameter;

[0007] Constructing a conduction transient process circuit based on the first switch transient circuit model and a conduction transient characteristic;

[0008] According to a common-source inductance compensation function, current equalization is performed on the conduction transient process circuit to update the state of the conduction transient process circuit, and a second switch transient circuit model corresponding to the conduction transient process circuit after state updating is obtained;

[0009] The ANSYS Q3D simulation tool is used to extract a parasitic inductance parameter in the second switch transient circuit model, and according to the common-source inductance compensation function and the parasitic inductance parameter, the copper layer shape and size of each power tube in the second switch transient circuit model are iteratively optimized multiple times through finite element simulation, so as to obtain an optimized layout scheme of the circuit breaker power module.

[0010] On the basis of the above technical scheme, preferably, the parasitic parameters of the circuit breaker power module include a parasitic inductance between the drain and the positive terminal of each power tube in the circuit breaker power module, a parasitic inductance between the source and the negative terminal of each power tube, and a coupling inductance between two parallel power tubes.

[0011] On the basis of the above technical scheme, preferably, the conduction transient process circuit includes a circuit driving unit, a plurality of parallel switch units, an equalization and voltage stabilization unit, and a power supply, wherein,

[0012] The first common end of the plurality of parallel switch units is electrically connected with the first end of the circuit driving unit, one end of the equalization and voltage stabilization unit, and the positive electrode of the power supply, respectively; the second common end of the plurality of parallel switch units is electrically connected with the second end of the circuit driving unit, the other end of the equalization and voltage stabilization unit, and the negative electrode of the power supply, respectively; and the third common end of the plurality of parallel switch units is electrically connected with the third end of the circuit driving unit.

[0013] Further preferably, the parallel switch unit includes a first MOS tube, a second MOS tube, a first parasitic inductance, a second parasitic inductance, and a common-source inductance, wherein,

[0014] The gate of the first MOS transistor is electrically connected with the first end of the circuit driving unit and the rest of the parallel switch units respectively, the drain of the first MOS transistor is electrically connected with one end of the first parasitic inductance, the other end of the first parasitic inductance is electrically connected with the rest of the parallel switch units respectively, the source of the first MOS transistor is electrically connected with one end of the common source inductance, the common end of the common source inductance and the second parasitic inductance is electrically connected with the third end of the circuit driving unit and the rest of the parallel switch units respectively, the other end of the second parasitic inductance is electrically connected with the source of the second MOS transistor, the gate of the second MOS transistor is electrically connected with the second end of the circuit driving unit and the rest of the parallel switch units respectively, and the drain of the first MOS transistor is electrically connected with the rest of the parallel switch units and one end of the equalizing voltage stabilizing unit.

[0015] More preferably, the expression of the common source inductance compensation function is:

[0016] L Loop = L D + L com + L S

[0017]

[0018] wherein L LOOP represents the loop inductance of the parallel switch unit, L D represents the parasitic inductance between the drain of the MOS transistor and the positive terminal of the DC power supply, L S represents the parasitic inductance between the source of the MOS transistor and the negative terminal of the DC power supply, L com represents the common source inductance value in the parallel switch unit, ΔI 1-2 represents the circulating current between the first parallel switch unit and the second parallel switch unit in the frequency domain form, s represents the Laplace operator, I d1 represents the drain current of the first parallel switch unit in the frequency domain form, I d2 represents the drain current of the second parallel switch unit in the frequency domain form, ΔI d1-2 represents the difference value of the drain currents of the first parallel switch unit and the second parallel switch unit in the frequency domain form, ΔL Loop1-2 represents the difference value of the loop inductances between the first parallel switch unit and the second parallel switch unit in the frequency domain form, ΔL com represents the difference value of the common source inductances between the first parallel switch unit and the second parallel switch unit in the frequency domain form, ΔL Loop represents the difference value of the loop inductances between the first parallel switch unit and the nth parallel switch unit in the frequency domain form, L Loop1 represents the loop inductance of the first parallel switch unit, Lcom1 represents a common source inductance value in the first parallel switch unit.

[0019] Further preferably, the step of extracting the parasitic inductance parameter in the second switch transient circuit model by using the ANSYS Q3D simulation tool comprises:

[0020] The second switch transient circuit model is imported into the ANSYS Q3D simulation tool, and material settings are performed on the second switch transient circuit model to obtain a transition switch transient circuit model.

[0021] The transition switch transient circuit model is sequentially subjected to meshing operations, and the current inflow end and the current outflow end of each mesh in the transition switch transient circuit model are correspondingly set with excitations.

[0022] The transition switch transient circuit model is simulated to obtain an inductance matrix corresponding to the transition switch transient circuit model and the parasitic inductance parameter in the transition switch transient circuit model.

[0023] Further preferably, each mesh in the transition switch transient circuit model comprises a plurality of current inflow ends and one current outflow end, and the current inflow ends and the current outflow end are edges or faces in the transition switch transient circuit model.

[0024] Further preferably, the equalizing and stabilizing unit comprises a first stabilizing diode, a second stabilizing diode, and a load inductor, the anode of the first stabilizing diode is electrically connected with the first common end of the plurality of parallel switch units and one end of the load inductor, the cathode of the first stabilizing diode is electrically connected with the cathode of the second stabilizing diode, the anode of the second stabilizing diode is electrically connected with the second common end of the plurality of parallel switch units and the negative electrode of the power supply, and the other end of the load inductor is electrically connected with the positive electrode of the power supply.

[0025] In a second aspect of the present application, a circuit breaker power module layout optimization system based on multi-chip current sharing is provided, which comprises a circuit construction module, a current equalization module, and a layout optimization module, wherein,

[0026] The circuit construction module is configured to collect parasitic parameters of a circuit breaker power module, and construct a first switch transient circuit model according to the parasitic parameters, and construct a conduction transient process circuit based on the first switch transient circuit model and conduction transient characteristics.

[0027] The current equalization module is configured to equalize the current of the turn-on transient process circuit according to a common-source inductance compensation function, to update the state of the turn-on transient process circuit, and obtain a second switch transient circuit model corresponding to the turn-on transient process circuit after state updating.

[0028] The layout optimization module is configured to extract a parasitic inductance parameter in the second switch transient circuit model by using an ANSYS Q3D simulation tool, to perform multiple iterative optimizations on the copper layer shape and size of each power tube in the second switch transient circuit model by finite element simulation according to the common-source inductance compensation function and the parasitic inductance parameter, and to obtain an optimized layout scheme of the circuit breaker power module.

[0029] In a third aspect of the present application, a computer device is provided, which comprises a memory and a processor, the memory storing a computer program, and the computer program being executed by the processor to enable the processor to perform the steps of the circuit breaker power module layout optimization method based on multi-chip current sharing.

[0030] The circuit breaker power module layout optimization method and system based on multi-chip current sharing provided by the present application have the following beneficial effects over the prior art:

[0031] (1) By establishing a detailed switch transient circuit model, combining with the turn-on transient characteristics, a more accurate turn-on transient process circuit model is constructed, which can better reflect the voltage and current changes in the actual switching process, and is helpful for more accurately predicting and controlling the switching performance. At the same time, by optimizing the current equalization of the turn-on transient process circuit, current sharing among multiple power devices is realized, avoiding the problem of local overload caused by uneven current distribution, improving the device current sharing degree under the condition of multi-chip parallel connection, effectively avoiding the decline of power module current-carrying capacity and irreversible device damage caused by uneven current, to meet the demand for power module current-carrying capacity and use stability in solid-state circuit breaker applications.

[0032] (2) By meshing and exciting the transition switch transient circuit model, the actual current distribution can be more accurately simulated, so as to obtain more accurate inductance matrix and parasitic inductance parameters. At the same time, ANSYS Q3D simulation can more comprehensively consider the influence of circuit topology, material properties and other factors on parasitic parameters, improving the accuracy of parameter extraction, which is helpful for more accurately predicting and controlling electromagnetic interference and thermal stress and other problems in the switching transient process, and improving the electromagnetic compatibility and reliability of the optimized layout scheme. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative work based on these drawings also belong to the protection scope of the present application.

[0034] Figure 1 A flowchart of a circuit breaker power module layout optimization method based on multi-chip current sharing provided by the present application is shown in the figure.

[0035] Figure 2 A structure diagram of a turn-on transient process circuit provided by the present application is shown in the figure.

[0036] Figure 3 A simulation waveform diagram of a second switch transient circuit model provided by the present application is shown in the figure.

[0037] Figure 4 A framework diagram of a circuit breaker power module layout optimization system provided by the present application is shown in the figure.

[0038] Legend: 1, circuit driving unit; 2, parallel switch unit; 3, balance voltage stabilizing unit; 4, power supply; 5, new energy equipment system maintenance decision system; 51, information acquisition module; 52, fault operation module; 53, decision optimization module. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below, obviously, the described embodiments only are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work also belong to the protection scope of the present application.

[0040] The present application discloses a circuit breaker power module layout optimization method based on multi-chip current sharing, referring to Figure 1 The steps of the method include S1-S4.

[0041] Step S1, collect the parasitic parameters of the circuit breaker power module, and construct a first switch transient circuit model according to the parasitic parameters.

[0042] In this embodiment, for simplifying the analysis process, only the parasitic inductance caused by packaging in the circuit breaker power module is considered, which usually includes the upper copper of DBC, bonding wire, and lead terminal. The four-terminal measurement method can be used to calculate the equivalent inductance by measuring the voltage drop and current between the upper copper of DBC, or the LCR tester can be used to directly measure the inductance between the upper copper of DBC. The equivalent inductance can be calculated by measuring the voltage drop and current of the bonding wire segment from the MOSFET to the DBC, or directly measured using a special test probe for the bonding wire. The equivalent inductance is calculated by measuring the voltage drop and current of the wire segment from the DBC to the external lead terminal, or the inductance of the lead terminal segment is directly measured using the LCR tester.

[0043] In this embodiment, the parasitic parameters of the circuit breaker power module include the parasitic inductance between the drain and the positive terminal of each power tube in the circuit breaker power module, the parasitic inductance between the source and the negative terminal of each power tube, and the coupling inductance between the two parallel power tubes.

[0044] Further, according to the actual structure of the power module, a topology structure diagram containing key components such as MOSFET / power tube, PCB / DBC, and lead terminal is drawn, and the parasitic inductance, capacitance, and other parameters existing in key positions such as between MOSFET / power tube, between PCB / DBC, and PCB / DBC wire are identified on the topology structure diagram. According to the topology structure diagram, a first switching transient circuit model is constructed, the switching characteristics of the MOSFET / power tube itself are modeled as ideal switches, various parasitic inductance and capacitance obtained by measurement or simulation are added around the switches, and the parasitic parameters of the PCB / DBC and the lead terminal are reasonably organized into the equivalent circuit.

[0045] Step S2, based on the first switching transient circuit model and the conduction transient characteristics, a conduction transient process circuit is constructed.

[0046] In this step, the characteristic curve of the circuit breaker power device in the conduction process is obtained, including the relationship between voltage, current, and time, and the first switching transient circuit model and the obtained conduction transient characteristics are combined to establish an equivalent circuit describing the changes of current, voltage, etc. in the conduction process of the entire power module, i.e. the conduction transient process circuit.

[0047] In circuit modeling, the parasitic inductance corresponding to the packaging of a certain MOSFET is divided into L D , L com and L S three parts. For simplification, the parasitic parameters corresponding to two MOSFETs in the parallel switching unit are combined and represented. L DL represents the parasitic inductance between the drain of the MOSFET chip and the terminal leading to the positive terminal of the DC power supply. S L represents the parasitic inductance between the chip source and the terminals leading out from the negative terminal of the DC power supply. com Common source inductance refers to the coupling inductance between the gate circuit and the power circuit. It includes both the shared inductance of the overlapping path between the two circuits and the mutual inductance caused by the coupling effect between the circuits.

[0048] In this embodiment, the conduction transient process circuit includes a circuit driving unit 1, multiple parallel switching units 2, a voltage equalization and regulation unit 3, and a power supply 4. The first common terminal of the multiple parallel switching units 2 is electrically connected to the first terminal of the circuit driving unit 1, one terminal of the voltage equalization and regulation unit 3, and the positive terminal of the power supply 4, respectively. The second common terminal of the multiple parallel switching units 2 is electrically connected to the second terminal of the circuit driving unit 1, the other terminal of the voltage equalization and regulation unit 3, and the negative terminal of the power supply 4, respectively. The third common terminal of the multiple parallel switching units 2 is electrically connected to the third terminal of the circuit driving unit 1.

[0049] Further, the parallel switching unit 2 includes a first MOSFET, a second MOSFET, a first parasitic inductor, a second parasitic inductor, and a common source inductor. The gate of the first MOSFET is electrically connected to the first terminal of the circuit driving unit 1 and the remaining parallel switching units 2. The drain of the first MOSFET is electrically connected to one end of the first parasitic inductor. The other end of the first parasitic inductor is electrically connected to the remaining parallel switching units 2. The source of the first MOSFET is electrically connected to one end of the common source inductor. The common terminal of the common source inductor and the second parasitic inductor is electrically connected to the third terminal of the circuit driving unit 1 and the remaining parallel switching units 2. The other end of the second parasitic inductor is electrically connected to the source of the second MOSFET. The gate of the second MOSFET is electrically connected to the second terminal of the circuit driving unit 1 and the remaining parallel switching units 2. The drain of the first MOSFET is electrically connected to one end of the remaining parallel switching units 2 and the equalizing voltage regulator unit 3.

[0050] The equalizing voltage regulator unit 3 includes a first Zener diode, a second Zener diode, and a load inductor. The anode of the first Zener diode is electrically connected to the first common terminal of the multiple parallel switching units 2 and one end of the load inductor. The cathode of the first Zener diode is electrically connected to the cathode of the second Zener diode. The anode of the second Zener diode is electrically connected to the second common terminal of the multiple parallel switching units 2 and the cathode of the power supply 4. The other end of the load inductor is electrically connected to the positive terminal of the power supply 4.

[0051] In one example, such as Figure 2 As shown, the conduction transient process circuit includes a circuit driving unit, a first parallel switching unit, a second parallel switching unit, ..., an nth parallel switching unit, a voltage equalization and regulation unit, and a power supply.

[0052] The first parallel switching unit includes a MOSFET SW 11 MOSFET SW 21 Parasitic inductance L D1 Parasitic inductance L S1 and common source inductor L com1 The second parallel switching unit includes a MOSFET SW 12 MOSFET SW 22 Parasitic inductance L D2 Parasitic inductance L S2 and common source inductor L com2 The nth parallel switching unit includes a MOSFET SW 1n MOSFET SW 2n Parasitic inductance L Dn Parasitic inductance L Sn and common source inductor L comn The equalization voltage regulation unit includes Zener diode D1, Zener diode D2, and load inductor L. load .

[0053] MOSFET SW 11 Gate of MOSFET SW 12 The gate, ... and the MOSFET SW 1n The gates of all transistors are electrically connected to the first terminal of the circuit driving unit, and the MOSFET SW 11 The drain is connected to the parasitic inductance L D1 With inductor L respectively D2 One end, ..., inductor L Dn One end, load inductance L load One end of the inductor is electrically connected to the positive terminal of the Zener diode D1, and the inductor L... D2 The other end is connected to the MOSFET SW 12 The drain electrical connection, inductor L Dn The other end is connected to the MOSFET SW 1n The drain electrical connection of the MOSFET SW 11 The source and common source inductor L com1 One end is electrically connected to the MOSFET SW. 12 The source and common source inductor L com2 One end is electrically connected to the MOSFET SW. 1n The source and common source inductor L comn One end is electrically connected, common source inductor L com1 With parasitic inductance L S1 common terminal, common source inductor L com2 With parasitic inductance L S2 The common terminal, ... and the common source inductor L comn With parasitic inductance LSn The common end of the parasitic inductance L S1 is electrically connected with the third end of the circuit driving unit, and the other end of the parasitic inductance L 21 is electrically connected with the source of the MOS tube SW S2 The other end of the parasitic inductance L 22 is electrically connected with the source of the MOS tube SW Sn The other end of the parasitic inductance L 2n is electrically connected with the source of the MOS tube SW 21 The gate of the MOS tube SW 22 The gate of the MOS tube SW 2n The gate of the MOS tube SW 21 The drain of the MOS tube SW 22 The drain of the MOS tube SW 2n The drain of the MOS tube SW load is electrically connected with the positive pole of the voltage stabilizing diode D2 and the common end of the negative pole of the power supply, the negative pole of the voltage stabilizing diode D1 and the negative pole of the voltage stabilizing diode D2 are electrically connected, and the load inductance L Loop is electrically connected with the positive pole of the power supply.

[0054] In step S3, the current of the turn-on transient process circuit is balanced according to the common-source inductance compensation function, so as to update the state of the turn-on transient process circuit, and obtain a second switch transient circuit model corresponding to the turn-on transient process circuit after the state update.

[0055] In this embodiment, the expression of the common-source inductance compensation function is as follows:

[0056] L Loop =L D +L com +L S

[0057]

[0058] Wherein, L LOOP represents the loop inductance of the parallel switch unit, L D represents the parasitic inductance between the drain of the MOS tube and the positive pole of the DC power supply, L S represents the parasitic inductance between the source of the MOS tube and the negative pole of the DC power supply, L com represents the common-source inductance value in the parallel switch unit, ΔI 1-2 represents the circulating current between the branches of the first parallel switch unit and the second parallel switch unit in the frequency domain form, s represents the Laplace operator, I d1 represents the drain current of the first parallel switch unit in the frequency domain form, I d2represents the drain current of the second parallel switch unit in the frequency domain form, ΔI d1-2 represents the difference of the drain current between the first parallel switch unit and the second parallel switch unit in the frequency domain form, ΔL Loop1-2 represents the difference of the loop inductance between the first parallel switch unit and the second parallel switch unit in the frequency domain form, ΔL com represents the difference of the common source inductance between the first parallel switch unit and the nth parallel switch unit in the frequency domain form, ΔL Loop represents the difference of the loop inductance between the first parallel switch unit and the nth parallel switch unit in the frequency domain form, L Loop1 represents the loop inductance of the first parallel switch unit, L com1 represents the common source inductance of the first parallel switch unit.

[0059] It can be understood that, since the transient process of switch on and off are mirror images of each other, only the conduction process is analyzed here. At the beginning of the conduction process, the device channel current is controlled by the gate-source voltage V gs . In this transient process, the drain current through each switch is i d .

[0060] i d = g m (V gs -V th )

[0061] Since SiC MOSFET switches with similar electrical parameters are used in the device electrical parameter pre-screening process, it is considered that the transconductance g m and the threshold voltage V th between the chips are approximately equal. Let the difference of the power loop inductance between any two chips in the parallel switch unit be ΔL Loop , and the difference of the common source inductance be ΔL com , such as the difference of the power loop inductance between the first parallel switch unit and the second parallel switch unit is ΔL Loop1-2 , and the difference of the common source inductance is ΔL com1-2 , which can be represented as ΔL Loop1-2 =L Loop1 -L Loop2 and ΔL com1-2 =L com1 -L com2 .

[0062] The parasitic inductance imbalance between the first parallel switch unit and the second parallel switch unit due to the difference in packaging layout, such as the power ring of the parallel switch unit where the chip is close to the DC power terminal is smaller, so the power ring parasitic inductance is smaller. Uneven voltage drops will occur between the parallel switch units, thereby generating circulating current ΔI1-2 Taking the first and second parallel switching units as examples, for ease of representation, ΔI is shown in the frequency domain. 1-2 The calculation formula is as follows, where s is the Laplace operator:

[0063]

[0064] Common source inductor L com It acts as negative feedback between the power loop and the gate voltage, when At higher voltages, the gate-source voltage of the device will be pulled down by the voltage drop across the common-source inductor.

[0065]

[0066] Considering the negative feedback compensation effect of the common-source inductor, for ΔI 1-2 In terms of ΔI in the molecule d The calculation method will be updated, thereby making ΔI 1-2 Elimination becomes possible (without introducing L) com When, ΔI d =0), after simplification, the condition required to eliminate inter-branch circulating current is further obtained:

[0067]

[0068] This formula describes the required proportional relationship between the parasitic inductance and the common source inductance of the power loops in two branches under the condition of balanced current between branches. By properly allocating the common source inductance, when the imbalance ratio of the common source inductance between parallel switches and the imbalance ratio of the power loop are opposites, the dynamic current caused by the parasitic parameter imbalance can be compensated by the common source inductance. For example, for the power loop inductance L... Loop Smaller switches should be designed with a higher common-source inductance L. com Since the relationship between the two is in proportional form, even if a certain chip is located in branch L... Loop With L com The two values ​​differ significantly in absolute terms, but the unbalanced current can be balanced by adjusting the ratio, which provides greater flexibility in the packaging layout of the power module.

[0069] Step S4: Use ANSYS Q3D simulation tool to extract parasitic inductance parameters from the second switch transient circuit model. Based on the common source inductance compensation function and parasitic inductance parameters, perform multiple iterative optimizations on the copper layer shape and copper layer size of each power transistor in the second switch transient circuit model through finite element simulation to obtain an optimized layout scheme for the circuit breaker power module.

[0070] ANSYS Q3D is a high-efficiency electromagnetic field simulation tool mainly used for analyzing and optimizing electromagnetic design. It can be associated with large modeling tools such as solidworks and supports coupling analysis of electromagnetic fields and other physical fields (such as thermal fields), so it is suitable for modeling and solving high-frequency electromagnetic problems in three-dimensional scenes and multi-physical field coupling analysis. ANSYS Q3D provides rich geometric modeling tools that can quickly build complex three-dimensional electromagnetic structure models. When solving parasitic parameters, the grid can be automatically optimized to improve the accuracy and efficiency of the solution, and the grid can be flexibly set when dealing with complex geometric shapes and material interfaces. In this design, solidworks is used to model the internal packaging of the solid-state circuit breaker power module, and the 3D model is imported into Q3D for parasitic parameter extraction.

[0071] In this step, steps S41-S43 are also included.

[0072] In step S41, the second switch transient circuit model is imported into the ANSYS Q3D simulation tool, and the material settings of the second switch transient circuit model are set to obtain the transition switch transient circuit model.

[0073] In this step, the circuit breaker power module contains 12 SiC MOSFET chips in parallel, and the chips are arranged symmetrically up and down, with 6 chips on one side and 3 on each side. The DBC is divided into 3 layers, with the upper copper and lower copper thickness of 0.3mm, and the middle ceramic thickness of 0.32mm. The DBC ceramic substrate is 64.5mm long and 28mm wide; the upper copper is 62.5mm long and 26mm wide (including a 0.5mm round corner). The packaging drain D pin is equivalent to a rectangular sheet attached to the upper copper in the model, placed symmetrically on the right side, and the source S pin is placed on the left side in the same way, and the gate G pin is placed at the end of the right lower recessed area. Since only the parasitic inductance in the package needs to be extracted, we only need to keep the upper copper, chips and bonding wires in the model, and do not keep the modeling of the module substrate layer, solder layer, lower copper and ceramic substrate when importing the model.

[0074] After importing the simplified second switch transient circuit model into Q3D, the material settings of the second switch transient circuit model are set, and the upper copper is set to copper in Material, and the SiC chip is set to vacuum since it does not participate in the extraction of parasitic parameters, and the bonding wire is set to aluminum.

[0075] In step S42, the transition switch transient circuit model is sequentially meshed, and the current inflow end and current outflow end of each mesh in the transition switch transient circuit model are correspondingly set to excitation.

[0076] In this step, the second switch transient circuit model is automatically meshed after the material is set, and whether there is an over-defined or under-defined state at the boundary of different partitions is checked. The over-defined and under-defined states specifically refer to the material being defined multiple times or lacking definition at the boundary. The final meshing should ensure that the area where parasitic parameters need to be extracted remains continuous and uninterrupted.

[0077] In this embodiment, each mesh in the transition switch transient circuit model includes multiple current inflow ends and one current outflow end. The current inflow end and the current outflow end are edges or faces in the transition switch transient circuit model. The source and sink in net are set by referring to the current injection direction in the actual application scenario. The source refers to the current inflow end, and the sink refers to the outflow end. There can be multiple sources in the same net, but only one sink. For the actual situation where there are multiple outflow ends in a net, the excitation needs to be set in reverse in Q3D and adjusted in the corresponding inductance matrix result. The selection of source and sink should be the face or edge of the model.

[0078] After completing the excitation setting, the sweep frequency parameters are added in the simulation analysis. The sweep frequency used in this scheme is three-section, the first and third sections use linear sweep points, and the second section uses logarithmic sweep points. The corresponding sweep frequency parameter settings are shown in Table 1.

[0079] Table 1

[0080]

[0081] Step S43, simulating the transition switch transient circuit model to obtain the inductance matrix corresponding to the transition switch transient circuit model and the parasitic inductance parameters in the transition switch transient circuit model.

[0082] In this step, the transition switch transient circuit model is verified for correctness before simulation. In the simulation results, the inductance matrix is viewed. The inductance matrix is an r-order square matrix, where r is the number of nets in the mesh. The main diagonal line is the self-inductance of the net, and the rest is the mutual inductance between nets. The model can also be subjected to a matrix reduce operation before simulation, which connects different nets according to the actual flow conditions, which can reduce the number of nets and shorten the simulation time. The selected frequency range is 100MHz-1GHz, and the verification shows that the parasitic inductance has a small variation in this frequency range, which can be used as a reference.

[0083] In the circuit breaker power module, the parasitic inductance of the bonding wire on a certain chip in the circuit breaker power module is extracted. Then, the parasitic inductance near the source S end net of the model is extracted in two steps. The end of the bonding wire on the chip is defined as source. In the first step, the source outlet of the power circuit is defined as sink, and the power circuit is extracted. In the second step, the source pin of the gate circuit is redefined as sink, and part of the common source inductance L is extracted. com At this time, the common source inductor L com =L wire +L com Since the power loop source pin and the gate source pin are in the same copper layer region, according to relevant literature, this extraction method can include the influence of the mutual inductance between the gate ring and the power ring on the value of the common source inductance.

[0084] Furthermore, in the power module packaging design, an initial first version of the design scheme was provided, and the layout scheme was optimized and improved by using the common source inductor compensation theory.

[0085] The main flaw in the first design was the unusual shape of the upper copper layer in the area corresponding to the lower right gate circuit. This disrupted the symmetry of the copper layers in the branches where the upper and lower chips were located, increasing the imbalance of parasitic parameters and hindering current balancing in parallel chips. Furthermore, because the original design placed the gate circuit in the concave, elongated area on the lower right, the elongated copper layer further increased parasitic inductance and thermal resistance.

[0086] For the six chips on the lower side, the concave design of the gate circuit results in inconsistent copper layer widths near the source (S) of the three chip branches on the right side, with a significant degree of irregularity. This makes it difficult to adjust the parasitic inductance value by changing the copper layer length. According to the parasitic parameter results from ANSYS Q3D, the common source inductance L of chip 1 from the right is... com Extremely small (1-2nh), while the L of the chip at the left end... com Relatively large (approximately 30nH), compared to the total inductance L of the power circuit. Loop The trends of change are vastly different. Although they satisfy the trend law obtained from the common source inductance compensation theory, namely that the larger the parasitic inductance of the power circuit where the chip is located, the smaller the common source inductance, they obviously cannot satisfy the equation relationship.

[0087] The optimized layout first adjusted the irregular gate region, placing the gate pin on the centerline of the power module and ensuring the upper copper dimensions on the branches containing the upper and lower chips were consistent. Simultaneously, considering that connecting the left and right copper layers requires adding a bonding wire or an "I"-shaped thin copper sheet in the middle, this area has a relatively large parasitic inductance. Since only the common-source region of the left chip (from the bonding wire end face to the gate source pin) needs to pass through the middle connection area, this increases the difference in common-source parasitic inductance between the left and right chips. The common-source inductance L of the left chip... com It is still quite large.

[0088] In one example, the method employed is to adjust the shape and size of the copper layers corresponding to the power circuit and the gate circuit within a reasonable package layout. By adjusting the shape and size of the copper layers, the parasitic inductance is controlled, aiming to satisfy the equality condition as much as possible. Considering practical realities, for power module packages with many parallel chips, fully satisfying the common-source inductance compensation theoretical relationship is difficult and costly due to constraints imposed by the chip spacing and substrate size. It has been verified that if within the existing... and When the difference between the two values ​​is large, a better flow uniformity can be achieved by narrowing the numerical gap between them.

[0089] Therefore, the optimization scheme only narrows the copper layer in the common-source region on the right side of the chip, increasing the base L. com1 The value narrowed the L between the 6 chips on the same side. com The difference is small. Because the power circuit does not pass through the copper layer on the right side of the chip, adjusting this area has little impact on the chip's power circuit. The value remains basically unchanged, and we can... Reduce when the change is small The value is compared with the parasitic parameter extraction results of the original and new versions. It can be considered unchanged. The new version is This largely balances the gap between the two, reduces the circulating current between branches caused by the asymmetric parasitic parameters of the chip, and improves the current sharing between parallel branches.

[0090] like Figure 3 The simulation waveforms shown extract parasitic parameters from both the original and new package designs. Based on the transient circuit model of the parallel chip, a circuit schematic was built in Ltspice. The chip model is L75NT021ZJ, 750V / 21mΩ, with a DC power supply of 400V and a load inductance L. Load =250-300nh, gate internal resistance R g A double-pulse test was performed under a current impedance of 12Ω, with six chips connected in parallel. In the half-bridge, the high-side switch was off, and the low-side switch was on. The improvement in chip current sharing by the new layout design was judged based on the degree of current waveform balance in the simulation results.

[0091] The scheme can better reflect the voltage and current changes in the actual switching process by establishing a more accurate on-state transient process circuit model by combining the on-state transient characteristics, which helps to more accurately predict and control the switching performance. At the same time, by optimizing the current balance of the on-state transient process circuit, current sharing among multiple power devices is realized, avoiding the problem of local overload caused by uneven current distribution, improving the current sharing degree of devices in the multi-chip parallel situation, effectively avoiding the decline of the current-carrying capacity of the power module and irreversible device damage caused by uneven current, to meet the demand for power module on-off capacity and stability in solid-state circuit breaker applications.

[0092] Based on the above method, the embodiment of the application discloses a new energy equipment system maintenance decision system based on a fault coupling model, which refers to Figure 4 The circuit breaker power module layout optimization system 5 includes a circuit construction module 51, a current balance module 52, and a layout optimization module 53, wherein

[0093] The circuit construction module 51 is configured to collect the parasitic parameters of the circuit breaker power module, and construct a first switching transient circuit model according to the parasitic parameters. Based on the first switching transient circuit model and the on-state transient characteristics, an on-state transient process circuit is constructed.

[0094] The current balance module 52 is configured to perform current balance on the on-state transient process circuit according to a common-source inductance compensation function, to update the state of the on-state transient process circuit, and obtain a second switching transient circuit model corresponding to the on-state transient process circuit after state updating.

[0095] The layout optimization module 53 is configured to extract the parasitic inductance parameters in the second switching transient circuit model using the ANSYS Q3D simulation tool, and perform multiple iterative optimizations on the copper layer shape and size of each power tube in the second switching transient circuit model according to the common-source inductance compensation function and the parasitic inductance parameters through finite element simulation, to obtain an optimized layout scheme of the circuit breaker power module.

[0096] In one example, the parasitic parameters of the circuit breaker power module include the parasitic inductance between the drain and anode output terminals of each power tube in the circuit breaker power module, the parasitic inductance between the source and cathode output terminals of each power tube, and the coupling inductance between two parallel power tubes.

[0097] In one example, the on-state transient process circuit includes a circuit driving unit, a plurality of parallel switching units, a balance voltage stabilizing unit, and a power supply, wherein

[0098] The first common end of the plurality of parallel switch units is electrically connected with the first end of the circuit driving unit and one end of the equalizing voltage stabilizing unit respectively, and the second common end of the plurality of parallel switch units is electrically connected with the second end of the circuit driving unit and the other end of the equalizing voltage stabilizing unit respectively.

[0099] In one example, the parallel switch unit comprises a first MOS tube, a second MOS tube, a first parasitic inductance, a second parasitic inductance and a common-source inductance, wherein,

[0100] The gate of the first MOS tube is electrically connected with the first end of the circuit driving unit and the rest of the parallel switch units respectively, the drain of the first MOS tube is electrically connected with one end of the first parasitic inductance, the other end of the first parasitic inductance is electrically connected with the rest of the parallel switch units respectively, the source of the first MOS tube is electrically connected with one end of the common-source inductance, the common end of the common-source inductance and the second parasitic inductance is electrically connected with the third end of the circuit driving unit and the rest of the parallel switch units respectively, the other end of the second parasitic inductance is electrically connected with the source of the second MOS tube, the gate of the second MOS tube is electrically connected with the second end of the circuit driving unit and the rest of the parallel switch units respectively, the drain of the first MOS tube is electrically connected with the rest of the parallel switch units and one end of the equalizing voltage stabilizing unit respectively.

[0101] In one example, the expression of the common-source inductance compensation function is:

[0102] L Loop = L D + L com + L S

[0103]

[0104] wherein, L LOOP represents the loop inductance of the parallel switch unit, L D represents the parasitic inductance between the drain of the MOS tube and the positive terminal of the DC power supply, L S represents the parasitic inductance between the source of the MOS tube and the negative terminal of the DC power supply, L com represents the common-source inductance value in the parallel switch unit, ΔI 1-2 represents the circulating current between the first parallel switch unit and the second parallel switch unit in the form of frequency domain, s represents the Laplace operator, I d1 represents the drain current of the first parallel switch unit in the form of frequency domain, I d2 represents the drain current of the second parallel switch unit in the form of frequency domain, ΔI d1-2 represents the difference value of the drain current between the first parallel switch unit and the second parallel switch unit in the form of frequency domain, ΔL Loop1-2represents the difference in loop inductance between the first parallel switch unit and the second parallel switch unit in the frequency domain form, AL com represents the difference in common source inductance between the first parallel switch unit and the nth parallel switch unit in the frequency domain form, AL Loop represents the difference in loop inductance between the first parallel switch unit and the nth parallel switch unit in the frequency domain form, L Loop1 represents the loop inductance of the first parallel switch unit, L com1 represents the common source inductance value in the first parallel switch unit.

[0105] In one example, the layout optimization module 53 is configured to import the second switch transient circuit model into the ANSYS Q3D simulation tool, perform material setting on the second switch transient circuit model to obtain a transition switch transient circuit model, sequentially perform meshing operations on the transition switch transient circuit model, and correspondingly set excitations for the current inflow end and the current outflow end of each mesh in the transition switch transient circuit model, and perform simulation operations on the transition switch transient circuit model to obtain an inductance matrix corresponding to the transition switch transient circuit model and a parasitic inductance parameter in the transition switch transient circuit model.

[0106] In one example, each mesh in the transition switch transient circuit model includes a plurality of current inflow ends and one current outflow end, and the current inflow ends and the current outflow end are edges or faces in the transition switch transient circuit model.

[0107] In one example, the equalization and voltage stabilization unit includes a first voltage stabilization diode, a second voltage stabilization diode, and a load inductor, the anode of the first voltage stabilization diode is electrically connected to the first common end of the plurality of parallel switch units and one end of the load inductor, the cathode of the first voltage stabilization diode is electrically connected to the cathode of the second voltage stabilization diode, the anode of the second voltage stabilization diode is electrically connected to the second common end of the plurality of parallel switch units and the negative electrode of the power supply, and the other end of the load inductor is electrically connected to the positive electrode of the power supply.

[0108] Based on the above method, an embodiment of the present application discloses a computer device, which includes a memory and a processor, the memory stores a computer program, and the computer program is executed by the processor to make the processor execute the steps of the circuit breaker power module layout optimization method based on multi-chip current sharing.

[0109] It should be noted that embodiments of the present application can be realized in hardware, software, or a combination of software and hardware. The hardware portion can be realized utilizing specialized logic; the software portion can be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or application specific design hardware. Those ordinarily skilled in the art will appreciate that the above-described apparatus and methods can be realized using computer-executable instructions and / or in processor control code, for example, provided on a carrier medium such as a carrier wave transmittable over a wired or wireless network, a magnetic or optical storage media, such as a floppy diskette, a CD-ROM, or DVD-ROM, a Programmable Memory such as read-only memory (Firmware), or a data carrier wave such as an optical or electrical signal carrier. The apparatus of the present application and its modules can be realized by hardware circuitry, such as very large scale integration circuits or gate arrays, semiconductors, such as logic chips, transistors, etc., or programmable hardware devices, such as field programmable gate arrays, programmable logic devices, etc., by software executed by various types of processors, or by a combination of the above, such as firmware.

[0110] The above description is merely that of the preferred embodiments of the present application and is not intended to limit the present application. Modification, equivalent replacements, improvements, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A multi-chip current sharing based circuit breaker power module layout optimization method, characterized in that, The method comprises: Collecting the parasitic parameters of the circuit breaker power module, and constructing a first switching transient circuit model according to the parasitic parameters; Based on the first switching transient circuit model and the conduction transient characteristics, a conduction transient process circuit is constructed; According to the common-source inductance compensation function, the current of the conduction transient process circuit is balanced to update the state of the conduction transient process circuit, and a second switching transient circuit model corresponding to the state updated conduction transient process circuit is obtained; The conduction transient process circuit comprises a plurality of parallel switch units (2), and the parallel switch unit (2) comprises two MOS tubes; The expression of the common-source inductance compensation function is: = ； ； ； in, L LOOP Indicates the loop inductance of the parallel switching unit. This represents the parasitic inductance between the drain of the MOSFET and the terminals leading out from the positive terminal of the DC power supply. This represents the parasitic inductance between the source of the MOSFET and the terminals leading out from the negative terminal of the DC power supply. This indicates the common source inductance value in the parallel switching unit. This represents the inter-branch circulating current between the first and second parallel switching units in the frequency domain. s Represents the Laplace operator. I d1 This represents the drain current of the first parallel switching unit in the frequency domain. I d2 This represents the drain current of the second parallel switching unit in the frequency domain. This represents the difference in drain current between the first and second parallel switching units in the frequency domain. This represents the difference in loop inductance between the first and second parallel switching units in the frequency domain. This indicates that the first parallel switching unit and the second parallel switching unit in the frequency domain are connected in the frequency domain. n The difference in common source inductance between parallel switching units In frequency domain form, the first parallel switching unit and the second n The difference in loop inductance between parallel switching units, This represents the loop inductance of the first parallel switching unit. This represents the common source inductance value in the first parallel switching unit; The ANSYS Q3D simulation tool is used to extract the parasitic inductance parameters in the second switching transient circuit model, and the copper layer shape and size of each power tube in the second switching transient circuit model are iteratively optimized through finite element simulation according to the common-source inductance compensation function and the parasitic inductance parameters, so as to obtain the optimized layout scheme of the circuit breaker power module.

2. The method of claim 1, wherein, The parasitic parameters of the circuit breaker power module include the parasitic inductance between the drain and the positive terminal of each power tube in the circuit breaker power module, the parasitic inductance between the source and the negative terminal of each power tube, and the coupling inductance between two parallel power tubes.

3. The method of claim 1, wherein, The conduction transient process circuit further comprises a circuit driving unit (1), an equalization voltage stabilizing unit (3) and a power supply (4), wherein, The first common end of the plurality of parallel switch units (2) is electrically connected with the first end of the circuit driving unit (1), one end of the equalization voltage stabilizing unit (3) and the positive electrode of the power supply (4) respectively, the second common end of the plurality of parallel switch units (2) is electrically connected with the second end of the circuit driving unit (1), the other end of the equalization voltage stabilizing unit (3) and the negative electrode of the power supply (4) respectively, and the third common end of the plurality of parallel switch units (2) is electrically connected with the third end of the circuit driving unit (1).

4. The method of claim 3, wherein, The parallel switch unit (2) comprises a first MOS tube, a second MOS tube, a first parasitic inductance, a second parasitic inductance and a common-source inductance, wherein, The gate of the first MOS tube is electrically connected with the first end of the circuit driving unit (1) and the rest of the parallel switch units (2) respectively, the drain of the first MOS tube is electrically connected with one end of the first parasitic inductor, the other end of the first parasitic inductor is electrically connected with the rest of the parallel switch units (2) respectively, the source of the first MOS tube is electrically connected with one end of the common source inductor, the common end of the common source inductor and the second parasitic inductor is electrically connected with the third end of the circuit driving unit (1) and the rest of the parallel switch units (2) respectively, the other end of the second parasitic inductor is electrically connected with the source of the second MOS tube, the gate of the second MOS tube is electrically connected with the second end of the circuit driving unit (1) and the rest of the parallel switch units (2) respectively, and the drain of the first MOS tube is electrically connected with the rest of the parallel switch units (2) and one end of the equalizing voltage stabilizing unit (3).

5. The method of claim 1, wherein, The method for extracting the parasitic inductor parameters in the second switch transient circuit model by using the ANSYS Q3D simulation tool specifically comprises the following steps: The second switch transient circuit model is imported into the ANSYS Q3D simulation tool, material settings are performed on the second switch transient circuit model, and a transition switch transient circuit model is obtained; Grid division operations are sequentially performed on the transition switch transient circuit model, and the current inflow end and the current outflow end of each grid in the transition switch transient circuit model are set to correspond to excitations; Simulation is performed on the transition switch transient circuit model, and an inductance matrix corresponding to the transition switch transient circuit model and the parasitic inductor parameters in the transition switch transient circuit model are obtained.

6. The method of claim 5, wherein, Each grid in the transition switch transient circuit model comprises a plurality of current inflow ends and one current outflow end, and the current inflow ends and the current outflow end are edges or faces in the transition switch transient circuit model.

7. The method of claim 3, wherein, The equalizing voltage stabilizing unit (3) comprises a first voltage stabilizing diode, a second voltage stabilizing diode, and a load inductor, the anode of the first voltage stabilizing diode is electrically connected with the first common end of a plurality of the parallel switch units and one end of the load inductor respectively, the cathode of the first voltage stabilizing diode is electrically connected with the cathode of the second voltage stabilizing diode, the anode of the second voltage stabilizing diode is electrically connected with the second common end of a plurality of the parallel switch units and the negative electrode of the power supply respectively, and the other end of the load inductor is electrically connected with the positive electrode of the power supply.

8. A multi-chip current sharing based circuit breaker power module layout optimization system, comprising: The circuit construction module (51) is configured to collect parasitic parameters of the circuit breaker power module, and construct a first switch transient circuit model according to the parasitic parameters, and construct a conduction transient process circuit based on the first switch transient circuit model and conduction transient characteristics. The circuit construction module (51) is configured to collect parasitic parameters of the circuit breaker power module, and construct a first switch transient circuit model according to the parasitic parameters, and construct a conduction transient process circuit based on the first switch transient circuit model and conduction transient characteristics. The current equalization module (52) is configured to perform current equalization on the turn-on transient process circuit according to a common-source inductance compensation function, to update the state of the turn-on transient process circuit, and obtain a second switch transient circuit model corresponding to the turn-on transient process circuit after state updating. The turn-on transient process circuit includes a plurality of parallel switch units (2), and each parallel switch unit (2) includes two MOS tubes. The expression of the common-source inductance compensation function is as follows: = ； ； ； in, L LOOP Indicates the loop inductance of the parallel switching unit. This represents the parasitic inductance between the drain of the MOSFET and the terminals leading out from the positive terminal of the DC power supply. This represents the parasitic inductance between the source of the MOSFET and the terminals leading out from the negative terminal of the DC power supply. This indicates the common source inductance value in the parallel switching unit. This represents the inter-branch circulating current between the first and second parallel switching units in the frequency domain. s Represents the Laplace operator. I d1 This represents the drain current of the first parallel switching unit in the frequency domain. I d2 This represents the drain current of the second parallel switching unit in the frequency domain. This represents the difference in drain current between the first and second parallel switching units in the frequency domain. This represents the difference in loop inductance between the first and second parallel switching units in the frequency domain. This indicates that the first parallel switching unit and the second parallel switching unit in the frequency domain are connected in the frequency domain. n The difference in common source inductance between parallel switching units In frequency domain form, the first parallel switching unit and the second n The difference in loop inductance between parallel switching units, This represents the loop inductance of the first parallel switching unit. This represents the common source inductance value in the first parallel switching unit; The layout optimization module (53) is configured to extract a parasitic inductance parameter in the second switch transient circuit model by using an ANSYS Q3D simulation tool, to perform multiple iterative optimizations on the copper layer shape and the copper layer size of each power tube in the second switch transient circuit model by finite element simulation according to the common-source inductance compensation function and the parasitic inductance parameter, and to obtain an optimized layout scheme of the circuit breaker power module. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is executed by the processor to make the processor perform the steps of the circuit breaker power module layout optimization method based on multi-chip current sharing according to any one of claims 1 to 7.

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