Wiring layout design method, program, and recording medium

Abstract

A novel wiring layout design method is provided. The layout information and the netlist are used to generate a wiring layout that electrically connects the start terminal group and the end terminal group. And when the wiring layout meets the design rule, extracting the wiring resistance and the parasitic capacitance of the wiring layout. And updating the layout information by using Q learning, and generating a new wiring layout. In Q learning, a positive reward is given when the wiring resistance value and the parasitic capacitance value decrease, and the weight of the neural network is updated according to the reward. And when the new wiring layout meets the design rule, extracting the wiring resistance and the parasitic capacitance of the new wiring layout. When the change rate of the wiring resistance and the parasitic capacitance is large, the layout information is updated by using Q learning.

Description

[0001] This application is a divisional application of an application filed on March 9, 2020, with PCT application number PCT / IB2020 / 052002, which entered the Chinese national phase on September 2, 2021, with national application number 202080018248.4, and invention name “Wiring layout design method, program and recording medium”. Technical Field

[0002] One embodiment of the present invention relates to a wiring layout design method, a program, a recording medium, and the like.

[0003] In addition, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification, etc. relates to an object, a working method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter.

[0004] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one form of semiconductor devices. In addition, display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, imaging devices, and electronic devices, etc., are sometimes said to be semiconductor devices. Or, sometimes, it can be said that they include semiconductor devices. Background Art

[0005] In recent years, the demand for miniaturization and high density of integrated circuits has increased. Generally speaking, an integrated circuit is composed of a plurality of circuits. Each circuit is electrically connected by wiring, and signals are sent and received by the wiring. With the miniaturization and high density of integrated circuits, the parasitic capacitance and wiring resistance of the wiring are required to be reduced. For example, in Patent Document 1, a design method for wiring layout is proposed for setting the parasitic capacitance and wiring resistance to below the allowable value.

[0006] In addition, the application of artificial intelligence is being studied for various purposes. In particular, it is expected that a computer with higher performance than the existing Neumann type computer can be realized by applying the structure of an artificial neural network, and in recent years, various research works on constructing an artificial neural network on an electronic circuit have been carried out.

[0007] For example, Patent Document 2 discloses an invention in which a memory device using a transistor including an oxide semiconductor in a channel formation region holds weight data required for calculation using an artificial neural network.

[0008] [Prior technical literature]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2003-50835

[0011] [Patent Document 2] U.S. Patent Application Publication No. 2016 / 0343452 Summary of the invention

[0012] Technical problem to be solved by the invention

[0013] The parasitic capacitance and wiring resistance generated in the wiring can cause the degradation and attenuation of the signal waveform transmitted by the wiring. Therefore, it is necessary to reduce these parasitic capacitance and wiring resistance as much as possible. On the other hand, the layout used to reduce the parasitic capacitance and wiring resistance needs to meet the design rules. In the method of patent document 1, because the layout design ends when the parasitic capacitance and wiring resistance reach below the allowable value, the most suitable wiring layout is sometimes not obtained. In addition, since it is necessary to meet the design rules, the allowable values ​​of parasitic capacitance and wiring resistance are sometimes set high.

[0014] One of the purposes of one embodiment of the present invention is to provide a design system for a wiring layout in which wiring resistance and parasitic capacitance are reduced while satisfying design rules. In addition, one of the purposes of one embodiment of the present invention is to provide a design method for a wiring layout in which wiring resistance and parasitic capacitance are reduced while satisfying design rules. In addition, one of the purposes of one embodiment of the present invention is to provide a novel wiring layout design system. In addition, one of the purposes of one embodiment of the present invention is to provide a novel wiring layout design method.

[0015] Note that the recording of these purposes does not prevent the existence of other purposes. Note that one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes are obvious from the description of the specification, drawings, claims, etc., and can be extracted from the description.

[0016] Solutions to technical problems

[0017] One embodiment of the present invention is a wiring layout design method, which includes a first step of obtaining first layout information, a second step of generating a first wiring layout using the first layout information, a third step of obtaining a first parasitic capacitance value as a parasitic capacitance value of the first wiring layout, a fourth step of generating a second wiring layout using the first layout information, a fifth step of performing DRC on the second wiring layout, a sixth step of obtaining a second parasitic capacitance value as a parasitic capacitance value of the second wiring layout, a seventh step of learning using a result of DRC, the first parasitic capacitance value, and the second parasitic capacitance value, and an eighth step of changing the first layout information according to the result of the learning.

[0018] Another embodiment of the present invention is a wiring layout design method, which includes a first step of obtaining first layout information, a second step of generating a first wiring layout using the first layout information, a third step of obtaining a first parasitic capacitance value as a parasitic capacitance value of the first wiring layout and a first wiring resistance value as a wiring resistance value of the first wiring layout, a fourth step of generating a second wiring layout using the first layout information, a fifth step of performing DRC on the second wiring layout, a sixth step of obtaining a second parasitic capacitance value as a parasitic capacitance value of the second wiring layout and a second wiring resistance value as a wiring resistance value of the second wiring layout, a seventh step of learning using a result of DRC, the first parasitic capacitance value, the second parasitic capacitance value, the first wiring resistance value and the second wiring resistance value, and an eighth step of changing the first layout information according to the result of the learning.

[0019] Another embodiment of the present invention is a wiring layout design method, wherein the fourth step to the eighth step are repeated multiple times.

[0020] The learning is preferably Q-learning. The learning can also be performed using a neural network. The neural network has the function of inferring an action value function.

[0021] Another embodiment of the present invention is a program for causing a computer to execute the above wiring layout design method.

[0022] Another embodiment of the present invention is a computer-readable recording medium having the program recorded thereon.

[0023] Effects of the Invention

[0024] According to one embodiment of the present invention, a design system for a wiring layout in which wiring resistance and parasitic capacitance are reduced while satisfying design rules can be provided. In addition, according to one embodiment of the present invention, a design method for a wiring layout in which wiring resistance and parasitic capacitance are reduced while satisfying design rules can be provided. In addition, according to one embodiment of the present invention, a novel wiring layout design system can be provided. In addition, according to one embodiment of the present invention, a novel wiring layout design method can be provided.

[0025] Note that the description of these effects does not prevent the existence of other effects. Note that one mode of the present invention does not necessarily have all of the above effects. Effects other than the above effects are obvious from the description of the specification, drawings, claims, etc., and can be extracted from the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a diagram showing a configuration example of a wiring layout design system.

[0027] Figure 2 A diagram showing an example of a wiring layout design method.

[0028] Figure 3 A diagram showing an example of a wiring layout design method.

[0029] Figure 4A and Figure 4B is a diagram showing a structural example of a neural network.

[0030] Figure 5 is a diagram showing a structural example of a semiconductor device.

[0031] Figure 6 is a diagram showing a structural example of a storage unit.

[0032] Figure 7 is a diagram showing a configuration example of a bias circuit.

[0033] Figure 8 It is a timing diagram. DETAILED DESCRIPTION

[0034] The embodiments are described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and a person skilled in the art can easily understand that the method and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that in the structure of the invention described below, the same symbols are used in different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted.

[0035] In addition, in order to facilitate understanding of the invention, the position, size, range, etc. of each structure shown in the drawings and the like sometimes do not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask and the like may be unintentionally thinned due to a process such as etching, but this is sometimes omitted in the drawings for ease of understanding.

[0036] Furthermore, in particular, in a top view (also referred to as a plan view) or a perspective view, some components may be omitted for ease of understanding of the drawings.

[0037] In addition, in this specification, etc., "electrode" or "wiring" does not limit its constituent elements in terms of function. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wiring" are formed as one.

[0038] In addition, in this specification, etc., a "terminal" in an electronic circuit refers to a part that inputs or outputs current, inputs or outputs voltage, and / or receives or transmits a signal. Therefore, a part of a wiring or an electrode may be used as a terminal.

[0039] In addition, in this specification, etc., "above" or "below" is not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, "electrode B on insulating layer A" does not need to form electrode B on insulating layer A in direct contact, and may also include the case where other components are included between insulating layer A and electrode B.

[0040] In addition, since the functions of the "source" and "drain" are interchanged depending on the operating conditions, such as when transistors of different polarities are used or when the direction of the current changes during circuit operation, it is difficult to define which is the "source" and which is the "drain". Therefore, in this specification, the "source" and "drain" can be interchanged.

[0041] In this specification, "electrical connection" includes direct connection and connection through "a component having some electrical function". Here, "a component having some electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. Therefore, even if it is described as "electrical connection", there may be parts in the actual circuit that are not physically connected but are just extended wiring.

[0042] In addition, in this specification, "parallel" refers to, for example, a state in which two straight lines are arranged in an angle range of -10° or more and 10° or less. Therefore, the case where the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" or "orthogonal" refers to, for example, a state in which two straight lines are arranged in an angle range of 80° or more and 100° or less. Therefore, the case where the angle is 85° or more and 95° or less is also included.

[0043] In addition, in this specification, unless otherwise stated, when "same", "identical", "equal", or "uniform" is mentioned about count values ​​or measured values, a variation of ±10% is included as an error.

[0044] In addition, voltage often refers to the potential difference between a certain potential and a standard potential (e.g., ground potential or source potential, etc.). Therefore, the terms "voltage" and "potential" are sometimes interchangeable. In this specification, unless otherwise specified, voltage and potential are interchangeable.

[0045] Note that, for example, when the conductivity is sufficiently low, even if it is expressed as a "semiconductor", it has the characteristics of an "insulator". Therefore, "insulator" can also be used instead of "semiconductor". In this case, the boundary between "semiconductor" and "insulator" is blurred, so it is difficult to distinguish accurately. Therefore, sometimes the "semiconductor" recorded in this specification can be replaced by "insulator".

[0046] In addition, for example, when the conductivity is sufficiently high, even if it is expressed as a "semiconductor", it has the characteristics of a "conductor". Therefore, "conductor" can also be used instead of "semiconductor". In this case, the boundary between "semiconductor" and "conductor" is blurred, so it is difficult to distinguish accurately. Therefore, sometimes the "semiconductor" recorded in this specification can be replaced by "conductor".

[0047] Ordinal numbers such as "first" and "second" in this specification are used to avoid confusion between constituent elements, and do not indicate an order or sequence such as a process sequence or a stacking sequence. In addition, with respect to words that are not accompanied by ordinal numbers in this specification, ordinal numbers are sometimes added to these words in the claims to avoid confusion between constituent elements. Note that with respect to words that are accompanied by ordinal numbers in this specification, ordinal numbers are sometimes omitted in the claims.

[0048] Note that in this specification, etc., the "on state" of a transistor refers to a state in which the source and drain of the transistor are electrically short-circuited (also referred to as a "conductive state"). In addition, the "off state" of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected (also referred to as a "non-conductive state").

[0049] In addition, in this specification, etc., "on-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the on state. In addition, "off-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the off state.

[0050] In addition, in this specification, etc., a high power supply potential VDD (also referred to as "VDD" or "H potential") refers to a power supply potential whose potential is higher than a low power supply potential VSS. In addition, a low power supply potential VSS (also referred to as "VSS" or "L potential") refers to a power supply potential whose potential is lower than a high power supply potential VDD. In addition, a ground potential may be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.

[0051] In this specification, the term "gate" refers to a part or all of a gate electrode and a gate wiring. A gate wiring refers to a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0052] In addition, in this specification, etc., the source refers to a part or all of the source region, source electrode, and source wiring. The source region refers to a region in the semiconductor layer whose resistivity is less than a certain value. The source electrode refers to a portion of the conductive layer connected to the source region. The source wiring refers to a wiring used to electrically connect the source electrode of at least one transistor to other electrodes or other wiring.

[0053] In addition, in this specification, etc., the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region in the semiconductor layer whose resistivity is less than a certain value. The drain electrode refers to a portion of the conductive layer connected to the drain region. The drain wiring refers to a wiring used to electrically connect the drain electrode of at least one transistor to other electrodes or other wirings.

[0054] (Implementation Method 1)

[0055] A wiring layout design system (hereinafter also referred to as a “design system”) according to one embodiment of the present invention will be described with reference to the drawings.

[0056] <Configuration Example of Wiring Layout Design System>

[0057] Figure 1 is a block diagram illustrating a configuration example of the design system 100.

[0058] Notice, Figure 1The block diagram of FIG. 1 classifies the components according to their functions and illustrates them as independent blocks. However, the actual components are sometimes difficult to be clearly divided according to their functions. Therefore, one component sometimes involves multiple functions or one function sometimes involves multiple components.

[0059] also, Figure 1 The structure of the design system 100 shown is an example and does not necessarily include all the components. Figure 1 The required components among the components shown in the figure may be used. Figure 1 Constituent elements other than those shown in the figure.

[0060] The design system 100 includes a control unit 130 (Controller), a computing unit 140, a storage unit 160 (Memory), an auxiliary storage unit 170 (Storage), an external input / output unit 180 (Interface), and a communication unit 190 as components. In addition, the design system 100 preferably includes AI 150 (AI: Artificial Intelligence).

[0061] These components are electrically connected to each other via the transmission channel 101. The transmission channel 101 can be used to transmit and receive information between the components.

[0062] As the transistor included in the above-mentioned constituent elements, it is preferable to use a transistor (also referred to as an "OS transistor") containing an oxide semiconductor (Oxide Semiconductor) which is one of metal oxides in the channel formation region. Since the off-state current of the OS transistor is extremely low, the power consumption of the design system can be reduced. In addition, the off-state current is not easily increased in a high temperature environment, and the operation is stable, thereby improving the reliability of the design system 100.

[0063] In addition, in this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplification effect, a rectification effect and a switching effect, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor), or it can be abbreviated as OS.

[0064] The metal oxide possessed by the channel formation region preferably contains indium (In). In the case where the metal oxide possessed by the channel formation region contains indium, the carrier mobility (electron mobility) of the OS transistor is improved. In addition, the metal oxide possessed by the channel formation region is preferably an oxide semiconductor containing element M. Element M is preferably aluminum (Al), gallium (Ga) or tin (Sn) and the like. As other elements that can be used as element M, there are boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), yttrium (Y), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W) and the like. Note that as element M, multiple of the above elements may also be combined sometimes. Element M is, for example, an element with a high bond energy with oxygen. Element M is, for example, an element with a higher bond energy with oxygen than indium. In addition, the metal oxide possessed by the channel formation region preferably contains zinc (Zn). Metal oxides containing zinc are sometimes easy to crystallize.

[0065] The metal oxide included in the channel formation region is not limited to the metal oxide containing indium, and the semiconductor layer may be a metal oxide containing zinc, gallium or tin without containing indium, such as zinc tin oxide or gallium tin oxide.

[0066] Note that as the semiconductor layer of the OS transistor, it is preferred to use an oxide semiconductor including a crystalline portion, such as CAAC-OS and nc-OS. CAAC-OS is the abbreviation of c-axis-aligned crystalline oxide semiconductor. CAAC-OS has a c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has a distortion. Note that the distortion refers to the part where the direction of the lattice arrangement changes between the region where the lattice arrangement is consistent and other regions where the lattice arrangement is consistent in the region where multiple nanocrystals are connected. nc-OS is the abbreviation of nanocrystalline oxide semiconductor.

[0067] [Control unit 130]

[0068] The control unit 130 (Controller) has a function of controlling operations of the computing unit 140 , the AI ​​150 , the storage unit 160 , the auxiliary storage unit 170 , the external input / output unit 180 , the communication unit 190 , and the like.

[0069] [Calculation unit 140]

[0070] The calculation unit 140 has a function of performing calculations related to the work of the entire design system, and, for example, a central processing unit (CPU) or the like may be used.

[0071] The calculation unit 140 has a function of setting a wiring layout (wiring shape, wiring path, etc.) for connecting a plurality of terminals based on layout information.

[0072] 〔AI150〕

[0073] An artificial neural network (ANN: Artificial Neural Network, hereinafter sometimes referred to as a neural network (NN)) is preferably used as the AI ​​150. The AI ​​150 may be provided in the computing unit 140. Alternatively, the AI ​​150 may be configured by software.

[0074] In addition, the control unit 130, the computing unit 140 or the AI ​​150 may also include a microprocessor such as a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit). The microprocessor may also be implemented by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).

[0075] [Storage unit 160]

[0076] The storage unit 160 has the function of storing programs and setting contents (parameters) related to the operation of the design system 100, and at least a part of the memory is preferably rewritable. For example, the storage unit 160 may include a volatile memory such as a RAM (Random Access Memory) or a non-volatile memory such as a ROM (Read Only Memory).

[0077] As the RAM provided in the storage unit 160, for example, DRAM (Dynamic Random Access Memory) can be used, and a storage space is virtually allocated and used as a work space of the design system 100. The operating system, application programs, program modules, program data, etc. stored in the auxiliary storage unit 170 are loaded into the RAM when executed.

[0078] On the other hand, BIOS (Basic Input / Output System) or firmware that does not need to be rewritten can be stored in ROM. As ROM, mask ROM, OTPROM (One Time Programmable Read Only Memory), EPROM (Erasable Programmable Read Only Memory), etc. can be used. As EPROM, UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory) that can erase stored data by ultraviolet irradiation, EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory can be cited.

[0079] [Auxiliary storage unit 170]

[0080] The auxiliary storage unit 170 is a storage device for storing calculated data. In addition, data used in the AI ​​150 is stored. In addition, as described above, the auxiliary storage unit 170 can store an operating system, application programs, program modules, program data, and the like.

[0081] As the auxiliary storage unit 170, for example, a storage device using a nonvolatile storage element such as a flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase change RAM), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM), etc., or a storage device using a volatile storage element such as DRAM (Dynamic RAM), SRAM (Static RAM), etc. can also be used. In addition, for example, a recording medium drive such as a hard disk drive (HDD) or a solid state drive (SSD) can also be used.

[0082] In addition, for example, a storage device such as a HDD or SSD, a flash memory, a media drive for recording media such as a Blu-ray disc or a DVD, etc., which can be attached and detached via the external input / output unit 180, may be used as the auxiliary storage unit 170. In addition, a storage device provided outside the design system 100 may be used as the auxiliary storage unit 170 instead of being built into the design system 100. In this case, a structure may be provided in which data is connected via the external input / output unit 180 or a structure may be provided in which data is transmitted and received by wireless communication via the communication unit 190.

[0083] [External input / output unit 180]

[0084] The external input / output unit 180 has a function of controlling the input / output of signals between an external device and the design system 100. In addition, as an external port included in the external input / output unit 180, an HDMI (registered trademark) terminal, a USB terminal, and a LAN (Local Area Network) connection terminal, etc., may be used. In addition, the external input / output unit 180 may also have a transceiver function for optical communication using infrared rays, visible light, ultraviolet rays, etc.

[0085] For example, layout data or the like generated in the design system 100 may be supplied to the outside through the external input / output section 180 .

[0086] [Ministry of Communications 190]

[0087] The communication unit 190 can communicate via an antenna. For example, the communication unit 190 controls a control signal for connecting the design system 100 to a computer network according to an instruction from the operation unit 140, and sends the signal to the computer network. Thus, the design system 100 can be connected to a computer network such as the Internet, an intranet, an extranet, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), or a GAN (Global Area Network) based on the World Wide Web (WWW) to communicate. In addition, when a plurality of methods are used as a communication method, a plurality of antennas may be included according to the communication method.

[0088] For example, a high-frequency circuit (RF circuit) may be provided in the communication unit 190 to transmit and receive RF signals. A high-frequency circuit is a circuit used to convert electromagnetic signals and electrical signals in the frequency bands specified by the laws of various countries and to communicate wirelessly with other communication devices using the electromagnetic signals. As a practical frequency band, a frequency band of tens of kHz to tens of GHz is generally used. The high-frequency circuit connected to the antenna has a high-frequency circuit unit corresponding to multiple frequency bands, and the high-frequency circuit unit may have an amplifier, a mixer, a filter, a DSP (Digital Signal Processor), an RF transceiver, and the like. When wireless communication is performed, the following communication protocols or communication technologies can be used: communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark: Global System for Mobile Communications), EDGE (Enhanced Data Rates for GSM Evolution: GSM Enhanced Data Rates Evolution), CDMA2000 (Code Division Multiple Access 2000: Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access: registered trademark: Wideband Code Division Multiple Access); or specifications standardized by IEEE (Institute of Electrical and Electronics Engineers) communications such as Wi-Fi (Wireless Fidelity: registered trademark: Wireless Fidelity), Bluetooth (registered trademark: Bluetooth), ZigBee (registered trademark), etc.

[0089] For example, a computer can be used as the design system 100 of one embodiment of the present invention. At this time, when a signal for starting the execution program of the design system 100 of one embodiment of the present invention is input through the external input / output unit 180 or the communication unit 190, the control unit 130 causes the storage unit 160 to read the execution program stored in the auxiliary storage unit 170. By causing the storage unit 160 to read the execution program, the computer can be used as the design system 100.

[0090] <Working Example of Wiring Layout Design System>

[0091] Next, an operation example of the design system 100 will be described. In this embodiment, a design method of a wiring layout for electrically connecting a plurality of terminals will be described. Figure 2 and Figure 3 It is a flow chart illustrating the design method of wiring layout.

[0092] [Step S311]

[0093] First, basic information such as layout information 111, netlist 112, and design rules 113 are obtained. Layout information 111 includes information showing the configuration of each terminal. Netlist 112 includes information showing the connection relationship between terminals (also called "connection information"). Design rules 113 include information showing the lower limit values ​​of wiring width, wiring spacing, and connection hole diameter, the upper limit values ​​of the number of layers, prohibition rules, etc.

[0094] The layout information 111 , the netlist 112 , the design rule 113 , and the like may be information stored in the auxiliary storage unit 170 , or may be information supplied to the design system 100 through the external input / output unit 180 .

[0095] [Step S312]

[0096] Next, an initial wiring layout (wiring shape and wiring path, etc.) that electrically connects each terminal is randomly generated. When the initial wiring layout is configured according to a predetermined rule, the result of the optimization process sometimes deviates. Therefore, it is preferable to randomly generate the initial wiring layout. The generated wiring layout is added to the layout information 111.

[0097] Note that in this specification and the like, when two terminals are electrically connected by wiring, one terminal may be referred to as a “starting point terminal” and the other terminal may be referred to as an “end point terminal”.

[0098] Generally speaking, there are multiple starting terminals and multiple end terminals in many cases. Therefore, multiple wirings electrically connecting the starting terminals and the end terminals are generated in many cases. In this specification, multiple starting terminals are sometimes collectively referred to as a "starting terminal group". In addition, multiple end terminals are sometimes collectively referred to as a "end terminal group". In addition, multiple wirings are sometimes collectively referred to as a "wiring group".

[0099] In addition, the number of the starting point terminals and the number of the end point terminals are not necessarily equal. In addition, one starting point terminal is not necessarily electrically connected to only one end point terminal. For example, sometimes one starting point terminal is electrically connected to multiple end point terminals. Similarly, sometimes multiple starting point terminals are electrically connected to one end point terminal. Based on the netlist 112, it is determined which starting point terminal is electrically connected to which end point terminal.

[0100] [Step S313]

[0101] Next, it is checked whether the wiring layout of the randomly generated wiring group satisfies the design rule 113. The confirmation of whether the layout satisfies the design rule is called DRC (Design Rule Check).

[0102] When the layout does not satisfy the design rule 113, the process returns to step S312 and randomly generates wiring.

[0103] [Step S314]

[0104] When the wiring layout satisfies the design rule 113, layout parasitic extraction (LPE) is performed. The parasitic capacitance value extracted in step S314 is the initial value of the optimization process to be performed later. In addition, the wiring resistance value at this time is the initial value of the optimization process to be performed later.

[0105] Note that steps S311 to S314 may also be collectively referred to as step S310. Step S310 is a step for initialization or preprocessing.

[0106] The layout information obtained in step S310 may be a netlist in which the connection relationship between terminals is described using a hardware description language (HDL) or a simulation program with integrated circuit emphasis (SPICE).

[0107] [Step S320]

[0108] Next, use AI150 to optimize various parameters. The parameters to be optimized include wiring length, wiring width, distance between adjacent wirings, number of times crossing other wirings, etc. Figure 3 The details of step S320 will be described.

[0109] In the optimization of various parameters, the layout information, parasitic capacitance, and wiring resistance obtained in step S310 are used as initial information. In addition, on the premise of satisfying the design rule 113, various parameters are optimized so as to minimize the parasitic capacitance and wiring resistance.

[0110] Optimization of various parameters can be performed using reinforcement learning. "Reinforcement learning" is a type of machine learning, but it is different from "supervised learning" which is mainly used for image recognition, etc., or "unsupervised learning" which is mainly used for clustering, etc. Reinforcement learning is a learning method that rewards when good results are obtained and punishes when bad results are obtained. It is mainly used when it is difficult to control the means of achieving the goal.

[0111] As reinforcement learning, for example, TD learning (Temporal Difference Learning), Q learning (Q-Learning), etc. It is also preferable to use a learning algorithm using deep learning for Q learning.

[0112] Q learning is the process of learning to select action a when the agent is in state s1 at time t. t The agent is the subject of the action, and the environment is the object of the action. t , the environment changes from state s t Change to state s t+1 , the agent receives a reward r t+1 In Q-learning, action a is learned in such a way that the total reward that can be obtained is ultimately maximized. t . It can be represented by the action value function Q(s t , a t ) means in state s t Next select action a t In this specification, etc., the action value function Q is sometimes referred to as the Q function, and the action value function Q(s t , a t ) is called the Q value. For example, the action value function Q(s t , a t ) can be expressed by equation 1.

[0113] [Formula 1]

[0114]

[0115] Here, α represents the learning rate (α is greater than 0 and less than 1), and γ represents the discount rate (γ is greater than 0 and less than 1). The learning rate α indicates whether to emphasize the current value or the result obtained through the action. The closer the learning rate α is to 1, the more emphasis is placed on the result obtained, and the greater the change in value. The closer the learning rate α is to 0, the more emphasis is placed on the current value, and the smaller the change in value. The discount rate γ indicates whether to emphasize the current reward or the future reward. The closer the discount rate γ is to 0, the more emphasis is placed on the current reward. The closer the discount rate γ is to 1, the more emphasis is placed on the future reward. For example, the learning rate α and the discount rate γ can be set to 0.10 and 0.90, respectively.

[0116] In the above action value function Q(s t , a t ) is estimated using deep learning. Sometimes the action value function Q(s t , a t ) is called Deep Q-Learning, and the neural network used in DeepQ-Learning is called Deep Q-Network (DQN).

[0117] In the design system of one embodiment of the present invention, it is particularly preferred that Deep Q-Learning is used for parameter optimization, and Deep Q-Network has a convolutional neural network (CNN) structure. In this specification, etc., Deep Q-Network may be simply referred to as a neural network.

[0118] Generally speaking, in Q-learning, the action-value function Q(s) is stored in a lookup table (LUT) in advance. t , a t ) status t and actiona t However, due to the state s t and action a t There are many combinations of, and sometimes a large amount of memory is required. On the other hand, in the design system as one embodiment of the present invention, by t , a t ) can reduce the amount of memory required.

[0119] In this specification, etc., a neural network refers to any model that simulates a biological neural circuit network and determines the strength of the connection between neurons through learning, thereby obtaining problem-solving capabilities. A neural network includes an input layer, an output layer, and one or more intermediate layers (hidden layers) between the input layer and the output layer.

[0120] In this specification and other documents, when describing a neural network, determining the connection strength (also called weight coefficient) between neurons based on existing information may be referred to as "learning."

[0121] In this specification and the like, constructing a neural network using the combination strength obtained through learning and deriving a new conclusion from the structure may be referred to as "inference".

[0122] Neural networks are executed using huge product-sum operations. These operations can be performed using one or both of digital circuits and analog circuits. When using digital circuits, the number of transistors required is huge, the efficiency is low, and the power consumption is high. Therefore, the product-sum operations are preferably performed using analog product-sum circuits (hereinafter referred to as APS (Analog Product-Sum circuit)). In addition, APS preferably includes an analog memory. By storing the weight coefficients obtained by learning in the above-mentioned analog memory, APS can directly perform product-sum operations on analog data. As a result, by using APS, a neural network can be efficiently constructed with a small number of transistors.

[0123] In this specification, analog memory refers to a storage device capable of storing analog data. In this specification, analog data refers to data having a resolution of 3 bits (8 values) or more. Multi-value data is sometimes referred to as analog data.

[0124] As the analog memory, a multi-value flash memory, ReRAM (Resistive Random Access Memory), MRAM (Magnetoresistive Random Access Memory), or a memory using an OS transistor (also referred to as “OS memory”) can be used.

[0125] [Step S321]

[0126] The layout information, parasitic capacitance value, and wiring resistance value determined in step S310 are input to AI 150 .

[0127] [Step S322]

[0128] AI150 is based on the action value function Q(s t , a t ) value to change the values ​​of various parameters and generate new layout information. For example, the operation of changing each parameter can be assigned as an action. AI150 selects the action with the largest value of the action value function Q and changes the parameter. Note that it is preferable to select the action randomly.

[0129] [Step S323]

[0130] The calculation unit 140 re-sets the wiring layout connecting the start point terminal and the end point terminal using the new layout information.

[0131] [Step S324]

[0132] Next, DRC is performed on the new wiring layout generated in step S323. When the new wiring layout does not meet the design rules, step S326 is performed instead of step S325. When the new wiring layout meets the design rules, step S325 is performed.

[0133] [Step S325]

[0134] When the new wiring layout meets the design rules, the wiring resistance value and the parasitic capacitance value are extracted.

[0135] [Step S326]

[0136] Next, the reward given to AI150 is determined. For example, when the wiring layout does not meet the design rules in step S324, a negative reward is given. In addition, a negative reward is also given when the wiring resistance value or parasitic capacitance value increases. In addition, a positive reward is given when the wiring resistance value or parasitic capacitance value decreases.

[0137] The reward value may be a predetermined value, or may be determined according to the increase or decrease in the wiring resistance value and / or the parasitic capacitance value.

[0138] The reward may also be determined based on the time constant τ. The time constant τ is the product of the wiring resistance value R and the parasitic capacitance value C. For example, a negative reward may be given when the time constant τ increases, and a positive reward may be given when the time constant τ decreases.

[0139] The negative reward when the wiring layout does not satisfy the design rules is preferably greater than the negative reward when the wiring resistance value, parasitic capacitance value or time constant τ increases.

[0140] [Step S327]

[0141] Next, AI 150 determines new weights based on the rewards received.

[0142] [Step S328]

[0143] Next, it is determined whether the optimization process meets the termination condition. For example, when the rate of change of the wiring resistance value, parasitic capacitance value, or time constant τ reaches below the specified value and is determined not to decrease further, the optimization process ends. When it is determined that the termination condition is not met, the process returns to step S321. In step S321, the layout information determined in step S322 is input to AI150.

[0144] Furthermore, in consideration of the case where the wiring resistance value, parasitic capacitance value, or time constant τ does not completely change, the optimization process may be terminated when the number of repetitions of step S320 reaches a predetermined number or more.

[0145] [Step S330]

[0146] After the optimization process is completed, the generated layout information is stored in the auxiliary storage unit 170. The layout information is preferably stored in the GDS2 (Graphic Data System 2) format. In addition, the layout information can also be supplied to the outside through the external input / output unit 180 or the communication unit 190.

[0147] According to one embodiment of the present invention, it is possible to automatically perform repetitive work for optimization, thereby achieving the most suitable wiring layout in a short time. In addition, the burden on the layout designer is reduced, and work efficiency can be improved. In addition, by using reinforcement learning, one of machine learning, for the optimization of wiring layout, it is possible to explore wiring layouts that cannot be explored by humans.

[0148] This embodiment mode can be combined with other embodiment modes and the like as appropriate.

[0149] (Implementation Method 2)

[0150] In this embodiment, a structural example of a semiconductor device that can be used for the neural network described in the above embodiment will be described.

[0151] like Figure 4A As shown, the neural network NN can be composed of an input layer IL, an output layer OL and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL and the intermediate layer HL all include one or more neurons (units). Note that the intermediate layer HL can be one layer or more than two layers. A neural network including more than two layers of intermediate layers HL can be called a DNN (deep neural network), and learning using a deep neural network can be called deep learning.

[0152] Each neuron in the input layer IL is input with input data, each neuron in the intermediate layer HL is input with output signals of neurons in the previous or next layer, and each neuron in the output layer OL is input with output signals of neurons in the previous layer. Note that each neuron can be connected to all neurons in the previous and next layers (fully connected) or to some neurons.

[0153] Figure 4B An example of operation using neurons is shown. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N is input with the output x1 of the neuron in the previous layer and the output x2 of the neuron in the previous layer. In neuron N, the sum x1w1+x2w2 of the multiplication result (x1w1) of the output x1 and the weight w1 and the multiplication result (x2w2) of the output x2 and the weight w2 is calculated, and then a bias b is added as needed to obtain the value a=x1w1+x2w2+b. The value a is transformed by the activation function h, and the output signal y=h(a) is output from neuron N.

[0154] In this way, the operation using neurons includes the operation of adding the product of the output of the neurons in the previous layer and the weight, that is, the sum-of-products operation (the above x1w1+x2w2). The sum-of-products operation can be performed in software through a program or in hardware. When the sum-of-products operation is performed by hardware, a sum-of-products operation circuit can be used. As the sum-of-products operation circuit, both a digital circuit and an analog circuit can be used. When an analog circuit is used as a sum-of-products operation circuit, the circuit scale of the sum-of-products operation circuit can be reduced or the number of accesses to the memory can be reduced, thereby achieving an increase in processing speed and a reduction in power consumption.

[0155] The product-sum operation circuit can be composed of a transistor containing silicon (single crystal silicon, etc.) in the channel formation region (hereinafter also referred to as a Si transistor) or an OS transistor. In particular, since the OS transistor has an extremely small off-state current, it is preferably used as a transistor of an analog memory constituting the product-sum operation circuit. Note that the product-sum operation circuit can also be composed of both Si transistors and OS transistors. Below, a structural example of a semiconductor device having the function of a product-sum operation circuit is described.

[0156] <Structural Example of Semiconductor Device>

[0157] Figure 5 An example of the structure of a semiconductor device MAC having a function of performing a neural network operation is shown. The semiconductor device MAC has a function of performing a product-sum operation of first data corresponding to the connection strength (weight) between neurons and second data corresponding to input data. Note that the first data and the second data may be analog data or multi-valued data (dispersed data), respectively. In addition, the semiconductor device MAC has a function of transforming data obtained by the product-sum operation using an activation function.

[0158] The semiconductor device MAC includes a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, a bias circuit OFST, and an activation function circuit ACTV.

[0159] The cell array CA includes a plurality of memory cells MC and a plurality of memory cells MCref. Figure 5 The cell array CA includes m rows and n columns (m and n are integers greater than 1) of memory cells MC (MC[1, 1] to [m, n]) and m memory cells MCref (MCref[1] to [m]). The memory cell MC has a function of storing first data. In addition, the memory cell MCref has a function of storing reference data for product-sum operations. Note that the reference data may be analog data or multi-valued data.

[0160] The memory cell MC[i, j] (i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n) is connected to the wiring WL[i], the wiring RW[i], the wiring WD[j], and the wiring BL[j]. In addition, the memory cell MCref[i] is connected to the wiring WL[i], the wiring RW[i], the wiring WDref, and the wiring BLref. Here, the current flowing between the memory cell MC[i, j] and the wiring BL[j] is recorded as I MC[i，j] , the current flowing between the memory cell MCref[i] and the wiring BLref is recorded as I MCref[i] .

[0161] Figure 6 Specific structural examples of the memory cell MC and the memory cell MCref are shown. Figure 6 1 and 2 are typical examples of memory cells MC[1,1], MC[2,1] and memory cells MCref[1], MCref[2], but the same structure can be used in other memory cells MC and memory cells MCref. Both memory cells MC and memory cells MCref include transistors Tr11, Tr12 and capacitor C11. Here, the case where transistors Tr11 and Tr12 are n-channel transistors is described.

[0162] In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, one of the source and the drain is connected to the gate of the transistor Tr12 and the first electrode of the capacitor C11, and the other of the source and the drain is connected to the wiring WD. One of the source and the drain of the transistor Tr12 is connected to the wiring BL, and the other of the source and the drain is connected to the wiring VR. The second electrode of the capacitor C11 is connected to the wiring RW. The wiring VR has a function of supplying a predetermined potential. Here, as an example, a case where a low power supply potential (ground potential, etc.) is supplied from the wiring VR is described.

[0163] The node connected to one of the source and drain of transistor Tr11, the gate of transistor Tr12, and the first electrode of capacitor C11 is referred to as node NM. In addition, the nodes NM of memory cells MC[1,1] and MC[2,1] are referred to as nodes NM[1,1] and [2,1], respectively.

[0164] The memory cell MCref also has the same structure as the memory cell MC. However, the memory cell MCref is connected to the wiring WDref instead of the wiring WD and is connected to the wiring BLref instead of the wiring BL. In the memory cells MCref[1] and MCref[2], nodes connected to one of the source and drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitor C11 are respectively referred to as nodes NMref[1] and [2].

[0165] The node NM and the node NMref are used as holding nodes of the memory cell MC and the memory cell MCref, respectively. The node NM holds the first data, and the node NMref holds the reference data. MC[1，1] ,I MC[2，1] The current I flows from the wiring BL[1] to the transistors Tr12 of the memory cells MC[1,1] and MC[2,1]. MCref[1] ,I MCref[2] The power flows from the wiring BLref to the transistors Tr12 of the memory cells MCref[1] and MCref[2], respectively.

[0166] Since the transistor Tr11 has the function of maintaining the potential of the node NM or the node NMref, the off-state current of the transistor Tr11 is preferably small. Therefore, as the transistor Tr11, it is preferable to use an OS transistor with a very small off-state current. As a result, the potential variation of the node NM or the node NMref can be suppressed to improve the calculation accuracy. In addition, the frequency of the operation of refreshing the potential of the node NM or the node NMref can be suppressed to a low level, thereby reducing power consumption.

[0167] There is no particular limitation on the transistor Tr12, and for example, a Si transistor or an OS transistor may be used. When an OS transistor is used as the transistor Tr12, the transistor Tr12 can be manufactured using the same manufacturing apparatus as the transistor Tr11, thereby reducing manufacturing costs. Note that the transistor Tr12 may be an n-channel transistor or a p-channel transistor.

[0168] The current source circuit CS is connected to the wirings BL[1] to [n] and the wiring BLref. The current source circuit CS has a function of supplying current to the wirings BL[1] to [n] and the wiring BLref. Note that the current value supplied to the wirings BL[1] to [n] may be different from the current value supplied to the wiring BLref. Here, the current supplied from the current source circuit CS to the wirings BL[1] to [n] is recorded as I C The current supplied from the current source circuit CS to the wiring BLref is recorded as I Cref .

[0169] The current mirror circuit CM includes wirings IL[1] to [n] and wiring ILref. The wirings IL[1] to [n] are connected to the wirings BL[1] to [n], respectively, and the wiring ILref is connected to the wiring BLref. Here, the connection between the wirings IL[1] to [n] and the wirings BL[1] to [n] is referred to as a node NP[1] to [n]. In addition, the connection between the wirings ILref and the wirings BLref is referred to as a node NPref.

[0170] The current mirror circuit CM has a function of converting a current I corresponding to the potential of the node NPref into CM The function of flowing to the wiring ILref and also transferring the current I CM Function that flows to wiring IL[1] to [n]. Figure 5 Shows the current I CM The current I is discharged from the wiring BLref to the wiring ILref. CM This is an example of a current flowing from the wiring BL[1] to [n] to the wiring IL[1] to [n]. The current flowing from the current mirror circuit CM to the cell array CA through the wiring BL[1] to [n] is expressed as I B [1] to [n]. In addition, the current flowing from the current mirror circuit CM to the cell array CA through the wiring BLref is expressed as I Bref .

[0171] The circuit WDD is connected to the wirings WD[1] to [n] and the wiring WDref. The circuit WDD has a function of supplying a potential corresponding to the first data stored in the memory cell MC to the wirings WD[1] to [n]. In addition, the circuit WDD has a function of supplying a potential corresponding to the reference data stored in the memory cell MCref to the wiring WDref. The circuit WLD is connected to the wirings WL[1] to [m]. The circuit WLD has a function of supplying a signal selecting the memory cell MC or the memory cell MCref to which data is written to the wirings WL[1] to [m]. The circuit CLD is connected to the wirings RW[1] to [m]. The circuit CLD has a function of supplying a potential corresponding to the second data to the wirings RW[1] to [m].

[0172] The bias circuit OFST is connected to the wirings BL[1] to [n] and the wirings OL[1] to [n]. The bias circuit OFST has a function of detecting the amount of current flowing from the wirings BL[1] to [n] to the bias circuit OFST and / or the amount of change in the current flowing from the wirings BL[1] to [n] to the bias circuit OFST. In addition, the bias circuit OFST has a function of outputting the detection result to the wirings OL[1] to [n]. Note that the bias circuit OFST can output the current corresponding to the detection result to the wirings OL, and can also convert the current corresponding to the detection result into a voltage and output it to the wirings OL. The current flowing between the cell array CA and the bias circuit OFST is recorded as I α [1] to [n].

[0173] Figure 7 A configuration example of the bias circuit OFST is shown. Figure 7The bias circuit OFST shown includes circuits OC[1] to [n]. Circuits OC[1] to [n] all include transistors Tr21, Tr22, Tr23, capacitor C21 and resistor R1. The connection relationship of each element is as follows: Figure 7 Note that the node connected to the first electrode of the capacitor C21 and the first terminal of the resistor R1 is referred to as the node Na. In addition, the node connected to the second electrode of the capacitor C21, one of the source and drain of the transistor Tr21, and the gate of the transistor Tr22 is referred to as the node Nb.

[0174] The wiring VrefL has a function of supplying the potential Vref, the wiring VaL has a function of supplying the potential Va, and the wiring VbL has a function of supplying the potential Vb. The wiring VDDL has a function of supplying the potential VDD, and the wiring VSSL has a function of supplying the potential VSS. Here, the case where the potential VDD is a high power supply potential and the potential VSS is a low power supply potential is described. The wiring RST has a function of supplying a potential for controlling the conduction state of the transistor Tr21. The transistor Tr22, the transistor Tr23, the wiring VDDL, the wiring VSSL, and the wiring VbL constitute a source follower circuit.

[0175] Next, an operation example of circuits OC[1] to [n] is described. Note that although the operation example of circuit OC[1] is described here as a typical example, circuits OC[2] to [n] can also operate in the same manner. First, when a first current flows to wiring BL[1], the potential of node Na becomes a potential corresponding to the first current and the resistance value of resistor R1. At this time, transistor Tr21 is in the on state, and potential Va is supplied to node Nb. Then, transistor Tr21 becomes in the off state.

[0176] Next, when the second current flows to the wiring BL[1], the potential of the node Na changes to a potential corresponding to the second current and the resistance value of the resistor R1. At this time, the transistor Tr21 is in the off state and the node Nb is in the floating state, so when the potential of the node Na changes, the potential of the node Nb changes due to capacitive coupling. Here, the potential change at the node Na is ΔV Na When the capacitive coupling coefficient is 1, the potential of node Nb is Va+ΔV Na The threshold voltage of transistor Tr22 is V th When the potential Va+ΔV is output from the wiring OL[1] Na -V th Here, by satisfying Va=V th , the potential ΔV can be output from the wiring OL[1] Na .

[0177] Potential ΔV NaThe voltage ΔV is determined by the change from the first current to the second current, the resistance value of the resistor R1, and the potential Vref. Na The amount of change in the current flowing to the wiring BL.

[0178] As described above, a signal corresponding to the amount of current and / or the amount of change in current detected by the bias circuit OFST is input to the activation function circuit ACTV through the wirings OL[1] to [n].

[0179] The activation function circuit ACTV is connected to the wiring OL[1] to [n] and the wiring NIL[1] to [n]. The activation function circuit ACTV has a function of performing an operation to transform the signal input from the bias circuit OFST according to a predetermined activation function. As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, and a threshold function can be used. The signal transformed by the activation function circuit ACTV is output to the wiring NIL[1] to [n] as output data.

[0180] <Operation Example of Semiconductor Device>

[0181] The semiconductor device MAC described above can perform a product-sum operation on the first data and the second data. Next, an operation example of the semiconductor device MAC when performing a product-sum operation will be described.

[0182] Figure 8 A timing chart showing an operation example of the semiconductor device MAC. Figure 8 Show Figure 6 The potential changes of the wiring WL[1], wiring WL[2], wiring WD[1], wiring WDref, node NM[1,1], node NM[2,1], node NMref[1], node NMref[2], wiring RW[1], and wiring RW[2], and the current I B [1]-I α [1] and current I Bref The value of current I B [1]-I α [1] corresponds to the total of currents flowing from the wiring BL[1] to the memory cells MC[1,1] and MC[2,1].

[0183] Although we focus on Figure 6 The operation is described using the memory cells MC[1,1], MC[2,1] and the memory cells MCref[1], MCref[2] as typical examples, but other memory cells MC and memory cells MCref can also perform the same operation.

[0184] [Storage of First Data]

[0185] First, at time T01-T02, the potential of the wiring WL[1] becomes a high level, and the potential of the wiring WD[1] becomes V higher than the ground potential (GND). PR -V W[1，1] The potential of the wiring WDref becomes V greater than the ground potential. PR The potential of wiring RW[1] and wiring RW[2] becomes the standard potential (REFP). Note that the potential V W[1，1] corresponds to the first data stored in the memory cell MC[1,1]. PR Therefore, the transistor Tr11 included in the memory cell MC[1,1] and the memory cell MCref[1] is turned on, and the potential of the node NM[1,1] becomes V PR -V W[1，1] , the potential of node NMref[1] becomes V PR .

[0186] At this time, the current I flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1] MC[1，1]，0 It can be expressed as follows. Here, k is a constant depending on the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor Tr12. In addition, V th is the threshold voltage of transistor Tr12.

[0187] I MC[1，1]，0 = k(V PR -V W[1，1] -V th ) 2 (E1)

[0188] Furthermore, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1]，0 It can be expressed as the following formula.

[0189] I MCref[1]，0 = k(V PR -V th ) 2 (E2)

[0190] Next, at time T02-T03, the potential of wiring WL[1] becomes low level, so that transistor Tr11 included in memory cell MC[1,1] and memory cell MCref[1] becomes off, and the potentials of node NM[1,1] and node NMref[1] are maintained.

[0191] As described above, it is preferable to use an OS transistor as the transistor Tr11. This can suppress the leakage current of the transistor Tr11 and accurately maintain the potentials of the node NM[1, 1] and the node NMref[1].

[0192] Next, at time T03-T04, the potential of the wiring WL[2] becomes high level, and the potential of the wiring WD[1] becomes V higher than the ground potential. PR -V W[2，1] The potential of the wiring WDref becomes V greater than the ground potential. PR Note that the potential V W[2，1] This corresponds to the first data stored in the memory cell MC[2,1]. Therefore, the transistor Tr11 included in the memory cell MC[2,1] and the memory cell MCref[2] becomes on, and the potential of the node NM[2,1] becomes V PR -V W[2，1] , the potential of node NMref[2] becomes V PR .

[0193] At this time, the current I flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] MC[2，1]，0 It can be expressed as the following formula.

[0194] I MC[2，1]，0 = k(V PR -V W[2，1] -V th ) 2 (E3)

[0195] Furthermore, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2]，0 It can be expressed as the following formula.

[0196] I MCref[2]，0 = k(V PR -V th ) 2 (E4)

[0197] Next, at time T04-T05, the potential of wiring WL[2] becomes low level, so that transistors Tr11 included in memory cells MC[2,1] and MCref[2] become off, and the potentials of nodes NM[2,1] and NMref[2] are maintained.

[0198] Through the above operation, the first data is stored in the memory cells MC[1, 1] and MC[2, 1], and the reference data is stored in the memory cells MCref[1] and MCref[2].

[0199] Here, at time T04-T05, consider the current flowing to wiring BL[1] and wiring BLref. Current is supplied to wiring BLref from current source circuit CS. The current flowing through wiring BLref is discharged to current mirror circuit CM and memory cells MCref[1] and MCref[2]. The current supplied from current source circuit CS to wiring BLref is referred to as I Cref The current discharged from the wiring BLref to the current mirror circuit CM is called I CM，0 , then the following equation is satisfied.

[0200] I Cref -I CM，0 =I MCref[1]，0 +I MCref[2]，0 (E5)

[0201] Current is supplied from the current source circuit CS to the wiring BL[1]. The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and MC[2,1]. In addition, current flows from the wiring BL[1] to the bias circuit OFST. The current supplied from the current source circuit CS to the wiring BL[1] is referred to as I C，0 The current flowing from the wiring BL[1] to the bias circuit OFST is called I α，0 , then the following equation is satisfied.

[0202] I C -I CM，0 =I MC[1，1]，0 +I MC[2，1]，0 +I α，0 (E6)

[0203] [Product-sum operation of first data and second data]

[0204] Next, at time T05-T06, the potential of wiring RW[1] is V higher than the standard potential. X[1] At this time, the potential V X[1] The voltage V is supplied to each capacitor C11 of the memory cell MC[1,1] and the memory cell MCref[1], and the gate potential of the transistor Tr12 rises due to capacitive coupling. X[1] Corresponding to the second data supplied to the memory cell MC[1, 1] and the memory cell MCref[1].

[0205] The change in the potential of the gate of the transistor Tr12 is equivalent to the change in the potential of the wiring RW multiplied by the value of the capacitive coupling coefficient determined by the structure of the memory cell. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor C11, the gate capacitance of the transistor Tr12, and the parasitic capacitance. Below, for the sake of convenience, the case where the change in the potential of the wiring RW is equal to the change in the potential of the gate of the transistor Tr12, that is, the case where the capacitive coupling coefficient is 1 is described. In fact, considering that the capacitive coupling coefficient determines the potential V X , that's it.

[0206] When the potential V X[1] When the voltage is supplied to the capacitor C11 of the memory cell MC[1,1] and the memory cell MCref[1], the potential of the node NM[1,1] and the node NMref[1] both rises by V X[1] .

[0207] Here, at time T05-T06, the current I flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1] MC[1，1]，1 It can be expressed as the following formula.

[0208] I MC[1，1]，1 = k(V PR -V W[1，1] +V X[1] -V th ) 2 (E7)

[0209] That is, by supplying the potential V to the wiring RW[1] X[1] , the current flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1] increases by ΔI MC[1，1] =I MC[1，1]，1 -I MC[1，1]， 0.

[0210] Furthermore, at time T05-T06, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[1]. MCref[1]，1 It can be expressed as the following formula.

[0211] I MCref[1]，1 = k(V PR +V X[1] -V th ) 2 (E8)

[0212] That is, by supplying the potential V to the wiring RW[1] X[1] , the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[1] increases by ΔI MCref[1] =I MCref[1]，1 -IMCref[1]， 0.

[0213] In addition, consider the current flowing to the wiring BL[1] and the wiring BLref. The current I is supplied from the current source circuit CS to the wiring BLref. Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and MCref[2]. The current discharged from the wiring BLref to the current mirror circuit CM is referred to as I CM，1 , then the following equation is satisfied.

[0214] I Cref -I CM，1 =I MCref[1]，1 +I MCref[2]，0 (E9)

[0215] The current I is supplied from the current source circuit CS to the wiring BL[1]. C The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and MC[2,1]. Furthermore, the current flows from the wiring BL[1] to the bias circuit OFST. The current flowing from the wiring BL[1] to the bias circuit OFST is referred to as I α，1 , then the following equation is satisfied.

[0216] I C -I CM，1 =I MC[1，1]，1 +I MC[2，1]，1 +I α，1 (E10)

[0217] According to equations (E1) to (E10), the current I can be expressed as follows: α，0 With current I α，1 The difference (difference current ΔI α ).

[0218] ΔI α =I α，1 -I α，0 =2kV W[1，1] V X[1] (E11)

[0219] Thus, the difference current ΔI α Indicates the potential V W[1，1] With V X[1] The value of the product.

[0220] Then, at time T06-T07, the potential of the wiring RW[1] becomes the standard potential, and the potentials of the node NM[1, 1] and the node NMref[1] become the same as at time T04-T05.

[0221] Next, at time T07-T08, the potential of wiring RW[1] becomes V higher than the standard potential. X[1] The potential of wiring RW[2] becomes V greater than the standard potential. X[2] Therefore, the potential V X[1] The capacitor C11 supplied to the memory cell MC[1,1] and the memory cell MCref[1] increases the potential of both the node NM[1,1] and the node NMref[1] by V due to capacitive coupling. X[1] In addition, the potential V X[2] The capacitor C11 supplied to the memory cell MC[2,1] and the memory cell MCref[2] increases the potential of both the node NM[2,1] and the node NMref[2] by V due to capacitive coupling. X[2] .

[0222] Here, at time T07-T08, the current I flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] MC[2，1]，1 It can be expressed as the following formula.

[0223] I MC[2，1]，1 = k(V PR -V W[2，1] +V X[2] -V th ) 2 (E12)

[0224] That is, by supplying the potential V to the wiring RW[2] X[2] , the current flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] increases by ΔI MC[2，1] =I MC[2，1]，1 -I MC[2，1]， 0.

[0225] Furthermore, at time T07-T08, the current I flows from the wiring BLref to the transistor Tr12 of the memory cell MCref[2]. MCref[2]，1 It can be expressed as the following formula.

[0226] I MCref[2]，1 = k(V PR +V X[2] -V th ) 2 (E13)

[0227] That is, by supplying the potential V to the wiring RW[2] X[2] , the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[2] increases by ΔI MCref[2] =I MCref[2]，1 -I MCref[2]， 0.

[0228] In addition, consider the current flowing to the wiring BL[1] and the wiring BLref. The current I is supplied from the current source circuit CS to the wiring BLref. Cref The current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1] and MCref[2]. The current discharged from the wiring BLref to the current mirror circuit CM is referred to as I CM，2 , then the following equation is satisfied.

[0229] I Cref -I CM，2 =I MCref[1]，1 +I MCref[2]，1 (E14)

[0230] The current I is supplied from the current source circuit CS to the wiring BL[1]. C The current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1] and MC[2,1]. Furthermore, the current flows from the wiring BL[1] to the bias circuit OFST. The current flowing from the wiring BL[1] to the bias circuit OFST is referred to as I α，2 , then the following equation is satisfied.

[0231] I C -I CM，2 =I MC[1，1]，1 +I MC[2，1]，1 +I α，2 (E15)

[0232] According to equations (E1) to (E8) and equations (E12) to (E15), the current I can be expressed as follows: α，0 With current I α，2 The difference (difference current ΔI α ).

[0233] ΔI α =I α，2 -I α，0 =2k(V W[1，1] V X[1] +V W[2，1] V X[2] )(E16)

[0234] Thus, the difference current ΔI α Indicates the potential V W[1，1] With potential V X[1] The product of the potential V W[2，1] With potential V X[2] The value of the result of adding the products.

[0235] Then, at time T08-T09, the potentials of the wirings RW[1] and [2] become the standard potential, and the potentials of the nodes NM[1,1] and [2,1] and the nodes NMref[1] and [2] become the same as at time T04-T05.

[0236] As shown in equations (E11) and (E16), the differential current ΔI input to the bias circuit OFST is α The potential V corresponding to the first data (weight) can be W and the potential V corresponding to the second data (input data) X That is, by using the bias circuit OFST to calculate the difference current ΔI α By performing the measurement, a result of a product-sum operation of the first data and the second data can be obtained.

[0237] Note that although the above description focuses on memory cells MC[1,1], MC[2,1] and memory cells MCref[1], MCref[2], the number of memory cells MC and memory cells MCref can be set arbitrarily. When the number of rows m of memory cells MC and memory cells MCref is set to an arbitrary number i, the difference current ΔI can be expressed as follows: α .

[0238] ΔI α =2kΣ i V W[i，1] V X[i] (E17)

[0239] Furthermore, by increasing the number n of columns of memory cells MC and memory cells MCref, the number of parallel sum-of-product operations can be increased.

[0240] As described above, by using the semiconductor device MAC, a product-sum operation can be performed on the first data and the second data. Figure 6 The structures of the memory cells MC and MCref shown above can form a product-sum operation circuit using a small number of transistors, thereby reducing the circuit scale of the semiconductor device MAC.

[0241] When the semiconductor device MAC is used for calculations using a neural network, the number m of rows of storage cells MC can correspond to the number of input data supplied to one neuron and the number n of columns of storage cells MC can correspond to the number of neurons. Figure 4AIn the case where a product-sum operation using the semiconductor device MAC is performed in the intermediate layer HL shown in the figure, the number m of rows of the storage cells MC can be set to the number of input data supplied from the input layer IL (the number of neurons in the input layer IL) and the number n of columns of the storage cells MC can be set to the number of neurons in the intermediate layer HL.

[0242] Note that there is no particular limitation on the structure of the neural network using the semiconductor device MAC. For example, the semiconductor device MAC can be used for a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a Boltzmann machine (including a restricted Boltzmann machine), and the like.

[0243] As described above, by using the semiconductor device MAC, it is possible to perform product-sum operations in a neural network. Figure 6 The memory cell MC and the memory cell MCref shown are used in the cell array CA, and an integrated circuit with high calculation accuracy, low power consumption or small circuit scale can be provided.

[0244] This embodiment mode can be combined with other embodiment modes and the like as appropriate.

[0245] [Explanation of symbols]

[0246] 100: Design system, 101: Transmission channel, 111: Layout information, 112: Netlist, 113: Design rule, 130: Control unit, 140: Calculation unit, 150: AI, 160: Storage unit, 170: Auxiliary storage unit, 180: External input / output unit, 190: Communication unit

Claims

1. A semiconductor device having a program stored thereon, wherein when the program is executed by one or more processors, the one or more processors are caused to perform operations for wiring layout design, the operations comprising: Get basic information; generating a wiring layout using the basic information; Checking whether the wiring layout meets the design rules; In response to determining that the wiring layout satisfies the design rule: Obtaining a parasitic capacitance value of the wiring layout; as well as performing learning using the parasitic capacitance value; as well as Parameter optimization is performed based on the learning result.

2. A semiconductor device having a program stored thereon, wherein when the program is executed by one or more processors, the one or more processors are caused to perform operations for wiring layout design, the operations comprising: Get basic information; generating a wiring layout using the basic information; Checking whether the wiring layout meets the design rules; In response to determining that the wiring layout satisfies the design rule: Obtaining a parasitic capacitance value of the wiring layout; as well as performing learning using the parasitic capacitance value; as well as Parameter optimization is performed based on the learning results. Wherein, the learning is performed using a neural network.

3. The semiconductor device according to claim 1 or 2, wherein The basic information includes layout information, netlist and the design rules; The layout information includes information about the arrangement of terminals; The netlist includes information about connection relationships between the terminals; Also, the design rule includes information on a wiring width or a wiring interval. The semiconductor device according to claim 1 , wherein the learning is Q-learning.

5. The semiconductor device according to claim 2, wherein the neural network is configured to infer an action-value function.

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