Level conversion circuit and driving method, display panel, circuit board and display device

Abstract

The application discloses a level conversion circuit and a driving method, a display panel, a circuit board and a display device. The level conversion circuit is electrically connected between a driving chip and a gate driving circuit, and is used for converting a first driving signal of the driving chip into a second driving signal. The second driving signal is used for driving the gate driving circuit. A difference between a high level and a low level of the first driving signal is a first difference, a difference between a high level and a low level of the second driving signal is a second difference, and the second difference is greater than the first difference. According to the embodiment of the application, by introducing the level conversion circuit, the difference between the high level and the low level of the driving signal output by the display driving chip is increased, the effective utilization of the existing display driving chip is realized, and the waste of resources can be reduced while meeting the demand of a larger cross voltage.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a level conversion circuit and driving method, a display panel, a circuit board and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, the display performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This application provides a level conversion circuit and driving method, a display panel, a circuit board, and a display device. By introducing a level conversion circuit, the difference between the high and low levels of the driving signal output by the display driver chip is increased, realizing the effective utilization of existing display driver chips and reducing resource waste while meeting greater voltage requirements.

[0005] In a first aspect, embodiments of this application provide a level conversion circuit, which is electrically connected between a driver chip and a gate driver circuit, for converting a first driving signal of the driver chip into a second driving signal. The second driving signal is used to drive the gate driver circuit. The difference between the high level and the low level of the first driving signal is a first difference value, and the difference between the high level and the low level of the second driving signal is a second difference value. The second difference value is greater than the first difference value.

[0006] In one possible embodiment of the first aspect, at the same time, a high potential of the second driving signal corresponds to a low potential of the first driving signal; or, at the same time, a low potential of the second driving signal corresponds to a high potential of the first driving signal.

[0007] In one possible embodiment of the first aspect, the high level of the second driving signal is equal to the high level of the first driving signal, and the low level of the second driving signal is less than the low level of the first driving signal.

[0008] Alternatively, the high level of the second driving signal is greater than the high level of the first driving signal, and the low level of the second driving signal is equal to the low level of the first driving signal.

[0009] In one possible embodiment of the first aspect, the level shifting circuit includes:

[0010] The first output module has its first terminal electrically connected to the first power supply terminal and its second terminal electrically connected to the gate drive circuit.

[0011] The second output module has its first end electrically connected to the second power supply terminal, its second end electrically connected to the gate drive circuit, and its control terminal connected to the first drive signal.

[0012] The output control module has a first terminal electrically connected to the reference power supply terminal and a second terminal electrically connected to the control terminal of the first output module, and its control terminal is connected to the first drive signal.

[0013] Under the control of the output control module and the first drive signal, the first output module and the second output module are alternately turned on;

[0014] One of the first power supply terminal and the second power supply terminal is at a high level and the other is at a low level. When the first power supply terminal is at a low level, the low level of the first power supply terminal is less than the low level of the first drive signal; when the first power supply terminal is at a high level, the high level of the first power supply terminal is greater than the high level of the first drive signal.

[0015] In one possible embodiment of the first aspect, when the first power supply terminal is at a low level, the high level of the second power supply terminal is equal to the high level of the first drive signal; when the first power supply terminal is at a high level, the low level of the second power supply terminal is equal to the low level of the first drive signal.

[0016] In one possible embodiment of the first aspect, the first output module includes a first transistor, the first electrode of the first transistor serves as the first terminal of the first output module, the second electrode of the first transistor serves as the second terminal of the first output module, and the gate of the first transistor serves as the control terminal of the first output module.

[0017] The second output module includes a second transistor, the first terminal of the second transistor serves as the first terminal of the second output module, the second terminal of the second transistor serves as the second terminal of the second output module, and the gate of the second transistor serves as the control terminal of the second output module.

[0018] The output control module includes a third transistor, the first terminal of the third transistor serves as the first terminal of the third output module, the second terminal of the third transistor serves as the second terminal of the third output module, and the gate of the third transistor serves as the control terminal of the third output module.

[0019] In one possible embodiment of the first aspect, when the first power supply terminal is at a low level, the second transistor is a P-type transistor, and the first and third transistors are N-type transistors;

[0020] In one possible embodiment of the first aspect, when the first power supply terminal is at a low level, the reference voltage configured for the reference power supply terminal is 0V or less than 0V.

[0021] Alternatively, when the first power supply terminal is high, the first and third transistors are P-type transistors, and the second transistor is an N-type transistor;

[0022] In one possible embodiment of the first aspect, when the first power supply terminal is at a high level, the reference voltage configured for the reference power supply terminal is 0V or greater than 0V.

[0023] In one possible embodiment of the first aspect, a coupling module is further included, which is electrically connected between the driver chip and the control terminal of the first output module;

[0024] In one possible embodiment of the first aspect, the coupling module includes a first capacitor, a first terminal of the first capacitor being electrically connected to a driver chip, and a second terminal of the first capacitor being electrically connected to a first output module.

[0025] Based on the same inventive concept, in a second aspect, embodiments of this application also provide a driving method for a level conversion circuit, applied to a level conversion circuit as described in any embodiment of the first aspect, the method comprising:

[0026] The original driving signal is inverted using a driver chip to obtain a first driving signal and then output the first driving signal.

[0027] The control level conversion circuit converts the first drive signal into a second drive signal to drive the gate drive circuit.

[0028] Based on the same inventive concept, in a third aspect, embodiments of this application also provide a display panel, including:

[0029] Gate drive circuit;

[0030] And, as described in any embodiment of the first aspect, a level conversion circuit is provided for outputting a second driving signal, which is used to drive a gate driving circuit.

[0031] In one possible embodiment of the third aspect, the driver chip is used to output N first driving signals, the timing of the N first driving signals is different, and the display panel includes N level conversion circuits, the N level conversion circuits correspond one-to-one with the N first driving signals, and N is an integer greater than or equal to 2.

[0032] Based on the same inventive concept, in a fourth aspect, embodiments of this application also provide a circuit board for driving a display panel, the display panel including a gate driving circuit;

[0033] The circuit board includes a level conversion circuit as described in any embodiment of the first aspect;

[0034] In one possible embodiment of the third aspect, the circuit board includes a printed circuit board or a flexible circuit board;

[0035] In one possible embodiment of the third aspect, the transistors of the level shifting circuit include N-type metal-oxide-semiconductor field-effect transistors and P-type metal-oxide-semiconductor field-effect transistors.

[0036] Based on the same inventive concept, in a fifth aspect, embodiments of this application also provide a display device, including:

[0037] Display panel, including gate drive circuitry;

[0038] The driver chip is used to provide the first drive signal;

[0039] And, as described in any embodiment of the first aspect, a level conversion circuit is used to convert a first driving signal into a second driving signal, the second driving signal being used to drive a gate driving circuit.

[0040] In one possible embodiment of the fifth aspect, the level shifting circuit is disposed on the display panel.

[0041] In one possible embodiment of the fifth aspect, where the display device further includes a circuit board, the level conversion circuit is disposed on the circuit board.

[0042] In one possible embodiment of the fifth aspect, the second power supply terminal is provided by the driver chip, and the second power supply terminal is also electrically connected to the gate drive circuit.

[0043] In one possible embodiment of the fifth aspect, the first power supply terminal is provided by a power supply or circuit outside the driver chip, and the first power supply terminal is also electrically connected to the gate drive circuit.

[0044] The level conversion circuit, driving method, display panel, circuit board, and display device of this application embodiment are described below. The level conversion circuit is electrically connected between the driving chip and the gate driving circuit. It is used to convert the first driving signal of the driving chip into a second driving signal. The second driving signal is used to drive the gate driving circuit. The second difference between the high level and the low level of the second driving signal is greater than the first difference between the high level and the low level of the first driving signal. Therefore, by introducing the level conversion circuit, the difference between the high level and the low level of the driving signal output by the display driving chip is increased, which realizes the effective utilization of the existing display driving chip and can reduce the waste of resources while meeting the greater voltage requirements. Attached Figure Description

[0045] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0046] Figure 1 This is a schematic diagram of the connection relationship of the level conversion circuit provided in an embodiment of this application;

[0047] Figure 2 This is a signal timing diagram of the input and output signals of the level conversion circuit provided in the embodiments of this application;

[0048] Figure 3 This is yet another signal timing diagram of the input and output signals of the level conversion circuit provided in the embodiments of this application;

[0049] Figure 4 This is a schematic diagram of a level conversion circuit provided in an embodiment of this application;

[0050] Figure 5 This is another schematic diagram of the level conversion circuit provided in the embodiments of this application;

[0051] Figure 6-a This is a schematic diagram of a level conversion circuit 20 provided in an embodiment of this application, which can meet the requirement of lower voltage.

[0052] Figure 6-b This is a schematic diagram of a level conversion circuit 20 provided in an embodiment of this application, which can meet higher voltage requirements;

[0053] Figure 7 This is a schematic flowchart of the driving method for the level conversion circuit provided in the embodiments of this application;

[0054] Figure 8-a This is a schematic diagram of a display panel provided in an embodiment of this application;

[0055] Figure 8-b This is another structural schematic diagram of the display panel provided in the embodiments of this application;

[0056] Figure 9-a This is a power connection diagram of a gate driving circuit in a display device provided in an embodiment of this application;

[0057] Figure 9-b This is another power connection diagram of the gate driving circuit in the display device provided in the embodiments of this application. Detailed Implementation

[0058] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0059] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0060] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0061] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0062] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0063] In related technologies, a display driver IC (DDIC) can provide drive signals to a gate in panel (GIP) circuit. The drive signals may include power supply signals (such as fixed high power supply voltage and fixed low power supply voltage), trigger signals (STV signals) and clock signals (CLK signals) for the gate in panel circuit to operate under the control of the drive signals.

[0064] The voltage of the drive signal that a display driver chip can provide typically includes a high voltage VGH (VGH > 0) and a low voltage VGL (VGL < 0). VGH and VGL together determine the voltage range of the drive signal that the display driver chip can output, that is, the maximum voltage range of the drive signal is the difference between VGH and VGL.

[0065] However, with the continuous advancement of display technology and the emergence of new display devices, the demand for voltage across the gate drive circuit is gradually increasing. When the voltage across the gate drive circuit exceeds the output capability of the display driver chip, even if the existing display driver chip is still in good working order, it cannot meet the needs of the gate drive circuit, resulting in idle and wasted resources.

[0066] Based on this, embodiments of this application provide a level conversion circuit and driving method, a display panel, a circuit board, and a display device. By introducing a level conversion circuit, the difference between the high and low levels of the driving signal output by the display driver chip is increased, realizing the effective utilization of existing display driver chips and reducing resource waste while meeting greater voltage requirements.

[0067] The level conversion circuit and driving method, display panel, circuit board and display device provided in the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0068] Figure 1 This is a schematic diagram of the connection relationship of a level conversion circuit provided in an embodiment of this application.

[0069] like Figure 1 As shown, the level conversion circuit 20 is electrically connected between the driver chip 10 and the gate drive circuit 30.

[0070] The level conversion circuit 20 can be used to convert the first drive signal of the driver chip 10 into a second drive signal.

[0071] The second drive signal can be used to drive the gate drive circuit 30.

[0072] The gate driving circuit 30 is used to generate a gate driving signal and is electrically connected to the sub-pixels in the display panel. Under the control of the gate driving signal, the sub-pixels can perform tasks such as writing data signals and emitting light.

[0073] It should be noted that both the first driving signal and the second driving signal are pulse signals. In the embodiments of this application, the relatively higher potential level in the pulse signal can be referred to as a high level, and the relatively lower potential level can be referred to as a low level.

[0074] The difference between the high and low levels of the first driving signal is a first difference ΔU1, and the difference between the high and low levels of the second driving signal is a second difference ΔU2, where ΔU2 > ΔU1. In other words, the level conversion circuit 20 can increase the first difference ΔU1 between the high and low levels of the input signal (first driving signal) to the second difference ΔU2.

[0075] According to the level conversion circuit 20 provided in the embodiments of this application, the level conversion circuit 20 is electrically connected between the driver chip 10 and the gate driving circuit 30, and is used to convert the first driving signal of the driver chip 10 into a second driving signal. The second driving signal is used to drive the gate driving circuit 30. The second difference ΔU2 between the high level and the low level of the second driving signal is greater than the first difference ΔU1 between the high level and the low level of the first driving signal. Therefore, by introducing the level conversion circuit 20, the difference between the high level and the low level of the first driving signal output by the driver chip 10 is increased, and the existing driver chip 10 is effectively utilized. It can meet the larger voltage requirements of the gate driving circuit 30 while reducing the waste of resources.

[0076] In some embodiments, such as Figure 2 As shown, at the same moment, a high potential of the second driving signal corresponds to a low potential of the first driving signal; or, at the same moment, a low potential of the second driving signal corresponds to a high potential of the first driving signal. In other words, when one of the second driving signal and the first driving signal reaches a high level, the other reaches a low level. This can be simply understood as the first driving signal and the second driving signal having opposite phases but different voltage ranges. For example, when the first driving signal is high, the second driving signal is low; when the first driving signal is low, the second driving signal is high. In this embodiment, the driving chip 10 can invert the original gate circuit driving signal and output the first driving signal to the level conversion circuit 20. Since the level conversion circuit 20 can convert the first driving signal into a second driving signal, and the second driving signal is out of phase with the first driving signal, the second driving signal after two inversions has the same phase as the original gate circuit driving signal. This can increase the voltage range of the original gate circuit driving signal without changing the control logic, thus meeting the larger voltage requirements of the gate driving circuit 30. This achieves effective utilization of the existing driving chip 10 and reduces resource waste while meeting larger voltage requirements.

[0077] Figure 3This is a timing diagram of the input signal (first driving signal) and output signal (second driving signal) of the level conversion circuit 20 provided in the embodiments of this application.

[0078] like Figure 3 The second driving signal (1), the second driving signal (2), and the second driving signal (3) shown correspond to different voltage requirements of the gate driving circuit 30.

[0079] In one embodiment, the gate drive circuit 30 has a lower voltage requirement, see [reference needed]. Figure 3 The signal waveform of the second driving signal (1) is shown. The high level of the second driving signal is equal to the high level of the first driving signal, and the low level of the second driving signal is less than the low level of the first driving signal. In this embodiment, the low level of the first driving signal can be reduced by using the level conversion circuit 20, based on the high level of the first driving signal, which can meet the requirement of a lower voltage for the gate driving circuit 30.

[0080] In yet another embodiment, the gate drive circuit 30 has a higher voltage requirement, see [reference needed] Figure 3 The signal waveform of the second driving signal (2) is shown in the figure. The high level of the second driving signal is greater than the high level of the first driving signal, and the low level of the second driving signal is equal to the low level of the first driving signal. In this embodiment, the high level of the first driving signal can be increased by using the level conversion circuit 20 based on the low level of the first driving signal, which can meet the higher voltage requirement of the gate driving circuit 30.

[0081] In yet another embodiment, the gate drive circuit 30 has higher and lower voltage requirements, see [reference needed]. Figure 3 The signal waveform of the second driving signal (3) is shown in the figure. The high level of the second driving signal is greater than the high level of the first driving signal, and the low level of the second driving signal is less than the low level of the first driving signal. In this embodiment of the application, by using the level conversion circuit 20 to increase the high level of the first driving signal while decreasing the low level of the first driving signal, the voltage range of the first driving signal can be flexibly increased, and the requirements of the gate driving circuit 30 for both lower and higher voltages can be met at the same time.

[0082] The following describes some exemplary structures of the level conversion circuit 20. It should be noted that these are merely examples and are not intended to limit this application. Any circuit structure capable of converting a first driving signal with a small difference into a second driving signal with a large difference can be applied to the level conversion circuit.

[0083] Figure 4 This is a schematic diagram of a level conversion circuit 20 provided in an embodiment of this application.

[0084] As an example, such as Figure 4 As shown, the level conversion circuit 20 may include a first output module 21 and a second output module 22. The first output module 21 and the second output module 22 may alternately transmit power signals from the first power supply terminal and the second power supply terminal to the gate drive circuit 30.

[0085] It should be noted that, as Figure 3 The second driving signals (1), (2), and (3) shown can correspond to different voltage requirements of the gate driving circuit. To meet the voltage requirements of the gate driving circuit 30, they can be flexibly adjusted. Figure 4 The magnitude of the power supply voltage configured at the first and second power supply terminals in the process can generate... Figure 3 Any of the second driving signals.

[0086] In one example, please refer to [link / reference]. Figure 4 The first output module 21 and the second output module 22 may include triggers with different triggering conditions, one being high-level trigger and the other low-level trigger, so that the first output module 21 and the second output module 22 can alternately reach the triggering condition. When the first output module 21 meets the triggering condition, it can output a power signal from the first power supply terminal; when the second output module 22 meets the triggering condition, it can output a power signal from the second power supply terminal. Therefore, the power signals from the first power supply terminal and the second power supply terminal can be alternately transmitted to the gate drive circuit 30, and by adjusting the magnitude of the power supply voltage configured at the first power supply terminal and the second power supply terminal, a [function / mechanism] can be generated. Figure 3 Any of the second driving signals.

[0087] Figure 5 This is another schematic diagram of the level conversion circuit 20 provided in the embodiments of this application.

[0088] like Figure 5 As shown, the level conversion circuit 20 may include a first output module 21, a second output module 22, and an output control module 23.

[0089] The first end of the first output module 21 is electrically connected to the first power supply terminal, and the second end of the first output module 21 is electrically connected to the gate drive circuit 30.

[0090] The first terminal of the second output module 22 is electrically connected to the second power supply terminal, and the second terminal of the second output module 22 is electrically connected to the gate drive circuit 30. The control terminal of the second output module 22 can be connected to the first drive signal. In response to the first drive signal, the second output module 22 can output the power signal from the second power supply terminal to the gate drive circuit 30.

[0091] The first terminal of the output control module 23 is electrically connected to the reference power supply terminal, the second terminal of the output control module 23 is electrically connected to the control terminal of the first output module 21, and the control terminal of the output control module 23 is connected to the first drive signal.

[0092] Under the control of the output control module 23 and the first drive signal, the first output module 21 and the second output module 22 can be turned on alternately, so that the power signals of the first power supply terminal and the second power supply terminal can be alternately transmitted to the gate drive circuit 30.

[0093] In this configuration, one of the first power supply terminal and the second power supply terminal is at a high level, and the other is at a low level, which are used to generate the high and low levels of the second drive signal.

[0094] When the first power supply terminal is at a low level, the low level of the first power supply terminal can be lower than the low level of the first drive signal, in order to meet the lower voltage requirement of the gate drive circuit 30.

[0095] When the first power supply terminal is at a high level, the high level of the first power supply terminal can be greater than the high level of the first drive signal, in order to meet the higher voltage requirements of the gate drive circuit 30.

[0096] In this embodiment, the level conversion circuit 20, through the coordinated operation of the first output module 21, the second output module 22 and the output control module 23, can alternately transmit the power signals of the first power supply terminal and the second power supply terminal to the gate drive circuit 30, and can drive the gate drive circuit 30 with a larger voltage requirement.

[0097] In one embodiment, when the first power supply terminal is at a low level VGL2, the low level VGL2 of the first power supply terminal is less than the low level VGL1 of the first drive signal, and the high level VGH of the second power supply terminal is equal to the high level VGH of the first drive signal, which can be used to output such as Figure 3 The second drive signal (1) is shown.

[0098] In another embodiment, when the first power supply terminal is at a high level VGH2, the high level VGH2 of the first power supply terminal is greater than the high level VGH1 of the first drive signal, and the low level VGL of the second power supply terminal is equal to the low level VGL of the first drive signal, which can be used to output such as Figure 3 The second drive signal (2) is shown.

[0099] In one embodiment, the second power supply terminal is the power supply terminal of the driver chip 10. In this embodiment, the power signal provided by the driver chip 10 to the second power supply terminal allows one voltage level in the second driving signal to be equal to one voltage level in the first driving signal, enabling the generation of... Figure 3The second drive signal (1) or the second drive signal (2) shown can also effectively utilize the existing pin functions of the drive chip 10, thereby saving resources and costs.

[0100] In another embodiment, the second power supply terminal can also be a power supply terminal of another power supply. The voltage magnitude of the power supply signal of the other power supply can be configured according to the actual voltage requirements of the gate drive circuit 30, providing greater flexibility and enabling the generation of signals such as... Figure 3 Any one of the second driving signal (1), the second driving signal (2), and the second driving signal (3) shown.

[0101] In some embodiments, see Figure 6-a or Figure 6-b The first output module 21 may include a first transistor T1. The first terminal of the first transistor T1 may serve as the first terminal of the first output module 21, the second terminal of the first transistor T1 may serve as the second terminal of the first output module 21, and the gate of the first transistor T1 may serve as the control terminal of the first output module 21.

[0102] The second output module 22 may include a second transistor T2. The first terminal of the second transistor T2 may serve as the first terminal of the second output module 22, the second terminal of the second transistor T2 may serve as the second terminal of the second output module 22, and the gate of the second transistor T2 may serve as the control terminal of the second output module 22.

[0103] The output control module 23 may include a third transistor T3. The first terminal of the third transistor T3 may serve as the first terminal of the output control module 23, the second terminal of the third transistor T3 may serve as the second terminal of the output control module 23, and the gate of the third transistor T3 may serve as the control terminal of the output control module 23.

[0104] In this embodiment, by controlling the on and off states of each transistor, power signals of different levels at the first and second power supply terminals can be output alternately, thereby generating a second driving signal with a wider voltage range, providing a more stable driving signal for the gate driving circuit 30.

[0105] Figure 6-a This is a schematic diagram of a level conversion circuit 20 provided in this application embodiment that can meet lower voltage requirements, and can generate such as Figure 3 The second drive signal (1) is shown.

[0106] In one embodiment, such as Figure 6-aAs shown, when the first power supply terminal is low, the second transistor T2 is a P-type transistor, and the first transistor T1 and the third transistor T3 are N-type transistors. In this embodiment, the first transistor T1 and the third transistor T3 can respond to the high level VGH of the first drive signal to transmit the power signal VGL2 from the first power supply terminal to the gate drive circuit 30; the second transistor T2 can respond to the low level VGL of the first drive signal to transmit the power signal VGH from the second power supply terminal to the gate drive circuit 30, thereby alternately transmitting VGH and VGL2 to the gate drive circuit 30 to meet the lower voltage requirement of the gate drive circuit 30, thereby generating... Figure 2 The second drive signal (1) is shown.

[0107] In yet another embodiment, see [link to relevant documentation]. Figure 6-a When the first power supply terminal is at a low level, the reference voltage Vref1 configured on the reference power supply terminal is 0V or <0V. In this embodiment, the magnitude of the reference voltage Vref1 determines the gate voltage of the first transistor T1, and the source voltage of the first transistor T1 is VGL2. Therefore, by adjusting the magnitude of the voltage Vref1, the on or off state of the first transistor T1 can be precisely controlled under different values ​​of VGL2.

[0108] Figure 6-b This is a schematic diagram of a level conversion circuit 20 provided in this application embodiment that can meet higher voltage requirements and generate, as shown in the diagram. Figure 3 The second drive signal (2) is shown.

[0109] In one embodiment, such as Figure 6-b As shown, when the first power supply terminal is high, the first transistor T1 and the third transistor T3 are P-type transistors, and the second transistor T2 is an N-type transistor. In this embodiment, the first transistor T1 and the third transistor T3 can respond to the low level VGL of the first drive signal and transmit the power signal VGH2 from the first power supply terminal to the gate drive circuit 30; the second transistor T2 can respond to the high level VGH1 of the first drive signal and transmit the power signal VGH2 from the second power supply terminal to the gate drive circuit 30, thereby alternately transmitting VGH2 and VGL to the gate drive circuit 30 to meet the higher voltage requirements of the gate drive circuit 30, thereby generating... Figure 3 The second drive signal (2) is shown.

[0110] In yet another embodiment, see also [link to previous document]. Figure 6-bWhen the first power supply terminal is at a high level, the reference voltage Vref2 configured on the reference power supply terminal is 0V or >0V. In this embodiment, the magnitude of the reference voltage Vref2 determines the gate voltage of the first transistor T1, and the source voltage of the first transistor T1 is VGH2. Therefore, by adjusting the magnitude of the voltage Vref2, the on or off state of the first transistor T1 can be precisely controlled under different values ​​of VGH2.

[0111] It should be noted that, through research, the inventors discovered that the source of the second transistor T2 is connected to VGH or VGL, and the gate of the second transistor T2 is also connected to VGH or VGL. Therefore, the state of the second transistor T2 is simple and controllable, and there is no need to introduce an output control module 23. However, since the source of the first transistor T1 is connected to VGL2 or VGH2, and VGL2 or VGH2 is determined according to the voltage requirements of the gate drive circuit 30, an output control module 23 is needed to effectively control the on and off states of the first transistor T1.

[0112] Further research by the inventors revealed that controlling the second transistor T2 to conduct requires effectively controlling the first transistor T1 to turn off. Figure 6-a and Figure 6-b Without coupling module 24, the first transistor T1 is turned off by first turning off the third transistor T3, leaving its gate floating and thus preventing it from meeting the turn-on condition. However, leaving the gate of the first transistor T1 floating makes its voltage Vgs uncertain, leading to the problem that the first transistor T1 cannot be effectively turned off. Therefore, by introducing coupling module, we can ensure that the gate of the first transistor T1 is always connected to a fixed voltage, making its voltage Vgs a fixed value, thereby ensuring that the first transistor T1 can be effectively turned off.

[0113] In some embodiments, see [link to relevant documentation] Figure 6-a or Figure 6-b The level conversion circuit 20 may further include a coupling module 24, which is electrically connected between the driver chip 10 and the control terminal of the first output module 21. The coupling module 24 ensures that the gate of the first transistor T1 is always connected to a defined voltage, and that this voltage can effectively control the turn-on and turn-off of the first transistor T1.

[0114] In one embodiment, see [link to previous article] Figure 6-a or Figure 6-b The coupling module 24 may include a first capacitor C1, the first terminal of the first capacitor C1 is electrically connected to the driver chip 10, and the second terminal of the first capacitor C1 is electrically connected to the first output module 21.

[0115] The following details the example of Vref1 = 0V. Figure 6-a The operation of the level conversion circuit 20 shown is as follows: Specifically:

[0116] 1) The driver chip 10 inverts the original gate circuit drive signal and outputs the first drive signal with levels VGH and VGL1, and transmits it to the level conversion circuit 20.

[0117] 2) When the first drive signal is high level VGH, the second transistor T2 of the level conversion circuit 20 is turned off and the third transistor T3 is turned on. Therefore, the gate of the first transistor T1 is Vref1=0V.

[0118] The voltage difference Vgs between the gate and source of the first transistor T1 is 0-VGL2 > the threshold voltage Vth_N of the first transistor T1, so the first transistor T1 is turned on. Therefore, the second drive signal is low level VGL2 at this time.

[0119] At this moment, the potential of the left plate of capacitor C1 is VGH, and the potential of the right plate is 0V.

[0120] 3) When the first drive signal is low (VGL1), the second transistor T2 is turned on, and the third transistor T3 is turned off. Since the second transistor T2 is on, the second drive signal is high (VGH) at this time.

[0121] It should be noted that, at this time, if the coupling module 24 is not connected, the gate of the first transistor T1 is in a floating state because the third transistor T3 is turned off, thus preventing the first transistor T1 from conducting. However, it cannot be guaranteed that it will turn off quickly and effectively, therefore the second drive signal cannot be guaranteed to be a pure high level VGH, which will affect the output quality of the second drive signal. Therefore, the coupling module 24 can be connected to output a high-quality second drive signal.

[0122] Based on the capacitor bootstrap effect (the voltage difference stored on the left and right plates of a capacitor cannot change abruptly), since the voltage change on the left plate of capacitor C1 is VGL1-VGH, the potential of the right plate of capacitor C1 is 0+(VGL1-VGH). Therefore, the gate potential of the first transistor T1 is 0+(VGL1-VGH). The voltage difference Vgs between the gate and source of the first transistor T1 is 0+(VGL1-VGH)-VGL2 < the threshold voltage Vth_N of the first transistor T1 (this voltage relationship is a prerequisite for the scheme), which satisfies the turn-off condition of the first transistor T1, allowing the first transistor T1 to be quickly turned off.

[0123] In this embodiment, by introducing the coupling module 24, the level conversion circuit 20 can achieve high-quality output of the second drive signal while processing the first drive signal output by the driver chip 10. Specifically, when the first drive signal becomes low level VGL1, due to the bootstrap effect of capacitor C1, the Vgs of the first transistor T1 is lower than its threshold voltage Vth_N, thereby ensuring that the first transistor T1 can be turned off quickly and effectively, allowing the second drive signal to quickly reach high level VGH. This effectively solves the problem that the first transistor T1 may not be able to turn off quickly when the gate is floating when the third transistor T3 is turned off, thereby improving the output quality and stability of the second drive signal and ensuring the quality and reliability of the output signal.

[0124] It should be noted that, Figure 6-a The power signal VGL1 generated by the driver chip 10 shown does not need to be connected to the gate driver circuit 30. Instead, the power signal VGH generated by the driver chip 10 can be connected to the gate driver circuit to provide a power signal for the gate driver circuit 30, improving the utilization of chip pins and saving resources and costs. Alternatively, other circuits can be used to generate the VGL2 power supply to power the gate driver circuit 30 and the level conversion circuit 20.

[0125] In another embodiment, see also Figure 6-a Since VGL2 is determined by the specific voltage requirements of the gate drive circuit 30, there is a situation where the turn-off condition of the first transistor T1 is not met when Vref1 = 0V, causing the first transistor T1 to be unable to turn off quickly and effectively when it needs to be turned off. That is, when Vref1 = 0V, the turn-off condition of the first transistor T1, "the voltage difference between the gate and source of the first transistor T1 is 0 + (VGL1 - VGH) - VGL2 < the threshold voltage Vth_N of the first transistor T1," is not met. Therefore, Vref1 must be set < 0V and must also satisfy:

[0126]

[0127] Wherein, VGH is the high level of the first drive signal, VGL1 is the low level of the first drive signal, VGL2 is the signal at the first power supply terminal, Vth_T1 is the threshold voltage of the first switch T1, and Vth_T3 is the threshold voltage of the third switch T3. In this embodiment, by adjusting... Figure 6-a The voltage magnitude of the reference voltage Vref1 at the reference power supply terminal can precisely control the rapid on and off of the first output module 21, thereby quickly and accurately alternating the output of power signals from the first power supply terminal and the second power supply terminal, and quickly and accurately generating the second drive signal.

[0128] In this embodiment, the first output module 21 (specifically, the first transistor T1) can be precisely controlled to turn on and off rapidly by adjusting the reference voltage Vref1 at the reference power supply terminal. When Vref1 = 0V, the turn-off condition of the first transistor T1 is not met, causing the first transistor T1 to fail to turn off quickly and effectively when it needs to be turned off.

[0129] The following section uses Vref2 = 0V as an example to provide a detailed explanation. Figure 6-b The operation of the level conversion circuit 20 shown is as follows: Specifically:

[0130] 1) When the first drive signal is low (VGL), the second transistor T2 is off and the third transistor T3 is on. Therefore, the gate voltage of the first transistor T1 is Vref2 = 0V. The voltage difference Vgs between the gate and source of the first transistor T1 is 0 - VGH2 < the threshold voltage Vth_P of the first transistor T1. The first transistor T1 is on, so the second drive signal outputs a high level (VGH2).

[0131] At this moment, the potential of the left plate of capacitor C1 is VGL, and the potential of the right plate is 0V.

[0132] 2) When the first drive signal is high (VGH1), the second transistor T2 is turned on, and the third transistor T3 is turned off. Since the voltage across the left plate of capacitor C1 is VGH1 - VGL, and the original voltage across the right plate is 0V, the right plate potential changes to approximately 0 + (VGH1 - VGL) due to the capacitor bootstrap effect. Therefore, the gate voltage of the first transistor T1 is approximately 0 + (VGH1 - VGL). The voltage difference Vgs between the gate and source of the first transistor T1 is approximately 0 + (VGH1 - VGL) - VGH2 > the threshold voltage Vth_P of the first transistor T1 (this voltage relationship is a prerequisite for the scheme). Therefore, the first transistor T1 is turned off, and the second drive signal outputs a low level (VGL).

[0133] In this embodiment, a coupling module 24 and a level conversion circuit 20 are introduced to achieve high-quality output of a second driving signal while processing the first driving signal output by the driver chip 10. Specifically, when the first driving signal becomes high level VGH1, due to the bootstrap effect of capacitor C1, the Vgs of the first transistor T1 is higher than its threshold voltage Vth_P, thereby ensuring that the first transistor T1 can be turned off quickly and effectively, allowing the second driving signal to quickly reach low level VGL. This effectively solves the problem that the first transistor T1 may not be able to turn off quickly when the gate is floating when the third transistor T3 is turned off, thereby improving the output quality and stability of the second driving signal and ensuring the quality and reliability of the output signal.

[0134] It should be noted that when the display screen is set to a higher ELVDD, the gate drive circuit 30 requires a higher VGH voltage. If the driver chip 10 cannot output such a high VGH power supply and corresponding drive signal, it may be unusable. Figure 6-b The level conversion circuit 20 shown.

[0135] In another embodiment, see also Figure 6-a Since VGH2 is determined by the specific voltage requirements of the gate drive circuit 30, there is a situation where the turn-off condition of the first transistor T1 is not met when Vref2 = 0V, causing the first transistor T1 to be unable to turn off quickly and effectively when it needs to be turned off. That is, when Vref2 = 0V, the turn-off condition of the first transistor T1, "the voltage difference between the gate and source of the first transistor T1 is 0 + (VGH1 - VGL) - VGH2 > the threshold voltage Vth_P of the first transistor T1," is not met. Therefore, Vref2 must be set > 0V and must satisfy the following:

[0136]

[0137] Wherein, VGL is the low level of the first drive signal, VGH1 is the high level of the first drive signal, VGH2 is the signal at the second power supply terminal, Vth_T1 is the threshold voltage of the first switch T1, and Vth_T3 is the threshold voltage of the third switch T3. In this embodiment, by adjusting... Figure 6-b The voltage of the power signal Vref2 at the reference power supply terminal can be used to precisely control the rapid turn-on and turn-off of the first transistor T1, thereby quickly and accurately alternating the output of the power signals at the first power supply terminal and the second power supply terminal, ensuring the quality and reliability of the output signal.

[0138] It should be noted that the threshold voltage Vth_P of a P-type transistor is negative, for example, Vth_P = -1V, while the threshold voltage Vth_N of an N-type device is positive, for example, Vth_N = +1V.

[0139] Based on the same inventive concept, such as Figure 7 As shown, this application embodiment also provides a driving method for a level conversion circuit, applied to the level conversion circuit described in any of the above embodiments. The driving method for the level conversion circuit includes steps S110 and S120.

[0140] S110: The original driving signal is inverted using the driver chip 10 to obtain the first driving signal and output the first driving signal.

[0141] The original driving signal is the gate circuit driving signal that the driving chip 10 should have output. The voltage range of the original driving signal cannot meet the larger voltage requirements of the gate driving circuit 30.

[0142] Specifically, the driver chip 10 can be used to invert the original drive signal and output a first drive signal, which is opposite in phase to the original drive signal and has the same voltage range.

[0143] S120, the control level conversion circuit 20 converts the first driving signal into a second driving signal to drive the gate driving circuit 30.

[0144] Specifically, the level conversion circuit 20 can be controlled to convert the first driving signal into a second driving signal. The second driving signal is out of phase with the first driving signal but has a different voltage range. The voltage range of the second driving signal is greater than that of the first driving signal, so the second driving signal can be used to drive the gate driving circuit, which can meet the greater voltage requirements of the gate driving circuit.

[0145] In this embodiment, the driver chip 10 can invert the original gate circuit drive signal and output the first drive signal to the level conversion circuit 20. Since the level conversion circuit 20 can convert the first drive signal into a second drive signal, the second drive signal is out of phase with the first drive signal and has a different voltage range. Therefore, the second drive signal after two inversions is in phase with the original gate circuit drive signal. This can increase the voltage range of the original gate circuit drive signal without changing the control logic, thus meeting the greater voltage requirements of the gate drive circuit 30. This achieves effective utilization of the existing driver chip 10 and reduces resource waste while meeting greater voltage requirements.

[0146] Based on the same inventive concept, such as Figure 8-a As shown, this application embodiment also provides a display panel 100, which may include a gate driving circuit 30 and a level conversion circuit 20 as described in any of the above embodiments. The level conversion circuit 20 is used to output a second driving signal, which is used to drive the gate driving circuit 30.

[0147] In this embodiment, the level conversion circuit 20 can be located on the display panel, which can greatly improve the integration and reduce the overall size and weight.

[0148] It should be noted that since the display panel 100 includes the level conversion circuit 20 provided in any of the above embodiments, the display panel 100 has all the beneficial effects of the level conversion circuit 20.

[0149] In some embodiments, see [link to relevant documentation] Figure 8-aThe driver chip 10 outputs N first driving signals (STV1, CLK1, CLK2, etc.), with different timing sequences for each of the N first driving signals. The display panel 100 may include N level conversion circuits 20, each corresponding one-to-one with one of the N first driving signals, where N is an integer greater than or equal to 2. In this embodiment, each level conversion circuit 20 performs level conversion for a specific first driving signal, which helps improve signal stability and accuracy.

[0150] In one embodiment, the transistor of the level conversion circuit 20 is a thin film transistor (TFT). In this embodiment, the transistor of the level conversion circuit 20 located on the display panel 100 can be a thin film transistor (TFT), which can achieve more precise and reliable control and improve response speed.

[0151] Based on the same inventive concept, such as Figure 8-b As shown, this application embodiment also provides a circuit board 200, which is used to drive a display panel 100. The display panel 100 may include a gate driving circuit 30.

[0152] The circuit board 200 may include the level conversion circuit 20 described in any of the above embodiments.

[0153] In some embodiments, circuit board 200 may include a printed circuit board or a flexible circuit board.

[0154] In some embodiments, the transistors of the level shifting circuit 20 include two types of transistors: N-Metal-Oxide Semiconductor Field-Effect Transistor (NMOS-FET) and P-Metal-Oxide Semiconductor Field-Effect Transistor (PMOS-FET).

[0155] In this embodiment, the level conversion circuit 20 can be located on a printed circuit board (PCB) or flexible circuit board (FPC) outside the screen, thus allowing for disassembly and maintenance. Furthermore, the suitability of the existing driver chip 10 for direct use can be determined based on whether the gate drive circuit 30 has a higher voltage requirement, thereby deciding whether to connect the level conversion circuit 20. And if the gate drive circuit 30 has a higher voltage requirement, the appropriate decision can be made based on factors such as… Figure 2 Different high voltage requirements can be selected to connect to different level conversion circuits 20, which provides greater flexibility.

[0156] It should be noted that since the circuit board 200 includes the level conversion circuit 20 provided in any of the above embodiments, the circuit board 200 has all the beneficial effects of the level conversion circuit 20.

[0157] Based on the same inventive concept, this application also provides a display device 1000, comprising:

[0158] Display panel 100 includes gate drive circuit 30;

[0159] Driver chip 10 is used to provide the first drive signal;

[0160] And, as described in any of the above embodiments, the level conversion circuit 20 is used to convert the first driving signal into a second driving signal, the second driving signal being used to drive the gate driving circuit.

[0161] The display device 1000 includes the level conversion circuit 20 provided in any of the above embodiments, and therefore the display device 1000 has all the beneficial effects of the level conversion circuit 20.

[0162] In some embodiments, the level conversion circuit 20 is disposed on the display panel 100. By disposing the level conversion circuit 10 on the display panel 100 in this application embodiment, the integration of the entire display device 1000 can be improved, the assembly process simplified, and the overall reliability of the product enhanced.

[0163] In one embodiment, if the display device further includes a circuit board 200, the level conversion circuit 10 may also be disposed on the circuit board 200. By disposing the level conversion circuit 10 on the circuit board 200 in this embodiment, it is possible to flexibly address the different voltage requirements of the gate drive circuit 30.

[0164] In one embodiment, such as Figure 9-a or Figure 9-b As shown, the second power supply terminal is provided by the driver chip 10, and the second power supply terminal is also electrically connected to the gate drive circuit 30. In this embodiment, the second power supply terminal is provided by the driver chip 10, which helps to make efficient use of resources, reduce the number of external power supplies, and reduce costs.

[0165] In one embodiment, see continue to see Figure 9-a or Figure 9-b The first power supply terminal is provided by a power supply or circuit other than the driver chip. The first power supply terminal is also electrically connected to the gate drive circuit 30, so that it can provide a larger voltage requirement for the gate drive circuit 30 while providing a matching power signal, making full use of existing resources and saving costs.

[0166] It should be noted that the display device 1000 can be at least one of wearable devices, cameras, mobile phones, tablets, displays, televisions, and vehicle-mounted display terminals. Since the display device 1000 includes the level conversion circuit 20 provided in any of the above embodiments, the display device 1000 has all the beneficial effects of the level conversion circuit 20.

[0167] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0168] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A level conversion circuit, characterized in that, The level conversion circuit is electrically connected between the driver chip and the gate driver circuit, and is used to convert the first driving signal of the driver chip into a second driving signal. The second driving signal is used to drive the gate driver circuit. The difference between the high level and the low level of the first driving signal is a first difference value, and the difference between the high level and the low level of the second driving signal is a second difference value. The second difference value is greater than the first difference value. The level conversion circuit includes: The first output module has a first terminal electrically connected to a first power supply terminal and a second terminal electrically connected to the gate drive circuit. The second output module has a first terminal electrically connected to the second power supply terminal, a second terminal electrically connected to the gate drive circuit, and a control terminal connected to the first drive signal. An output control module, the first end of which is electrically connected to the reference power supply terminal, and the second end of which is electrically connected to the control terminal of the first output module, and the control terminal is connected to the first drive signal; Under the control of the output control module and the first drive signal, the first output module and the second output module are alternately turned on; One of the first power supply terminal and the second power supply terminal is at a high level, and the other is at a low level. When the first power supply terminal is at a low level, the low level of the first power supply terminal is less than the low level of the first drive signal; when the first power supply terminal is at a high level, the high level of the first power supply terminal is greater than the high level of the first drive signal. When the first power supply terminal is at a low level, the high level of the second power supply terminal is greater than or equal to the high level of the first drive signal; when the first power supply terminal is at a high level, the low level of the second power supply terminal is less than or equal to the low level of the first drive signal.

2. The level conversion circuit according to claim 1, characterized in that, At the same time, the high potential of the second driving signal corresponds to the low potential of the first driving signal; or, at the same time, the low potential of the second driving signal corresponds to the high potential of the first driving signal.

3. In the level conversion circuit according to claim 2, the high level of the second driving signal is equal to the high level of the first driving signal, and the low level of the second driving signal is less than the low level of the first driving signal; Alternatively, the high level of the second driving signal is greater than the high level of the first driving signal, and the low level of the second driving signal is equal to the low level of the first driving signal.

4. The level conversion circuit according to claim 1, characterized in that, The first output module includes a first transistor, the first terminal of the first transistor serves as the first terminal of the first output module, the second terminal of the first transistor serves as the second terminal of the first output module, and the gate of the first transistor serves as the control terminal of the first output module. The second output module includes a second transistor, the first terminal of the second transistor serves as the first terminal of the second output module, the second terminal of the second transistor serves as the second terminal of the second output module, and the gate of the second transistor serves as the control terminal of the second output module; The output control module includes a third transistor, the first terminal of which serves as the first terminal of the output control module, the second terminal of which serves as the second terminal of the output control module, and the gate of which serves as the control terminal of the output control module.

5. In the level conversion circuit according to claim 4, when the first power supply terminal is at a low level, the second transistor is a P-type transistor, and the first transistor and the third transistor are N-type transistors.

6. In the level conversion circuit according to claim 5, when the first power supply terminal is at a low level, the reference voltage configured for the reference power supply terminal is 0V or less than 0V.

7. In the level conversion circuit according to claim 4, when the first power supply terminal is at a high level, the first transistor and the third transistor are P-type transistors, and the second transistor is an N-type transistor.

8. In the level conversion circuit according to claim 7, when the first power supply terminal is at a high level, the reference voltage configured for the reference power supply terminal is 0V or greater than 0V.

9. The level conversion circuit according to any one of claims 1 to 8, characterized in that, It also includes a coupling module, which is electrically connected between the driver chip and the control terminal of the first output module.

10. The level conversion circuit according to claim 9, wherein the coupling module includes a first capacitor, the first terminal of the first capacitor is electrically connected to the driving chip, and the second terminal of the first capacitor is electrically connected to the first output module.

11. A driving method for a level conversion circuit, characterized in that, The method, applied to the level conversion circuit as described in any one of claims 1 to 10, comprises: The original driving signal is inverted using a driving chip to obtain a first driving signal, which is then output. The level conversion circuit is controlled to convert the first driving signal into a second driving signal to drive the gate driving circuit.

12. A display panel, characterized in that, include: Gate drive circuit; And, the level conversion circuit according to any one of claims 1 to 10, wherein the level conversion circuit is used to output a second driving signal, the second driving signal being used to drive the gate driving circuit.

13. The display panel according to claim 12, wherein the driving chip is used to output N first driving signals, the timing of the N first driving signals is different, the display panel includes N level conversion circuits, the N level conversion circuits correspond one-to-one with the N first driving signals, and N is an integer greater than or equal to 2.

14. A circuit board, characterized in that, The circuit board is used to drive the display panel, and the display panel includes a gate driving circuit. The circuit board includes a level conversion circuit as described in any one of claims 1 to 10.

15. The circuit board according to claim 14, wherein the circuit board comprises a printed circuit board or a flexible circuit board.

16. The circuit board according to claim 14, wherein the transistors of the level conversion circuit include N-type metal-oxide-semiconductor field-effect transistors and P-type metal-oxide-semiconductor field-effect transistors.

17. A display device, characterized in that, include: Display panel, including gate drive circuitry; The driver chip is used to provide the first drive signal; And, the level conversion circuit according to any one of claims 1 to 10, wherein the level conversion circuit is used to convert the first driving signal into a second driving signal, the second driving signal being used to drive the gate driving circuit.

18. The display device according to claim 17, characterized in that, The level conversion circuit is located on the display panel.

19. The display device according to claim 18, wherein if the display device further includes a circuit board, the level conversion circuit is disposed on the circuit board.

20. The display device according to claim 19, wherein the second power supply terminal is provided by the driving chip, and the second power supply terminal is also electrically connected to the gate driving circuit.

21. The display device according to claim 20, wherein the first power supply terminal is provided by a power supply or circuit other than the driving chip, and the first power supply terminal is also electrically connected to the gate driving circuit.

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