Semiconductor structure and method for forming memory circuit

Abstract

A semiconductor structure according to the present disclosure includes a first memory array in a first cache memory and a second memory array in a second cache memory. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to N1 first memory cells in one of the M1 rows, and a second bit line coupled to N2 second memory cells in one of the M2 rows. N1 is less than N2 and a width of the first bit line is less than a width of the second bit line. The embodiment of the invention also discloses a method for forming the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming memory circuits. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and advanced functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs. However, this scaling down has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] This scaling down of integrated circuit technology not only complicates the manufacturing process, but also poses specific challenges in the design and functionality of memory arrays within memory devices. For example, the operation of memory arrays in different cache memory levels (e.g., a primary cache memory and a secondary cache memory) requires a tailored structural design for the corresponding signal lines (e.g., bit lines). The traditional approach of using bit lines with uniform widths across different cache memory levels is increasingly insufficient because it does not optimally meet the different performance requirements of these cache memories. Using a unified bitline structure between these cache memories may result in suboptimal performance, where the specific requirements of each cache memory type (e.g., low parasitic capacitance in a primary cache memory and low voltage drop for a secondary cache memory) are not fully met. This difference highlights the need for a differentiated approach in bitline architecture to improve the overall efficiency and performance of memory devices, especially in the context of advanced semiconductor technologies. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a first memory array in a first cache memory, the first memory array comprising a plurality of first memory cells arranged in M1 rows and N1 columns, M1 and N1 being respectively integers; a first bit line coupled to N1 first memory cells in a row among the M1 rows, the first bit line having a first width; a second memory array in a second cache memory, the second memory array comprising a plurality of second memory cells arranged in M2 rows and N2 columns, M2 and N2 being respectively integers; and a second bit line coupled to N2 second memory cells in a row among the M2 rows, the second bit line having a second width, wherein N1 is less than N2 and the first width is less than the second width.

[0005] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a first memory array, arranged in a first region of the semiconductor structure, the first memory array having a plurality of first memory cells, the first memory array comprising a first bit line electrically coupled to a first number of first memory cells; and a second memory array, arranged in a second region of the semiconductor structure, the second memory array having a plurality of second memory cells, the second memory array comprising a second bit line electrically coupled to a second number of second memory cells, wherein the first number is smaller than the second number, and a width of the first bit line is smaller than a width of the second bit line.

[0006] According to another aspect of an embodiment of the present application, a method for forming a memory circuit is provided, comprising: forming a first memory array in a first cache memory located in the memory circuit, the first memory array comprising a plurality of first memory cells; forming a second memory array in a second cache memory located in the memory circuit, the second memory array comprising a plurality of second memory cells; forming a first bit line suspended above the first memory array, the first bit line being coupled to at least a portion of the first memory cells; and forming a second bit line suspended above the second memory array, the second bit line being coupled to at least a portion of the second memory cells, wherein a width of the first bit line is different from a width of the second bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a block diagram of an integrated circuit (IC) having memory circuits according to various aspects of the present disclosure.

[0009] Figure 2 is a block diagram of a memory macro having a memory array according to various aspects of the present disclosure.

[0010] Figure 3 is a circuit schematic of a static random access memory (SRAM) cell according to various aspects of the present disclosure.

[0011] Figure 4 Cross-sectional views of various layers of a memory device according to various aspects of the present disclosure are shown.

[0012] Figure 5 and Figure 6 The following are respectively shown according to various aspects of the present disclosure. Figure 3The SRAM cell shown includes the layout of the device layers and metal layers.

[0013] Figure 7 and Figure 8 The following are shown according to various aspects of the present disclosure. Figure 2 Portions of a memory macro are shown including layouts of device and metal layers, respectively.

[0014] Fig. 9 A layout of device and metal layers including a portion of a memory circuit including at least two different memory arrays according to various aspects of the present disclosure is shown.

[0015] Fig.10 Options for design parameters implemented in a memory circuit according to various aspects of the present disclosure are shown.

[0016] Fig.11 The invention is shown along the Fig. 9 Partial cross-sectional views of sections AA, BB, A'-A' and B'-B' in FIG.

[0017] Fig.12 is a block diagram of an IC manufacturing flow according to various aspects of the present disclosure.

[0018] Fig.13 is a flow chart of a method of adjusting bit line width in an IC layout according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0021] In addition, when "about," "approximately," etc. are used to describe a number or range of numbers, the term is intended to include numbers within a reasonable range, taking into account the variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features associated with the number, the number or range covers a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer with a thickness of "about 5nm" may include a size range of 4.25nm to 5.75nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / - 15%. When describing aspects of transistors, the source / drain regions may be referred to individually or collectively as the source or drain, depending on the context.

[0022] Static random access memory (SRAM) is a semiconductor memory that retains data statically as long as power is applied. Unlike dynamic RAM (DRAM), SRAM is faster, more reliable, and does not need to be constantly refreshed. SRAM is widely used in various applications, including computer memory. Computer memory can include different cache memory levels, such as a primary cache memory and a secondary cache memory. Each cache memory level may have different structural design requirements to achieve optimal performance. For example, the primary cache memory, which is the fastest cache memory, may prefer a structural design of signal lines that minimize delays and maximize data transfer rates by reducing parasitic capacitance. In contrast, the secondary cache memory, which acts as a secondary buffer and is located farther away from the CPU, may prefer a structural design of signal lines with reduced resistance to provide greater voltage margin. In the context of bitline structure, using a uniform bitline width across different cache memory levels may result in suboptimal performance because it does not meet the unique requirements of each cache memory type.

[0023] The present disclosure introduces a bitline structure that provides different bitline widths for SRAM arrays of different cache memory levels. In one embodiment, a memory device can have two or more bitline widths for different cache memory levels of an SRAM array, thereby improving performance to meet different needs. Another embodiment allows the same cache memory levels of different sizes within an SRAM array to have different bitline widths, thereby further optimizing the performance of the memory device. In addition, it is proposed to pair different bitline widths with various SRAM cell designs (such as high current and high density cell designs) to further optimize the performance of the memory device.

[0024] Figure 1 1 shows a simplified block diagram of an IC 10 according to some embodiments. The IC 10 includes a processing unit 12 and a memory circuit 14 integrated in the IC 10. As shown, the processing unit 12 includes an arithmetic logic unit (ALU) 16 and a memory management unit (MMU) 18. The processing unit 12 may include various components, such as one or more flip-flops, one or more scan chains, one or more registers, etc. For ease of illustration, Figure 1 These components are omitted.

[0025] The memory circuit 14 includes memory cells (e.g., SRAM cells and / or DRAM cells), which are organized into one or more primary cache memories 20, one or more secondary cache memories 22, one or more tertiary cache memories 24, and a main memory 26. Optionally, the memory circuit 14 may also include one or more n-level cache memories (n>3). Any suitable type of SRAM cells and / or DRAM cells may be used. For example, the primary cache memory 20, the secondary cache memory 22, and the tertiary cache memory 24 may be implemented by SRAM cells, while the main memory 26 may be implemented by DRAM cells. The processing unit 12 and the memory circuit 14 are communicatively coupled together via an internal bus system 28 in the IC 10.

[0026] Typically, the primary cache memory 20 is the fastest cache memory and is used to store data that is recently accessed by the processing unit 12. In addition, when the processing unit 12 executes a computer instruction, the primary cache memory 20 is the first cache memory to be accessed and processed. The secondary cache memory 22 may not be as fast as the primary cache memory 20, but the capacity can be increased. The tertiary cache memory 24 works in conjunction with the primary and secondary cache memories to improve computer performance by preventing bottlenecks caused by long fetch execution cycles. In addition, the memory performance of the tertiary cache memory 24 is slower than that of the secondary cache memory 22. For example, the primary cache memory 20 can generally have a faster response speed than the secondary cache memory 22, and the secondary cache memory 22 can generally have a faster response speed than the tertiary cache memory 24. Regarding memory capacity, the primary cache memory 20 is smaller than the secondary cache memory 22, and the secondary cache memory 22 is smaller than the tertiary cache memory 24. For example, a level 1 cache memory 20 may include 64K memory bits, a level 2 cache memory 22 may include 128K memory bits and a level 3 cache memory 24 may include 512K or even more memory bits.

[0027] The one or more processing units 12, in operation, generate one or more signals to control the operation of the IC 10. Such functionality may be provided, for example, by the processing unit 12 executing instructions retrieved from the memory circuit 14. The MMU 18 of the processing unit 12, in operation, may control the storage and retrieval of data and instructions from the primary cache 20, the secondary cache 22, the tertiary cache 24, and the main memory 26 of the memory circuit 14 and / or one or more memories external to the IC 10 via the internal bus system 28 and / or one or more interfaces (not shown). The MMU 18 may include a plurality of addressing circuits that may facilitate simultaneous use of the primary cache 20, the secondary cache 22, the tertiary cache 24, and the main memory 26.

[0028] Memory management routines (e.g., cache control routines) may be used to control data and instruction transfers between the primary cache 20, the secondary cache 22, the tertiary cache 24, and the main memory 26. Embodiments of the IC 10 may have fewer components than shown (e.g., the tertiary cache 24 may be optional), may have more components than shown, may combine or separate the components shown, and may rearrange the components shown. For example, the MMU 18 may be divided into multiple MMUs 18 (e.g., a first MMU 18 for controlling the primary cache 20, a second MMU 18 for controlling the secondary cache 22 and the tertiary cache 24, and a third MMU 18 for controlling the main memory 26). In another example, the MMU 18 may be part of the memory circuit 14 rather than part of the processing unit 12.

[0029] Figure 2 It shows that it can be Figure 1 14. For example, the memory macro 30 may be part of the primary cache 20, the secondary cache 22, the tertiary cache 24, or the main memory 26 in the memory circuit 14. In the illustrated embodiment, the memory macro 30 is an SRAM macro, such as a single-port SRAM macro, a dual-port SRAM macro, or another type of SRAM macro. However, the present disclosure contemplates some embodiments in which the memory macro 30 is another type of memory, such as a dynamic random access memory (DRAM), a non-volatile random access memory (NVRAM), flash memory, or another suitable memory. For clarity, Figure 2 It is simplified to better understand the inventive concepts of the present disclosure. Additional components may be added to the memory macro 30, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the memory macro 30.

[0030] Memory macro 30 includes a memory array 32, input / output (I / O) circuits 34, word line drivers 36, and control circuits 38. Memory array 32 includes memory cells arranged in rows and columns. In the illustrated embodiment, the memory cells are arranged from row 1 to row M, each row extending along a first direction (here, the X direction), and from column 1 to column N, each column extending along a second direction (here, the Y direction), where M and N are positive integers. To simplify the description, Figure 2 Only a few rows and columns and the corresponding memory cells are shown. Each memory cell stores one bit of data. Therefore, the memory cell is also called a bit cell or represented as a BC according to the position of the memory cell in the memory array 32. mn , where m represents the row and n represents the column. For example, BC 11BC represents a memory cell located in the first row (row 1) and the first column (column 1), which is the memory cell in the first row (row 1) closest to the I / O circuit 34; 12 BC represents a memory cell located in the first row (row 1) and the second column (column 2), which is the memory cell in the first row (row 1) that is the second closest to the I / O circuit 34; 1N BC represents a memory cell located in the first row (row 1) and the last column (column N), which is the memory cell farthest from the I / O circuit 34 in the first row (row 1); MN Denotes the memory cell located in the last row (row M) and the last column (column N). For simplicity, memory cell BC mn It can be called BC.

[0031] Rows 1 to M each include a bit line pair extending in the X direction, such as a bit line (BL) and an inverted bit line (BLB) (also referred to as a complementary bit line), which facilitates reading data from and / or writing data to each memory cell BC in true and complementary form row by row. Columns 1 to N each include a word line (WL) that facilitates accessing each memory cell BC column by column. Each memory cell BC is electrically connected to a corresponding BL, a corresponding BLB, and a corresponding WL.

[0032] I / O circuit 34 is coupled to memory array 32 through bit line pair BL and BLB. In some embodiments, I / O circuit 34 is configured to select one of the rows in memory array 32 and provide a bit line signal on one of the bit line pairs arranged on the selected row. The bit line signal is transmitted to the corresponding memory cell BC through the selected bit line pair BL and BLB for writing bit data into the corresponding memory cell BC or reading bit data from the corresponding memory cell BC.

[0033] The word line driver 36 is coupled to the memory array 32 through the word lines WL. In some embodiments, the word line driver 36 is configured to select one of the columns in the memory array 32 and provide a word line signal on one of the word lines WL arranged on the selected column. The word line signal is transmitted to the corresponding memory cell BC through the selected word line WL for writing bit data into the corresponding memory cell BC or reading bit data from the corresponding memory cell BC.

[0034] The control circuit 38 is coupled to the I / O circuit 34 and the word line driver 36 and is disposed next to them. The control circuit 38 configures the I / O circuit 34 and the word line driver 36 to generate one or more signals to select at least one WL and at least one bit line pair (here BL and BLB) to access at least one of the memory cells BC for a read operation and / or a write operation. The control circuit 38 includes any circuit suitable for facilitating operations of reading from or writing to the memory cells BC, including but not limited to a column decoder circuit, a row decoder circuit, a column selection circuit, a row selection circuit, a read / write circuit (e.g., configured to read data from and / or write data to the memory cell BC corresponding to the selected bit line pair (in other words, the selected column), other suitable circuits or combinations thereof. In some embodiments, the control circuit 38 is implemented by a processor. In some other embodiments, the control circuit 38 is integrated with the processor. The processor is implemented by a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0035] In a write or read operation, the I / O circuit 34 and the word line driver 36 select at least one pair of bit lines and at least one word line WL, respectively. When a word line WL on a corresponding column is selected, a bit line signal is transmitted from the I / O circuit 34 to a corresponding memory cell BC, or the bit line signal is transmitted from the memory cell BC to the I / O circuit 34. For a smaller memory array 32, such as a memory array in a first-level cache memory, the transmission path along the signal line in the bit line pair (here, the BL and BLB extending through column 1 to column N) becomes shorter; in contrast, for a larger memory array 32, such as a memory array in a second-level cache memory, the transmission path along the signal line in the bit line pair (here, the BL and BLB extending through column 1 to column N) becomes longer. The shorter transmission path of a smaller array can result in faster access time and lower power consumption because reduced capacitance and resistance contribute to faster signal transmission and reduced dynamic power consumption. In contrast, the longer transmission path of a larger array increases resistance and capacitance, which may slow down access time and increase power consumption. Therefore, the size of the signal lines in a bit line pair directly affects the performance optimization of different levels of cache memory in a computing system.

[0036] Figure 3 is a circuit diagram of an exemplary SRAM cell 50, which may be implemented as Figure 2 The memory cell BC in the Figure 1In the illustrated embodiment, the SRAM cell 50 is a single-port (SP) six-transistor (6T) SRAM cell. In various embodiments, the SRAM cell 50 may be other types of memory cells, such as a dual-port memory cell or a memory cell having more than six transistors. For clarity, Figure 3 It is simplified for better understanding of the inventive concepts of the present disclosure. Additional components may be added in the single-port SRAM cell 50 , and some of the components described below may be replaced, modified, or eliminated in other embodiments of the single-port SRAM cell 50 .

[0037] The exemplary SRAM cell 50 is a single-port SRAM cell that includes six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-2. In operation, the pass-gate transistor PG-1 and the pass-gate transistor PG-2 provide access to a storage portion of the SRAM cell 50, which includes a cross-coupled pair of inverters, inverter 52 and inverter 54. Inverter 52 includes a pull-up transistor PU-1 and a pull-down transistor PD-1, and inverter 54 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. In some embodiments, the pull-up transistors PU-1 and PU-2 are configured as p-type FinFET transistors or p-type GAA transistors, and the pull-down transistors PD-1 and PD-2 are configured as n-type FinFET transistors or n-type GAA transistors.

[0038] The gate of the pull-up transistor PU-1 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the first common drain (CD1), and the gate of the pull-down transistor PD-1 is inserted between the source (electrically coupled to the power supply voltage (VSS), which may be an electrical ground) and the first common drain. The gate of the pull-up transistor PU-2 is inserted between the source (electrically coupled to the power supply voltage (VDD)) and the second common drain (CD2), and the gate of the pull-down transistor PD-2 is inserted between the source (electrically coupled to the power supply voltage (VSS)) and the second common drain. In some embodiments, the first common drain (CD1) is a storage node (SN) storing data in a true form, and the second common drain (CD2) is a complementary storage node (SNB) storing data in a complementary form. The gate of the pull-up transistor PU-1 and the gate of the pull-down transistor PD-1 are electrically coupled to the second common drain (CD2), and the gate of the pull-up transistor PU-2 and the gate of the pull-down transistor PD-2 are electrically coupled to the first common drain (CD1). The gate of the transfer gate transistor PG-1 is inserted between the source (electrically coupled to the bit line BL) and the drain, and the drain is electrically coupled to the first common drain (CD1). The gate of the transfer gate transistor PG-2 is inserted between the source (electrically coupled to the complementary bit line BLB) and the drain, and the drain is electrically coupled to the second common drain (CD2). The gates of the transfer gate transistors PG-1 and PG-2 are electrically coupled to the word line WL. In some embodiments, the transfer gate transistors PG-1 and PG-2 provide access to the storage nodes SN and SNB during a read operation and / or a write operation. For example, the transfer gate transistors PG-1 and PG-2 couple the storage nodes SN and SNB to the bit lines BL and BLB, respectively, in response to the voltage applied to the gates of the transfer gate transistors PG-1 and PG-2 by the word line WL.

[0039] Figure 4 1 is a partial schematic cross-sectional view of a semiconductor device 100 according to various aspects of the present disclosure, the semiconductor device 100 including a portion (such as a semiconductor substrate or wafer) that can be fabricated on a semiconductor substrate (or wafer) 60 to form a memory. Figure 2 Memory macro 30) and / or part of the SRAM cell (such as Figure 3 The various layers (levels) of the SRAM cell 50). Figure 4In the embodiment, the various layers include a device layer DL and a multi-layer interconnect MLI disposed on the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain components). In some embodiments, the device layer DL includes a substrate 60, a doped region 62 (e.g., an n-well and / or a p-well) disposed in the substrate 60, an isolation component 64, and a transistor T. In the described embodiment, the transistor T includes a suspended channel layer 70 and a gate structure 68 located between the source / drain 72, wherein the gate structure 68 wraps or surrounds the channel layer 70. Each gate structure 68 has a metal gate stack formed by a gate electrode 74 disposed on a gate dielectric 76 and a gate spacer 78 disposed along the sidewall of the metal gate stack. The multi-layer interconnect MLI electrically couples the various devices and / or components of the device layer DL so that the various devices and / or components can operate according to the design requirements of the memory.

[0040] In the depicted embodiment, the multilayer interconnect MLI includes a contact layer (CO level), a via zero layer (V0 level), a metal zero (M0) level, a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), and a metal three layer (M3 level). The present disclosure contemplates multilayer interconnect MLIs with more or fewer layers and / or levels, for example, the total number of metal layers (levels) of the multilayer interconnect MLI is 2 to 10. Each layer of the multilayer interconnect MLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features of the same level (e.g., M0 level) of the multilayer interconnect MLI are formed simultaneously. In some embodiments, conductive features at the same level of the multilayer interconnect MLI have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially planar to each other. The CO level includes a source / drain contact (MD) disposed in the dielectric layer 66; the V0 level includes a gate via VG, a source / drain contact via VD, and a butt contact disposed in the dielectric layer 66; the M0 level includes an M0 metal line disposed in the dielectric layer 66, wherein the gate via VG connects the gate structure to the M0 metal line, the source / drain contact via VD connects the source / drain to the M0 metal line, and the butt contact connects the gate structure and the source / drain together and to the M0 metal line. 0 metal line; the V1 level includes a V1 via set in the dielectric layer 66, wherein the V1 via connects the M0 metal line to the M1 metal line; the M1 level includes the M1 metal line set in the dielectric layer 66; the V2 level includes a V2 via set in the dielectric layer 66, wherein the V2 via connects the M1 line to the M2 line; the M2 level includes the M2 metal line set in the dielectric layer 66; the V3 level includes a V3 via set in the dielectric layer 66, wherein the V3 via connects the M2 line to the M3 line.

[0041] According to various aspects of the present disclosure, an exemplary manufacturing process for forming a device layer DL and a multilayer interconnect MLI of the semiconductor device 100 may include forming an active region on a substrate, forming an isolation structure (e.g., shallow trench isolation (STI)) between adjacent active regions, forming a dummy gate on the active region, forming a gate spacer on a sidewall of the dummy gate, recessing the active region to form a source / drain recess, forming an internal spacer and a source / drain component in the source / source recess, depositing an interlayer dielectric (ILD) layer on the source / drain component and the dummy gate structure, performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to expose the dummy gate structure, replacing the dummy gate structure with a metal gate structure, and forming contacts, vias, and metal layers in the multilayer interconnect MLI.

[0042] For the sake of clarity, Figure 4It is simplified to better understand the inventive concepts of the present disclosure. Additional components may be added in various layers of the memory, and some of the components described may be replaced, modified or eliminated in other embodiments of the memory. Figure 4 This is merely an example and may not reflect an actual cross-sectional view of the memory macro 30 and / or the SRAM cell 50 discussed in further detail below.

[0043] Figure 5 and Figure 6 Shown as Figure 3 An exemplary layout 200 of an SRAM cell 50 is shown, wherein Figure 5 The DL level, CO level and V0 level of the layout 200 are shown. Figure 6 The V0 level and the M0 level of the layout 200 are shown. The SRAM cell 50 has Figure 5 and Figure 6 . The cell boundary 202 is represented by the dotted line in . The cell boundary 202 is a rectangular box that is longer in the Y direction than in the X direction (e.g., about 3.5 times to about 6 times longer). The first dimension of the cell boundary 202 in the X direction is represented as the cell width W, and the second dimension of the cell boundary 202 in the Y direction is represented as the memory cell height H. In the case where the SRAM cell 50 is repeated in the memory array, the cell width W can be represented and referred to as the memory cell pitch in the memory array along the X direction, and the cell height H can be represented and referred to as the memory cell pitch in the memory array along the Y direction. In the illustrated embodiment, the cell width W is twice the polysilicon pitch. The polysilicon pitch refers to the minimum center-to-center distance between two adjacent gate structures in the X direction.

[0044] The SRAM cell 50 includes an active region 205 (including 205A, 205B, 205C, and 205D) oriented longitudinally along the X direction, and a gate structure 240 (including 240A, 240B, 240C, and 240D) oriented longitudinally along the Y direction perpendicular to the X direction. The active regions 205B and 205C are arranged above an n-type well (or n-well) 204N. The active regions 205A and 205D are arranged above a p-type well 204P located on both sides of the n-well 204N along the Y direction. The gate structure 240 joins the channel regions of the respective active regions 205 to form a transistor. In this regard, gate structure 240A is joined to the channel region of active region 205A to form an n-type transistor as a pass gate transistor PG-1; gate structure 240B is joined to the channel region of active region 205A to form an n-type transistor as a pull-down transistor PD-1, and is joined to the channel region of active region 205B to form a p-type transistor as a pull-up transistor PU-1; gate structure 240C is joined to the channel region of active region 205D to form an n-type transistor as a pull-down transistor PD-2, and is joined to the channel region of active region 205C to form a p-type transistor as a pull-up transistor PU-2; gate structure 240D is joined to the channel region of active region 205D to form an n-type transistor as a pass gate transistor PG-2. In this embodiment, each channel region is in the form of a vertically stacked nanostructure, and each transistor PU-1, PU-2, PD-1, PD-2, PG-1, and PG-2 is a GAA transistor. Alternatively, each channel region 215A-F is in the form of a fin, and each transistor PU- 1 , PU- 2 , PD- 1 , PD- 2 , PG- 1 , and PG- 2 is a FinFET transistor.

[0045] Different active areas in different transistors of the SRAM cell 50 may have different widths (e.g., dimensions measured in the Y direction) to optimize device performance. In more detail, the active area 205A of the pull-down transistor PD-1 and the pass-gate transistor PG-1 has a width W1, the active area 205B of the pull-up transistor PU-1 has a width W2, the active area 205C of the pull-up transistor PU-2 has a width W2, and the active area 205D of the pass-gate transistor PG-2 and the pull-down transistor PD-2 has a width W1. The widths W1 and W2 may also be measured in portions of the active area corresponding to the channel region. In other words, these portions of the active area (from which the widths W1 and W2 are measured) are the channel regions of the transistors (e.g., the vertically stacked nanostructures of the GAA device). In order to optimize SRAM performance, in some embodiments, the width W1 is configured to be greater than the width W2 (W1>W2) to balance the speed between the n-type transistor and the p-type transistor. In some embodiments, the ratio of W1 / W2 may be in the range of about 1.1 to about 3.

[0046] Width W1 being greater than width W2 increases the strength of the n-type transistor in the SRAM cell 50, which results in a higher current handling capability of the SRAM cell 50. This configuration of the active area is suitable for high current applications (such SRAM cells are referred to as high current SRAM cells), such as in a first-level and / or second-level cache memory. In some other embodiments, widths W1 and W2 may be the same (W1=W2). The reduced width W1 allows the SRAM cell 50 to have a smaller cell height H. This active area configuration is suitable for high-density applications (such SRAM cells are referred to as high-density SRAM cells), such as in a second-level and / or third-level cache memory. Figure 1 Taking the memory circuit 14 in the example, in one embodiment, the first-level cache memory 20 includes high-current SRAM cells, and all other cache memories include high-density SRAM cells; in another embodiment, the first-level cache memory 20 and the second-level cache memory 22 include high-current SRAM cells, and the third-level cache memory 24 and the main memory 26 include high-density SRAM cells; in another embodiment, the first-level cache memory 20, the second-level cache memory 22 and the third-level cache memory 24 include high-current SRAM cells, and the main memory 26 includes high-density SRAM cells.

[0047] The SRAM cell 50 also includes conductive components at the CO level, the V0 level, the M0 level, and even higher metal levels (e.g., the M1 level, the M2 level, etc.). The gate contact 260A electrically connects the gate of the pass-gate transistor PG-1 (formed by the gate structure 240A) to the first word line WL landing pad 280A. The first WL landing pad 280A is electrically coupled to the word line WL at a higher metal level. The gate contact 260L electrically connects the gate of the pass-gate transistor PG-2 (formed by the gate structure 240D) to the second word line WL landing pad 280L. The second WL landing pad 280L is electrically coupled to the word line WL at a higher metal level. The source / drain (S / D) contact 260K electrically connects the drain region of the pull-down transistor PD-1 (formed on the active region 205A (which may include an n-type epitaxial source / drain component)) and the drain region of the pull-up transistor PU-1 (formed on the active region 205B (which may include a p-type epitaxial source / drain component) so that the common drain of the pull-down transistor PD-1 / pull-up transistor PU-1 forms a storage node SN. The gate contact 260B electrically connects the gate of the pull-up transistor PI-2 (formed by the gate structure 240C) and the gate of the pull-down transistor PD-2 (also formed by the gate structure 240C) to the storage node SN. The gate contact 260B may be a butt contact that butts with the S / D contact 260K. . The S / D contact 260C electrically connects the drain region of the pull-down transistor PD-2 (formed on the active region 205D (which may include an n-type epitaxial source / drain component)) and the drain region of the pull-up transistor PU-2 (formed on the active region 205C (which may include a p-type epitaxial source / drain component)), so that the common drain of the pull-down transistor PD-2 and the pull-up transistor PU-2 forms a complementary storage node SNB. The gate contact 260D electrically connects the gate of the pull-up transistor PU-1 (formed by the gate structure 240B) and the gate of the pull-down transistor PD-1 (also formed by the gate structure 240B) to the complementary storage node SNB. The gate contact 260D may be a butt contact of the butt S / D contact 260C.

[0048] The S / D contact 260E and the S / D contact via 270E landed thereon electrically connect the source region of the pull-up transistor PU-1 (formed on the active area 205B (which may include a p-type epitaxial source / drain component)) to the VDD line 280E. The VDD line 280E is electrically coupled to the power supply voltage VDD. The S / D contact 260F and the S / D contact via 270F landed thereon electrically connect the source region of the pull-up transistor PU-2 (formed on the active area 205C (which may include a p-type epitaxial source / drain component)) to the VDD line 280E. The S / D contact 260G and the S / D contact via 270G landed thereon electrically connect the source region of the pull-down transistor PD-1 (formed on the active area 205A (which may include an n-type epitaxial source / drain component)) to the first VSS landing pad 280G. The first VSS landing pad 280G is electrically coupled to the electrical ground VSS. The S / D contact 260H and the S / D contact via 270H landing thereon electrically connect the source region of the pull-down transistor PD-2 (formed on the active area 205D (which may include an n-type epitaxial source / drain component)) to the second VSS landing pad 280H. The second VSS landing pad 280H is electrically coupled to the electrical ground VSS. The S / D contact 260G and the S / D contact 260 can be device-level contacts shared by adjacent SRAM cells 50 (for example, four SRAM cells 50 adjacent at the same corner can share one S / D contact 260H). The S / D contact 260I and the S / D contact via 270I landing thereon electrically connect the source region of the pass-gate transistor PG-1 (formed on the active area 205A (which may include an n-type epitaxial source / drain component)) to the bit line BL 280I. S / D contact 260J and S / D contact via 270J landing thereon electrically connect the source region of pass-gate transistor PG-2 formed on active region 205D (which may include n-type epitaxial source / drain features) to complementary bit line (bar bit line) BLB 280J.

[0049] Conductive components in the CO level, M0 level, and higher metal levels (e.g., M1 level, M2 level, etc.) are routed along a first routing direction or a second routing direction different from the first routing direction. For example, the first routing direction is the X direction (and is substantially parallel to the longitudinal direction of the active regions 205A-205D), and the second routing direction is the Y direction (and is substantially parallel to the longitudinal direction of the gate structures 240A-240D). In the depicted embodiment, the source / drain contacts (260C, 260E, 260F, 260G, 260H, 260I, 260J) have a longitudinal (length) direction substantially along the Y direction (i.e., the second routing direction), and the butt contacts (260B, 260D) have a longitudinal (length) direction substantially along the X direction (i.e., the first routing direction). The metal lines of the even-numbered metal layers (i.e., the M0 and M2 levels) are wired along the X direction (i.e., the first wiring direction), and the metal lines of the odd-numbered metal layers (i.e., the M1 and M3 levels) are wired along the Y direction (i.e., the second wiring direction). Figure 6 In the M0 level shown, the bit line 280I, the inverted bit line 280J, the VDD line 280E, the VSS landing pad 280G, the VSS landing pad 280H, the word line landing pad 280A, and the word line landing pad 280L have a longitudinal direction substantially along the X direction. In addition, since the metal lines in the same metal layer (e.g., the M0 level) have the same longitudinal direction, the metal lines can be arranged as parallel metal tracks. The metal track can include one or more metal lines. For example, the metal track can include a single metal line extending through the entire SRAM cell, or the metal track can include one or more local metal lines that do not extend through the entire SRAM cell.

[0050] The metal lines shown are generally rectangular (i.e., each metal line is longer than its width), but the present disclosure contemplates metal lines having different shapes and / or combinations of shapes to optimize and / or improve performance (e.g., reduce resistance) and / or layout footprint (e.g., reduce density). For example, VDD line 280E may optionally be added as Figure 6 280E has a greater width than other portions of VDD line 280E. The step can add between about 1% and about 50% additional width to VDD line 280E. The step is added to the interconnect region (area) of VDD line 280E to increase the cross-sectional area of ​​the interconnect region. Increasing the cross-sectional area of ​​the interconnect region of VDD line 280E allows for increasing the cross-sectional area of ​​S / D contact vias 270E and 270F in the V0 level, which reduces the wiring resistance between the connection of VDD line 280E and the corresponding source / drain contacts (thereby reducing the wiring resistance to the underlying source / drain regions).

[0051] A "landing pad" generally refers to a metal line in a metal layer that provides an intermediate local interconnect for an SRAM cell, such as an intermediate local interconnect between (1) a device level component (e.g., a gate or source / drain) and a bit line, an inverted bit line, a word line, a voltage line, or (2) an intermediate local interconnect between a bit line, a word line, or a voltage line. For example, a VSS landing pad 280G is connected to a source / drain contact 260G of transistor PD-1 and further connected to a VSS line at a higher metal level, a VSS landing pad 280H is connected to a source / drain contact 260H of transistor PD-2 and further connected to a VSS line at a higher metal level, a word line landing pad 280A is connected to a gate of transistor PG-1 and further connected to a word line WL at a higher metal level, and a word line landing pad 280L is connected to a gate of transistor PG2 and further connected to a word line WL at a higher metal level. The landing pad has a longitudinal dimension that is large enough to provide sufficient landing area for the overlying via (thereby minimizing coverage issues and providing greater patterning flexibility). In the depicted embodiment, the longitudinal dimension of the landing pad is smaller than the dimension of the SRAM cell 50, such as a dimension that is smaller than the cell width W in the X direction, and a dimension that is smaller than the cell height H in the Y direction. Compared to the landing pad, the bit line 280I, the inverted bit line 280J, and the VDD line 280E have a longitudinal dimension that is larger than the width W of the SRAM cell 50 cell in the X direction. When passing through the entire SRAM cell 50 along the X direction, the bit line 280I, the inverted bit line 280J, and the VDD line 280E of the M0 level are also referred to as global metal lines, while the other lines are referred to as local metal lines (including the landing pad). In some embodiments, the length of each of the bit line 280I, the inverted bit line 280J, and the VDD line 280E is sufficient to allow multiple SRAM cells in a column (or row) to be electrically connected to the corresponding global metal line.

[0052] The metal lines (global metal lines and local metal lines) in the SRAM cell 50 at the M0 level can have different widths. For example, the VDD line 280E has a width Wa, and the bit line 280I and the inverted bit line 280J each have a width Wb. In some embodiments, the width Wb is greater than the width Wa (Wb>Wa). The maximum width reserved for the bit line 280I and the inverted bit line 280J allows the signal line in the bit line pair to generally benefit from the reduction in resistance, thereby reducing the voltage drop along the signal line. In some embodiments, the ratio of the width Wb to the width Wa (i.e., Wb / Wa) is about 1.1 to about 2. In some embodiments, the width Wa is greater than the width Wb (Wa>Wb). The maximum width reserved for the VDD line 280E allows the VDD line 280E to generally benefit from the reduction in resistance, thereby reducing the voltage drop along the power line. In some embodiments, the ratio of the width Wa to the width Wb (i.e., Wa / Wb) is about 1.1 to about 2.

[0053] Figure 7 Memory macro 30 ( Figure 2 ) of the portion of the layout 300, which includes the first two rows (rows 1-2) of the memory array 32 and a portion of the logic cells in the I / O circuit (or I / O region) 34. For clarity, Figure 7 Simplified to better understand the inventive concept of the present disclosure. For example, the memory array 32 ( Figure 2 ) of the first two columns and rows of SRAM cells (i.e., BC 11 , B.C. 12 , B.C. 21 , B.C. 22 ) in the V0 level active area, gate structure, gate cut isolation components and vias, and Figure 7 Many other parts are omitted.

[0054] The SRAM cells in the memory array 32 include active regions of the first type (e.g., 205A and 205B), and the logic cells in the I / O region 34 include active regions of the second type (e.g., 305). The active regions in the memory array 32 are arranged along the Y direction and are longitudinally oriented along the X direction. As described above, the active regions (e.g., 205A and 205B) may have different widths and / or the same width (e.g., Figure 5 305 are arranged along the Y direction and are longitudinally oriented in the X direction. In the illustrated embodiment, the active regions 305 are uniformly distributed along the Y direction, and each active region has a uniform width. The memory macro also includes a gate structure 340 arranged along the X direction and extending longitudinally in the Y direction. In the illustrated embodiment, the gate structures 340 are uniformly distributed along the X direction, and the distance between two adjacent gate structures 340 is uniform. The uniform distance is expressed as a gate pitch or a polysilicon pitch ("PP"). The SRAM cell width W can also be measured by the number of polysilicon pitches. In the illustrated embodiment, the SRAM cell width W is twice the polysilicon pitch. The width of the memory array 32 along the X direction can also be measured by the number of polysilicon pitches. Since the width W of each SRAM cell is twice the polysilicon pitch, for the case where there are N SRAM cells in a row, the width of the memory array 32 is 2*N polysilicon pitches.

[0055] The gate structures 340 intersect the active regions to form transistors. The transistors formed at the intersections of the active regions and the gate structures 340 within the memory array 32 are used to form SRAM cells. The transistors formed at the intersections of the active regions and the gate structures 340 within the I / O region 34 are used to form logic cells. In the illustrated embodiment, the transistors in the SRAM array 32 form a plurality of SRAM cells, such as SRAM cells BC.11 , B.C. 12 , B.C. 21 , B.C. 22 (collectively referred to as SRAM cells BC). Each SRAM cell BC in the array can be used as follows Figure 5 Layout 200 of the SRAM cell 50 is shown. In some embodiments, two adjacent SRAM cells in the X direction are line symmetrical with respect to the common boundary between them, and two adjacent SRAM cells in the Y direction are also line symmetrical with respect to the common boundary between them. That is, the SRAM cells BC 12 It is SRAM cell BC 11 A replica of the cell, but flipped on the Y axis; SRAM cell BC 22 It is SRAM cell BC 12 A replica of the cell, but flipped on the X axis; SRAM cell BC 21 It is SRAM cell BC 11 A copy of the cell, but flipped on the X axis.

[0056] Some active regions extend across multiple SRAM cells in a row. For example, SRAM cell BC 11 The active regions of transistors PD-1 and PG-1 extend through the SRAM cell BC. 12 As the active area of ​​its transistors PG-1, PD-1, and further through other SRAM cells BC in row 1; SRAM cell BC 11 The active regions of transistors PG-2 and PD-2 extend through the SRAM cell BC. 12 As the active area of ​​its transistors PD-2, PG-2, and further through other SRAM cells BC in row 1; SRAM cell BC 11 The active area of ​​transistor PU-2 in the SRAM cell BC extends to 12 The active area of ​​the transistor PU_2 is used as the active area of ​​the SRAM cell BC. 21 , B.C. 22 The active regions in are arranged similarly. Figure 7 Also shown in FIG. 5 is a through hole at the V0 level in the SRAM cell.

[0057] In the illustrated embodiment, the transistors in the I / O region 34 form a plurality of logic cells. The logic cells may be standard cells, such as inverters (INV), ANDs, ORs, NANDs, NORs, flip-flops (Flip Flip), scanners (SCAN), and the like. The logic cells implement various logic functions for the SRAM cells BC. The logic functions of the logic cells include, for example, write and / or read decoding, word line selection, bit line selection, data drive, and memory self-test. As shown, each logic cell has a logic cell height CH, which is half the height H of the SRAM cell. Therefore, the two logic cells have opposite edges aligned with opposite edges of one SRAM cell, the edges are spaced apart in the Y direction, and each edge extends in the X direction.

[0058] Between the relative boundary lines of the SRAM cells in the memory array 32 and the logic cells in the I / O area 34 is an active area transition area 40, or simply referred to as a transition area 40. In the transition area 40, the active area 205A extending from the edge column of the SRAM cell intersects with the active area 305 extending from the edge column of the logic cell. Since the intersecting pair of active areas 205A, 305 can have different widths, a step is generated where the active areas 205A, 305 intersect. A step refers to the junction where two parts of different widths intersect. For example, in the area 372A represented by the dotted circle, the relatively wide active area 205A intersects with the relatively narrow active area 305, thereby forming a step. The upper edges of the active areas 205A, 305 are aligned, and the lower edges of the active areas 205A, 305 form a step profile. Similarly, in region 372B represented by another dashed circle, relatively narrow active region 205B intersects relatively wide active region 305, creating another step. The lower edges of active regions 205B, 305 are aligned, while the upper edges of active regions 205A, 305 form a stepped profile.

[0059] As shown in the layout 300, the transition region 40 has a span of one polysilicon pitch along the X direction between the opposite boundary lines of the SRAM cell and the logic cell. In the transition region 40, the dielectric component (or isolation component) 374 is oriented longitudinally in the Y direction and provides isolation between the active area in the memory array 32 and the I / O region 34. The dielectric component 374 overlaps the step. In the exemplary layout 300, the dielectric component 374 extends continuously along the boundary line of the SRAM cell and the logic cell in the Y direction. In other words, the dielectric component 374 is higher than the SRAM cell height H.

[0060] The dielectric component 374 can be formed in a continuous polycrystalline diffusion edge (CPODE) process. In the CPODE process, the polysilicon gate is replaced by a dielectric component. For the purpose of this disclosure, a "diffusion edge" can be equivalently referred to as an active edge, where, for example, the active edge abuts an adjacent active area. Before the CPODE process, the active edge can include a pseudo GAA structure having a pseudo gate structure (e.g., a polysilicon gate) and a plurality of vertically stacked nanostructures as a channel layer. In addition, an internal spacer can be disposed between the lateral ends of adjacent nanostructures. In various examples, the source / drain epitaxial component is disposed on either side of the pseudo GAA structure so that the adjacent source / drain epitaxial component contacts the internal spacer and nanostructure of the pseudo GAA structure. The subsequent CPODE etching process removes the pseudo gate structure and the channel layer from the pseudo GAA structure to form a CPODE trench. The dielectric material that fills the CPODE trench for isolation is called a CPODE component. In some embodiments, after the CPODE component is formed, the remaining dummy gate structure is replaced by a metal gate structure in a replacement gate (last gate) process. In other words, in some embodiments, the CPODE component replaces part or all of the originally continuous gate structure and is confined between the relative gate spacers of the replaced portion of the gate structure. The dielectric component 374 is also referred to as a gate cutting component or a CPODE component. Since the CPODE component 374 is formed by replacing the previously formed polysilicon gate structure, the CPODE structure 374 inherits the arrangement of the gate structure 340. That is, the CPODE component 374 can have the same width as the gate structure 340 and the same pitch as the gate structure 340.

[0061] Figure 8 Memory macro 30 ( Figure 2 ) of the portion of the layout 300 including the first two rows (rows 1-2) of the memory array 32 and a portion of the logic cells in the I / O circuit 34. At the M0 level, the I / O region 34 includes a plurality of metal tracks arranged in parallel. Specifically, in the illustrated embodiment of the layout 300, two adjacent logic cells include eleven metal tracks arranged in sequence from the first (M0 track 1) to the eleventh (M0 track 11) along the Y direction. The center line of the metal track is Figure 8 The dotted line in .

[0062] The metal lines in the SRAM cells are aligned with the metal tracks in the I / O region 34, allowing the metal lines in the logic cells to extend into the SRAM cells. Therefore, no edge cells are required to provide metal transitions between the SRAM cells and the logic cells. In the M0 track 1, the VSS line extends to the SRAM cell BC 11and merged with the VSS landing pad. In M0 track 2, the metal line as the signal line in the logic cell is maintained within the boundary of the corresponding logic cell. In M0 track 3, the metal line as the signal line in the logic cell is maintained within the boundary of the corresponding logic cell. In M0 track 4, the metal line as the bit line BL in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the bit line BL of multiple SRAM cells in the same row. In M0 track 5, the metal line as the signal line in the logic cell is maintained within the boundary of the corresponding logic cell. In M0 track 6, the metal line as the VDD line in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the VDD line of multiple SRAM cells in the same row. In M0 track 7, the metal line as the signal line in the logic cell is maintained within the boundary of the corresponding logic cell. In M0 track 8, the metal line as the inverted bit line BLB in the logic cell also extends into the SRAM cell and passes through the SRAM cell, serving as the inverted bit line BLB of multiple SRAM cells in the same row. In M0 track 9, the metal line as the signal line in the logic cell remains in the boundary of the corresponding logic cell. In M0 track 10, the metal line as the signal line in the logic cell remains within the boundary of the corresponding logic cell. In M0 track 11, the metal line as the VSS line in the logic cell can extend through the boundary of the corresponding logic cell but does not contact the word line WL landing pad.

[0063] The boundary of the SRAM cell can be adjacent to the boundary of one or two logic cells. One or two logic cells provide 2*N+1 metal tracks, where N is an integer. The metal line in the center metal track (the N+1th metal track) extends into the SRAM cell as a common VDD line for the SRAM cell and one or two logic cells. The two metal lines in the two metal tracks equidistant from the center metal track extend into the SRAM cell, respectively, as the bit line BL and the inverted bit line BLB of the SRAM cell and one or two logic cells. The two metal lines in the first and (2*N+1)th metal tracks extend across the boundary of one or two logic cells and are connected to one of the VSS landing pads in the SRAM cell.

[0064] In the illustrated embodiment, metal lines in metal tracks 4 and 8 extend from the logic cell and pass through the SRAM cells in the same row to serve as the bit line BL and the inverted bit line BLB, respectively. Alternatively, depending on the layout, metal lines in metal tracks 2 and 10, or metal tracks 3 and 9, or metal tracks 5 and 7 extend from the logic cell and pass through the SRAM cells to serve as the bit line BL and the inverted bit line BLB, respectively. In this context, if not separately indicated, the bit line BL and the complementary bit line BLB may also be collectively referred to as the bit line.

[0065] In semiconductor memory design, a uniform bitline width is often used for memory arrays of different sizes. However, the preference for bitline width may vary for small and large memory arrays. For smaller arrays, such as L1 (first level) cache memory, narrower bitlines help reduce parasitic capacitance, thereby achieving faster access times and lower power consumption. In contrast, for large memory arrays, such as L2 (second level) cache memory, wider bitlines help achieve reduced resistance, which helps maintain signal integrity over longer distances.

[0066] Fig. 9 Layout 400 is shown, which shows memory circuit 14 ( Figure 1 ), which has a first cache memory including a first memory array 32A and a second cache memory including a second memory array 32B. The first memory array 32A includes memory cells arranged in M1 rows and N1 columns, and the second memory array 32B includes memory cells arranged in M2 rows and N2 columns. For simplicity, Fig. 9 Only the first two rows (rows 1-2) of the first memory array 32A and the second memory array 32B are shown. Also for simplicity, Fig. 9 Only the first two columns and rows of SRAM cells (i.e., BC 11 , B.C. 12 , B.C. 21 , B.C. 22 ), the active areas of the V0 level, gate structures, vias, and the bit lines (BL and BLB) of the first two rows of the corresponding memory array, while many other components are omitted.

[0067] The first memory array 32A is a smaller array and the second memory array 32B is a larger array (M1<M2, N1<N2). In other words, in the first memory array 32A, fewer memory cells (N1) in the same row share a single bit line (BL or BLB), while in the second memory array 32B, more memory cells (N2) in the same row share a single bit line (BL or BLB). The smaller first memory array 32A can reside in a first cache memory that is generally smaller and faster, such as a first-level cache memory or a second-level cache memory, while the larger second memory array 32B can reside in a second cache memory that is generally larger and slower, such as a second-level cache memory or a third-level cache memory. In one example, the first cache memory is a first-level cache memory, using a first memory array 32A, each bit line feeds 32 or 64 memory cells in the same row (N1=32 or 64), and the second cache memory is a second-level cache memory, using a second memory array 32B, each bit line feeds 128 or more memory cells in the same row (N2=128 or N2>128).

[0068] In the illustrated embodiment, the width of a single SRAM cell in the X direction is twice the polysilicon pitch (PP). By having a plurality of N1 SRAM cells in a row, the first memory array 32A has a width W of 2*N1 polysilicon pitches. 32A By having N2 SRAM cells in a row, the second memory array 32B has a width W3 of 2*N2 polysilicon pitches. 2B . The height of a single SRAM cell along the Y direction depends on whether it is a high current design or a high density design. As described above, making the width W1 of the active area 205A greater than the width W2 of the active area 205B (W1>W2) allows each SRAM cell to handle more current; in contrast, making the width W1 of the active area 205A equal to the width W2 of the active area 205B (W1=W2) allows each SRAM cell to be more compact, thereby saving area. In the illustrated embodiment, the first memory array 32A and the second memory array 32B have the same high current SRAM cells, where W1>W2. Alternatively, the first memory array 32A and the second memory array 32B can have the same high density SRAM cells (where W1=W2), or the first memory array 32A can have high current SRAM cells (where W1>W2) and the second memory array 32B can have high density SRAM cells (where W1=W2).

[0069] The bit lines in the first memory array 32A have a uniform width Wb1, and the bit lines in the second memory array 32B have a uniform width Wb2 that is greater than Wb1 (Wb2>Wb1). In smaller memory arrays with fewer SRAM cells in a row, the bit line length is shorter, so the voltage drop along the bit line is less important, while the bit line width affects parasitic capacitance, which may hinder circuit speed. The smaller width Wb1 reduces parasitic capacitance, which increases circuit speed and reduces power consumption without compromising on voltage margin along the bit line. In contrast, in larger memory arrays with more SRAM cells in a row, the bit line length is longer, so the voltage drop along the bit line is a greater problem. The larger width Wb2 reduces resistance, which increases the voltage margin along the bit line and improves signal integrity. Although the larger width Wb2 introduces more parasitic capacitance, the slight impact on circuit speed is not too worrying due to the use of larger memory arrays in relatively slow cache memories.

[0070] In various embodiments, the ratio between the larger width Wb2 in the high current SRAM cell (i.e., the SRAM cell with W1>W2) and the width W1 of the active area 205A is between about 1.5 and about 5 (1.5<Wb2 / W1≤5), and the ratio between the smaller width Wb1 in the high current DRAM cell and the width W1 of the active area 205A is between about 1 and about 1.5 (1<Wb1 / W1≤1.5). These ranges are not trivial or arbitrary. If Wb2 / W1 is less than about 1.5, there may not be enough voltage margin for long bit lines; if Wb2 / W1 is greater than about 5, the bit lines may be too wide and intersect with adjacent power / signal lines; if Wb1 / W1 is less than about 1, the bit lines may become too resistive, which in turn reduces circuit speed; and if Wb1 / W1 is greater than about 1.5, parasitic capacitance may be too large and circuit speed may be impaired. Further in some embodiments, the semiconductor memory design may optionally provide a third bit line width Wb0 that is even smaller than Wb1 (Wb0 < Wb1 < Wb2). The bit line width Wb0 may be used for a memory array of a micro cache memory ( Fig. 9(not shown in the figure). The micro cache memory can be a level 1 cache memory in the memory circuit 14 with the smallest memory array and the fastest speed. In the micro cache memory, each bit line may feed only 16 or 32 SRAM cells in the same row. If a third bit line width Wb0 is provided in the semiconductor memory design, then in some embodiments, in the high-current SRAM cells, the ratio between the minimum width Wb0 and the width W1 of the active region 205A is between about 0.3 and about 1 (0.3 < Wb0 / W1 ≤ 1). Similarly, these ranges are not trivial or arbitrary. If Wb0 / W1 is less than about 0.3, the bit lines may become too resistive, which in turn reduces the circuit speed of the micro cache memory; if Wb0 / W1 is greater than about 1, the parasitic capacitance may be too large and impede the circuit speed of the micro cache memory. Similarly, in various embodiments, the ratio between the larger width Wb2 and the width W1 of the active region 205A in the high-density SRAM cells (i.e., SRAM cells where W1 = W2) is between about 3 and about 15 (3 < Wb2 / W1 ≤ 15), the ratio between the smaller width Wb1 and the width W1 of the active region 205A in the high-density SRAM cells is between about 2 and about 3 (2 < Wb1 / W1 ≤ 3), and the ratio between the minimum width Wb0 (if any) and the width W1 of the active region 205A in the high-density SRAM cells is between about 0.5 and about 2 (0.5 < Wb0 / W1 ≤ 2).

[0071] Fig.10 is shown as possibly existing in the memory macro 30( Figure 2) and corresponding various SRAM arrays in the table 500 of specific examples of various bit line widths. Table 500 is only an example and is not intended to be limiting. The exemplary memory macro 30 includes a micro cache memory. The micro cache memory adopts an SRAM array, and each bit line is coupled to 8 or 16 memory cells in the same row. The array width of the SRAM array is 16 or 32 polysilicon pitches. Each bit line has a bit line width Wb0 that is the smallest among the available bit line widths. The memory cells in the SRAM array are based on a high current design. The exemplary memory macro 30 includes a first type of primary cache memory. The first type of primary cache memory adopts an SRAM array, and each bit line is connected to 32 memory cells in the same row. The array width of the SRAM array is 64 polysilicon pitches. Each bit line has a bit line width Wb1 that is in the middle of the available bit line widths. The memory cells in the SRAM array are based on a high current design. The exemplary memory macro 30 includes a second type of primary cache memory. The second type of primary cache memory adopts an SRAM array, and each bit line is connected to 64 memory cells in the same row. The array width of the SRAM array is 128 polysilicon pitches. Each bit line has a bit line width Wb1 that is in the middle of the available bit line widths. The memory cells in the SRAM array are based on a high current design. The exemplary memory macro 30 includes a first type of secondary high-speed cache memory. The first type of secondary high-speed cache memory adopts an SRAM array, and each bit line is connected to 128 memory cells in the same row. The array width of the SRAM array is 256 polysilicon pitches. Each bit line has a bit line width Wb2 that is the largest among the available bit line widths. The memory cells in the SRAM array are based on a high current design. The exemplary memory macro 30 includes a second type of secondary high-speed cache memory. The second type of secondary high-speed cache memory adopts an SRAM array, and each bit line is connected to 256 memory cells in the same row. The array width of the SRAM array is 512 polysilicon pitches. Each bit line has a bit line width Wb2 that is the largest among the available bit line widths. The memory cells in the SRAM array are based on a high current design. The exemplary memory macro 30 includes a three-level high-speed cache memory. The three-level cache memory adopts an SRAM array, and each bit line is connected to 512 memory cells in the same row. The array width of the SRAM array is 1024 polysilicon pitches. Each bit line has a bit line width Wb2 that is the largest among the available bit line widths. The memory cells in the SRAM array are based on a high-density design. The exemplary memory macro 30 includes a main memory. The main memory adopts an SRAM array, and each bit line is coupled to more than 512 memory cells in the same row. The array width of the SRAM array is greater than 1024 polysilicon pitches. Each bit line has a bit line width Wb2 that is the largest among the available bit line widths. The memory cells in the SRAM array are based on a high-density design.

[0072] Fig.11 The Fig. 9 Partial cross-sectional views of the AA, BB, A'-A' and B'-B' sections in FIG. Fig. 9 As shown, the cross section AA is along the memory cell BC in the first memory array 32A. 11 and B.C. 12 Between and memory cell BC 21 and B.C. 22 The cell boundary between the two passes through the source / drain region; the cross section BB passes through the memory cell BC in the first memory array 32A 11 and B.C. 21 The gate structure 340; the cross section A'-A' is along the memory cell BC in the second memory array 32B 11 and B.C. 12 Between and memory cell BC 21 and B.C. 22 The cell boundary between the two passes through the source / drain region; the cross section B'-B' passes through the memory cell BC in the second memory array 32B 11 and B.C. 21 The gate structure 340. Fig.11 In the figure, each cross section is symmetric with respect to the mirror symmetry axis MA.

[0073] Now, reference is made to cross sections AA and BB located in the first memory array 32A. The active region 205A includes a plurality of nanostructures as channel layers vertically stacked above a fin-shaped substrate. The channel layer provides a channel region for an n-type pass gate transistor PG-1. The active region 205A has a width W1 measured on the topmost channel layer. In the source / drain region, the source / drain epitaxial component SD 205A Epitaxial growth is performed on the fin-shaped substrate of the active area 205A. The source / drain epitaxial component SD 205AElectrically coupled to the bit line BL through the S / D contact 260I and the S / D contact via 270I. The bit line BL has a first width Wb1, which is less than the second width Wb2 in the second memory array 32B. The active area 205B includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-1. Measured on the topmost channel layer, the active area 205B has a width W2. In a high current SRAM cell, the width W2 is less than the width W1 (W2<W1); in a high density SRAM cell, the width W2 can be equal to the width W1 (W1=W2). The active area 205C includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-2. Measured on the topmost channel layer, the active area 205C has a width W2. In the source / drain region, the source / drain epitaxial component SD 205C Epitaxial growth is performed on the fin-shaped substrate of the active region 205C. The source / drain epitaxial component SD 205C Electrically coupled to the VDD line through the S / D contact 260F and the S / D contact via 270F. Section AA can be cut along a stepped portion of the VDD line, the width Wa' of the stepped portion being greater than the width Wa of the VDD line in section BB. As shown, the width Wb1 of the bit line BL can be wider than both the width Wa and Wa'; alternatively, the width Wb1 can be greater than the width Wa of the stepped portion but less than the width Wa'. The selection of the width may depend on specific circuit performance requirements. The active area 205D includes a plurality of nanostructures as a channel layer stacked vertically above the fin-shaped substrate. The channel layer provides a channel region for the n-type pull-down transistor PD-2. Measured on the topmost channel layer, the active area 205D has a width W1. In the source / drain region, the source / drain epitaxial component SD 205D Epitaxial growth is performed on the fin-shaped substrate of the active region 205D. The source / drain epitaxial component SD 205D The S / D contact 260H and S / D contact via 270H are electrically coupled to the VSS landing pad. The mirror configuration of the SRAM cell allows a larger S / D contact 260H to land on the source / drain epitaxial feature SD. 205D Sections AA and BB also depict a bit bar line BLB disposed between the VDD line and the VSS landing pad. The bit bar line BLB has the same width Wb1 as the bit line BL.

[0074] Now refer to the cross sections A'-A' and B'-B' in the second memory array 32B. The active region 205A includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the n-type pass gate transistor PG-1. The active region 205A has a width W1 measured on the topmost channel layer. In the source / drain region, the source / drain epitaxial component SD 205A Epitaxial growth is performed on the fin-shaped substrate of the active area 205A. The source / drain epitaxial component SD 205A Electrically coupled to the bit line BL through the S / D contact 260I and the S / D contact via 270I. The bit line BL has a second width Wb2, which is greater than the first width Wb1 in the first memory array 32A. The active area 205B includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-1. Measured on the topmost channel layer, the active area 205B has a width W2. In a high-current SRAM cell, the width W2 is less than the width W1 (W2<W1); in a high-density SRAM cell, the width W2 can be equal to the width W1 (W1=W2). The active area 205C includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the p-type pull-up transistor PU-2. Measured on the topmost channel layer, the active area 205C has a width W2. In the source / drain region, the source / drain epitaxial component SD 205C Epitaxial growth is performed on the fin-shaped substrate of the active region 205C. The source / drain epitaxial component SD 205C Electrically coupled to the VDD line through the S / D contact 260F and the S / D contact via 270F. Section A'-A' can be cut along a stepped portion of the VDD line, the width Wa' of the stepped portion being greater than the width Wa of the VDD line in section B'-B'. As shown, the width Wb2 of the bit line BL can be wider than both the width Wa and Wa'; alternatively, the width Wb2 can be greater than the width Wa of the stepped portion but less than the width Wa'. The selection of the width may depend on specific circuit performance requirements. The active area 205D includes a plurality of nanostructures as a channel layer vertically stacked above the fin-shaped substrate. The channel layer provides a channel region for the n-type pull-down transistor PD-2. Measured on the topmost channel layer, the active area 205D has a width W1. In the source / drain region, the source / drain epitaxial component SD 205D Epitaxial growth is performed on the fin-shaped substrate of the active region 205D. The source / drain epitaxial component SD 205D The S / D contact 260H and S / D contact via 270H are electrically coupled to the VSS landing pad. The mirrored placement of the SRAM cell allows a larger S / D contact 260H to land on the source / drain epitaxial feature SD. 205DSections A'-A' and B'-B' also depict a bit bar line BLB disposed between the VDD line and the VSS landing pad. The bit bar line BLB has the same width Wb2 as the bit line BL.

[0075] Fig.12 6 is a simplified block diagram of an embodiment of an IC manufacturing system 600 and an IC manufacturing process associated therewith. The IC manufacturing system 600 includes multiple entities, such as a design company 620, a mask company 630, and an IC manufacturing plant 650 (i.e., a manufacturer), which interact in the design, development, and manufacturing cycles and / or services associated with manufacturing IC devices 660. The various entities are connected via a communication network, which can be a single network or a variety of different networks, such as an intranet and the Internet, and can include wired and / or wireless communication channels. Each entity can interact with other entities, and can provide services to other entities and / or receive services from other entities. One or more of the design company 620, the mask company 630, and the IC manufacturing plant 650 can be owned by different companies or a single company, and can even coexist in a public facility and use public resources.

[0076] The design office (or design team) 620 generates an IC design layout (or IC layout) 622. The IC design layout 622 includes various geometric patterns (e.g., polygons representing metal lines) designed for the IC device 660. The geometric patterns correspond to IC components in one or more semiconductor layers that constitute the IC device 660. Exemplary IC components include active regions, gate electrodes, source and drain components, isolation components, metal lines, contact plugs, vias, etc. The design office 620 implements appropriate design procedures to form the IC design layout 622. The design process may include logic design, physical design, placement and routing, and / or various design check operations. The IC design layout 622 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout 622 can be represented in a GDSII file format or a DFII file format. In the present embodiment, the IC device 660 may include a memory circuit, such as Figure 1 14 in the memory circuit 14. However, the IC design layout 622 represented in the GDSII file format or the DFII file format may have a geometric pattern that represents the bit line as a uniform bit line width. That is, only checking the IC design layout 622 will not find options for different memory array sizes to have multiple bit line widths.

[0077] The mask room 630 uses the IC design layout 622 to manufacture a set of masks for manufacturing various layers of the IC device 660 according to the IC design layout 622. The mask room 630 performs data preparation 632 and mask manufacturing 644. The data preparation 632 converts the IC design layout 622 into a form that can be physically written by a mask writer. The mask manufacturing 644 manufactures the set of masks (photomasks or reticles).

[0078] In the present embodiment, data preparation 632 includes layout adjustment 634, which is configured to adjust the metal line width corresponding to the bit line. Layout adjustment 634 adjusts the bit line width based on a threshold set for the memory array size. For example, the threshold can be set to 128. Therefore, the bit line feeding 128 or more memory cells in the same row will have a width adjusted from the uniform bit line width to a larger width Wb2. At the same time, the width of the bit line feeding less than 128 memory cells (e.g., 64) in the same row will be adjusted from the uniform bit line width to a smaller width Wb1. This adjustment can also be controlled by the design company (or customer) ID associated with the IC design layout 622. For example, a design company may not be given the option of having more than one bit line width, so only a uniform bit line width will be used in the final design, so that the operation of layout adjustment 634 can be skipped; another design company may be given the option of having more than one bit line width, and layout adjustment 634 will adjust the metal line width of the final design. Data preparation 632 may also include other manufacturing processes such as optical proximity correction (OPC), off-axis illumination, sub-resolution assist features, other suitable techniques, or combinations thereof.

[0079] After data preparation 632 prepares data for the mask layer, mask manufacturing 644 manufactures a set of masks, including masks for metal lines for bit lines. For example, based on the data file derived from the IC design layout 622, a pattern is formed on the mask using an electron beam (e-beam) or a plurality of electron beam mechanisms. The mask can be formed using various techniques, such as a binary mask, a phase shift mask, and an EUV mask. For example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated on the substrate. The opaque material is patterned according to the mask data, thereby forming an opaque area and a transparent area on the binary mask. A radiation beam, such as an ultraviolet (UV) beam, is blocked by the opaque area and transmitted through the transparent area, thereby transferring the image of the mask to a sensitive material layer (e.g., photoresist) coated on the wafer 652. As another example, an EUV mask includes a low thermal expansion coefficient substrate, a reflective multilayer (ML) on the substrate, and an absorption layer on the ML. The absorption layer is patterned according to the mask data. The EUV beam is absorbed by the patterned absorber layer or reflected by the ML, thereby transferring the image of the mask to a layer of sensitive material (e.g., photoresist) coated on the wafer 652. In some embodiments, the manufacturing plant 650 may also use some kind of maskless lithography, such as electron beam lithography. For example, one of the masks may be based on electron beam lithography. In this case, data preparation 632 may directly write data files for maskless lithography preparation, and mask manufacturing 644 does not make photomasks for those specific subsets to be produced by maskless lithography.

[0080] An IC fabrication plant (FAB) 650, such as a semiconductor foundry, manufactures an IC device 660 using a mask by, for example, a photolithography process. The fabrication plant 650 may include a front-end-of-line (FEOL) fabrication facility and a back-end-of-line (BEOL) fabrication facility. In particular, the fabrication plant 650 implements a photolithography process to define metal lines on a semiconductor wafer 652. The metal lines may include a smaller bit line width for a memory array that is less than a threshold and a larger bit line width for another memory array that is equal to or greater than the threshold. There may be a single threshold (e.g., a threshold 128 for distinguishing between a primary cache memory and a secondary cache memory) that defines two different bit line widths (e.g., Wb1 and Wb2). Alternatively, there may be two thresholds (e.g., a first threshold 32 and a second threshold 128 for distinguishing between a micro cache memory, a primary cache memory, and a secondary cache memory) that define three different bit line widths (e.g., Wb0, Wb1, and Wb2).

[0081] Fig.13 634 ( Fig.12) is implemented. Method 700 is an example and is not intended to limit the present disclosure beyond the scope explicitly cited in the claims. Additional operations may be provided before, during, and after method 700, and some of the operations described may be replaced, eliminated, or relocated for additional embodiments of the method. At operation 702, an IC layout including metal lines for a memory array is provided. Among the metal lines, there are metal lines representing bit lines. These bit lines have a uniform width. At operation 704, by verifying that the design company ID associated with the IC layout represents a client with multiple bit line width options, each bit line width is adjusted according to the number of memory cells to which the bit line is electrically coupled. If the number of memory cells is equal to or exceeds a threshold value (e.g., 128), the bit line width is adjusted from a uniform bit line width to a larger bit line width (e.g., Wb2). If the number of memory cells is less than a threshold value (e.g., 128), the bit line width is adjusted from a uniform bit line width to a smaller bit line width (e.g., Wb1). At operation 706, the adjusted layout is released to mask manufacturing 644 ( Fig.12 ) to prepare a mask.

[0082] In one example aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes a first memory array in a first cache memory, the first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns, M1 and N1 are each integers; a first bit line coupled to N1 first memory cells in one of the M1 rows, the first bit line having a first width; a second memory array in a second cache memory, the second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns, M2 and N2 are each integers; a second bit line coupled to N2 second memory cells in one of the M2 rows, the second bit line having a second width, wherein N1 is less than N2 and the first width is less than the second width. In some embodiments, M1 is less than M2. In some embodiments, the storage capacity of the first cache memory is less than that of the second cache memory, and the speed of the first cache memory is faster than that of the second cache memory. In some embodiments, the first cache memory is a first-level cache memory, and the second cache memory is a second-level cache memory or a third-level cache memory. In some embodiments, the first cache memory and the second cache memory are at the same cache memory level, and the storage capacity of the first cache memory is less than that of the second cache memory. In some embodiments, N1 is less than 128 and N2 is not less than 128. In some embodiments, the first memory cells each have a first cell width and a first cell height, and the second memory cells each have a second cell width and a second cell height, and the first cell height is greater than the second cell height. In some embodiments, the first cell width is equal to the second cell width. In some embodiments, the first memory array includes a first active area for an n-type transistor in the first memory cell, and a ratio of the first width to the width of the first active area is in a range of about 1 to about 1.5. In some embodiments, the second memory array includes a second active area for an n-type transistor in the second memory cell, and a ratio of the second width to the width of the second active area is in a range of about 1.5 to about 5.

[0083] Another aspect of the present invention provides a semiconductor structure. The semiconductor structure includes: a first memory array disposed in a first region of the semiconductor structure, the first memory array having a plurality of first memory cells, the first memory array including a first bit line electrically coupled to a first number of first memory cells; and a second memory array disposed in a second region of the semiconductor structure, the second memory array having a plurality of second memory cells, the second memory array including a second bit line electrically coupled to a second number of second memory cells. The first number is less than the second number, and the width of the first bit line is less than the thickness of the second bit line. In some embodiments, the first memory cell and the second memory cell are static random access memory (SRAM) cells. In some embodiments, the first region is a first-level cache memory, and the second region is a second-level cache memory. In some embodiments, the first number is 32 or 64, and the second number is 128, 256, or 512. In some embodiments, the first memory cell and the second memory cell each have an active region for an n-type transistor, a ratio of a width of the first bit line to a width of the active region is in a range of about 1 to about 1.5, and a ratio of a width of the second bit line to a width of the active region is in a range of about 1.5 to about 5. In some embodiments, the first memory cells each have a first active region for an n-type transistor, the second memory cells each have a second active region for an n-type transistor, and a width of the first active region is greater than a width of the second active region. In some embodiments, the semiconductor structure further comprises: a first input / output (I / O) region coupled to the first memory array, wherein the first bit line extends continuously into the first I / O region; and a second I / O region coupled to the second memory array, wherein the second bit line extends continuously into the second I / O region.

[0084] Another aspect of the present disclosure provides a method for forming a memory circuit. The method includes: forming a first memory array in a first cache memory located in the memory circuit, the first memory array including a plurality of first memory cells; forming a second memory array in a second cache memory located in the memory circuit, the second memory array including a plurality of second memory cells; forming a first bit line suspended above the first memory array, the first bit line coupled to at least a portion of the first memory cells; and forming a second bit line suspended above the second memory array, the second bit line coupled to at least a portion of the second memory cells. The width of the first bit line is different from the width of the second bit line. In some embodiments, the first memory array is smaller than the second memory array, and the width of the first bit line is smaller than the width of the second bit line. In some embodiments, the storage capacity of the first cache memory is smaller than the second cache memory, and the speed of the first cache memory is faster than that of the second cache memory.

[0085] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: a first memory array in a first cache memory, the first memory array comprising a plurality of first memory cells arranged in M1 rows and N1 columns, M1 and N1 each being an integer; a first bit line coupled to N1 first memory cells in one of the M1 rows, the first bit line having a first width; a second memory array in a second cache memory, the second memory array comprising a plurality of second memory cells arranged in M2 rows and N2 columns, M2 and N2 each being an integer; as well as A second bit line coupled to N2 second memory cells in one of the M2 rows, the second bit line having a second width, Wherein, N1 is smaller than N2 and the first width is smaller than the second width.

2. The semiconductor structure according to claim 1, wherein: M1 is smaller than M2.

3. The semiconductor structure according to claim 1, wherein: The storage capacity of the first cache memory is smaller than that of the second cache memory, and the speed of the first cache memory is faster than that of the second cache memory.

4. The semiconductor structure according to claim 1, wherein: The first cache memory and the second cache memory are at the same cache memory level, and a storage capacity of the first cache memory is smaller than that of the second cache memory.

5. The semiconductor structure according to claim 1, wherein: The first memory cells each have a first cell width and a first cell height, and the second memory cells each have a second cell width and a second cell height, the first cell height being greater than the second cell height.

6. The semiconductor structure according to claim 1, wherein: The first memory array includes a first active area for an n-type transistor in the first memory cell, and a ratio of the first width to a width of the first active area is in a range from about 1 to about 1.

5.

7. The semiconductor structure according to claim 1, wherein: The second memory array includes a second active area for an n-type transistor in the second memory cell, and a ratio of the second width to a width of the second active area is in a range of about 1.5 to about 5.

8. A semiconductor structure comprising: a first memory array disposed in a first region of the semiconductor structure, the first memory array having a plurality of first memory cells, the first memory array including a first bit line electrically coupled to a first number of the first memory cells; as well as a second memory array disposed in a second region of the semiconductor structure, the second memory array having a plurality of second memory cells, the second memory array including second bit lines electrically coupled to a second number of the second memory cells, The first number is smaller than the second number, and the width of the first bit line is smaller than the width of the second bit line.

9. The semiconductor structure according to claim 8, further comprising: a first input / output region coupled to the first memory array, wherein the first bit line extends continuously into the first input / output region; and A second input / output region is coupled to the second memory array, wherein the second bit line continuously extends into the second input / output region.

10. A method of forming a memory circuit, comprising: forming a first memory array in a first cache memory located in the memory circuit, the first memory array comprising a plurality of first memory cells; forming a second memory array in a second cache memory located in the memory circuit, the second memory array comprising a plurality of second memory cells; forming a first bit line suspended above the first memory array, the first bit line coupled to at least a portion of the first memory cells; as well as forming a second bit line suspended above the second memory array, the second bit line coupled to at least a portion of the second memory cells, The width of the first bit line is different from the width of the second bit line.

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