A filterable transformer area arcless circuit breaker and control method

Abstract

The application discloses a substation arcless circuit breaker with filtering capability and a control method, and comprises a microprocessor and a voltage sensor, a current sensor, a mechanical circuit breaker, a filtering module, a wireless communication module and a first IGBT driving circuit. The microprocessor receives sensing signals of the voltage sensor and the current sensor and control information of the wireless communication module, calculates a substation operation state according to the sensing signals of the voltage sensor and the current sensor and the control information of the wireless communication module, and controls the mechanical circuit breaker, the first IGBT driving circuit and the filtering module according to a calculation result, thereby solving the problem that a traditional circuit breaker cannot meet the increasing demand for new energy such as photovoltaic power and charging piles in a substation.

Description

Technical Field

[0001] This invention belongs to the field of circuit breaker technology, specifically relating to a transformer substation arc-free circuit breaker with filtering capability and its control method. Background Technology

[0002] Current inventions and utility models have proposed arc-free AC circuit breaker designs, such as an intelligent arc-free circuit breaker (patent number ZL200520096776.4), a three-phase arc-free circuit breaker (application number 201020652885.0), a high-breaking capacity arc-free circuit breaker (application number CN201710544678.X), and an arc-suppression module for an arc-free miniature circuit breaker (application number 202221641724.0). However, all of these have certain shortcomings. Due to the increasing use of new energy sources, the number of charging piles and rooftop photovoltaic systems in power distribution areas is increasing, leading to a decline in power quality. Traditional circuit breaker interruption decisions can no longer meet the growing needs of new energy sources in these areas. The integration of new energy sources also presents new demands for arc-free AC circuit breakers. This invention designs an arc-free circuit breaker based on the increasing demand for new energy integration in existing power distribution areas. Summary of the Invention

[0003] To address the aforementioned shortcomings in the existing technology, this invention provides an arc-free circuit breaker with filtering capabilities for distribution areas and a control method that solves the problem that traditional circuit breakers can no longer meet the growing demand for new energy sources such as photovoltaics and charging piles in distribution areas.

[0004] To achieve the above-mentioned objectives, the technical solution adopted by the present invention is as follows: a transformer area arc-free circuit breaker with filtering capability, comprising a voltage sensor, a current sensor, a mechanical circuit breaker, a filtering module, a wireless communication module, a microprocessor, a first IGBT driving circuit, and a first IGBT.

[0005] The voltage sensor, current sensor, mechanical circuit breaker and filter module are connected in sequence. The microprocessor is connected to the voltage sensor, current sensor, mechanical circuit breaker and filter module, wireless communication module and first IGBT drive circuit respectively. The first IGBT drive circuit is also connected to the first IGBT. One end of the first IGBT is connected to the current sensor and mechanical circuit breaker respectively. The other end of the first IGBT is connected to the mechanical circuit breaker and filter module respectively.

[0006] The voltage sensor is used to collect the three-phase voltage values ​​output by the transformer in the distribution area, the current sensor is used to collect the three-phase current values ​​output by the transformer in the distribution area, the wireless communication module is used to receive the control information of the circuit breaker in the distribution area, the microprocessor is used to calculate the operating status of the distribution area based on the three-phase voltage and current values ​​output by the transformer in the distribution area, the clock signal and the control information, and to control the mechanical circuit breaker, the first IGBT drive circuit and the filter module based on the calculation results, and the thyristor is used to control the current.

[0007] Furthermore: the filter module includes a grid-side inductor, a grid-side resistor, a neutral line resistor, a neutral line capacitor, a filter controller, a filter resistor, a filter inductor, a load-side resistor, and a load-side inductor;

[0008] One end of the grid-side inductor is connected to the mechanical circuit breaker, and the other end of the grid-side inductor is connected to one end of the grid-side resistor. The other end of the grid-side resistor is connected to one end of the neutral line resistor, one end of the filter inductor, and one end of the load-side resistor, respectively. The other end of the neutral line resistor is connected to the neutral line through a neutral line capacitor. The other end of the filter inductor is connected to the filter controller through a filter resistor. The other end of the load-side resistor is connected to the load of the distribution area through a load-side inductor.

[0009] Furthermore: The filter controller includes a voltage conversion circuit, an upper voltage control capacitor, a lower voltage control capacitor, an output capacitor, a current control inductor, an output inductor, an input positive terminal switch, an output positive terminal switch, an output negative terminal switch, an input negative terminal switch, a switching switch, a positive terminal bridging switch, a positive left interconnection switch, a positive right interconnection switch, a negative left interconnection switch, a negative right interconnection switch, a negative terminal bridging switch, a negative terminal bridging output switch, and a positive terminal bridging output switch;

[0010] The voltage conversion circuit's connection terminals A, B, and C are connected to power supply phases A, B, and C respectively. The voltage conversion circuit's connection terminal N is connected to the power supply neutral line, the emitter of the output negative switch, and the input negative switch. The voltage conversion circuit's connection terminal D is connected to the collector of the input positive switch and the collector of the output positive switch. The emitter of the input positive switch is connected to the emitter of the positive bridge switch, the collector of the switching switch, and the collector of the positive left interconnect switch. The emitter of the output positive switch is connected to the collector of the output negative switch, one end of the output capacitor, and the output negative terminal. The collector of the positive bridge switch is connected to the collector of the positive bridge output switch and one end of the upper voltage control capacitor. The emitter of the positive left interconnect switch is connected to the emitter of the positive right interconnect switch. The collector of the positive right interconnect switch is connected to the other end of the upper voltage control capacitor and one end of the current control inductor.

[0011] The collector of the input negative terminal switch is connected to the collector of the negative terminal bridge switch, the emitter of the switching switch, and the collector of the negative left interconnect switch. The emitter of the negative left interconnect switch is connected to the emitter of the negative right interconnect switch. The collector of the negative right interconnect switch is connected to one end of the lower voltage control capacitor and the other end of the current control inductor. The emitter of the negative terminal bridge switch is connected to the other end of the lower voltage control capacitor and the emitter of the negative terminal bridge output switch. The collector of the negative terminal bridge output switch is connected to the emitter of the positive terminal bridge output switch and one end of the output inductor. The other end of the output inductor is connected to the other end of the output capacitor and the output positive terminal.

[0012] Furthermore: the voltage conversion circuit includes a first power diode, a second power diode, a third power diode, connection terminal A, connection terminal B, connection terminal C, connection terminal D, and connection terminal N;

[0013] The negative terminals of the first, second, and third power diodes are all connected to terminal D, and the positive terminals of the first, second, and third power diodes are connected to terminals A, B, and C respectively.

[0014] Furthermore: the input positive terminal switch, output positive terminal switch, output negative terminal switch, input negative terminal switch, switching switch, positive terminal bridging switch, positive left interconnection switch, positive right interconnection switch, negative left interconnection switch, negative right interconnection switch, negative terminal bridging switch, negative terminal bridging output switch and positive terminal bridging output switch have the same structure, and include: a second IGBT driver and a second IGBT;

[0015] The second IGBT driver is connected to the gate of both the microprocessor and the second IGBT.

[0016] A control method for arc-free circuit breakers with filtering capabilities in distribution areas includes the following steps:

[0017] S1. Initialization is performed through an initialization subroutine;

[0018] S2. In response to startF equaling 1, the trip and compensation calculation subroutine is called to calculate the trip criteria.

[0019] S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform the tripping action.

[0020] Further: S1 includes the following sub-steps:

[0021] S11. Set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds;

[0022] S12. Set the low-frequency interrupt condition and set the low-frequency interrupt subroutine to be called when the interrupt occurs; set the high-frequency interrupt condition and set the high-frequency interrupt subroutine to be called when the interrupt occurs.

[0023] S13. Set variables, including:

[0024] Phase A voltage phase zero degree millisecond counter, Phase A voltage phase zero degree microsecond counter, CH represents high frequency interrupt counter, value range: 0~999, VY represents trip voltage threshold, IY represents trip current threshold, BY represents compensation threshold, TZ represents trip mark, CVA represents sensor read counter, value range: 0~999, CZQ represents period counter, value range: 0~199, SUMV represents voltage summation, MINSUMV represents minimum voltage, MINSUMVG represents minimum voltage threshold, SUMI represents current summation, MAXSUMI represents maximum current, MAXSUMIG represents maximum current threshold;

[0025] The array AVINA

[400] represents the first reading value of phase A of the voltage sensor, the array AVINB

[400] represents the second reading value of phase A of the voltage sensor, the array AFV

[400] represents the floating-point value of phase A voltage, the array AIINA

[400] represents the first reading value of phase A of the current sensor, the array AIINB

[400] represents the second reading value of phase A of the current sensor, the array AFI

[400] represents the floating-point value of phase A current, and the array AVBZ

[400] represents phase A compensation.

[0026] The array BVINA

[400] represents the first reading value of phase B of the voltage sensor, the array BVINB

[400] represents the second reading value of phase B of the voltage sensor, the array BFV

[400] represents the floating-point value of phase B voltage, the array BIINA

[400] represents the first reading value of phase B of the current sensor, the array BINB

[400] represents the second reading value of phase B of the current sensor, the array BFI

[400] represents the floating-point value of phase B current, and the array BVBZ

[400] represents phase B compensation.

[0027] The array CVINA

[400] represents the first reading value of phase C of the voltage sensor, the array CVINB

[400] represents the second reading value of phase C of the voltage sensor, the array CFV

[400] represents the floating-point value of phase C voltage, the array CIINA

[400] represents the first reading value of phase C of the current sensor, the array CIINB

[400] represents the second reading value of phase C of the current sensor, the array CFI

[400] represents the floating-point value of phase C current, and the array CVBZ

[400] represents phase C compensation;

[0028] PT represents the time update data position, FTZ represents the trip calculation variable, TZF represents the trip calculation variable, FBZ represents the compensation calculation variable, FZD represents the low frequency interruption flag, SELF represents the storage selection flag, CNTCNN represents the loop counter, startF represents the start calculation flag, AZK represents the A-phase impedance, BZK represents the B-phase impedance, CZK represents the C-phase impedance, MINZK represents the minimum impedance, ZKYZ represents the impedance trip threshold, ASUMBZ represents the A-phase compensation sum, BSUMBZ represents the B-phase compensation sum, CSUMBZ represents the C-phase compensation sum, MAXSUMBZ represents the maximum compensation sum, and BZYZ represents the compensation threshold.

[0029] S14. Initialize variables. The variables to be initialized are:

[0030] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF=0, ACNTVI=0, BCNTVI=0, CCNTVI= 0, CNTCNN=0, startF=0, FZD=0; FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0031] AVINA, AVINB, BVINA, BVINB, CVINA, and CVINB are initialized to all zeros;

[0032] S15. Set the first parameter M1data and the comparison variable BiJiao.

[0033] Furthermore: In S11, the method for calling the low-frequency interrupt subroutine is specifically as follows:

[0034] A1. Determine if SELF is false. If it is, let ACDATA[i] = AVINA[i], where i = 0 to 799, and proceed to A2.

[0035] If not, let ACDATA[i] = AVINB[i], where i = 0 to 799, and proceed to A2;

[0036] A2. Invert SELF. In response to the condition that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero and AVINA[i+2] is greater than or equal to AVINA[i], let WZ = i and startF = 1.

[0037] Further: In S12, the method for calling the high-frequency interrupt subroutine is specifically as follows:

[0038] B1. Determine if SELF is false. If it is, proceed to SB2.

[0039] If not, then let AVINA equal the stored value of the memory corresponding to the voltage sensor, let AIINA equal the stored value of the memory corresponding to the current sensor, let BVINA equal the stored value of the memory corresponding to the voltage sensor, let BIINA equal the stored value of the memory corresponding to the current sensor, let CVINA equal the stored value of the memory corresponding to the voltage sensor, and let CIINA equal the stored value of the memory corresponding to the current sensor.

[0040] AFV[CNTCNN]=(AVINA–32768) / 32768

[0041] AFI[CNTCNN]=(AIINA–32768) / 32768

[0042] BFV[CNTCNN]=(BVINA–32768) / 32768

[0043] BFI[CNTCNN]=(BIINA–32768) / 32768

[0044] CFV[CNTCNN]=(CVINA–32768) / 32768

[0045] CFI[CNTCNN]=(CIINA–32768) / 32768

[0046] Enter B3;

[0047] B2. Let AVINB be equal to the stored value of the memory corresponding to the voltage sensor, let AIINB be equal to the stored value of the memory corresponding to the current sensor, let BVINB be equal to the stored value of the memory corresponding to the voltage sensor, let BIINB be equal to the stored value of the memory corresponding to the current sensor, let CVINB be equal to the stored value of the memory corresponding to the voltage sensor, and let CIINB be equal to the stored value of the memory corresponding to the current sensor.

[0048] AFV[CNTCNN]=(AVINB–32768) / 32768

[0049] AFI[CNTCNN]=(AIINB–32768) / 32768

[0050] BFV[CNTCNN]=(BVINB–32768) / 32768

[0051] BFI[CNTCNN]=(BIINB–32768) / 32768

[0052] CFV[CNTCNN]=(CVINB–32768) / 32768

[0053] CFI[CNTCNN]=(CIINB–32768) / 32768

[0054] Enter B3;

[0055] B3. Increment the value of CNTCNN by 1. In response to CNTCNN being greater than 800, set CNTCNN = 0.

[0056] Enter B4;

[0057] B4, responding to FBZ equal to 1, proceed to B5;

[0058] B5. Determine if CNTCNN is greater than WZ. If yes, let WZ1 = CNTCNN - WZ; otherwise, let WZ1 = 400 + CNTCNN - WZ.

[0059] Enter B6;

[0060] B6. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1.

[0061] Enter B7;

[0062] B7. Control the A-phase circuit, then proceed to B8;

[0063] B8. Add 133 to the WZ value and determine whether CNTCNN is greater than WZ. If it is, let WZ1 = CNTCNN - WZ; if not, let WZ1 = 400 + CNTCNN - WZ.

[0064] Enter B9;

[0065] B9. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1;

[0066] Enter B10;

[0067] B10. Control the B-phase circuit, then proceed to B11;

[0068] B11. Add 266 to the WZ value and determine whether CNTCNN is greater than WZ. If yes, set WZ1 = CNTCNN - WZ; otherwise, set WZ1 = 400 + CNTCNN - WZ and proceed to B12.

[0069] B12. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400, and then proceed to B13.

[0070] B13. Control of the C-phase circuit;

[0071] The control methods for phases A, B, and C are the same, specifically as follows:

[0072] If the response is greater than or equal to 0.875, then:

[0073] Turn off the positive output switch, negative input switch, positive bridge switch, positive left interconnect switch, positive right interconnect switch, negative left interconnect switch, negative right interconnect switch, and negative bridge output switch;

[0074] Turn on the output negative terminal switch, input positive terminal switch, toggle switch, negative terminal bridge switch, and positive terminal bridge output switch;

[0075] If the response is that AVBZ[WZ1] is less than 0.875 and greater than or equal to 0.625, then:

[0076] Turn off the positive output switch, toggle switch, positive bridge switch, negative left interconnect switch, negative right interconnect switch, and negative bridge output switch;

[0077] Turn on the output negative terminal switch, input positive terminal switch, input negative terminal switch, negative terminal bridging switch, positive terminal bridging output switch, positive left interconnection switch, and positive right interconnection switch;

[0078] If the response is that AVBZ[WZ1] is less than 0.625 and greater than or equal to 0.375, then:

[0079] Turn on the positive output switch, toggle switch, positive left interconnect switch, and positive right interconnect switch; turn off the negative bridge output switch and the negative bridge switch.

[0080] Turn on the output negative terminal switch, input positive terminal switch, input negative terminal switch, positive terminal bridged output switch, positive terminal bridged switch, negative left interconnection switch, and negative right interconnection switch;

[0081] If the response is that AVBZ[WZ1] is less than 0.375 and greater than or equal to 0.125, then:

[0082] Turn off the output negative terminal switch, toggle switch, positive terminal bridge switch, negative left interconnect switch, negative right interconnect switch, and negative terminal bridge output switch;

[0083] Turn on the output positive terminal switch, input positive terminal switch, input negative terminal switch, positive left interconnection switch, positive right interconnection switch, negative terminal bridging switch, and positive terminal bridging output switch;

[0084] If the response is that AVBZ[WZ1] is less than 0.125 and greater than or equal to -0.125, then:

[0085] Turn off the positive output switch, toggle switch, positive bridge switch, negative left interconnect switch, negative right interconnect switch, and positive bridge output switch;

[0086] Turn on the output negative terminal switch, input positive terminal switch, input negative terminal switch, positive left interconnection switch, positive right interconnection switch, negative terminal bridging switch, and negative terminal bridging output switch;

[0087] If the response is that AVBZ[WZ1] is less than -0.125 and greater than or equal to -0.375, then:

[0088] Turn off the positive output switch, toggle switch, positive left interconnection switch, positive right interconnection switch, negative bridge switch, and positive bridge output switch;

[0089] Turn on the output negative terminal switch, input positive terminal switch, input negative terminal switch, positive terminal bridging switch, negative left interconnection switch, negative right interconnection switch, and negative terminal bridging output switch;

[0090] If the response is that AVBZ[WZ1] is less than -0.375 and greater than or equal to -0.625, then:

[0091] Turn off the output negative terminal switch, toggle switch, positive terminal bridge switch, negative left interconnect switch, negative right interconnect switch, and positive terminal bridge output switch;

[0092] Turn on the output positive terminal switch, input positive terminal switch, input negative terminal switch, positive left interconnection switch, positive right interconnection switch, negative terminal bridging switch, and negative terminal bridging output switch;

[0093] If the response is that AVBZ[WZ1] is less than -0.625 and greater than or equal to -0.875, then:

[0094] Turn off the positive input switch, negative output switch, toggle switch, positive left interconnect switch, positive right interconnect switch, negative bridge switch, and positive bridge output switch;

[0095] Turn on the output positive terminal switch, input negative terminal switch, positive terminal bridging switch, negative left interconnection switch, negative right interconnection switch, and negative terminal bridging output switch;

[0096] If the response is that AVBZ[WZ1] is less than -0.875, then:

[0097] Turn off the output negative terminal switch, positive left interconnection switch, positive right interconnection switch, negative left interconnection switch, negative right interconnection switch, negative terminal bridging switch, and positive terminal bridging output switch;

[0098] Turn on the output positive terminal switch, the toggle switch, the input positive terminal switch, the input negative terminal switch, the positive terminal bridging switch, and the negative terminal bridging output switch.

[0099] Further: In S2, the method of calling the tripping and compensation calculation subroutine is specifically as follows:

[0100] S21. Calculate the following data:

[0101]

[0102]

[0103]

[0104]

[0105]

[0106]

[0107] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0108] S22. Calculate the minimum value of SUMVA, SUMVB, and SUMVC, and assign it to MINSUMV.

[0109] S23. Calculate the maximum value of SUMIA, SUMIB, and SUMIC, and assign it to MAXSUMI;

[0110] S24. Determine whether either MINSUMV is less than MINSUMVG or MAXSUMI is greater than MAXSUMIG. If yes, then TZF = 1; otherwise, then TZF = 0.

[0111] S25. Calculate the following data:

[0112] AIBZ[i]=M1data[i]–AFI[i+WZ]

[0113] In the formula, i = 0 to 399;

[0114] WZ1 = WZ + 133

[0115] If WZ1 is greater than 400, then the value of WZ1 is reduced by 400.

[0116] BIBZ[i]=M1data[i]–BFI[i+WZ1]

[0117] WZ1 = WZ + 266

[0118] If WZ1 is greater than 400, then the value of WZ1 is reduced by 400.

[0119] CIBZ[i]=M1data[i]–CFI[i+WZ1]

[0120] S26. Calculate the following data:

[0121]

[0122]

[0123]

[0124] S27. Calculate the maximum value of ASUMZB, BSUMZB and CSUMZB, and assign it to MAXSUMBZ.

[0125] Determine if MAXSUMBZ is greater than or equal to BZYZ; if yes, set FBZ = 1; if no, set FBZ = 0.

[0126] In S3, the method for calling the tripping action subroutine is as follows:

[0127] S31. Control the first IGBT to turn on and control the mechanical circuit breaker to turn off;

[0128] S32, Control the first IGBT to turn off.

[0129] The beneficial effects of this invention are as follows: A transformer substation arc-free circuit breaker with filtering capability and its control method, comprising a microprocessor, a voltage sensor, a current sensor, a mechanical circuit breaker, a filtering module, a wireless communication module, and a first IGBT drive circuit. The microprocessor receives the sensing signals from the voltage and current sensors, and the control information from the wireless communication module; based on the sensing signals from the voltage and current sensors and the control information from the wireless communication module, it calculates the operating status of the transformer substation, and controls the mechanical circuit breaker, the first IGBT drive circuit, and the filtering module according to the calculation results, thus solving the problem that traditional circuit breakers can no longer meet the increasing demand from photovoltaic, charging piles, and other new energy sources in transformer substations. Attached Figure Description

[0130] Figure 1 This is a schematic diagram of a transformer substation arc-free circuit breaker with filtering capabilities.

[0131] Figure 2 This is a structural diagram of the filtering module.

[0132] Figure 3 This is a structural diagram of the filter controller.

[0133] Figure 4 This is a diagram of a voltage conversion circuit.

[0134] Figure 5 This is a structural diagram of the switch module.

[0135] Figure 6This is a flowchart of a control method for a transformer substation arc-free circuit breaker with filtering capabilities.

[0136] The components include: 1. Voltage sensor; 2. Current sensor; 3. Mechanical circuit breaker; 4. Filter module; 5. Wireless communication module; 6. Microprocessor; 7. First IGBT drive circuit; 8. First IGBT; 21. Grid-side inductor; 22. Grid-side resistor; 23. Neutral line resistor; 24. Neutral line capacitor; 25. Neutral line; 26. Filter controller; 27. Filter resistor; 28. Filter inductor; 29. ​​Load-side resistor; 30. Load-side inductor; 41. Voltage conversion circuit; 42. Upper voltage control capacitor; 43. Lower voltage control capacitor; 44. Output capacitor; 45. Current control inductor; 46. Output inductor; 47. Output positive terminal; 48. Output negative terminal; 61. Input positive terminal switch; 62. Output positive terminal switch; 63. 64. Output negative terminal switch; 65. Input negative terminal switch; 66. Toggle switch; 67. Positive terminal bridging switch; 68. Positive left interconnection switch; 69. Positive right interconnection switch; 70. Negative left interconnection switch; 71. Negative terminal bridging switch; 72. Negative terminal bridging output switch; 73. Positive terminal bridging output switch; 81. Connection terminal A; 82. Connection terminal B; 83. Connection terminal C; 84. Connection terminal N; 85-1. First power diode; 85-2. Second power diode; 85-3. Third power diode; 86. Connection terminal D; 91. Second IGBT driver; 92. Second IGBT; 93. Collector of the second IGBT driver; 94. Emitter of the second IGBT driver. Detailed Implementation

[0137] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0138] Example 1:

[0139] like Figure 1 As shown, in one embodiment of the present invention, a transformer area arc-free circuit breaker with filtering capability includes a voltage sensor 1, a current sensor 2, a mechanical circuit breaker 3, a filtering module 4, a wireless communication module 5, a microprocessor 6, a first IGBT drive circuit 7, and a first IGBT 8.

[0140] Among them, voltage sensor 1, current sensor 2, mechanical circuit breaker 3 and filter module 4 are connected in sequence. Microprocessor 6 is connected to voltage sensor 1, current sensor 2, mechanical circuit breaker 3 and filter module 4, wireless communication module 5 and first IGBT drive circuit 7 respectively. First IGBT drive circuit 7 is also connected to first IGBT 8. One end of first IGBT 8 is connected to current sensor 2 and mechanical circuit breaker 3 respectively. The other end of first IGBT 8 is connected to mechanical circuit breaker 3 and filter module 4 respectively.

[0141] Voltage sensor 1 is used to collect the three-phase voltage values ​​output by the transformer in the distribution area; current sensor 2 is used to collect the three-phase current values ​​output by the transformer in the distribution area; wireless communication module 5 is used to receive control information from the circuit breaker in the distribution area; microprocessor 6 is used to calculate the operating status of the distribution area based on the three-phase voltage and current values ​​output by the transformer in the distribution area, clock signal and control information, and to control the mechanical circuit breaker 3, the first IGBT drive circuit 7 and the filter module 4 based on the calculation results; thyristor 9 is used to control the current.

[0142] The output of the transformer in the distribution area is a three-phase conductor, which passes through voltage sensor 1 and current sensor 2 and is connected to the input terminal of mechanical circuit breaker 3. The output terminal of mechanical circuit breaker 3 is connected to the input terminal of filter module 4, and the output terminal of filter module 4 is connected to the load in the distribution area to supply power to the load.

[0143] Voltage sensor 1 and current sensor 2 collect the voltage and current values ​​of the three phases (A, B, and C) output from the transformer in the distribution area. The sensor outputs are connected to the analog-to-digital conversion interface of the microprocessor 6.

[0144] like Figure 2 As shown, the filter module 4 includes a grid-side inductor 21, a grid-side resistor 22, a neutral line resistor 23, a neutral line capacitor 24, a filter controller 26, a filter resistor 27, a filter inductor 28, a load-side resistor 29, and a load-side inductor 30.

[0145] One end of the grid-side inductor 21 is connected to the mechanical circuit breaker 3, and the other end of the grid-side inductor 21 is connected to one end of the grid-side resistor 22. The other end of the grid-side resistor 22 is connected to one end of the neutral line resistor 23, one end of the filter inductor 28, and one end of the load-side resistor 29, respectively. The other end of the neutral line resistor 23 is connected to the neutral line 25 through the neutral line capacitor 24. The other end of the filter inductor 28 is connected to the filter controller 26 through the filter resistor 27. The other end of the load-side resistor 29 is connected to the load of the distribution area through the load-side inductor 30.

[0146] In this embodiment, there are three filter modules 4, distributed on phases A, B, and C, with one connected to each phase.

[0147] like Figure 3As shown, the filter controller 26 includes a voltage conversion circuit 41, an upper voltage control capacitor 42, a lower voltage control capacitor 43, an output capacitor 44, a current control inductor 45, an output inductor 46, an input positive terminal switch 61, an output positive terminal switch 62, an output negative terminal switch 63, an input negative terminal switch 64, a switching switch 65, a positive terminal bridging switch 66, a positive left interconnection switch 67, a positive right interconnection switch 68, a negative left interconnection switch 69, a negative right interconnection switch 70, a negative terminal bridging switch 71, a negative terminal bridging output switch 72, and a positive terminal bridging output switch 73.

[0148] The connection terminals A81, B82, and C83 of the voltage conversion circuit 41 are connected to phases A, B, and C of the power supply, respectively. The connection terminal N84 of the voltage conversion circuit 41 is connected to the power supply neutral line, the emitter of the output negative switch 63, and the emitter of the input negative switch 64, respectively. The connection terminal D86 of the voltage conversion circuit 41 is connected to the collector of the input positive switch 61 and the collector of the output positive switch 62, respectively. The emitter of the input positive switch 61 is connected to the emitter of the positive bridge switch 66. The collector of the switching switch 65 is connected to the collector of the positive left interconnecting switch 67. The emitter of the output positive terminal switch 62 is connected to the collector of the output negative terminal switch 63, one end of the output capacitor 44, and the output negative terminal 48, respectively. The collector of the positive terminal bridging switch 66 is connected to the collector of the positive terminal bridging output switch 73 and one end of the upper voltage control capacitor 42, respectively. The emitter of the positive left interconnecting switch 67 is connected to the emitter of the positive right interconnecting switch 68. The collector of the positive right interconnecting switch 68 is connected to the other end of the upper voltage control capacitor 42 and one end of the current control inductor 45.

[0149] The collector of the input negative terminal switch 64 is connected to the collector of the negative terminal bridge switch 71, the emitter of the switching switch 65, and the collector of the negative left interconnect switch 69, respectively. The emitter of the negative left interconnect switch 69 is connected to the emitter of the negative right interconnect switch 70. The collector of the negative right interconnect switch 70 is connected to one end of the lower voltage control capacitor 43 and the other end of the current control inductor 45, respectively. The emitter of the negative terminal bridge switch 71 is connected to the other end of the lower voltage control capacitor 43 and the emitter of the negative terminal bridge output switch 72, respectively. The collector of the negative terminal bridge output switch 72 is connected to the emitter of the positive terminal bridge output switch 73 and one end of the output inductor 46, respectively. The other end of the output inductor 46 is connected to the other end of the output capacitor 44 and the output positive terminal 47, respectively.

[0150] like Figure 4 As shown, the voltage conversion circuit 41 includes a first power diode 85-1, a second power diode 85-2, a third power diode 85-3, a connection terminal A81, a connection terminal B82, a connection terminal C83, a connection terminal D86, and a connection terminal N84.

[0151] The negative terminals of the first power diode 85-1, the second power diode 85-2, and the third power diode 85-3 are all connected to the connection terminal D86, and the positive terminals of the first power diode 85-1, the second power diode 85-2, and the third power diode 85-3 are respectively connected to the connection terminals A81, B82, and C83.

[0152] like Figure 5 As shown, the input positive terminal switch 61, output positive terminal switch 62, output negative terminal switch 63, input negative terminal switch 64, switching switch 65, positive terminal bridging switch 66, positive left interconnection switch 67, positive right interconnection switch 68, negative left interconnection switch 69, negative right interconnection switch 70, negative terminal bridging switch 71, negative terminal bridging output switch 72, and positive terminal bridging output switch 73 have the same structure and include: a second IGBT driver 91 and a second IGBT 92;

[0153] The second IGBT driver 91 is connected to the gate of the microprocessor 6 and the gate of the second IGBT 92 respectively. The second IGBT 92 also includes the collector 93 and the emitter 94 of the second IGBT driver.

[0154] like Figure 6 As shown, the control method for an arc-free circuit breaker with filtering capability in a distribution area includes the following steps:

[0155] S1. Initialization is performed through an initialization subroutine;

[0156] S2. In response to startF equaling 1, the trip and compensation calculation subroutine is called to calculate the trip criteria.

[0157] S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform the tripping action.

[0158] S1 includes the following steps:

[0159] S11. Set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds;

[0160] S12. Set the low-frequency interrupt condition and set the low-frequency interrupt subroutine to be called when the interrupt occurs; set the high-frequency interrupt condition and set the high-frequency interrupt subroutine to be called when the interrupt occurs.

[0161] S13. Set variables, including:

[0162] Phase A voltage phase zero degree millisecond counter, Phase A voltage phase zero degree microsecond counter, CH represents high frequency interrupt counter, value range: 0~999, VY represents trip voltage threshold, IY represents trip current threshold, BY represents compensation threshold, TZ represents trip mark, CVA represents sensor read counter, value range: 0~999, CZQ represents period counter, value range: 0~199, SUMV represents voltage summation, MINSUMV represents minimum voltage, MINSUMVG represents minimum voltage threshold, SUMI represents current summation, MAXSUMI represents maximum current, MAXSUMIG represents maximum current threshold;

[0163] The array AVINA

[400] represents the first reading value of phase A of voltage sensor 1, the array AVINB

[400] represents the second reading value of phase A of voltage sensor 1, the array AFV

[400] represents the floating-point value of phase A voltage, the array AIINA

[400] represents the first reading value of phase A of current sensor 2, the array AIINB

[400] represents the second reading value of phase A of current sensor 2, the array AFI

[400] represents the floating-point value of phase A current, and the array AVBZ

[400] represents phase A compensation;

[0164] The array BVINA

[400] represents the first reading value of phase B of voltage sensor 1, the array BVINB

[400] represents the second reading value of phase B of voltage sensor 1, the array BFV

[400] represents the floating-point value of phase B voltage, the array BIINA

[400] represents the first reading value of phase B of current sensor 2, the array BINB

[400] represents the second reading value of phase B of current sensor 2, the array BFI

[400] represents the floating-point value of phase B current, and the array BVBZ

[400] represents phase B compensation;

[0165] The array CVINA

[400] represents the first reading value of phase C of voltage sensor 1, the array CVINB

[400] represents the second reading value of phase C of voltage sensor 1, the array CFV

[400] represents the floating-point value of phase C voltage, the array CIINA

[400] represents the first reading value of phase C of current sensor 2, the array CIINB

[400] represents the second reading value of phase C of current sensor 2, the array CFI

[400] represents the floating-point value of phase C current, and the array CVBZ

[400] represents phase C compensation;

[0166] PT represents the time update data position, FTZ represents the trip calculation variable, TZF represents the trip calculation variable, FBZ represents the compensation calculation variable, FZD represents the low frequency interruption flag, SELF represents the storage selection flag, CNTCNN represents the loop counter, startF represents the start calculation flag, AZK represents the A-phase impedance, BZK represents the B-phase impedance, CZK represents the C-phase impedance, MINZK represents the minimum impedance, ZKYZ represents the impedance trip threshold, ASUMBZ represents the A-phase compensation sum, BSUMBZ represents the B-phase compensation sum, CSUMBZ represents the C-phase compensation sum, MAXSUMBZ represents the maximum compensation sum, and BZYZ represents the compensation threshold.

[0167] S14. Initialize variables. The variables to be initialized are:

[0168] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF=0, ACNTVI=0, BCNTVI=0, CCNTVI= 0, CNTCNN=0, startF=0, FZD=0; FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0169] AVINA, AVINB, BVINA, BVINB, CVINA, and CVINB are initialized to all zeros;

[0170] S15. Set the first parameter M1data and the comparison variable BiJiao.

[0171] M1data

[400] = {0.015707,0.031411,0.047106,0.062791,0.078459,0.094108,0.109734,0.125333,0.140901,0.156434,0.171929,0.187381,0.2} 02787,0.218143,0.233445,0.248690,0.263873,0.278991,0.294040,0.309017,0.323917,0.338738,0.353475,0.368125,0.382683,0.397148,0. 411514,0.425779,0.439939,0.453990,0.467930,0.481754,0.495459,0.509041,0.522499,0.535827,0.549023,0.562083,0.575005,0.587785, 0.600420,0.612907,0.625243,0.637424,0.649448,0.661312,0.673013,0.684547,0.695913,0.707107,0.718126,0.728969,0.739631,0.750111 ,0.760406,0.770513,0.780430,0.790155,0.799685,0.809017,0.818150,0.827081,0.835807,0.844328,0.852640,0.860742,0.868632,0.8763 07,0.883766,0.891007,0.898028,0.904827,0.911403,0.917755,0.923880,0.929776,0.935444,0.940881,0.946085,0.951057,0.955793,0.960 294,0.964557,0.968583,0.972370,0.975917,0.979223,0.982287,0.985109,0.987688,0.990024,0.992115,0.993961,0.995562,0.996917,0.9 98027,0.998890,0.999507,0.999877,1.000000,0.999877,0.999507,0.998890,0.998027,0.996917,0.995562,0.993961,0.992115,0.990024,0.987688,0.985109,0.982287,0.979223,0.975917,0.972370,0.968583,0.964557,0.960294,0.955793,0.951057,0.946085,0.940881,0.935444,0.929776,0.923880,0.917755,0.911403,0.904827,0.898028,0.891007,0.883766,0.876307,0.868632,0.860742,0.852640,0.844328,0.835807,0.827081,0.818150,0.809017,0.799685,0.790155,0.780430,0.770513,0.760406,0.750111,0.739631,0.728969,0.718126,0.707107,0.695913,0.684547,0.673013,0.661312,0.649448,0.637424,0.625243,0.612907,0.600420,0.587785,0.575005,0.562083,0.549023,0.535827,0.522499,0.509041,0.495459,0.481754,0.467930,0.453990,0.439939,0.425779,0.411514,0.397148,0.382683,0.368125,0.353475,0.338738,0.323917,0.309017,0.294040,0.278991,0.263873,0.248690,0.233445,0.218143,0.202787,0.187381,0.171929,0.156434,0.140901,0.125333,0.109734,0.094108,0.078459,0.062791,0.047106,0.031411,0.015707,0.000000,-0.015707,-0.031411,-0.047106,-0.062791,-0.078459,-0.094108,-0.109734,-0.125333,-0.140901,-0.156434,-0.171929,-0.187381,-0.202787,-0.218143,-0.233445,-0.248690,-0.263873,-0.278991,-0.294040,-0.309017,-0.323917,-0.338738,-0.353475,-0.368125,-0.382683,-0.397148,-0.411514,-0.425779,-0.439939,-0.453990,-0.467930,-0.481754,-0.495459,-0.509041,-0.522499,-0.535827,-0.549023,-0.562083,-0.575005,-0.587785,-0.600420,-0.612907,-0.625243,-0.637424,-0.649448,-0.661312,-0.673013,-0.684547,-0.695913,-0.707107,-0.718126,-0.728969,-0.739631,-0.750111,-0.760406,-0.770513,-0.780430,-0.790155,-0.799685,-0.809017,-0.818150,-0.827081,-0.835807,-0.844328,-0.852640,-0.860742,-0.868632,-0.876307,-0.883766,-0.891007,-0.898028,-0.904827,-0.911403,-0.917755,-0.923880,-0.929776,-0.935444,-0.940881,-0.946085,-0.951057,-0.955793,-0.960294,-0.964557,-0.968583,-0.972370,-0.975917,-0.979223,-0.982287,-0.985109,-0.987688,-0.990024,-0.992115,-0.993961,-0.995562,-0.996917,-0.998027,-0.998890,-0.999507,-0.999877,-1.000000,-0.999877,-0.999507,-0.998890,-0.998027,-0.996917,-0.995562,-0.993961,-0.992115,-0.990024,-0.987688,-0.985109,-0.982287,-0.979223,-0.975917,-0.972370,-0.968583,-0.964557,-0.960294,-0.955793,-0.951057,-0.946085,-0.940881,-0.935444,-0.929776,-0.923880,-0.917755,-0.911403,-0.904827,-0.898028,-0.891007,-0.883766,-0.876307,-0.868632,-0.860742,-0.852640,-0.844328,-0.835807,-0.827081,-0.8181 50, -0.809017, -0.799685, -0.790155, -0.780430, -0.770513, -0.760406, -0.750111, -0.739631, -0.728969, -0.718126, -0.707107, -0.695913, -0.684547, -0.673013, -0.661312, -0.649448, -0.637424, -0.625243, -0.612907, -0.600420, -0 .587785,-0.575005,-0.562083,-0.549023,-0.535827,-0.522499,-0.509041,-0.495459,-0.481754,-0.467930,-0.453990,-0.439939,-0.425779,-0.411514,-0.397148,-0.382683,-0.368125,-0.353475,-0.338738,-0.323917,-0.309 017,-0.294040,-0.278991,-0.263873,-0.248690,-0.233445,-0.218143,-0.202787,-0.187381,-0.171929,-0.156434,-0.140901,-0.125333,-0.109734,-0.094108,-0.078459,-0.062791,-0.047106,-0.031411,-0.015707,-0.000000}.

[0172] In S11, the method for calling the low-frequency interrupt subroutine is as follows:

[0173] A1. Determine if SELF is false. If it is, let ACDATA[i] = AVINA[i], where i = 0 to 799, and proceed to A2.

[0174] If not, let ACDATA[i] = AVINB[i], where i = 0 to 799, and proceed to A2;

[0175] A2. Invert SELF. In response to the condition that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero and AVINA[i+2] is greater than or equal to AVINA[i], let WZ = i and startF = 1.

[0176] In S12, the method for calling the high-frequency interrupt subroutine is as follows:

[0177] B1. Determine if SELF is false. If it is, proceed to SB2.

[0178] If not, then let AVINA equal the stored value of the memory corresponding to voltage sensor 1, let AIINA equal the stored value of the memory corresponding to current sensor 2, let BVINA equal the stored value of the memory corresponding to voltage sensor 1, let BIINA equal the stored value of the memory corresponding to current sensor 2, let CVINA equal the stored value of the memory corresponding to voltage sensor 1, and let CIINA equal the stored value of the memory corresponding to current sensor 2.

[0179] AFV[CNTCNN]=(AVINA–32768) / 32768

[0180] AFI[CNTCNN]=(AIINA–32768) / 32768

[0181] BFV[CNTCNN]=(BVINA–32768) / 32768

[0182] BFI[CNTCNN]=(BIINA–32768) / 32768

[0183] CFV[CNTCNN]=(CVINA–32768) / 32768

[0184] CFI[CNTCNN]=(CIINA–32768) / 32768

[0185] Enter B3;

[0186] B2. Let AVINB be equal to the stored value of the memory corresponding to voltage sensor 1, let AIINB be equal to the stored value of the memory corresponding to current sensor 2, let BVINB be equal to the stored value of the memory corresponding to voltage sensor 1, let BIINB be equal to the stored value of the memory corresponding to current sensor 2, let CVINB be equal to the stored value of the memory corresponding to voltage sensor 1, and let CIINB be equal to the stored value of the memory corresponding to current sensor 2.

[0187] AFV[CNTCNN]=(AVINB–32768) / 32768

[0188] AFI[CNTCNN]=(AIINB–32768) / 32768

[0189] BFV[CNTCNN]=(BVINB–32768) / 32768

[0190] BFI[CNTCNN]=(BIINB–32768) / 32768

[0191] CFV[CNTCNN]=(CVINB–32768) / 32768

[0192] CFI[CNTCNN]=(CIINB–32768) / 32768

[0193] Enter B3;

[0194] B3. Increment the value of CNTCNN by 1. In response to CNTCNN being greater than 800, set CNTCNN = 0.

[0195] Enter B4;

[0196] B4, responding to FBZ equal to 1, proceed to B5;

[0197] B5. Determine if CNTCNN is greater than WZ. If yes, let WZ1 = CNTCNN - WZ; otherwise, let WZ1 = 400 + CNTCNN - WZ.

[0198] Enter B6;

[0199] B6. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1.

[0200] Enter B7;

[0201] B7. Control the A-phase circuit, then proceed to B8;

[0202] B8. Add 133 to the WZ value and determine whether CNTCNN is greater than WZ. If it is, let WZ1 = CNTCNN - WZ; if not, let WZ1 = 400 + CNTCNN - WZ.

[0203] Enter B9;

[0204] B9. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1;

[0205] Enter B10;

[0206] B10. Control the B-phase circuit, then proceed to B11;

[0207] B11. Add 266 to the WZ value and determine whether CNTCNN is greater than WZ. If yes, set WZ1 = CNTCNN - WZ; otherwise, set WZ1 = 400 + CNTCNN - WZ and proceed to B12.

[0208] B12. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400, and then proceed to B13.

[0209] B13. Control of the C-phase circuit;

[0210] The control methods for phases A, B, and C are the same, specifically as follows:

[0211] If the response is greater than or equal to 0.875, then:

[0212] Turn off the positive output switch 62, negative input switch 64, positive bridge switch 66, positive left interconnect switch 67, positive right interconnect switch 68, negative left interconnect switch 69, negative right interconnect switch 70 and negative bridge output switch 72;

[0213] Turn on the output negative terminal switch 63, the input positive terminal switch 61, the switching switch 65, the negative terminal bridging switch 71, and the positive terminal bridging output switch 73;

[0214] If the response is that AVBZ[WZ1] is less than 0.875 and greater than or equal to 0.625, then:

[0215] Turn off the positive output switch 62, the toggle switch 65, the positive bridging switch 66, the negative left interconnect switch 69, the negative right interconnect switch 70, and the negative bridging output switch 72.

[0216] Turn on the output negative terminal switch 63, input positive terminal switch 61, input negative terminal switch 64, negative terminal bridging switch 71, positive terminal bridging output switch 73, positive left interconnection switch 67, and positive right interconnection switch 68;

[0217] If the response is that AVBZ[WZ1] is less than 0.625 and greater than or equal to 0.375, then:

[0218] Turn on the positive output switch 62, the toggle switch 65, the positive left interconnect switch 67, and the positive right interconnect switch 68; turn off the negative bridge output switch 72 and the negative bridge switch 71.

[0219] Turn on the output negative terminal switch 63, input positive terminal switch 61, input negative terminal switch 64, positive terminal bridged output switch 73, positive terminal bridged switch 66, negative left interconnection switch 69, and negative right interconnection switch 70.

[0220] If the response is that AVBZ[WZ1] is less than 0.375 and greater than or equal to 0.125, then:

[0221] Turn off the output negative terminal switch 63, the switching switch 65, the positive terminal bridging switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the negative terminal bridging output switch 72.

[0222] Turn on the output positive terminal switch 62, input positive terminal switch 61, input negative terminal switch 64, positive left interconnection switch 67, positive right interconnection switch 68, negative terminal bridging switch 71, and positive terminal bridging output switch 73;

[0223] If the response is that AVBZ[WZ1] is less than 0.125 and greater than or equal to -0.125, then:

[0224] Turn off the positive output switch 62, the toggle switch 65, the positive bridge switch 66, the negative left interconnect switch 69, the negative right interconnect switch 70, and the positive bridge output switch 73.

[0225] Turn on the output negative terminal switch 63, input positive terminal switch 61, input negative terminal switch 64, positive left interconnection switch 67, positive right interconnection switch 68, negative terminal bridging switch 71, and negative terminal bridging output switch 72;

[0226] If the response is that AVBZ[WZ1] is less than -0.125 and greater than or equal to -0.375, then:

[0227] Turn off the positive output switch 62, the toggle switch 65, the positive left interconnect switch 67, the positive right interconnect switch 68, the negative bridge switch 71, and the positive bridge output switch 73.

[0228] Turn on the output negative terminal switch 63, input positive terminal switch 61, input negative terminal switch 64, positive terminal bridging switch 66, negative left interconnection switch 69, negative right interconnection switch 70, and negative terminal bridging output switch 72.

[0229] If the response is that AVBZ[WZ1] is less than -0.375 and greater than or equal to -0.625, then:

[0230] Turn off the output negative terminal switch 63, the switching switch 65, the positive terminal bridging switch 66, the negative left interconnection switch 69, the negative right interconnection switch 70, and the positive terminal bridging output switch 73.

[0231] Turn on the output positive terminal switch 62, input positive terminal switch 61, input negative terminal switch 64, positive left interconnection switch 67, positive right interconnection switch 68, negative terminal bridging switch 71, and negative terminal bridging output switch 72;

[0232] If the response is that AVBZ[WZ1] is less than -0.625 and greater than or equal to -0.875, then:

[0233] Turn off the positive input switch 61, negative output switch 63, toggle switch 65, positive left interconnect switch 67, positive right interconnect switch 68, negative bridge switch 71, and positive bridge output switch 73.

[0234] Turn on the output positive terminal switch 62, input negative terminal switch 64, positive terminal bridging switch 66, negative left interconnection switch 69, negative right interconnection switch 70, and negative terminal bridging output switch 72;

[0235] If the response is that AVBZ[WZ1] is less than -0.875, then:

[0236] Turn off the output negative terminal switch 63, positive left interconnection switch 67, positive right interconnection switch 68, negative left interconnection switch 69, negative right interconnection switch 70, negative terminal bridging switch 71, and positive terminal bridging output switch 73.

[0237] Turn on the output positive terminal switch 62, the switching switch 65, the input positive terminal switch 61, the input negative terminal switch 64, the positive terminal bridging switch 66, and the negative terminal bridging output switch 72.

[0238] In S2, the method for calling the tripping and compensation calculation subroutine is as follows:

[0239] S21. Calculate the following data:

[0240]

[0241]

[0242]

[0243]

[0244]

[0245]

[0246] In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400;

[0247] S22. Calculate the minimum value of SUMVA, SUMVB, and SUMVC, and assign it to MINSUMV.

[0248] S23. Calculate the maximum value of SUMIA, SUMIB, and SUMIC, and assign it to MAXSUMI;

[0249] S24. Determine whether either MINSUMV is less than MINSUMVG or MAXSUMI is greater than MAXSUMIG. If yes, then TZF = 1; otherwise, then TZF = 0.

[0250] S25. Calculate the following data:

[0251] AIBZ[i]=M1data[i]–AFI[i+WZ]

[0252] In the formula, i = 0 to 399;

[0253] WZ1 = WZ + 133

[0254] If WZ1 is greater than 400, then the value of WZ1 is reduced by 400.

[0255] BIBZ[i]=M1data[i]–BFI[i+WZ1]

[0256] WZ1 = WZ + 266

[0257] If WZ1 is greater than 400, then the value of WZ1 is reduced by 400.

[0258] CIBZ[i]=M1data[i]–CFI[i+WZ1]

[0259] S26. Calculate the following data:

[0260]

[0261]

[0262]

[0263] S27. Calculate the maximum value of ASUMZB, BSUMZB and CSUMZB, and assign it to MAXSUMBZ.

[0264] Determine if MAXSUMBZ is greater than or equal to BZYZ; if yes, set FBZ = 1; if no, set FBZ = 0.

[0265] In S3, the method for calling the tripping action subroutine is as follows:

[0266] S31, control the first IGBT8 to turn on, and control the mechanical circuit breaker 3 to turn off;

[0267] S32, control the first IGBT8 to turn off.

[0268] In the description of this invention, it should be understood that the terms "center," "thickness," "upper," "lower," "horizontal," "top," "bottom," "inner," "outer," and "radial," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying the relative importance or the number of technical features implicitly specified. Therefore, a feature defined by "first," "second," and "third" may explicitly or implicitly include one or more of that feature.

Claims

1. A transformer substation arc-free circuit breaker with filtering capability, characterized in that, It includes a voltage sensor (1), a current sensor (2), a mechanical circuit breaker (3), a filter module (4), a wireless communication module (5), a microprocessor (6), a first IGBT drive circuit (7), and a first IGBT (8); Among them, voltage sensor (1), current sensor (2), mechanical circuit breaker (3) and filter module (4) are connected in sequence. Microprocessor (6) is connected to voltage sensor (1), current sensor (2), mechanical circuit breaker (3) and filter module (4), wireless communication module (5) and first IGBT drive circuit (7) respectively. First IGBT drive circuit (7) is also connected to first IGBT (8). One end of first IGBT (8) is connected to current sensor (2) and mechanical circuit breaker (3) respectively. The other end of first IGBT (8) is connected to mechanical circuit breaker (3) and filter module (4) respectively. The voltage sensor (1) is used to collect the three-phase voltage values ​​output by the transformer in the distribution area, the current sensor (2) is used to collect the three-phase current values ​​output by the transformer in the distribution area, the wireless communication module (5) is used to receive the control information of the circuit breaker in the distribution area, and the microprocessor (6) is used to calculate the operating status of the distribution area based on the three-phase voltage and current values, clock signal and control information output by the transformer in the distribution area, and to control the mechanical circuit breaker (3), the first IGBT drive circuit (7) and the filter module (4) based on the calculation results. The filter module (4) includes a grid-side inductor (21), a grid-side resistor (22), a neutral line resistor (23), a neutral line capacitor (24), a filter controller (26), a filter resistor (27), a filter inductor (28), a load-side resistor (29), and a load-side inductor (30). One end of the grid-side inductor (21) is connected to the mechanical circuit breaker (3), and the other end of the grid-side inductor (21) is connected to one end of the grid-side resistor (22). The other end of the grid-side resistor (22) is connected to one end of the neutral line resistor (23), one end of the filter inductor (28), and one end of the load-side resistor (29). The other end of the neutral line resistor (23) is connected to the neutral line (25) through the neutral line capacitor (24). The other end of the filter inductor (28) is connected to the filter controller (26) through the filter resistor (27). The other end of the load-side resistor (29) is connected to the load of the distribution area through the load-side inductor (30). The filter controller (26) includes a voltage conversion circuit (41), an upper voltage control capacitor (42), a lower voltage control capacitor (43), an output capacitor (44), a current control inductor (45), an output inductor (46), an input positive terminal switch (61), an output positive terminal switch (62), an output negative terminal switch (63), an input negative terminal switch (64), a switching switch (65), a positive terminal bridging switch (66), a positive left interconnection switch (67), a positive right interconnection switch (68), a negative left interconnection switch (69), a negative right interconnection switch (70), a negative terminal bridging switch (71), a negative terminal bridging output switch (72), and a positive terminal bridging output switch (73). The connection terminals A (81), B (82), and C (83) of the voltage conversion circuit (41) are connected to phases A, B, and C of the power supply, respectively. The connection terminal N (84) of the voltage conversion circuit (41) is connected to the neutral line of the power supply, the emitter of the output negative terminal switch (63), and the emitter of the input negative terminal switch (64), respectively. The connection terminal D (86) of the voltage conversion circuit (41) is connected to the collector of the input positive terminal switch (61) and the collector of the output positive terminal switch (62), respectively. The emitter of the input positive terminal switch (61) is connected to the emitter of the positive terminal bridge switch (66), respectively. The collector of the switching switch (65) is connected to the collector of the positive left interconnection switch (67). The emitter of the output positive terminal switch (62) is connected to the collector of the output negative terminal switch (63), one end of the output capacitor (44), and the output negative terminal (48), respectively. The collector of the positive terminal bridge switch (66) is connected to the collector of the positive terminal bridge output switch (73) and one end of the upper voltage control capacitor (42), respectively. The emitter of the positive left interconnection switch (67) is connected to the emitter of the positive right interconnection switch (68). The collector of the positive right interconnection switch (68) is connected to the other end of the upper voltage control capacitor (42) and one end of the current control inductor (45). The collector of the input negative terminal switch (64) is connected to the collector of the negative terminal bridge switch (71), the emitter of the switching switch (65), and the collector of the negative left interconnect switch (69), respectively. The emitter of the negative left interconnect switch (69) is connected to the emitter of the negative right interconnect switch (70). The collector of the negative right interconnect switch (70) is connected to one end of the lower voltage control capacitor (43) and the other end of the current control inductor (45), respectively. The emitter of the negative terminal bridge switch (71) is connected to the other end of the lower voltage control capacitor (43) and the emitter of the negative terminal bridge output switch (72), respectively. The collector of the negative terminal bridge output switch (72) is connected to the emitter of the positive terminal bridge output switch (73) and one end of the output inductor (46), respectively. The other end of the output inductor (46) is connected to the other end of the output capacitor (44) and the output positive terminal (47), respectively.

2. The arc-free circuit breaker with filtering capability for transformer substations according to claim 1, characterized in that, The voltage conversion circuit (41) includes a first power diode (85-1), a second power diode (85-2), a third power diode (85-3), a connection terminal A (81), a connection terminal B (82), a connection terminal C (83), a connection terminal D (86), and a connection terminal N (84); The negative terminals of the first power diode (85-1), the second power diode (85-2), and the third power diode (85-3) are all connected to the connection terminal D (86). The positive terminals of the first power diode (85-1), the second power diode (85-2), and the third power diode (85-3) are respectively connected to the connection terminals A (81), B (82), and C (83).

3. The arc-free circuit breaker with filtering capability for transformer substations according to claim 2, characterized in that, The input positive terminal switch (61), output positive terminal switch (62), output negative terminal switch (63), input negative terminal switch (64), switching switch (65), positive terminal bridging switch (66), positive left interconnection switch (67), positive right interconnection switch (68), negative left interconnection switch (69), negative right interconnection switch (70), negative terminal bridging switch (71), negative terminal bridging output switch (72) and positive terminal bridging output switch (73) have the same structure and include: a second IGBT driver (91) and a second IGBT (92); The second IGBT driver (91) is connected to the gates of the microprocessor (6) and the second IGBT (92), respectively.

4. The control method for a transformer substation arc-free circuit breaker with filtering capability according to any one of claims 1 to 3, characterized in that, Includes the following steps: S1. Initialization is performed through an initialization subroutine; S1 includes the following steps: S11. Set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds; S12. Set the low-frequency interrupt condition and set the low-frequency interrupt subroutine to be called when an interrupt occurs; Set the high-frequency interrupt conditions and configure the high-frequency interrupt subroutine to be called when an interrupt occurs; S13. Set variables, including: Phase A voltage phase zero degree millisecond counter, Phase A voltage phase zero degree microsecond counter, CH represents high frequency interrupt counter, value range: 0~999, VY represents trip voltage threshold, IY represents trip current threshold, BY represents compensation threshold, TZ represents trip mark, CVA represents sensor read counter, value range: 0~999, CZQ represents period counter, value range: 0~199, SUMV represents voltage summation, MINSUMV represents minimum voltage, MINSUMVG represents minimum voltage threshold, SUMI represents current summation, MAXSUMI represents maximum current, MAXSUMIG represents maximum current threshold; The array AVINA[400] represents the first reading value of phase A of voltage sensor (1), the array AVINB[400] represents the second reading value of phase A of voltage sensor (1), the array AFV[400] represents the floating-point value of phase A voltage, the array AIINA[400] represents the first reading value of phase A of current sensor (2), the array AIINB[400] represents the second reading value of phase A of current sensor (2), the array AFI[400] represents the floating-point value of phase A current, and the array AVBZ[400] represents phase A compensation; The array BVINA[400] represents the first reading value of phase B of voltage sensor (1), the array BVINB[400] represents the second reading value of phase B of voltage sensor (1), the array BFV[400] represents the floating point value of phase B voltage, the array BIINA[400] represents the first reading value of phase B of current sensor (2), the array BINB[400] represents the second reading value of phase B of current sensor (2), the array BFI[400] represents the floating point value of phase B current, and the array BVBZ[400] represents phase B compensation; The array CVINA[400] represents the first reading value of phase C of voltage sensor (1), the array CVINB[400] represents the second reading value of phase C of voltage sensor (1), the array CFV[400] represents the floating value of phase C voltage, the array CIINA[400] represents the first reading value of phase C of current sensor (2), the array CIINB[400] represents the second reading value of phase C of current sensor (2), the array CFI[400] represents the floating value of phase C current, and the array CVBZ[400] represents phase C compensation; PT represents the time update data position, FTZ represents the trip calculation variable, TZF represents the trip calculation variable, FBZ represents the compensation calculation variable, FZD represents the low frequency interruption flag, SELF represents the storage selection flag, CNTCNN represents the loop counter, startF represents the start calculation flag, AZK represents the A-phase impedance, BZK represents the B-phase impedance, CZK represents the C-phase impedance, MINZK represents the minimum impedance, ZKYZ represents the impedance trip threshold, ASUMBZ represents the A-phase compensation sum, BSUMBZ represents the B-phase compensation sum, CSUMBZ represents the C-phase compensation sum, MAXSUMBZ represents the maximum compensation sum, and BZYZ represents the compensation threshold. S14. Initialize variables. The variables to be initialized are: MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF =0, ACNTVI=0, BCNTVI=0, CCNTVI=0, CNTCNN=0, startF = 0, FZD=0; FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0; AVINA, AVINB, BVINA, BVINB, CVINA, and CVINB are initialized to all zeros; S15. Set the first parameter M1data and the comparison variable BiJiao; S2. In response to startF equaling 1, the trip and compensation calculation subroutine is called to calculate the trip criteria. S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform the tripping action.

5. The control method according to claim 4, characterized in that, In S11, the method for calling the low-frequency interrupt subroutine is as follows: A1. Determine if SELF is false. If it is, let ACDATA[i] = AVINA[i], where i = 0~799, and proceed to A2. If not, let ACDATA[i] = AVINB[i], where i = 0~799, and proceed to A2; A2. Invert SELF. In response to the condition that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero and AVINA[i+2] is greater than or equal to AVINA[i] in the range of i=2~401, let WZ=i and startF = 1.

6. The control method according to claim 5, characterized in that, In S12, the method for calling the high-frequency interrupt subroutine is as follows: B1. Determine if SELF is false. If it is, proceed to SB2. If not, then let AVINA equal the stored value of the memory corresponding to voltage sensor (1), let AIINA equal the stored value of the memory corresponding to current sensor (2), let BVINA equal the stored value of the memory corresponding to voltage sensor (1), let BIINA equal the stored value of the memory corresponding to current sensor (2), let CVINA equal the stored value of the memory corresponding to voltage sensor (1), and let CIINA equal the stored value of the memory corresponding to current sensor (2). AFV[CNTCNN] = (AVINA–32768) / 32768 AFI [CNTCNN] = (AIINA–32768) / 32768 BFV[CNTCNN] = (BVINA–32768) / 32768 BFI [CNTCNN] = (BIINA–32768) / 32768 CFV[CNTCNN] = (CVINA–32768) / 32768 CFI [CNTCNN] = (CIINA–32768) / 32768 Enter B3; B2. Let AVINB equal the stored value of the memory corresponding to voltage sensor (1), let AIINB equal the stored value of the memory corresponding to current sensor (2), let BVINB equal the stored value of the memory corresponding to voltage sensor (1), let BIINB equal the stored value of the memory corresponding to current sensor (2), let CVINB equal the stored value of the memory corresponding to current sensor (2), let CIINB equal the stored value of the memory corresponding to current sensor (2). AFV[CNTCNN] = (AVINB–32768) / 32768 AFI [CNTCNN] = (AIINB–32768) / 32768 BFV[CNTCNN] = (BVINB–32768) / 32768 BFI [CNTCNN] = ( BIINB–32768) / 32768 CFV[CNTCNN] = (CVINB–32768) / 32768 CFI[CNTCNN] = (CIINB–32768) / 32768 Enter B3; B3. Increment the value of CNTCNN by 1. In response to CNTCNN being greater than 800, set CNTCNN=0. Enter B4; B4, responding to FBZ equal to 1, proceed to B5; B5. Determine if CNTCNN is greater than WZ. If so, let WZ1 = CNTCNN - WZ. If not, then let WZ1 = 400 + CNTCNN-WZ; Enter B6; B6. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1. Enter B7; B7. Control the A-phase circuit, then proceed to B8; B8. Add 133 to the WZ value and determine whether CNTCNN is greater than WZ. If so, let WZ1 = CNTCNN - WZ. If not, then let WZ1 = 400 + CNTCNN - WZ; Enter B9; B9. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1; Enter B10; B10. Control the B-phase circuit, then proceed to B11; B11. Add 266 to the WZ value and determine whether CNTCNN is greater than WZ. If so, let WZ1 = CNTCNN - WZ. If not, then set WZ1 = 400 + CNTCNN - WZ and proceed to B12; B12. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400, and then proceed to B13. B13. Control of the C-phase circuit; The control methods for phases A, B, and C are the same, specifically as follows: If the response is greater than or equal to 0.875, then: Turn off the positive output switch (62), negative input switch (64), positive bridge switch (66), positive left interconnect switch (67), positive right interconnect switch (68), negative left interconnect switch (69), negative right interconnect switch (70) and negative bridge output switch (72); Turn on the output negative terminal switch (63), input positive terminal switch (61), switching switch (65), negative terminal bridging switch (71) and positive terminal bridging output switch (73); If the response is less than 0.875 and greater than or equal to 0.625, then: Turn off the positive output switch (62), the toggle switch (65), the positive bridge switch (66), the negative left interconnect switch (69), the negative right interconnect switch (70), and the negative bridge output switch (72); Turn on the output negative terminal switch (63), input positive terminal switch (61), input negative terminal switch (64), negative terminal bridging switch (71), positive terminal bridging output switch (73), positive left interconnection switch (67), and positive right interconnection switch (68); If the response is less than 0.625 and greater than or equal to 0.375, then: Turn on the positive output switch (62), the toggle switch (65), the positive left interconnect switch (67), and the positive right interconnect switch (68), and turn off the negative bridge output switch (72) and the negative bridge switch (71); Turn on the output negative terminal switch (63), input positive terminal switch (61), input negative terminal switch (64), positive terminal bridged output switch (73), positive terminal bridged switch (66), negative left interconnection switch (69), and negative right interconnection switch (70); If the response is less than 0.375 and greater than or equal to 0.125, then: Turn off the output negative terminal switch (63), the switching switch (65), the positive terminal bridging switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the negative terminal bridging output switch (72); Turn on the output positive terminal switch (62), input positive terminal switch (61), input negative terminal switch (64), positive left interconnection switch (67), positive right interconnection switch (68), negative terminal bridging switch (71), and positive terminal bridging output switch (73); If the response is that AVBZ[WZ1] is less than 0.125 and greater than or equal to -0.125, then: Turn off the positive output switch (62), the toggle switch (65), the positive bridge switch (66), the negative left interconnect switch (69), the negative right interconnect switch (70), and the positive bridge output switch (73); Turn on the output negative terminal switch (63), input positive terminal switch (61), input negative terminal switch (64), positive left interconnection switch (67), positive right interconnection switch (68), negative terminal bridging switch (71), and negative terminal bridging output switch (72); If the response is that AVBZ[WZ1] is less than -0.125 and greater than or equal to -0.375, then: Turn off the positive output switch (62), the toggle switch (65), the positive left interconnect switch (67), the positive right interconnect switch (68), the negative bridge switch (71), and the positive bridge output switch (73); Turn on the output negative terminal switch (63), input positive terminal switch (61), input negative terminal switch (64), positive terminal bridging switch (66), negative left interconnection switch (69), negative right interconnection switch (70), and negative terminal bridging output switch (72); If the response is that AVBZ[WZ1] is less than -0.375 and greater than or equal to -0.625, then: Turn off the output negative terminal switch (63), the switching switch (65), the positive terminal bridging switch (66), the negative left interconnection switch (69), the negative right interconnection switch (70), and the positive terminal bridging output switch (73); Turn on the output positive terminal switch (62), input positive terminal switch (61), input negative terminal switch (64), positive left interconnection switch (67), positive right interconnection switch (68), negative terminal bridging switch (71), and negative terminal bridging output switch (72); If the response is that AVBZ[WZ1] is less than -0.625 and greater than or equal to -0.875, then: Turn off the positive input switch (61), negative output switch (63), switching switch (65), positive left interconnection switch (67), positive right interconnection switch (68), negative bridge switch (71), and positive bridge output switch (73); Turn on the output positive terminal switch (62), input negative terminal switch (64), positive terminal bridging switch (66), negative left interconnection switch (69), negative right interconnection switch (70), and negative terminal bridging output switch (72); If the response is less than -0.875, then: Turn off the output negative terminal switch (63), positive left interconnection switch (67), positive right interconnection switch (68), negative left interconnection switch (69), negative right interconnection switch (70), negative terminal bridging switch (71), and positive terminal bridging output switch (73); Turn on the output positive terminal switch (62), the switching switch (65), the input positive terminal switch (61), the input negative terminal switch (64), the positive terminal bridging switch (66), and the negative terminal bridging output switch (72).

7. The control method according to claim 6, characterized in that, In S2, the method for calling the tripping and compensation calculation subroutine is as follows: S21. Calculate the following data: In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400; S22. Calculate the minimum value of SUMVA, SUMVB, and SUMVC, and assign it to MINSUMV. S23. Calculate the maximum value of SUMIA, SUMIB, and SUMIC, and assign it to MAXSUMI; S24. Determine whether either MINSUMV is less than MINSUMVG or MAXSUMI is greater than MAXSUMIG. If yes, then TZF = 1; otherwise, then TZF = 0. S25. Calculate the following data: AIBZ[i]= M1data[i] – AFI[i+WZ] In the formula, i = 0~399; WZ1=WZ+133 If WZ1 is greater than 400, then the value of WZ1 is reduced by 400. BIBZ[i]= M1data[i] – BFI[i+WZ1] WZ1=WZ+266 If WZ1 is greater than 400, then the value of WZ1 is reduced by 400. CIBZ[i]= M1data[i] – CFI[i+WZ1] S26. Calculate the following data: S27. Calculate the maximum value of ASUMZB, BSUMZB and CSUMZB, and assign it to MAXSUMBZ. Determine if MAXSUMBZ is greater than or equal to BZYZ; if yes, set FBZ=1; otherwise, set FBZ=0. In S3, the method for calling the tripping action subroutine is as follows: S31, control the first IGBT (8) to turn on, and control the mechanical circuit breaker (3) to turn off; S32, control the first IGBT (8) to turn off.

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