Method for forming a semi-floating gate structure
By leaving the dielectric layer unetched when etching the third polysilicon layer, using the dielectric layer as a hard mask, and adding a SiARC layer etching step, the problems of SiARC residue and substrate damage are solved, and the performance of the semi-floating gate device is improved.
Patent Information
- Application Number
- CN202411547752.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2044-10-31
AI Technical Summary
In the prior art, when removing the SiARC layer, residues are likely to remain and the substrate is easily damaged, which affects the performance of the semi-floating gate device.
When etching the third polysilicon layer, the dielectric layer is retained without being etched, and the dielectric layer is used as a hard mask to increase the SiARC layer etching step, thereby increasing the SiARC residue-free process window and protecting the substrate through the dielectric layer.
Effectively avoid SiARC residue, reduce substrate loss risk, and improve the performance of semi-floating gate devices.
Smart Images
Figure CN119400696B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semi-floating gate structure. Background Art
[0002] Semi-floating gate devices have the advantages of fast read and write speeds and do not require capacitor devices. Therefore, they have great potential to replace DRAM (dynamic random access memory). At present, the 28nm semi-floating gate platform developed by the company has a triple gate structure with a layer of floating gate (poly1) and two layers of control gate (poly2 / poly3). By building a double control gate, the write and read operations of the device can be controlled at the same time, and the poly3 process is fully compatible with the existing 28HK logic manufacturing process platform. However, the triple gate structure also poses new challenges to process development. Among them, after the Poly3 etching is completed (such as Figure 1 As shown), it is necessary to cut the middle of poly1 and poly2 through a graphic process to form an isolation groove pattern (as shown Figure 3 As shown), compared with the existing 28HK logic process, poly2 and poly3 are thinner, and although the SiARC layer is consumed during the etching process (as shown Figure 2 As shown in the figure, the SiARC is consumed less, which may easily cause SiARC residue or a smaller SiARC process window. In addition, the area that does not need to be cut off is directly covered with SOC on the Si surface during the etching process. When O2Asher is removed during poly2 etching, the oxide layer formed in the active area AA will produce a near The loss of the contact resistance increases, hindering the migration of carriers in the channel and seriously affecting the subsequent device performance. Summary of the Invention
[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for forming a semi-floating gate structure, so as to solve the problem that residues are easily left when removing the SiARC layer and the substrate is easily damaged.
[0004] To achieve the above-mentioned and other related objectives, the present invention provides a method for forming a semi-floating gate structure, the method comprising:
[0005] Step 1) providing a semiconductor structure comprising a substrate divided into a gate region and an active region, a gate stack structure formed on the substrate in the gate region, a first oxide layer formed on the sidewalls and surface of the gate stack structure and the active region, and a dielectric layer formed on the surface of the first oxide layer, wherein the gate stack structure comprises, from bottom to top, a first polysilicon layer, an intergate dielectric layer, and a second polysilicon layer;
[0006] Step 2) forming a third polysilicon layer on the surface of the semiconductor structure;
[0007] Step 3) etching the third polysilicon layer formed above the second polysilicon layer until the dielectric layer is exposed to form a first opening, and removing the third polysilicon layer formed in the active area, wherein the width of the first opening is smaller than the width of the gate stack structure, and the third polysilicon layer on both sides of the first opening covers both sidewalls of the gate stack structure;
[0008] Step 4) forming a SOC layer on the surface of the semiconductor structure formed in step 3), wherein the SOC layer fills the first opening and extends above the third polysilicon layer;
[0009] Step 5) forming a SiARC layer on the surface of the SOC layer;
[0010] Step 6) etching the SiARC layer and the SOC layer thereunder until the dielectric layer is exposed to form a second opening, wherein the etched SOC layer is the SOC layer filling the first opening, and the width of the formed second opening is smaller than the width of the first opening;
[0011] Step 7) removing the SiARC layer;
[0012] Step 8) etching the dielectric layer, the first oxide layer, the second polysilicon layer, the inter-gate dielectric layer, and the first polysilicon layer along the second opening;
[0013] Step 9) removing the SOC layer to expose the dielectric layer covered by the SOC layer;
[0014] Step 10) etching and removing the exposed dielectric layer.
[0015] Optionally, the dielectric layer includes a high-K dielectric layer and a titanium nitride layer, and the titanium nitride layer is formed on a surface of the high-K dielectric layer.
[0016] Optionally, the first polysilicon layer is formed in the substrate and extends to the surface of the substrate, and the first polysilicon layer formed in the substrate and the first polysilicon layer extending to the surface of the substrate are in a T-shaped structure.
[0017] Optionally, a gate oxide layer is formed between the first polysilicon layer and the substrate.
[0018] Optionally, the method for performing step 3) includes:
[0019] forming a hard mask layer on a surface of the third polysilicon layer and performing patterning on the hard mask layer;
[0020] The third polysilicon layer is etched using the patterned hard mask layer as a mask.
[0021] Optionally, the hard mask layer includes a silicon nitride layer and an oxide layer, and the oxide layer is formed on a surface of the silicon nitride layer.
[0022] Optionally, since the hard mask layer is retained after patterned etching, in step 4), the SOC layer is formed on the surface of the hard mask layer when extending to above the third polysilicon layer.
[0023] Optionally, the method of performing step 6) includes:
[0024] forming a photoresist layer on the surface of the SiARC layer, and performing patterning on the photoresist layer;
[0025] The SiARC layer and the SOC layer are etched using the patterned photoresist layer as a mask to form the second opening.
[0026] Optionally, the substrate is a silicon substrate.
[0027] Optionally, the material of the inter-gate dielectric layer includes silicon oxide.
[0028] Optionally, applicable technology nodes include 28nm.
[0029] As described above, in the method for forming a semi-floating gate structure of the present invention, when etching the third polysilicon layer (for forming the second control gate), the dielectric layer (high-K dielectric layer and titanium nitride layer) is retained without being etched. After the etching of the SOC layer is completed, the dielectric layer is used as a hard mask to add a step of etching the SiARC layer to consume the SiARC layer, thereby increasing the process window for leaving no SiARC residue. Moreover, the dielectric layer formed in the active area can protect the substrate when removing the SOC layer, thereby reducing the risk of substrate loss. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 Shown is a schematic diagram of the cross-sectional structure of a semiconductor structure after existing poly3 etching.
[0031] Figure 2 It shows a schematic cross-sectional structure diagram of a semiconductor structure with a SiARC layer formed before conventional poly2 etching.
[0032] Figure 3 Shown is a schematic diagram of the cross-sectional structure of a semiconductor structure after existing poly2 etching.
[0033] Figure 4 An electron microscope image of a conventional semiconductor structure with SiARC residues is shown.
[0034] Figures 5 to 10It is a schematic cross-sectional structural diagram of the process of forming a semi-floating gate structure according to the present invention.
[0035] Figure 11 Shown is a flow chart of a method for forming a semi-floating gate structure according to the present invention.
[0036] Explanation of Figure Numbers
[0037] 10: semiconductor structure; 11: substrate; 12: gate stack structure; 121: first polysilicon layer; 122: intergate dielectric layer; 123: second polysilicon layer; 13: first oxide layer; 14: dielectric layer; 141: high-k dielectric layer; 142: titanium nitride layer; 20: third polysilicon layer; 31: first opening; 32: second opening; 40: SOC layer; 50: SiARC layer; 60: hard mask layer; 61: silicon nitride layer; 62: oxide layer; 70: photoresist layer DETAILED DESCRIPTION
[0038] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] See also Figures 1 to 11 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.
[0040] like Figure 11 As shown, this embodiment provides a method for forming a semi-floating gate structure, the method comprising:
[0041] Step 1) providing a semiconductor structure 10, comprising a substrate 11 divided into a gate region and an active region, a gate stack structure 12 formed on the substrate 11 in the gate region, a first oxide layer 13 formed on the sidewalls and surface of the gate stack structure 12 and in the active region, and a dielectric layer 14 formed on the surface of the first oxide layer 13, wherein the gate stack structure 12 comprises, from bottom to top, a first polysilicon layer 121, an intergate dielectric layer 122, and a second polysilicon layer 123;
[0042] Step 2) forming a third polysilicon layer 20 on the surface of the semiconductor structure 10;
[0043] Step 3) etching the third polysilicon layer 20 formed on the second polysilicon layer 123 until the dielectric layer 14 is exposed to form a first opening 31, and removing the third polysilicon layer 20 formed in the active area, wherein the width of the first opening 31 is smaller than the width of the gate stack structure 12, and the third polysilicon layer 20 on both sides of the first opening 31 covers both side walls of the gate stack structure 12;
[0044] Step 4) forming a SOC layer 40 on the surface of the semiconductor structure formed in step 3), wherein the SOC layer 40 fills the first opening 31 and extends above the third polysilicon layer 20;
[0045] Step 5) forming a SiARC layer 50 on the surface of the SOC layer 40;
[0046] Step 6) etching the SiARC layer 50 and the SOC layer 40 thereunder until the dielectric layer 14 is exposed to form a second opening 32, wherein the etched SOC layer 40 is the SOC layer 40 filling the first opening 31, and the width of the formed second opening 32 is smaller than the width of the first opening 31;
[0047] Step 7) removing the SiARC layer 50;
[0048] Step 8) etching the dielectric layer 14, the first oxide layer 13, the second polysilicon layer 123, the inter-gate dielectric layer 122 and the first polysilicon layer 121 along the second opening 32;
[0049] Step 9) removing the SOC layer 40 to expose the dielectric layer 14 covered by the SOC layer 40;
[0050] Step 10) etching and removing the exposed dielectric layer 14.
[0051] Specifically, applicable technology nodes include 28nm.
[0052] The following is combined with Figure 5 ~Attached Figure 10 The method for forming the semi-floating gate structure provided in this embodiment is described in detail.
[0053] like Figure 5As shown, in step 1), a semiconductor structure 10 is provided, which includes a substrate 11 divided into a gate region and an active region, a gate stack structure 12 formed on the substrate 11 in the gate region, a first oxide layer 13 formed on the sidewalls, surface and active region of the gate stack structure 12, and a dielectric layer 14 formed on the surface of the first oxide layer 13, wherein the gate stack structure 12 includes a first polysilicon layer 121, an inter-gate dielectric layer 122 and a second polysilicon layer 123 stacked from bottom to top.
[0054] Specifically, the substrate 11 is a silicon substrate.
[0055] Specifically, the material of the inter-gate dielectric layer 122 includes silicon oxide.
[0056] Specifically, the dielectric layer 14 includes a high-K dielectric layer 141 and a titanium nitride layer 142 , and the titanium nitride layer 142 is formed on the surface of the high-K dielectric layer 141 .
[0057] Specifically, the first polysilicon layer 121 is formed in the substrate 11 and extends to the surface of the substrate 11 , and the first polysilicon layer 121 formed in the substrate 11 and the first polysilicon layer 121 extending to the surface of the substrate 11 are in a T-shaped structure.
[0058] Specifically, a gate oxide layer is formed between the first polysilicon layer 121 and the substrate 11. It should be noted that in this embodiment, the gate oxide layer is not shown.
[0059] like Figure 5 As shown, in step 2), a third polysilicon layer 20 is formed on the surface of the semiconductor structure 10 .
[0060] like Figure 6 As shown, in step 3), the third polysilicon layer 20 formed above the second polysilicon layer 123 is etched until the dielectric layer 14 is exposed to form a first opening 31, and the third polysilicon layer 20 formed in the active area is removed, wherein the width of the first opening 31 is smaller than the width of the gate stack structure 12, and the third polysilicon layer 20 on both sides of the first opening 31 covers the two side walls of the gate stack structure 12.
[0061] Specifically, the method of performing step 3) includes: forming a hard mask layer 60 on the surface of the third polysilicon layer 20 and patterning the hard mask layer 60; and etching the third polysilicon layer 20 using the patterned hard mask layer 60 as a mask.
[0062] More specifically, the hard mask layer 60 includes a silicon nitride layer 61 and an oxide layer 62 , and the oxide layer 62 is formed on the surface of the silicon nitride layer 61 .
[0063] like Figure 7 As shown, in step 4), a SOC layer 40 is formed on the surface of the semiconductor structure formed in step 3), wherein the SOC layer 40 fills the first opening 31 and extends to above the third polysilicon layer 20 .
[0064] Specifically, since the hard mask layer 60 is retained after patterned etching, in step 3), the SOC layer 40 is formed on the surface of the hard mask layer 60 when extending to above the third polysilicon layer 20 .
[0065] In this embodiment, the SOC layer 40 is formed on the surface of the oxide layer 62 when extending to above the third polysilicon layer 20 .
[0066] like Figure 7 As shown, in step 5), a SiARC layer 50 is formed on the surface of the SOC layer 40 .
[0067] like Figure 8 As shown, in step 6), the SiARC layer 50 and the SOC layer 40 thereunder are etched until the dielectric layer 14 is exposed to form a second opening 32, wherein the etched SOC layer 40 is the SOC layer 40 filling the first opening 31, and the width of the formed second opening 32 is smaller than the width of the first opening 31.
[0068] Specifically, the method of performing step 6) includes: forming a photoresist layer 70 on the surface of the SiARC layer 50 and patterning the photoresist layer 70; and etching the SiARC layer 50 and the SOC layer 40 using the patterned photoresist layer 70 as a mask to form the second opening 32.
[0069] In step 7), the SiARC layer 50 is removed.
[0070] In this embodiment, by adding the step of removing the SiARC layer 50 , the SiARC residue-free process window can be expanded.
[0071] like Figure 9 As shown, in step 8), the dielectric layer 14 , the first oxide layer 13 , the second polysilicon layer 123 , the inter-gate dielectric layer 122 and the first polysilicon layer 121 are etched along the second opening 32 .
[0072] like Figure 10 As shown, in step 9), the SOC layer 40 is removed to expose the dielectric layer 14 covered by the SOC layer 40 .
[0073] In this embodiment, when the SOC layer 40 is removed, the dielectric layer 14 in the active area plays a role in protecting the substrate silicon, thereby reducing the risk of damage to the active area.
[0074] In step 10), the exposed dielectric layer 14 is removed by etching.
[0075] In summary, the method for forming a semi-floating gate structure of the present invention leaves the dielectric layer (high-K dielectric layer and titanium nitride layer) unetched during etching of the third polysilicon layer (used to form the second control gate). Furthermore, after etching the SOC layer, the dielectric layer is used as a hard mask to add a step of etching the SiARC layer, thereby increasing the process window for leaving no SiARC residue. Furthermore, the dielectric layer formed in the active area protects the substrate during removal of the SOC layer, thereby reducing the risk of substrate damage. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A method for forming a semi-floating gate structure, characterized in that: The method comprises: Step 1) providing a semiconductor structure, comprising a substrate divided into a gate region and an active region, a gate stack structure formed on the substrate in the gate region, a first oxide layer formed on the sidewalls and surface of the gate stack structure and the active region, and a dielectric layer formed on the surface of the first oxide layer, the dielectric layer being isolated by the first oxide layer and also located on the sidewalls, surface, and active region of the gate stack structure; wherein the gate stack structure comprises, stacked from bottom to top, a first polysilicon layer, an intergate dielectric layer, and a second polysilicon layer; Step 2) forming a third polysilicon layer on the surface of the semiconductor structure; Step 3) etching the third polysilicon layer formed above the second polysilicon layer until the dielectric layer is exposed to form a first opening, and removing the third polysilicon layer formed in the active area, wherein the width of the first opening is smaller than the width of the gate stack structure, and the third polysilicon layer on both sides of the first opening covers both sidewalls of the gate stack structure; Step 4) forming a SOC layer on the surface of the semiconductor structure formed in step 3), wherein the SOC layer fills the first opening and extends above the third polysilicon layer; Step 5) forming a SiARC layer on the surface of the SOC layer; Step 6) etching the SiARC layer and the SOC layer thereunder until the dielectric layer is exposed to form a second opening, wherein the etched SOC layer is the SOC layer filling the first opening, and the width of the formed second opening is smaller than the width of the first opening; Step 7) removing the SiARC layer; Step 8) etching the dielectric layer, the first oxide layer, the second polysilicon layer, the inter-gate dielectric layer, and the first polysilicon layer along the second opening; Step 9) removing the SOC layer to expose the dielectric layer covered by the SOC layer; Step 10) etching and removing the exposed dielectric layer.
2. The method for forming a semi-floating gate structure according to claim 1, wherein: The dielectric layer includes a high-K dielectric layer and a titanium nitride layer, and the titanium nitride layer is formed on the surface of the high-K dielectric layer.
3. The method for forming a semi-floating gate structure according to claim 1, wherein: The first polysilicon layer is formed in the substrate and extends to the surface of the substrate, and the first polysilicon layer formed in the substrate and the first polysilicon layer extending to the surface of the substrate form a T-shaped structure.
4. The method for forming a semi-floating gate structure according to claim 3, wherein: A gate oxide layer is formed between the first polysilicon layer and the substrate.
5. The method for forming a semi-floating gate structure according to claim 1, wherein: Methods for performing step 3) include: forming a hard mask layer on a surface of the third polysilicon layer and performing patterning on the hard mask layer; The third polysilicon layer is etched using the patterned hard mask layer as a mask.
6. The method for forming a semi-floating gate structure according to claim 5, wherein: The hard mask layer includes a silicon nitride layer and an oxide layer, and the oxide layer is formed on the surface of the silicon nitride layer.
7. The method for forming a semi-floating gate structure according to claim 5, wherein: Since the hard mask layer is retained after patterned etching, in step 4), the SOC layer is formed on the surface of the hard mask layer when extending to above the third polysilicon layer.
8. The method for forming a semi-floating gate structure according to claim 1, wherein: Methods for performing step 6) include: forming a photoresist layer on the surface of the SiARC layer, and performing patterning on the photoresist layer; The SiARC layer and the SOC layer are etched using the patterned photoresist layer as a mask to form the second opening.
9. The method for forming a semi-floating gate structure according to claim 1, wherein: The substrate is a silicon substrate.
10. The method for forming a semi-floating gate structure according to claim 1, wherein: The material of the inter-gate dielectric layer includes silicon oxide.
11. The method for forming a semi-floating gate structure according to claim 1, wherein: Applicable technology nodes include 28nm.