A single island packaging structure and method for asynchronous buck chip

Abstract

The invention discloses an asynchronous buck chip single-base island packaging structure and method, comprising a lead frame, a single-base island, an integrated control circuit wafer, a silicon wafer, a ceramic patch capacitor, a laminated patch inductor and a Schottky diode. The single-base island and a plurality of pins are arranged on the lead frame, the single-base island is divided into a first chip area and a second chip area, the integrated control circuit wafer is placed on the first chip area, the silicon wafer is placed on the second chip area, the ceramic patch capacitor and the laminated patch inductor are bonded and connected to each other and are respectively placed on the silicon wafer, and the Schottky diode is placed on the silicon wafer, thereby reducing the number of components on a circuit board, reducing the circuit board area, and reducing the manufacturing cost and the difficulty of PCB debugging.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a single-base island packaging structure and method for an asynchronous buck chip. Background Art

[0002] The asynchronous Buck circuit is a common switch mode power supply topology used to convert the input voltage into a stable output voltage lower than the input voltage. It is usually used in power conversion and voltage regulation. With the advancement of semiconductor technology and the development of power electronics, the application of asynchronous Buck circuits has become increasingly widespread.

[0003] Taking LED drive asynchronous Buck circuit as an example, it is usually built with driver chip and integrated control circuit wafer, inductor, capacitor, and packaged Schottky diode and resistor. However, the above method significantly increases the number of components on the circuit board, increases the circuit board area, increases the production cost and the difficulty of PCB debugging. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the current semiconductor packaging field, the present invention provides an asynchronous buck chip single-base island packaging structure and method, which divides the single-base island into a first chip area and a second chip area, places an integrated control circuit wafer on the first chip area, places a silicon wafer on the second chip area, bonds and connects ceramic chip capacitors and stacked chip inductors to each other and places them on the silicon wafer respectively, and places a Schottky diode on the silicon wafer, thereby reducing the number of components on the circuit board, reducing the circuit board area, and reducing the production cost and the difficulty of PCB debugging.

[0005] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0006] An asynchronous buck chip single base island packaging structure, comprising:

[0007] A lead frame, comprising a single base island and a plurality of pins, wherein the single base island comprises a first chip area and a second chip area;

[0008] An integrated control circuit wafer is placed in the first chip area, and a first conductive medium is provided between the integrated control circuit wafer and the first chip area;

[0009] A silicon wafer is placed in the second chip area, one side of the silicon wafer is set as a conductive metal layer, and the other side is set as a silicon surface, a first insulating medium is provided between the silicon surface and the second chip area, and a ceramic chip capacitor, a stacked chip inductor and a Schottky diode are also provided on the conductive metal layer;

[0010] The plastic package is used to encapsulate the lead frame, the integrated control circuit wafer, the silicon chip, the ceramic chip capacitor, the stacked chip inductor and the Schottky diode.

[0011] According to one aspect of the present invention, the lead frame includes a power input pin, a signal feedback pin, a power ground pin and a switch output pin, and the positions of the power input pin, signal feedback pin, power ground pin and switch output pin on the lead frame are not fixed.

[0012] According to one aspect of the present invention, it also includes an external capacitor, one end of which is grounded, and the other end of which is connected to the switch output pin of the lead frame.

[0013] According to one aspect of the present invention, it also includes a first feedback resistor and a second feedback resistor, one end of the first feedback resistor is connected to the switch output pin of the lead frame, and the other end is connected to one end of the second feedback resistor, the other end of the second feedback resistor is grounded, and the connection point of the first feedback resistor and the second feedback resistor is connected to the signal feedback pin of the lead frame.

[0014] According to one aspect of the present invention, the ceramic chip capacitor includes a first capacitor terminal and a second capacitor terminal, and a second insulating medium is provided between the ceramic chip capacitor and the conductive metal layer; the stacked chip inductor includes a first inductor terminal and a second inductor terminal, and a third insulating medium is provided between the stacked chip inductor and the conductive metal layer, and the second inductor terminal and the first capacitor terminal are bonded; the Schottky diode includes a top anode, a bottom cathode and a semiconductor, and a second conductive medium is provided between the Schottky diode and the conductive metal layer.

[0015] According to one aspect of the present invention, the power ground pin is bonded to the single base island and to the top anode of the Schottky diode; the switch output pin of the lead frame is bonded to the first inductor terminal of the stacked chip inductor.

[0016] According to one aspect of the present invention, the integrated control circuit wafer includes a power input VIN terminal, a switch output SW terminal, a bootstrap BST terminal, a power ground GND terminal and a signal feedback FB terminal.

[0017] According to one aspect of the present invention, the power input VIN terminal of the integrated control circuit wafer is bonded to the power input pin of the lead frame; the switch output SW terminal is bonded to the bottom cathode of the Schottky diode and the second inductor terminal of the stacked chip inductor; the bootstrap BST terminal is bonded to the second capacitor terminal of the ceramic chip capacitor; the signal feedback FB terminal is bonded to the signal feedback pin of the lead frame; and the power ground GND terminal is bonded to the power ground pin of the lead frame.

[0018] According to one aspect of the present invention, the back side of the single base island extends through the plastic package body and is provided with a heat dissipation pad structure.

[0019] A single-island packaging method for an asynchronous buck chip, comprising:

[0020] Arrange a single base island and pins of a lead frame, and divide the single base island into a first chip area and a second chip area;

[0021] A first conductive medium is disposed on the first chip region, and a first insulating medium is disposed on the second chip region;

[0022] An integrated control circuit wafer is arranged on the first conductive medium;

[0023] A silicon wafer is provided, one side of the silicon wafer is a conductive metal layer, and the other side is a silicon surface, the silicon surface is attached to the first insulating medium, and a ceramic chip capacitor, a stacked chip inductor and a Schottky diode are provided on the conductive metal layer;

[0024] Bonding the integrated control circuit wafer to the silicon wafer, the stacked chip inductor, and the ceramic chip capacitor respectively;

[0025] Bonding the pins of the lead frame to the integrated control circuit wafer, the single base island, the stacked chip inductor and the Schottky diode respectively;

[0026] The lead frame, the integrated control circuit wafer, the silicon chip, the ceramic chip capacitor, the stacked chip inductor and the Schottky diode are wrapped with a plastic package.

[0027] The advantages of the implementation of the present invention are as follows: by arranging a single base island and a plurality of pins on a lead frame, the single base island is divided into a first chip area and a second chip area, an integrated control circuit wafer is placed on the first chip area, a silicon wafer is placed on the second chip area, a ceramic chip capacitor and a stacked chip inductor are bonded and connected to each other and are placed on the silicon wafer respectively, and a Schottky diode is placed on the silicon wafer, thereby reducing the number of components on the circuit board, reducing the circuit board area, and reducing the production cost and the difficulty of debugging the PCB. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A circuit structure diagram of a single island packaging structure and method for an asynchronous buck chip according to the present invention;

[0030] Figure 2 A packaging diagram of a single-island packaging structure and method for an asynchronous buck chip according to the present invention;

[0031] Figure 3 A framework diagram of a single-island packaging structure and method for an asynchronous buck chip according to the present invention;

[0032] Figure 4 It is a vertical cross-sectional view of a portion of an asynchronous buck chip single island packaging structure and method described in the present invention.

[0033] Description of reference numerals:

[0034] 111. Power input pin VIN; 112. Single base island; 113. Signal feedback pin FB; 114. Power ground pin GND; 115. Switch output pin VOUT; 121. First conductive medium; 201. Silicon wafer; 202. Third insulating medium; 203. First inductor terminal; 204. Multilayer chip inductor; 205. Second inductor terminal; 206. First capacitor terminal; 207. Ceramic chip capacitor; 208. Second capacitor terminal; 209. Second insulating medium; 210. Schottky diode; 211. Second conductive medium; 212. First insulating medium; 220. Conductive metal layer; 221. Silicon surface; 222. Top anode; 223. Semiconductor; 224. Bottom cathode; 301. Plastic package; 302. Lead frame; 340. Integrated control circuit wafer. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] Embodiment 1:

[0037] like Figures 1 to 4As shown, an asynchronous buck chip single base island packaging structure includes: a lead frame 302, an integrated control circuit wafer 340, a silicon chip 201, a ceramic chip capacitor 207, a stacked chip inductor 204, a Schottky diode 210 and a plastic package 301. The lead frame 302 at least includes a single base island 112, a power input pin 111, a signal feedback pin 113, a power ground pin 114 and a switch output pin 115. The positions of the power input pin 111, the signal feedback pin 113, the power ground pin 114 and the switch output pin 115 on the lead frame 302 are not fixed, and the single base island 112 is bonded to the power ground pin 114. The single base island 112 is a power ground base island, and the single base island 112 includes a first chip area and a second chip area. The integrated control circuit wafer 340 is placed on the first chip area through the first conductive medium 121, including the power input VIN terminal, the switch output SW terminal, the bootstrap BST terminal, the power ground GND terminal and the signal feedback FB terminal. The silicon wafer 201 is placed on the second chip area through the first insulating medium 212, including the conductive metal layer 220 as the front side and the silicon surface 221 as the back side. For example, one side of the single crystal silicon can be plated with titanium, nickel and silver from the inside to the outside, and the silicon surface 221 is placed on the first insulating medium 212. The silicon wafer 201 is provided with a ceramic chip capacitor 207, a stacked chip inductor 204 and a Schottky diode 210. The ceramic chip capacitor 207 is placed on the conductive metal layer 220 of the silicon wafer 201 through the second insulating medium 209, and is indirectly placed on the single base island 112 of the lead frame 302, including a first capacitor terminal 206 and a second capacitor terminal 208. The stacked chip inductor 204 is placed on the conductive metal layer 220 of the silicon wafer 201 through the third insulating medium 202, and is indirectly placed on the single base island 112 of the lead frame 302, including a first inductor terminal 203 and a second inductor terminal 205. The Schottky diode 210 is placed on the conductive metal layer 220 of the silicon wafer 201 through the second conductive medium 211, and is indirectly placed on the single base island 112 of the lead frame 302. The Schottky diode 210 is a vertical structure, including a top anode 222, a semiconductor 223 and a bottom cathode 224 installed from top to bottom, the top anode 222 is located at the top of the vertical Schottky diode 210 structure, and the bottom cathode 224 is located at the bottom of the vertical Schottky diode 210 structure. The plastic package 301 is used to encapsulate the lead frame 302, the integrated control circuit wafer 340, the silicon chip 201, the ceramic chip capacitor 207, the stacked chip inductor 204 and the Schottky diode 210. The power input pin 111, the signal feedback pin 113, the power ground pin 114 and the switch output pin 115 extend to the outside along the side of the plastic package 301. A heat dissipation pad structure is provided at the back of the single base island 112 extending through the plastic package 301.The second inductor terminal 205 of the multilayer chip inductor 204 is bonded to the first capacitor terminal 206 of the ceramic chip capacitor 207. The first inductor terminal 203 of the multilayer chip inductor 204 is bonded to the switch output pin 115 of the lead frame 302.

[0038] The first conductive medium 121 and the second conductive medium 211 include materials in the field of semiconductor packaging that can connect two objects and conduct electricity under certain conditions, such as conductive epoxy resin, conductive wafer adhesive film, solder paste and other materials. In this example, the first conductive medium 121 and the second conductive medium 211 can be the same or different types of conductive materials. The first insulating medium 212, the second insulating medium 209 and the third insulating medium 202 include materials in the field of semiconductor packaging that can connect two objects and insulate under certain conditions, such as insulating epoxy resin, insulating wafer adhesive film and other materials. In this example, the first insulating medium 212, the second insulating medium 209 and the third insulating medium 202 can be the same or different types of insulating mediums, and the thickness and insulation performance of the insulating medium can withstand large voltages.

[0039] The power input VIN end of the integrated control circuit wafer 340 is bonded to the power input pin 111 of the lead frame 302; the switch output SW end of the integrated control circuit wafer 340 is connected to the bottom cathode 224 of the Schottky diode 210, and the corresponding switch output SW end of the integrated control circuit wafer 340 is bonded to the conductive metal layer 220 on the front side of the silicon wafer 201. As mentioned above, the bottom cathode 224 of the Schottky diode 210 is conductively connected to the front side 220 of the silicon wafer 201 through the second conductive medium 211, so the bonding of the SW end of the integrated control circuit wafer 340 to the conductive metal layer 220 on the front side of the silicon wafer 201 and the bonding of the switch output SW end of the integrated control circuit wafer 340 to the bottom cathode 224 of the Schottky diode 210 have the same effect. At the same time, the switch output SW terminal of the integrated control circuit wafer 340 is bonded to the second inductor terminal 205 of the stacked chip inductor 204. Because the second inductor terminal 205 of the stacked chip inductor 204 and the first capacitor terminal 206 of the ceramic chip capacitor 207 are bonded to each other, the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the second inductor terminal 205 of the stacked chip inductor 204 and the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the first capacitor terminal 206 of the ceramic chip capacitor 207 have the same effect; the bootstrap BST terminal is bonded to the second capacitor terminal 208 of the ceramic chip capacitor 207; the signal feedback FB terminal is bonded to the signal feedback pin 113 of the lead frame 302; and the power ground GND terminal is bonded to the power ground pin 114 of the lead frame 302.

[0040] The top anode 222 of the Schottky diode 210 is bonded to the power ground pin 114 of the package frame 302, and is indirectly connected to the power ground GND terminal of the integrated control circuit wafer 340. The bottom cathode 224 of the Schottky diode 210 is electrically connected to the conductive metal layer 220 on the front side of the silicon wafer 201 through the second conductive medium 211, so it is indirectly electrically connected to the switch output SW terminal of the integrated control circuit wafer 340.

[0041] It also includes an external capacitor, a first feedback resistor and a second feedback resistor. One end of the external capacitor is grounded, and the other end is connected to the switch output pin 115 of the lead frame 302. One end of the first feedback resistor is connected to the switch output pin 115 of the lead frame 302, and the other end is connected to one end of the second feedback resistor, the other end of the second feedback resistor is grounded, and the connection point of the first feedback resistor and the second feedback resistor is connected to the signal feedback pin 113 of the lead frame 302.

[0042] The advantages of the implementation of the present invention are as follows: by arranging a single base island and a plurality of pins on a lead frame, the single base island is divided into a first chip area and a second chip area, an integrated control circuit wafer is placed on the first chip area, a silicon wafer is placed on the second chip area, a ceramic chip capacitor and a stacked chip inductor are bonded and connected to each other and are placed on the silicon wafer respectively, and a Schottky diode is placed on the silicon wafer, thereby reducing the number of components on the circuit board, reducing the circuit board area, and reducing the production cost and the difficulty of debugging the PCB.

[0043] Embodiment 2:

[0044] like Figures 1 to 4 As shown, a single-base island packaging method for an asynchronous buck chip includes:

[0045] S1: Arrange the single base island 112 and the pins of the lead frame 302, and divide the single base island 112 into a first chip area and a second chip area.

[0046] S2: A first conductive medium 121 is disposed on the first chip region, and a first insulating medium 212 is disposed on the second chip region.

[0047] S3: An integrated control circuit wafer 340 is disposed on the first conductive medium 121 .

[0048] The integrated control circuit wafer 340 is placed on the first chip area through the first conductive medium 121 .

[0049] S4: A silicon wafer 201 is provided, one side of the silicon wafer 201 is a conductive metal layer 220 , and the other side is a silicon surface 221 . The silicon surface 221 is attached to the first insulating medium 212 . A ceramic chip capacitor 207 , a stacked chip inductor 204 , and a Schottky diode 210 are provided on the conductive metal layer 220 .

[0050] The silicon wafer 201 includes a conductive metal layer 220 as the front side and a silicon surface 221 as the back side. For example, titanium, nickel and silver can be plated on one side of a single crystal silicon from the inside to the outside, respectively. The silicon surface 221 is connected to the first insulating medium 212. The silicon wafer 201 is placed on the second chip area through the first insulating medium 212, and the ceramic chip capacitor 207 and the stacked chip inductor 204 are placed on the silicon wafer 201 through the second insulating medium 209 and the third insulating medium 202, respectively. The ceramic chip capacitor 207 and the stacked chip inductor 204 are bonded and connected to each other; the Schottky diode 210 is placed on the silicon wafer 201 through the second conductive medium 211.

[0051] The ceramic chip capacitor 207 is placed on the conductive metal layer 220 of the silicon wafer 201 through the second insulating medium 209, and is indirectly placed on the single base island 112 of the lead frame 302, including a first capacitor terminal 206 and a second capacitor terminal 208. The stacked chip inductor 204 is placed on the conductive metal layer 220 of the silicon wafer 201 through the third insulating medium 202, and is indirectly placed on the single base island 112 of the lead frame 302, including a first inductor terminal 203 and a second inductor terminal 205. Among them, the Schottky diode 210 is placed on the conductive metal layer 220 of the silicon wafer 201 through the second conductive medium 211, and is indirectly placed on the single base island 112 of the lead frame 302. The Schottky diode 210 is a vertical structure, including a top anode 222, a semiconductor 223 and a bottom cathode 224 installed from top to bottom. The top anode 222 refers to the top of the vertical Schottky diode 210 structure, and the bottom cathode 224 refers to the bottom of the vertical Schottky diode 210 structure.

[0052] The order of steps S3 and S4 can be interchanged.

[0053] S5: Bonding and connecting the integrated control circuit wafer 340 to the silicon wafer 201 , the multilayer chip inductor 204 , and the ceramic chip capacitor 207 , respectively.

[0054] The integrated control circuit wafer 340 includes a power input VIN terminal, a switch output SW terminal, a bootstrap BST terminal, a power ground GND terminal and a signal feedback FB terminal.

[0055] S6: bonding the pins of the lead frame 302 to the integrated control circuit wafer 340 , the single base island 112 , the stacked chip inductor 204 and the Schottky diode 210 , respectively.

[0056] The lead frame 302 further includes a power input pin 111, a signal feedback pin 113, a power ground pin 114, and a switch output pin 115. The positions of the power input pin 111, the signal feedback pin 113, the power ground pin 114, and the switch output pin 115 on the lead frame 302 are not fixed. The single base island 112 is bonded to the power ground pin 114. The single base island 112 of the lead frame 302 is a power ground base island. The second inductor terminal 205 of the stacked chip inductor 204 is bonded to the first capacitor terminal 206 of the ceramic chip capacitor 207. The first inductor terminal 203 of the stacked chip inductor 204 is bonded to the switch output pin 115 of the lead frame 302.

[0057] The order of steps S5 and S6 can be interchanged.

[0058] S7: Wrap the lead frame 302 , the integrated control circuit wafer 340 , the silicon wafer 201 , the ceramic chip capacitor 207 , the stacked chip inductor 204 and the Schottky diode 210 with a plastic package 301 .

[0059] The power input pin 111, signal feedback pin 113, power ground pin 114 and switch output pin 115 extend to the outside along the side of the plastic package 301. A heat dissipation pad structure is provided on the back of the single base island 112 where it extends through the plastic package 301.

[0060] The first conductive medium 121 and the second conductive medium 211 include materials in the field of semiconductor packaging that can connect two objects and conduct electricity under certain conditions, such as conductive epoxy resin, conductive wafer adhesive film, solder paste and other materials. In this example, the first conductive medium 121 and the second conductive medium 211 can be the same or different types of conductive materials. The first insulating medium 212, the second insulating medium 209 and the third insulating medium 202 include materials in the field of semiconductor packaging that can connect two objects and insulate under certain conditions, such as insulating epoxy resin, insulating wafer adhesive film and other materials. In this example, the first insulating medium 212, the second insulating medium 209 and the third insulating medium 202 can be the same or different types of insulating mediums, and the thickness and insulation performance of the insulating medium can withstand large voltages.

[0061] The power input VIN end of the integrated control circuit wafer 340 is bonded to the power input pin 111 of the lead frame 302; the switch output SW end of the integrated control circuit wafer 340 is connected to the bottom cathode 224 of the Schottky diode 210, and the corresponding switch output SW end of the integrated control circuit wafer 340 is bonded to the conductive metal layer 220 on the front side of the silicon wafer 201. As mentioned above, the bottom cathode 224 of the Schottky diode 210 is conductively connected to the front side 220 of the silicon wafer 201 through the second conductive medium 211, so the bonding of the SW end of the integrated control circuit wafer 340 to the conductive metal layer 220 on the front side of the silicon wafer 201 and the bonding of the switch output SW end of the integrated control circuit wafer 340 to the bottom cathode 224 of the Schottky diode 210 have the same effect. At the same time, the switch output SW terminal of the integrated control circuit wafer 340 is bonded to the second inductor terminal 205 of the stacked chip inductor 204. Because the second inductor terminal 205 of the stacked chip inductor 204 and the first capacitor terminal 206 of the ceramic chip capacitor 207 are bonded to each other, the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the second inductor terminal 205 of the stacked chip inductor 204 and the bonding of the switch output terminal SW of the integrated control circuit wafer 340 to the first capacitor terminal 206 of the ceramic chip capacitor 207 have the same effect; the bootstrap BST terminal is bonded to the second capacitor terminal 208 of the ceramic chip capacitor 207; the signal feedback FB terminal is bonded to the signal feedback pin 113 of the lead frame 302; and the power ground GND terminal is bonded to the power ground pin 114 of the lead frame 302.

[0062] The top anode 222 of the Schottky diode 210 is bonded to the power ground pin 114 of the package frame 302, and is indirectly connected to the power ground GND terminal of the integrated control circuit wafer 340. The bottom cathode 224 of the Schottky diode 210 is electrically connected to the conductive metal layer 220 on the front side of the silicon wafer 201 through the second conductive medium 211, so it is indirectly electrically connected to the switch output SW terminal of the integrated control circuit wafer 340.

[0063] It also includes an external capacitor, a first feedback resistor and a second feedback resistor. One end of the external capacitor is grounded, and the other end is connected to the switch output pin 115 of the lead frame 302. One end of the first feedback resistor is connected to the switch output pin 115 of the lead frame 302, and the other end is connected to one end of the second feedback resistor, the other end of the second feedback resistor is grounded, and the connection point of the first feedback resistor and the second feedback resistor is connected to the signal feedback pin 113 of the lead frame 302.

[0064] The advantages of the implementation of the present invention are as follows: by arranging a single base island and a plurality of pins on a lead frame, the single base island is divided into a first chip area and a second chip area, a first conductive medium is arranged on the first chip area, a first insulating medium is arranged on the second chip area, an integrated control circuit wafer is arranged on the first conductive medium, a silicon wafer is arranged, one side of the silicon wafer is a conductive metal layer, and the other side is a silicon surface, the silicon surface is attached to the first insulating medium, a ceramic chip capacitor, a stacked chip inductor and a Schottky diode are arranged on the conductive metal layer, the integrated control circuit wafer is bonded to the silicon wafer, the stacked chip inductor and the ceramic chip capacitor respectively, the pins of the lead frame are bonded to the integrated control circuit wafer, the single base island, the stacked chip inductor and the Schottky diode respectively, thereby reducing the number of components on the circuit board, reducing the circuit board area, and reducing the production cost and the difficulty of PCB debugging.

[0065] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. An asynchronous buck chip single base island packaging structure, characterized in that: include: A lead frame (302) comprises a single base island (112) and a plurality of pins, wherein the single base island (112) comprises a first chip region and a second chip region, and the lead frame (302) comprises a power input pin (111), a signal feedback pin (113), a power ground pin (114), and a switch output pin (115), wherein the positions of the power input pin (111), the signal feedback pin (113), the power ground pin (114), and the switch output pin (115) on the lead frame (302) are not fixed; An integrated control circuit wafer (340) is disposed in the first chip area, a first conductive medium (121) is provided between the integrated control circuit wafer (340) and the first chip area, and the integrated control circuit wafer (340) comprises a power input VIN terminal, a switch output SW terminal, a bootstrap BST terminal, a power ground GND terminal, and a signal feedback FB terminal; A silicon wafer (201) is disposed in the second chip region, one side of the silicon wafer (201) is provided as a conductive metal layer (220), and the other side is provided as a silicon surface (221), a first insulating medium (212) is provided between the silicon surface (221) and the second chip region, a ceramic chip capacitor (207), a stacked chip inductor (204) and a Schottky diode (210) are also provided on the conductive metal layer (220), the ceramic chip capacitor (207) comprises a first capacitor terminal (206) and a second capacitor terminal (208); the stacked chip inductor (204) comprises a first inductor terminal (203) and a second inductor terminal (205), and the second inductor terminal (205) and the first capacitor terminal (206) are bonded; The Schottky diode (210) comprises a top anode (222), a bottom cathode (224) and a semiconductor (223); the top anode (222) of the Schottky diode (210) is bonded to the lead frame (302), and the bottom cathode (224) of the Schottky diode (210) is connected to the conductive metal layer (220) of the silicon wafer (201) via a second conductive medium (211); A plastic package (301) used to encapsulate the lead frame (302), the integrated control circuit wafer (340), the silicon chip (201), the ceramic chip capacitor (207), the stacked chip inductor (204), and the Schottky diode (210); The power input VIN terminal of the integrated control circuit wafer (340) is bonded to the power input pin (111) of the lead frame (302); the switch output SW terminal is bonded to the bottom cathode (224) of the Schottky diode (210) and the second inductor terminal (205) of the stacked chip inductor (204); the bootstrap BST terminal is bonded to the second capacitor terminal (208) of the ceramic chip capacitor (207); the signal feedback FB terminal is bonded to the signal feedback pin (113) of the lead frame (302); and the power ground GND terminal is bonded to the power ground pin (114) of the lead frame (302) and is indirectly connected to the top anode (222) of the Schottky diode (210).

2. The single island packaging structure of an asynchronous buck chip according to claim 1, characterized in that: It also includes an external capacitor, one end of which is grounded, and the other end of which is connected to a switch output pin (115) of the lead frame (302).

3. The single island package structure of an asynchronous buck chip according to claim 1, characterized in that: It also includes a first feedback resistor and a second feedback resistor, one end of the first feedback resistor is connected to a switch output pin (115) of the lead frame (302), the other end is connected to one end of the second feedback resistor, the other end of the second feedback resistor is grounded, and the connection point between the first feedback resistor and the second feedback resistor is connected to a signal feedback pin (113) of the lead frame (302).

4. The single island package structure of an asynchronous buck chip according to claim 1, characterized in that: A second insulating medium (209) is provided between the ceramic chip capacitor (207) and the conductive metal layer (220); and a third insulating medium (202) is provided between the stacked chip inductor (204) and the conductive metal layer (220).

5. The single island packaging structure of an asynchronous buck chip according to claim 1, characterized in that: The power ground pin (114) is bonded to the single base island (112) and bonded to the top anode (222) of the Schottky diode (210); the switch output pin (115) of the lead frame (302) is bonded to the first inductor terminal (203) of the stacked chip inductor (204).

6. The single-island package structure of an asynchronous buck chip according to any one of claims 1 to 5, characterized in that: The back side of the single base island (112) extends through the plastic package body (301) and is provided with a heat dissipation pad structure.

7. A method for packaging an asynchronous buck chip single island based on the asynchronous buck chip single island packaging structure according to claims 1 to 6, characterized in that: include: Arranging a single base island (112) and pins of a lead frame (302), and dividing the single base island (112) into a first chip area and a second chip area; A first conductive medium (121) is arranged on the first chip area, and a first insulating medium (212) is arranged on the second chip area; An integrated control circuit wafer (340) is arranged on the first conductive medium (121); A silicon wafer (201) is provided, wherein one side of the silicon wafer (201) is a conductive metal layer (220) and the other side is a silicon surface (221); the silicon surface (221) is attached to the first insulating medium (212); and a ceramic chip capacitor (207), a stacked chip inductor (204), and a Schottky diode (210) are provided on the conductive metal layer (220); Bonding the integrated control circuit wafer (340) to the silicon wafer (201), the stacked chip inductor (204), and the ceramic chip capacitor (207) respectively; Bonding the pins of the lead frame (302) to the integrated control circuit wafer (340), the single base island (112), the stacked chip inductor (204) and the Schottky diode (210) respectively; The lead frame (302), the integrated control circuit wafer (340), the silicon chip (201), the ceramic chip capacitor (207), the stacked chip inductor (204), and the Schottky diode (210) are wrapped with a plastic package (301).

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