Semiconductor test structure and method of testing a semiconductor structure

Abstract

The application relates to a semiconductor test structure and a test method of a semiconductor structure. The semiconductor test structure comprises a main test structure and a secondary test structure which are insulated from each other; the main test structure comprises a main resistance structure, a first pad and a second pad, the first pad is connected to the first end of the main resistance structure, and the second pad is connected to the last end of the main resistance structure; the secondary test structure comprises a secondary resistance structure and a third pad, and the third pad is connected to the secondary resistance structure; wherein the secondary resistance structure comprises a plurality of jumper structures, and the orthographic projection of the jumper structure at least partially overlaps with the orthographic projection of the main resistance structure. The semiconductor test structure can simultaneously monitor the resistance and the same-layer capacitance, only occupies three pad areas, can effectively save the chip area, reduces the research and development cost, and can monitor the resistance value and the capacitance value of the semiconductor structure with the same actual process and the same density, thereby improving the fitting precision of the resistance-capacitance file simulation in the process design kit and the actual process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor test structure and a test method of a semiconductor structure. BACKGROUND

[0002] With the continuous advancement of semiconductor process nodes, the cost of tape-out is increasing. Consequently, the requirement for the simulation accuracy of parasitic parameters of a semiconductor process design kit (PDK) is also increasing for modules designed based on advanced processes.

[0003] However, for resistors of the same density and capacitors in the same layer, only discrete monitoring can be performed, and the resistors and capacitors of the same density under the actual same process cannot be monitored, which affects the fitting accuracy of the simulation of the capacitor-resistor file in the process design kit and the actual process. Moreover, the test structure for monitoring the resistors and capacitors discretely usually wastes chip area and increases the research and development cost. SUMMARY

[0004] Based on this, the embodiments of the present application provide a semiconductor test structure and a test method of a semiconductor structure.

[0005] According to some embodiments, the present application provides a semiconductor test structure, which includes a main test structure and a secondary test structure insulated from each other; the main test structure includes a main resistor structure, a first pad and a second pad, the first pad is connected to a first end of the main resistor structure, and the second pad is connected to a last end of the main resistor structure; the secondary test structure includes a secondary resistor structure and a third pad, the third pad is connected to the secondary resistor structure; wherein the secondary resistor structure includes a plurality of jumper structures, and the orthographic projection of the jumper structure at least partially overlaps the orthographic projection of the main resistor structure.

[0006] In the semiconductor test structure of the above embodiment, the semiconductor test structure comprises a main test structure and a sub test structure which are insulated from each other, the sub resistance structure comprises a plurality of jumper structures, the orthographic projection of the jumper structure at least partially overlaps with the orthographic projection of the main resistance structure, the main resistance structure of the main test structure is connected to the first pad and the second pad, and the sub resistance structure of the sub test structure is connected to the third pad. In this way, the sub test structure can not only provide a density environment for the main test structure, but also can be combined into one semiconductor test structure by combining the two test structures, so as to directly test the resistance and the same layer capacitance of the semiconductor structure through the first pad, the second pad and / or the third pad, so as to realize a test structure capable of monitoring the resistance and the same layer capacitance at the same time. Since the semiconductor test structure only occupies three pad areas, the chip area can be effectively saved, and the research and development cost is reduced. Moreover, the semiconductor test structure can monitor the resistance value and the capacitance value of the semiconductor structure of the same density under the same actual process, so as to improve the fitting accuracy of the resistance and capacitance file simulation in the process design kit and the actual process.

[0007] In some embodiments, the main resistance structure comprises a first end branch resistance, a last end branch resistance and a plurality of main resistance units connected in a head-to-tail manner, the first end branch resistance and the last end branch resistance are located on the same side of the main resistance units; one end of the first end branch resistance is connected to the first end of the first main resistance unit, and the other end is connected to the first pad; one end of the last end branch resistance is connected to the last end of the last main resistance unit, and the other end is connected to the second pad.

[0008] In some embodiments, the main resistance unit comprises a U-shaped resistance structure and two strip-shaped branch resistances connected in a head-to-tail manner with the U-shaped resistance structure; the strip-shaped branch resistance extends along a first direction and is connected to the strip-shaped branch resistance in the previous or next main resistance unit.

[0009] In some embodiments, the jumper structure comprises a first jumper resistance and a second jumper resistance extending along a second direction; the first jumper resistance is located above the first strip-shaped branch resistance along a third direction, and the second jumper resistance is located above the last strip-shaped branch resistance along the third direction, and the third direction, the second direction and the first direction are perpendicular to each other.

[0010] In some embodiments, the sub resistance structure further comprises a first sub resistance structure and a second sub resistance structure, and the orthographic projection of the first sub resistance structure and the second sub resistance structure does not overlap with the orthographic projection of the main resistance structure; the first jumper resistance is located between the first end of the first sub resistance structure and the first end of the second sub resistance structure; and the second jumper resistance is located between the last end of the first sub resistance structure and the last end of the second sub resistance structure.

[0011] In some embodiments, the first sub-resistance structure comprises a plurality of first sub-resistance units and a first extension branch extending along the first direction, and the first ends of the plurality of first sub-resistance units are connected to the first extension branch respectively; the second sub-resistance structure comprises a plurality of second sub-resistance units and a second extension branch extending along the first direction, and the first ends of the plurality of second sub-resistance units are connected to the second extension branch respectively; the first sub-resistance units extend along the second direction and are located on both sides of adjacent main resistance units; and the second sub-resistance units extend into the main resistance units along the second direction.

[0012] In some embodiments, the second sub-resistance structure further comprises an intermediate extension branch, the intermediate extension branch is located on the symmetry axis of the second extension branch and extends along the second direction; the first end of the intermediate extension branch is connected to the second extension branch, and the last end of the intermediate extension branch is connected to the third pad.

[0013] In some embodiments, the first sub-resistance structure further comprises a first contact electrode and a second contact electrode, the first contact electrode is located at the last end of the first sub-resistance unit, and the second contact electrode is located at the first end of the second extension branch; the second sub-resistance structure further comprises a third contact electrode and a fourth contact electrode, the third contact electrode is located at the last end of the first sub-resistance unit, and the fourth contact electrode is located at the last end of the second extension branch; the first jumper resistor is connected to the first contact electrode and the second contact electrode at the first end and the last end respectively, and the second jumper resistor is connected to the third contact electrode and the fourth contact electrode at the first end and the last end respectively.

[0014] According to some embodiments, the application further provides a testing method of a semiconductor structure, which uses the semiconductor testing structure in the above-mentioned embodiments to test the testing method of the semiconductor structure, and the method comprises:

[0015] applying a first voltage to the first pad, applying a second voltage to the second pad, applying a third voltage to the third pad, and obtaining the current of the second pad to test the resistance of the testing method of the semiconductor structure; and / or

[0016] applying a fourth voltage to the first pad, applying a fifth voltage to the second pad, applying a sixth voltage to the third pad, and obtaining the current of the third pad to test the capacitance of the testing method of the semiconductor structure.

[0017] In the test method of the semiconductor structure in the above embodiment, the resistance of the semiconductor structure is tested by applying the first voltage to the first pad, applying the second voltage to the second pad, applying the third voltage to the third pad, and obtaining the current of the second pad, and the capacitance of the semiconductor structure is tested by applying the fourth voltage to the first pad, applying the fifth voltage to the second pad, applying the sixth voltage to the third pad, and obtaining the current of the third pad. The resistance and the capacitance of the semiconductor structure are directly tested based on the same semiconductor test structure. Moreover, the resistance and the capacitance of the semiconductor structure with the same density under the same actual process can be monitored, so that the fitting accuracy of the resistance and capacitance file simulation in the process design kit and the actual process is improved.

[0018] In some embodiments, the first voltage is 0V, the second voltage is 1.8V, and the third voltage is 0V; and / or the first voltage is 0V, the second voltage is 0V, and the third voltage is 1.8V. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 FIG. 1 is a top view schematic diagram of a semiconductor test structure;

[0020] Figure 2 FIG. 2 is a top view schematic diagram of another semiconductor test structure;

[0021] Figure 3 FIG. 3 is a top view schematic diagram of a semiconductor test structure provided by an embodiment of the present application;

[0022] Figure 4 FIG. 4 is a flowchart schematic diagram of a test method of a semiconductor structure provided by an embodiment of the present application.

[0023] FIG. 1 is a top view schematic diagram of a semiconductor test structure; DETAILED DESCRIPTION

[0024] For the purposes of the present invention, a more complete understanding can be obtained by reference to the following description taken in connection with the accompanying drawings. The drawings are made for purposes of illustration only and are not intended to define the limits of the present invention. For the purposes of brevity and clarity, well-known structures and processing techniques, which are known to persons of ordinary skill in the relevant art, have been provided with only the most rudimentary description and detailed descriptions have not been provided.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] In the case of using "include", "have", and "contain" described herein, unless an explicit limiting term is used, such as "only", "consist of", etc., another component can be added. Unless otherwise mentioned, the singular form of the term can include the plural form, and it is not understood as the number of one.

[0027] In addition, in order to clearly show the plurality of layers and regions in the drawings, the thickness of each layer and the distribution of each region are exaggerated in the drawings. When a part of a layer, a film, a region, a plate, etc. is described as being "on one side" of another part, it includes not only the case of being "directly" on the other part, but also the case where there are other layers therebetween. Also, it can be understood that when a part of a layer, a film, a region, a plate, etc. is described as being "on one side" of another part, it is usually on the side directly above the other part.

[0028] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0029] Spatial terms such as "below," "beneath," "lower," "under," "above," "upper," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (for example, rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0030] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. Thus, the shapes of the regions are not intended to convey a meaning other than that of the illustrative embodiments.

[0031] Referring to Figure 1 and Figure 2 , a semiconductor process design kit (PDK) needs to test the resistance and capacitance values of an actual process when developing a capacitance resistance file, and derive actual size and thickness information under different densities according to the comprehensive test results of the resistance and capacitance. Generally, the resistance test structure of the same density is tested as shown in Figure 1 , and the same layer capacitance test structure of the same density is tested as shown in Figure 2 . That is, based on the limitations of the existing resistance and capacitance structures, the resistance test structure and the same layer capacitance test structure of the same density can only be monitored separately, which greatly wastes the chip area. Moreover, process deviations exist in different positions of the chip, which can cause the resistance values and capacitance values of the test structures of the same density tested at different positions to be unmatched, so that the resistance values and capacitance values of the same density under the actual same process cannot be completely monitored, thereby affecting the fitting accuracy of the capacitance resistance file simulation in the semiconductor process design kit and the actual process.

[0032] Therefore, in order to solve the above problems, the embodiments of the present application provide a semiconductor test structure and a test method of a semiconductor structure.

[0033] Figure 3Fig. 1 shows a top view of a semiconductor test structure according to some embodiments of the present application. Please refer to Figure 3 The present application provides a semiconductor test structure. The semiconductor test structure comprises a main test structure 100 and a sub test structure 200 which are insulated from each other. The main test structure 100 comprises a main resistance structure 110, a first pad 120 and a second pad 130, the first pad 120 is connected to a first end of the main resistance structure 110, and the second pad 130 is connected to a second end of the main resistance structure 110; the sub test structure 200 comprises a sub resistance structure 210 and a third pad 220, the third pad 220 is connected to the sub resistance structure 210; wherein the sub resistance structure 210 comprises a plurality of jumper structures 211, and a projection of the jumper structure 211 at least partially overlaps a projection of the main resistance structure 110.

[0034] In the semiconductor test structure of the above embodiment, the semiconductor test structure comprises a main test structure 100 and a sub test structure 200 which are insulated from each other, the sub resistance structure 210 comprises a plurality of jumper structures 211, and a projection of the jumper structure 211 at least partially overlaps a projection of the main resistance structure 110, the main resistance structure 110 of the main test structure 100 is connected to the first pad 120 and the second pad 130, and the sub resistance structure 210 of the sub test structure 200 is connected to the third pad 220. In this way, the sub test structure 200 not only can provide a density environment for the main test structure 100, but also can combine the two test structures into one semiconductor test structure, so as to directly test the resistance and the same layer capacitance of the semiconductor structure through the first pad 120, the second pad 130 and / or the third pad 220, so as to realize a test structure which can simultaneously monitor the resistance and the same layer capacitance. Since the semiconductor test structure only occupies three pad areas, the chip area can be effectively saved, and the research and development cost can be reduced. Moreover, the semiconductor test structure can monitor the resistance value and the capacitance value of the semiconductor structure of the same density under the same actual process, so as to improve the fitting precision of the resistance and capacitance file simulation in the process design kit and the actual process.

[0035] It should be noted that the projection of the jumper structure 211 can be understood as a projection which is perpendicular to an x direction as shown in Fig. 1 and perpendicular to a y direction as shown in Fig. 1. The projection of the jumper structure 211 at least partially overlaps the projection of the main resistance structure 110, which can be understood as that the jumper structure 211 is located in an upper structure of the main resistance structure 110. Figure 3 Figure 3

[0036] For example, the main test structure 100 and the sub test structure 200 are insulated from each other, which can be understood as that there is an insulating film layer between the main test structure 100 and the sub test structure 200.

[0037] ​​For example, the jumper structure 211 is insulated from the main resistance structure 110, and it can be understood that an insulating film layer is arranged between the jumper structure 211 and the main resistance structure 110.

[0038] In some embodiments, the main resistance structure 110 includes a first-end branch resistance 111, a last-end branch resistance 112, and a plurality of main resistance units 113 connected in series, the first-end branch resistance 111 and the last-end branch resistance 112 are located on the same side of the main resistance units 113; one end of the first-end branch resistance 111 is connected to the first end of the first main resistance unit 113, and the other end is connected to the first pad 120; one end of the last-end branch resistance 112 is connected to the last end of the last main resistance unit 113, and the other end is connected to the second pad 130.

[0039] For example, the number of the main resistance units 113 is 3-5. For example, the number of the main resistance units 113 can be 3, 4 or 5. Figure 3 For example, the number of the main resistance units 113 is 4.

[0040] For example, the first-end branch resistance 111 and the last-end branch resistance 112 are rectangular and extend along the second direction, which can be understood as the y direction as shown in the figure. Figure 3 Since the first-end branch resistance 111 and the last-end branch resistance 112 are located on the same side of the main resistance units 113, the first pad 120 and the second pad 130 are also located on the same side of the main resistance units 113.

[0041] In some embodiments, the first pad 120, the second pad 130 and the third pad 220 are made of conductive material. For example, the conductive material can be metal material, for example, the metal material can include tin, titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten or a combination thereof, for example, ruthenium, tungsten, gold or silver all belong to low resistance metal, which can reduce the resistance of the first pad 120, the second pad 130 and the third pad 220, and is beneficial to improve the test precision of the semiconductor test structure.

[0042] In some embodiments, the main resistance unit 113 includes a U-shaped resistance structure 1131 and two strip branch resistances 1132 connected in series with the U-shaped resistance structure 1131; the strip branch resistance 1132 extends along the first direction and is connected to the strip branch resistance 1132 in the previous or subsequent main resistance unit 113.

[0043] For example, two adjacent main resistance units 113 share a strip-shaped branch resistance 1132 between them. Each main resistance unit 113 includes a U-shaped resistance structure 1131. In some embodiments, the number of all strip-shaped branch resistances 1132 in the main resistance structure 110 is greater than the number of main resistance units 113. For example, the number of all strip-shaped branch resistances 1132 in the main resistance structure 110 is one more than the number of main resistance units 113. For example, the number of strip-shaped branch resistances 1132 is 4-6. For example, the number of strip-shaped branch resistances 1132 is 4, 5 or 6. As shown in FIG. 1, in an embodiment where the number of main resistance units 113 is 4, the number of strip-shaped branch resistances 1132 is 5. Figure 3

[0044] For example, the opening of the U-shaped resistance structure 1131 faces the head branch resistance 111 or the tail branch resistance 112. The first direction can be understood as the x direction as shown in FIG. 1. Figure 3

[0045] In some embodiments, the first strip-shaped branch resistance 1132 is connected to the end of the head branch resistance 111 away from the first pad 120, and the last strip-shaped branch resistance 1132 is connected to the end of the tail branch resistance 112 away from the second pad 130. For example, the strip-shaped branch resistance 1132 is rectangular. As shown in FIG. 1, in an embodiment where the number of strip-shaped branch resistances 1132 is 5, the first strip-shaped branch resistance 1132 is connected to the end of the head branch resistance 111 away from the first pad 120, and the fifth strip-shaped branch resistance 1132 is connected to the end of the tail branch resistance 112 away from the second pad 130. Figure 3

[0046] In some embodiments, the jumper structure 211 includes a first jumper resistance 2111 and a second jumper resistance 2112 extending along a second direction; the first jumper resistance 2111 is located above the first strip-shaped branch resistance 1132 along a third direction, and the second jumper resistance 2112 is located above the last strip-shaped branch resistance 1132 along the third direction, and the third direction, the second direction and the first direction are perpendicular. For example, the third direction can be understood as the direction of the orthographic projection of the jumper structure 211.

[0047] For example, the first jumper resistance 2111 and the second jumper resistance 2112 are rectangular and parallel to the head branch resistance 111 or the tail branch resistance 112.

[0048] ​​​In some embodiments, the auxiliary resistance structure 210 further comprises a first sub-resistance structure 212 and a second sub-resistance structure 213, the orthographic projections of the first sub-resistance structure 212 and the second sub-resistance structure 213 do not overlap with the orthographic projection of the main resistance structure 110; the first jumper resistance 2111 is located between the first end of the first sub-resistance structure 212 and the first end of the second sub-resistance structure 213; the second jumper resistance 2112 is located between the last end of the first sub-resistance structure 212 and the last end of the second sub-resistance structure 213.

[0049] In some embodiments, the first sub-resistance structure 212 comprises a plurality of first auxiliary resistance units 2121 and a first extension branch 2122 extending along the first direction, the first ends of the plurality of first auxiliary resistance units 2121 are connected to the first extension branch 2122 respectively; the first auxiliary resistance units 2121 extend along the second direction and are located on both sides of adjacent main resistance units 113.

[0050] In some embodiments, the second sub-resistance structure 213 comprises a plurality of second auxiliary resistance units 2131 and a second extension branch 2132 extending along the first direction, the first ends of the plurality of second auxiliary resistance units 2131 are connected to the second extension branch 2132 respectively; the second auxiliary resistance units 2131 extend into the main resistance units 113 along the second direction.

[0051] In some embodiments, the number of the first auxiliary resistance units 2121 is greater than the number of the second auxiliary resistance units 2131. For example, the number of the second auxiliary resistance units 2131 is the same as the number of the main resistance units 113, and the number of the first auxiliary resistance units 2121 is one more than the number of the second auxiliary resistance units 2131.

[0052] In some embodiments, the second sub-resistance structure 213 further comprises an intermediate extension branch 2133, the intermediate extension branch 2133 is located on the symmetry axis of the second extension branch 2132 and extends along the second direction; the first end of the intermediate extension branch 2133 is connected to the second extension branch 2132, and the last end of the intermediate extension branch 2133 is connected to the third pad 220.

[0053] For example, the third pad 220 is located between the first pad 120 and the second pad 130. For example, the third pad 220 is located at the midpoint of the connecting line between the first pad 120 and the second pad 130, so as to save the area of the semiconductor test structure.

[0054] In some embodiments, the first sub-resistance structure 212 further comprises a first contact electrode 2123 and a second contact electrode 2124, the first contact electrode 2123 is located at the end of the first first sub-resistance unit 2121, and the second contact electrode 2124 is located at the first end of the second extension branch 2132; the second sub-resistance structure 213 further comprises a third contact electrode 2134 and a fourth contact electrode 2135, the third contact electrode 2134 is located at the end of the last first sub-resistance unit 2121, and the fourth contact electrode 2135 is located at the end of the second extension branch 2132; the first jumper resistor 2111 is connected to the first contact electrode 2123 and the second contact electrode 2124 at the first end and the second end, respectively, and the second jumper resistor 2112 is connected to the third contact electrode 2134 and the fourth contact electrode 2135 at the first end and the second end, respectively.

[0055] In some embodiments, the first contact electrode 2123, the second contact electrode 2124, the third contact electrode 2134, and the fourth contact electrode 2135 are all made of conductive materials. For example, the conductive material can be a metal material, for example, the metal material can include tin, titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, or a combination thereof, for example, ruthenium, tungsten, gold, or silver all belong to low-resistance metals, which can reduce the resistance of the first contact electrode 2123, the second contact electrode 2124, the third contact electrode 2134, and the fourth contact electrode 2135, and is conducive to improving the test accuracy of the semiconductor test structure.

[0056] Please refer to Figure 4 According to some embodiments, the application further provides a test method of a semiconductor structure, comprising the following steps.

[0057] Step S10, a first voltage is applied to the first pad, a second voltage is applied to the second pad, a third voltage is applied to the third pad, and a current of the second pad is obtained to test the resistance of the test method of the semiconductor structure; and / or

[0058] Step S30, a fourth voltage is applied to the first pad, a fifth voltage is applied to the second pad, a sixth voltage is applied to the third pad, and a current of the third pad is obtained to test the capacitance of the test method of the semiconductor structure.

[0059] In the test method of the semiconductor structure in the above embodiment, the resistance of the semiconductor structure is tested by applying the first voltage to the first pad, the second voltage to the second pad, the third voltage to the third pad, and obtaining the current of the second pad, and the capacitance of the semiconductor structure is tested by applying the fourth voltage to the first pad, the fifth voltage to the second pad, the sixth voltage to the third pad, and obtaining the current of the third pad. The resistance and the capacitance of the same layer of the semiconductor structure can be directly tested based on the same semiconductor test structure. Moreover, the resistance and the capacitance of the semiconductor structure with the same density under the same actual process can be monitored, so that the fitting accuracy of the resistance and capacitance file simulation in the process design kit and the actual process is improved.

[0060] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method does not have strict sequence limitation, and the steps can not necessarily be executed in the order described, and can be executed in other manners. Moreover, at least part of each step can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or sub-steps or stages of other steps.

[0061] In some embodiments, the first voltage is 0V, the second voltage is 1.8V, and the third voltage is 0V; and / or the first voltage is 0V, the second voltage is 0V, and the third voltage is 1.8V

[0062] Each technical feature of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of each technical feature in the above embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

[0063] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A semiconductor test structure, characterized by, The main test structure and the auxiliary test structure are insulated from each other; The main test structure comprises a main resistance structure, a first pad and a second pad, the first pad is connected to a first end of the main resistance structure, and the second pad is connected to a last end of the main resistance structure; The auxiliary test structure comprises an auxiliary resistance structure and a third pad, the third pad is connected to the auxiliary resistance structure; The auxiliary resistance structure comprises a plurality of jumper structures, and a projection of the jumper structure at least partially overlaps with a projection of the main resistance structure; The auxiliary resistance structure further comprises a first sub-resistance structure and a second sub-resistance structure; The second sub-resistance structure comprises a plurality of second auxiliary resistance units and a second extension branch extending in a first direction, and first ends of the plurality of second auxiliary resistance units are respectively connected to the second extension branch; The second sub-resistance structure further comprises an intermediate extension branch, the intermediate extension branch is located on a symmetry axis of the second extension branch and extends in a second direction; A first end of the intermediate extension branch is connected to the second extension branch, and a last end of the intermediate extension branch is connected to the third pad.

2. The semiconductor test structure of claim 1, wherein, The main resistance structure comprises a first end branch resistance, a last end branch resistance and a plurality of main resistance units connected in sequence, the first end branch resistance and the last end branch resistance are located on the same side of the main resistance units; One end of the first end branch resistance is connected to a first end of a first main resistance unit, and the other end is connected to the first pad; One end of the last end branch resistance is connected to a last end of a last main resistance unit, and the other end is connected to the second pad.

3. The semiconductor test structure of claim 2, wherein, The main resistance unit comprises a U-shaped resistance structure and two strip-shaped branch resistances connected in sequence to the U-shaped resistance structure; The strip-shaped branch resistance extends in a first direction and is connected to the strip-shaped branch resistance in the previous or subsequent main resistance unit.

4. The semiconductor test structure of claim 3, wherein, The jumper structure comprises a first jumper resistance and a second jumper resistance extending in a second direction; The first jumper resistance is located above the first strip-shaped branch resistance in a third direction, and the second jumper resistance is located above the last strip-shaped branch resistance in the third direction, and the third direction, the second direction and the first direction are perpendicular to each other.

5. The semiconductor test structure of claim 4, wherein, The projections of the first sub-resistance structure and the second sub-resistance structure do not overlap with the projection of the main resistance structure; The first jumper resistance is located between the first end of the first sub-resistance structure and the first end of the second sub-resistance structure, and the second jumper resistance is located between the last end of the first sub-resistance structure and the last end of the second sub-resistance structure.

6. The semiconductor test structure of claim 5, wherein, The first sub-resistance structure comprises a plurality of first auxiliary resistance units and a first extension branch extending in the first direction, and first ends of the plurality of first auxiliary resistance units are respectively connected to the first extension branch; The first auxiliary resistance unit extends in the second direction and is located on both sides of adjacent main resistance units; The second auxiliary resistance unit extends into the main resistance unit in the second direction.

7. The semiconductor test structure of claim 6, wherein, The first sub-resistance structure further comprises a first contact electrode and a second contact electrode, the first contact electrode is located at the end of the first first sub-resistance unit, and the second contact electrode is located at the first end of the second extension branch; The second sub-resistance structure further comprises a third contact electrode and a fourth contact electrode, the third contact electrode is located at the end of the last first sub-resistance unit, and the fourth contact electrode is located at the end of the second extension branch; The first jumper resistance is connected with the first contact electrode and the second contact electrode at the first end and the second end respectively, and the second jumper resistance is connected with the third contact electrode and the fourth contact electrode at the first end and the second end respectively.

8. A method of testing a semiconductor structure, characterized by, A method for testing a semiconductor structure by using the semiconductor test structure according to any one of claims 1-7, the method comprising: applying a first voltage to the first pad, a second voltage to the second pad, a third voltage to the third pad, and obtaining the current of the second pad to test the resistance of the method for testing the semiconductor structure; and / or applying a fourth voltage to the first pad, a fifth voltage to the second pad, a sixth voltage to the third pad, and obtaining the current of the third pad to test the capacitance of the method for testing the semiconductor structure.

9. The method of testing a semiconductor structure of claim 8, wherein, The first voltage is 0V, the second voltage is 1.8V, and the third voltage is 0V; and / or The first voltage is 0V, the second voltage is 0V, and the third voltage is 1.8V.

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