Dead time control circuit for buck converter and buck converter

Abstract

The invention discloses a dead time control circuit for a buck converter and the buck converter, the buck converter comprises a main switch tube and a synchronous switch tube which are connected in series between a power supply voltage and a grounding end, and a common node of the main switch tube and the synchronous switch tube is a switch node. The dead time control circuit is used for controlling the dead time between turn-off of the synchronous switch tube and turn-on of the main switch tube, and comprises a switch node detection circuit used for detecting the voltage of a switch node and generating an effective first detection signal when the voltage of the switch node drops to a first threshold voltage; and the dead time adjusting circuit is used for generating an effective edge of the clock pulse signal at an effective edge of the first detection signal, counting the number of the effective edges of the clock pulse signal in a plurality of continuous switching periods to obtain a count value, and adaptively adjusting the size of the dead time according to the count value, therefore, ideal dead time can be obtained in a steady state.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a dead time control circuit for a buck converter and a buck converter. Background Art

[0002] In order to prevent the main switch and synchronous switch of the buck converter from being turned on at the same time, a dead time is usually added between their control signals to ensure that one switch is turned off before the other switch is turned on. Taking the synchronous rectification buck converter as an example, during the dead time, the body diode of the main switch is used for freewheeling, resulting in a large loss of efficiency. If the dead time is too long, it will affect the working efficiency of the buck converter. If the dead time is too short, there is a risk that the main switch and the synchronous switch are turned on at the same time.

[0003] Figure 1 FIG. 1 shows a circuit diagram of a buck converter according to the prior art. Figure 1 The buck converter 100 includes a driving circuit 110, a driving circuit 120, a dead time control circuit 130, and a dead time control circuit 140. The driving circuit 110 includes a NOT gate 111, a NOR gate 112, a level converter 113, and a driving unit 114. The driving circuit 120 includes a NOR gate 121, a level converter 122, and a driving unit 123. The dead time control circuit 130 includes delay units 131 and 132. The dead time control circuit 140 includes delay units 141 and 142.

[0004] The dead time control circuit 130 samples the driving signal ls_g of the synchronous switch tube ML and inputs it to the NOR gate 112 of the driving unit 110 after delaying, so that the driving unit 110 generates the driving signal hs_g of the main switch tube MH. The dead time control circuit 140 samples the driving signal hs_g of the main switch tube MH and inputs it to the NOR gate 121 of the driving unit 120 after delaying, so that the driving unit 120 generates the driving signal ls_g of the synchronous switch tube ML.

[0005] The dead time of the buck converter 100 is a fixed value, which is greatly affected by the power supply voltage and process parameter drift, so the dead time needs to be set to a longer time (generally about 10ns-20ns) to ensure that the main switch tube and the synchronous switch tube are not turned on at the same time under different conditions. Therefore, a new buck converter and its dead time control circuit are to be proposed to solve the above problem. Summary of the invention

[0006] In view of the above problems, the object of the present invention is to provide a dead time control circuit and a buck converter for a buck converter, so that the dead time between the turn-off of the synchronous switch tube and the turn-on of the main switch tube can be adaptively adjusted to obtain an ideal dead time in a steady state.

[0007] According to one aspect of the present invention, there is provided a dead time control circuit for a buck converter, wherein the buck converter comprises a main switch tube and a synchronous switch tube connected in series between a power supply voltage and a ground terminal, wherein a common node of the main switch tube and the synchronous switch tube is a switch node, and the dead time control circuit is used to control the dead time between the turn-off of the synchronous switch tube and the turn-on of the main switch tube, and the dead time control circuit comprises a switch node detection circuit, which is used to detect the voltage of the switch node and generate a valid first detection signal when the voltage of the switch node drops to a first threshold voltage; and a dead time adjustment circuit, which is used to generate an effective edge of a clock pulse signal at an effective edge of the first detection signal, and count the number of effective edges of the clock pulse signal in a plurality of consecutive switching cycles to obtain a count value, and adaptively adjust the size of the dead time according to the count value.

[0008] Optionally, the effective edge of the clock pulse signal is delayed by a set time relative to the effective edge of the first detection signal.

[0009] Optionally, the switch node detection circuit is also used to generate a valid second detection signal when the voltage of the switch node rises to a second threshold voltage, and to generate an invalid second detection signal when the pulse width modulation signal flips to a second level, and the second threshold voltage is greater than the first threshold voltage. The dead time adjustment circuit is used to generate a counting control signal based on a delay signal of the first detection signal and the second detection signal, and to add or subtract the valid edges of the clock pulse signal according to the counting control signal.

[0010] Optionally, the dead time adjustment circuit performs addition counting on the effective edges of the clock pulse signal when the count control signal is at a first level, and performs subtraction counting on the effective edges of the clock pulse signal when the count control signal is at a second level.

[0011] Optionally, the dead time adjustment circuit includes a clock signal generating module, which is used to generate the clock pulse signal according to the delayed signal of the first detection signal, the inverted signal of the pulse width modulation signal and the second detection signal; a counting direction control module, which is used to generate the counting control signal according to the delayed signal of the first detection signal and the second detection signal; a counting module, which is used to count the effective edges of the clock pulse signal according to the level state of the counting control signal to obtain a counting value; and a time adjustment module, which is used to generate a turn-on signal for controlling the turn-on moment of the main switch tube according to the control signal of the synchronous switch tube and the counting value.

[0012] Optionally, the clock signal generating module includes a first NOR gate, whose first input receives a delayed signal of the first detection signal; a second NOR gate, whose first input receives the second detection signal, whose second input receives an inverted signal of the pulse width modulation signal, whose third input receives an output of the first NOR gate, and whose output is connected to the second input of the first NOR gate; a count value detecting unit, used to receive the count value, determine whether the count value is a minimum value, and output a determination result; a first NAND gate, whose first input is connected to the output of the count value detecting unit, and whose second input is connected to the output of the second NOR gate; a first NOT gate, whose input is connected to the output of the first NAND gate, and whose output provides the clock pulse signal; and the counting direction control module includes a set end, a clock end and an output end, whose set end receives the second detection signal, whose clock end receives a delayed signal of the first detection signal, and whose output provides the counting control signal.

[0013] Optionally, the switch node detection circuit includes a first threshold detection circuit, which includes a first pull-up module and a voltage detection module, which are sequentially connected between the power supply voltage and the switch node, and their common node provides a detection voltage; an output module, used to output the first detection signal according to the detection voltage, wherein the first pull-up module is used to pull up the detection voltage to a first level when the voltage of the switch node has not dropped to the first threshold voltage; the voltage detection module is used to generate a pull-down current to pull down the detection voltage to a second level when the voltage of the switch node drops to the first threshold voltage, so that the output module outputs a valid first detection signal.

[0014] Optionally, the voltage detection module includes a high-voltage transistor, a control end receiving a power supply voltage, and a first end connected to the switch node; a first transistor, a first end connected to the first pull-up module, a second end connected to the second end of the high-voltage transistor, and a control end receiving a bias voltage, wherein the first threshold voltage can be set by setting the bias voltage; a clamp transistor, a first end connected to the second end of the first transistor, and the second end and the control end connected to a ground end; the output module includes an inverting Schmitt trigger and a second NOT gate, which are sequentially connected between a common node of the first pull-up module and the voltage detection module and an output end of the first detection signal.

[0015] Optionally, the switch node detection circuit also includes a second threshold detection circuit, which includes a high-voltage transistor, a control end receiving a power supply voltage, and a first end connected to the switch node; an inverter, a high-voltage power supply end connected to the power supply voltage, a low-voltage power supply end connected to the ground end via a second transistor, and an input end receiving a pulse width modulation signal; a third NOT gate, an input end connected to the output end of the inverter; a trigger connected to the output end of the third NOT gate, and used to output a valid second detection signal when the output signal of the third NOT gate is a first level, and to output an invalid second detection signal when the output signal of the third NOT gate is a second level; a second pull-up module, used to pull up the output signal of the inverter when the path between the low-voltage power supply end and the ground end of the inverter is disconnected, wherein the control end of the second transistor is connected to the second end of the high-voltage transistor.

[0016] According to another aspect of the present invention, a buck converter is provided, comprising a main switch tube and a synchronous switch tube, which are sequentially connected between an input voltage and a ground terminal, wherein a common node of the main switch tube and the synchronous switch tube is a switch node; a comparator, which is used to compare a feedback voltage of an output voltage with a reference voltage, and to generate a pulse width modulation signal according to a comparison result; a logic control circuit, which is used to output a first control signal for controlling the main switch tube to be turned on and off and a second control signal for controlling the synchronous switch tube to be turned on and off; and a dead time control circuit as described above.

[0017] The dead time control circuit for a buck converter and the buck converter provided by the present invention are used to control the dead time between the turn-off of a synchronous switch tube and the turn-on of a main switch tube. The dead time control circuit includes a switch node detection circuit, which is used to detect the voltage of the switch node and generate a valid first detection signal when the voltage of the switch node drops to a first threshold voltage; a dead time adjustment circuit, which is used to generate the effective edge of a clock pulse signal at the effective edge of the first detection signal, and count the number of effective edges of the clock pulse signal in multiple consecutive switching cycles to obtain a count value, and adaptively adjust the size of the dead time according to the count value, so that an ideal dead time can be obtained in a steady state. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 A circuit diagram of a buck converter according to the prior art is shown;

[0020] Figure 2 A circuit diagram of a buck converter according to an embodiment of the present invention is shown;

[0021] Figure 3 A circuit schematic diagram of a dead time adjustment circuit according to an embodiment of the present invention is shown;

[0022] Figure 4 A circuit diagram of a switch node detection circuit according to an embodiment of the present invention is shown;

[0023] Figure 5 FIG. 4 is a timing diagram of a buck converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0025] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0026] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0027] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0028] Figure 2 A circuit diagram of a buck converter according to an embodiment of the present invention is shown.

[0029] See also Figure 2 The buck converter 200 provided in the embodiment of the present invention adopts a buck topology. The buck converter 200 includes a power circuit and a control circuit. The power circuit includes a main switch tube MH and a synchronous switch tube ML connected in series between the input terminal and the ground terminal of the buck converter 200, a power element L and a capacitor Cout connected in series between the switch node SW and the ground terminal, and a load R connected in parallel with the capacitor Cout. The intermediate node between the power element L and the capacitor Cout is the output terminal of the buck converter 200, the output terminal of the buck converter 200 provides an output voltage Vout, and the input terminal of the buck converter 200 receives an input voltage Vin.

[0030] In addition, the buck converter 200 further includes a voltage divider network composed of resistors R1 and R2, which is used to obtain a feedback voltage Vfb of the output voltage Vout.

[0031] The switch node SW is the middle node of the main switch tube MH and the synchronous switch tube ML. When the main switch tube MH and the synchronous switch tube ML are both turned off, the voltage of the switch node SW drops until it is less than the first threshold voltage. When the main switch tube MH is turned on and the synchronous switch tube ML is turned off, the voltage of the switch node SW rises until it is greater than the second threshold voltage. When the main switch tube MH is turned off and the synchronous switch tube ML is turned on, the voltage of the switch node SW is between the first threshold voltage and the second threshold voltage. Therefore, the working state of the main switch tube MH and the synchronous switch tube ML can be determined by detecting the voltage of the switch node SW.

[0032] The control circuit includes an amplifier 210, a dead time control circuit, a logic control circuit 240 and a drive circuit 250. The dead time control circuit is used to control the dead time between the turn-off of the synchronous switch tube ML and the turn-on of the main switch tube MH. The dead time control circuit includes a switch node detection circuit 220 and a dead time adjustment circuit 230.

[0033] The amplifier 210 is used to compare the feedback voltage Vfb of the output voltage Vout with the reference voltage Vref, and generate a pulse width modulation signal PWM according to the comparison result. The amplifier 210 has a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal receives the reference voltage Vref, the negative input terminal receives the feedback voltage Vfb, and the output terminal provides the pulse width modulation signal PWM.

[0034] The switch node detection circuit 220 is used to detect the voltage of the switch node SW, and generate a valid first detection signal SW_low when the voltage of the switch node SW drops to a first threshold voltage, and generate a valid second detection signal SW_high when the voltage of the switch node SW rises to a second threshold voltage, and generate an invalid second detection signal SW_high when the pulse width modulation signal PWM flips to a second level. Wherein, when the voltage of the switch node SW drops to the first threshold voltage, the pulse width modulation signal PWM is generally at a first level. The second threshold voltage is greater than the first threshold voltage. The first level is, for example, a high level, and the second level is, for example, a low level. The first detection signal SW_low and the second detection signal SW_high are, for example, valid at a high level.

[0035] The dead time adjustment circuit 230 is used to generate the effective edge of the clock pulse signal clk at the effective edge of the first detection signal SW_low, and count the number of effective edges of the clock pulse signal clk in multiple consecutive cycles to obtain the count value V_d, and adaptively adjust the size of the dead time according to the count value V_d. During the dead time, the main switch tube MH and the synchronous switch tube ML are both turned off. Among them, the effective edge of the first detection signal SW_low refers to its rising edge. The effective edge of the clock pulse signal clk is delayed by a setting time t1 relative to the effective edge of the first detection signal SW_low, and the effective edge of the clock pulse signal clk refers to its rising edge.

[0036] The dead time adjustment circuit 230 is further used to generate a count control signal high_before_low_d according to the delay signal SW_low_d of the first detection signal and the second detection signal SW_high, and perform addition calculation or subtraction calculation on the effective edge of the clock pulse signal clk according to the count control signal high_before_low_d. When the count control signal high_before_low_d is at a first level, the dead time adjustment circuit 230 performs addition counting on the effective edge of the clock pulse signal clk, and when the count control signal high_before_low_d is at a second level, the dead time adjustment circuit 230 performs subtraction counting on the effective edge of the clock pulse signal clk.

[0037] The logic control circuit 240 is used to receive the pulse width modulation signal PWM and the on signal en_hs_on of the main switch tube MH, and output a first control signal hs_ctrl and a second control signal ls_ctrl. The first control signal hs_ctrl is used to control the on and off of the main switch tube MH, and the second control signal ls_ctrl is used to control the on and off of the synchronous switch tube ML.

[0038] In addition, in other embodiments of the present invention, the dead time control circuit 230 may also directly provide the driving unit 251 with the turn-on signal en_hs_on of the main switch tube MH. In this case, the first control signal hs_ctrl output by the logic control circuit 240 is only used to control the turn-off of the main switch tube MH.

[0039] The driving circuit 250 includes a driving unit 251 and a driving unit 252. The driving unit 251 is used to drive the main switch MH to turn on and off according to the first control signal hs_ctrl, and the driving unit 252 is used to drive the synchronous switch ML to turn on and off according to the second control signal ls_ctrl.

[0040] Figure 3 A circuit diagram of a dead time adjustment circuit according to an embodiment of the present invention is shown.

[0041] See also Figure 3 The dead time adjustment circuit 230 includes a delay module 231 , a clock signal generation module 232 , a counting direction control module 233 , a counting module 234 and a time adjustment module 235 .

[0042] The delay module 231 receives the pulse width modulation signal PWM and the first detection signal SW_low, and is used to delay the rising edge of the first detection signal SW_low by a set time t1 according to the pulse width modulation signal PWM, so as to obtain the delayed signal SW_low_d of the first detection signal. Specifically, when the pulse width modulation signal PWM is at a high level, the delay module 231 delays the rising edge of the first detection signal SW_low by a set time t1, so that the rising edge of the delayed signal SW_low_d of the first detection signal is delayed by a set time t1 compared with the rising edge of the first detection signal SW_low, and the falling edge of the delayed signal SW_low_d of the first detection signal is synchronized with the falling edge of the first detection signal SW_low. The set time t1 is the minimum dead time between the turning off of the synchronous switch tube ML and the turning on of the main switch tube MH. The set time t1 is, for example, 3ns.

[0043] The delay module 231 includes a NAND gate 231a, a NOT gate 231b and a rising edge delay unit 231c. The first input terminal and the second input terminal of the NAND gate 231a receive the pulse width modulation signal PWM and the first detection signal SW_low respectively. The input terminal of the NOT gate 231b is connected to the output terminal of the NAND gate 231a. The input terminal of the rising edge delay unit 231c is connected to the output terminal of the NOT gate 231b, and the output terminal of the rising edge delay unit 231c provides a delayed signal SW_low_d of the first detection signal.

[0044] The clock signal generating module 232 is used to generate a clock pulse signal clk according to the delayed signal SW_low_d of the first detection signal, the inverted signal of the pulse width modulation signal PWM, and the second detection signal SW_high. In addition, the generation of the clock pulse signal clk is also related to the count value V_d. Specifically, when the effective edge of the delayed signal SW_low_d of the first detection signal arrives, if the count value V_d is not the minimum value, the pulse width modulation signal PWM is at a high level, and the second detection signal SW_high is at a low level, the clock signal generating module 232 generates a rising edge of the clock pulse signal clk, and then if any condition changes, the clock pulse signal clk flips to a low level.

[0045] The clock signal generating module 232 includes a NOR gate 232a, a NOR gate 232b, a NAND gate 232c, a NOT gate 232d and a count value detecting unit 232e. The count value detecting unit 232e is used to determine whether the count value V_d is the minimum value and output the determination result. The first input end of the NOR gate 232a receives the delayed signal SW_low_d of the first detection signal, and the second input end is connected to the output end of the NOR gate 232b. The first to second input ends of the NOR gate 232b receive the second detection signal SW_high and the inverted signal of the pulse width modulation signal PWM respectively, and the third input end is connected to the output end of the NOR gate 232a. The first input end and the second input end of the NAND gate 232c are respectively connected to the output end of the count value detecting unit 232e and the output end of the NOR gate 232b. The input end of the NOT gate 232d is connected to the output end of the NAND gate 232c, and the output end provides the clock pulse signal clk. Among them, the count value V_d is, for example, a three-digit binary digit, whose maximum value is represented by 111 and the minimum value is represented by 000. The count value detection unit 232e is, for example, implemented by a three-input AND gate, and the three-digit binary digit of the count value V_d is respectively input to the three input terminals of the AND gate, so that when the count value V_d is the minimum value, a low-level signal is output, and when the count value V_d is not the minimum value, a high-level signal is output.

[0046] The counting direction control module 233 is used to generate a counting control signal high_before_low_d according to the delayed signal SW_low_d of the first detection signal and the second detection signal SW_high. Specifically, when the delayed signal SW_low_d of the first detection signal has a rising edge, the second detection signal SW_high is output as the counting control signal high_before_low_d. In addition, the counting direction control module 233 is also used to reset when the enable signal EN is at a high level.

[0047] The counting direction control module 233 has a setting terminal D, a clock terminal , reset terminal Reset and output terminal Q, the set terminal D receives the second detection signal SW_high, the clock terminal The delay signal SW_low_d of the first detection signal is received, the reset terminal Reset receives the enable signal EN, and the output terminal Q provides a counting control signal high_before_low_d.

[0048] The counting module 234 is used to count the effective edges of the clock pulse signal clk according to the level state of the counting control signal high_before_low_d to obtain the count value V_d. Specifically, the counting module 234 is used to count the effective edges of the clock pulse signal clk when the effective edge of the clock pulse signal clk arrives, if the counting control signal high_before_low_d is at a high level, then add the effective edges of the clock pulse signal clk, if the counting control signal high_before_low_d is at a low level, then the count value V_d subtracts the effective edges of the clock pulse signal clk.

[0049] The time adjustment module 235 is used to generate a turn-on signal en_hs_on for controlling the turn-on time of the main switch tube MH according to the control signal ls_ctrl of the synchronous switch tube ML and the count value V_d. Specifically, when the control signal ls_ctrl indicates that the synchronous switch tube ML is turned off, if the received count value V_d changes, the turn-on signal en_hs_on of the main switch tube MH is output after a delay time t2 after receiving the change in the count value V_d, wherein the time length of time t2 (t2≥0) changes with the count value V_d, and the larger the count value V_d, the longer the time t2. The dead time t=t1+t2 between the turn-off of the synchronous switch tube ML and the turn-on of the main switch tube MH.

[0050] Among them, the initial value of the count value V_d is generally the maximum value, and its initial value generally controls the time adjustment module 235 to make the time t2 greater than the maximum adjustment time required by the buck converter 200. Therefore, it will not exist that when the count value V_d is 111, it is necessary to continue to increase the second time t2. When the count value V_d is 000, it means that the time t2 is the minimum value and cannot be reduced any further, which means that there is no need to adjust the dead time. Therefore, at this time, the clock pulse signal clk needs to be in a low level state all the time.

[0051] In addition, the counting module 234 also receives an enable signal EN, so as to be reset when the enable signal EN is at a high level.

[0052] Figure 4 A circuit diagram of a switch node detection circuit according to an embodiment of the present invention is shown.

[0053] See also Figure 4 The switch node detection circuit 220 includes a first threshold detection circuit 221 and a second threshold detection circuit 222. The first threshold detection circuit 221 receives an enable signal EN and is started when the enable signal EN is at a high level, and is reset when the enable signal EN is at a low level.

[0054] The first threshold detection circuit 221 is used for detecting the voltage of the switch node SW, and generating a valid first detection signal SW_low when the voltage of the switch node SW drops to a first threshold voltage.

[0055] The first threshold detection circuit 221 includes a bias voltage generating module 221 a , a reset module 221 b , a voltage detection module 221 c , an output module 221 d and a pull-up module 221 e .

[0056] The bias voltage generating module 221a is used to generate a bias voltage Vbias according to an enable signal EN. The reset module 221b is used to reset the first threshold detection circuit 221 according to the enable signal EN.

[0057] The pull-up module 221e and the voltage detection module 221c are connected between the power supply voltage VDD and the switch node SW, and their common node A provides a detection voltage. The voltage detection module 221c is used to generate a pull-down current to pull down the detection voltage to a low level when the voltage of the switch node SW drops to a first threshold voltage. The pull-up module 221e is used to pull up the detection voltage to a high level when the voltage of the switch node SW does not drop to the first threshold voltage. The output module 221d is used to generate a first detection signal SW_low according to the detection voltage.

[0058] The pull-up module 221e is implemented by, for example, a pull-up resistor R5, and when the voltage of the switch node SW does not drop to the first threshold voltage, it pulls up the detection voltage to make it at a high level. The pull-up module 221e can also be implemented by a current source, and when the voltage of the switch node SW does not drop to the first threshold voltage, it pulls up the detection voltage to make it at a high level. When the voltage detection module 221c generates a pull-down current, the detection voltage is pulled down to a low level.

[0059] The bias voltage generating module 221a includes a transistor Mp1, a resistor R3, a transistor Mn1 and a transistor Mn3 connected in series between a power supply voltage VDD and a ground terminal VSS, and a transistor Mn2, a resistor R4 and a transistor Mn4 connected in series between the power supply voltage VDD and the ground terminal VSS, wherein the control end of the transistor Mp1 receives an enable signal EN, the control ends of the transistors Mn1 and Mn2 are connected to a common node of the resistor R3 and the transistor Mn1, the control ends of the transistors Mn3 and Mn4 are connected to an intermediate node of the transistor Mn1 and the transistor Mn3, and the common node of the resistor R4 and the transistor Mn4 provides a bias voltage Vbias. The bias voltage Vbias=Vgs1-I*R4, wherein Vgs1 represents a voltage difference between the control end and the second end of the transistor Mn1, the transistors Mn1-Mn4 have the same size, and I*R4 represents a voltage drop of the resistor R4.

[0060] The reset module 221b includes transistors Mn7-Mn9. Transistor Mn7 is connected between the control terminal of transistor Mn1 and the ground terminal VSS, transistor Mn8 is connected between the control terminal of transistor Mn3 and the ground terminal VSS, transistor Mn9 is connected between the bias voltage Vbias and the ground terminal VSS, and the control terminals of transistors Mn7-Mn9 are connected to the enable signal EN.

[0061] The voltage detection module 221c includes a transistor Mn5 and a high-voltage transistor MH1 connected between the node A and the switch node SW, the control end of the high-voltage transistor MH1 is connected to the power supply voltage VDD, and the control end of the transistor Mn5 receives the bias voltage Vbias. The first threshold voltage can be set by the bias voltage Vbias, and specifically, the voltage difference between the bias voltage Vbias and the first threshold voltage is equal to the threshold voltage Vth5 of the transistor Mn5.

[0062] Furthermore, the voltage detection module 221c further includes a clamping transistor Mn6, which is connected between the common node of the transistor Mn5 and the high-voltage transistor MH1 and the ground terminal, and has a control terminal connected to the ground terminal. The transistor Mn6 is used to clamp the voltage of the common node of the transistor Mn5 and the high-voltage transistor MH1 so that it is not greater than the power supply voltage VDD.

[0063] The output module 221d includes an inverting Schmitt trigger 221d_1 and a NOT gate 221d_2 which are connected in series between the node A and the output terminal of the first detection signal SW_low.

[0064] When the enable signal EN is at a high level, the bias voltage generating module 221a generates a bias voltage Vbias. When the main switch tube MH is turned off, the high-voltage transistor MH1 is turned on, and the voltage of the switch node SW is provided to the second end of the transistor Mn5. When the voltage of the switch node SW drops to the first threshold voltage, the transistor Mn5 is turned on to generate a pull-down current, and the detection voltage is pulled down to a low level, so that the level of the inverting Schmitt trigger 221d_1 is flipped, so that the NOT gate 221d_2 outputs a valid first detection signal SW_low. When the enable signal EN is at a low level, the reset transistors Mn7-Mn9 are turned on to reset the first threshold detection circuit 221.

[0065] The second threshold detection circuit 222 is used to detect the voltage of the switch node SW, and generates a valid second detection signal SW_high when the pulse width modulation signal PWM is at a high level and the voltage of the switch node SW rises to a second threshold voltage, and outputs an invalid second detection signal SW_high when the pulse width modulation signal PWM is at a low level.

[0066] The second threshold detection circuit 222 includes a high-voltage transistor MH1, a transistor Mn10, an inverter 222a, a pull-up module 222b, a NOT gate 222c, and a trigger 222d. The control end of the high-voltage transistor MH1 is connected to the power supply voltage VDD, the first end is connected to the switch node SW, and the second end is connected to the control end of the transistor Mn10, wherein the first threshold detection circuit 221 and the second threshold detection circuit 222 can share the high-voltage transistor MH1. The high-voltage power supply end of the inverter 222a is connected to the power supply voltage VDD, and the low-voltage power supply end is connected to the ground end VSS through the transistor Mn10. The control end of the transistor Mn10 is connected to the second end of the high-voltage transistor MH1. The input end of the inverter 222a receives the pulse width modulation signal PWM, and the output end is connected to the input end of the NOT gate 222c. The trigger 222d has a set end D, a clock end CLK, and an output end Q, wherein the set end D is connected to the power supply voltage VDD, the clock end CLK is connected to the output end of the inverter 222c, and the output end Q provides the second detection signal SW_high. The pull-up module 222 b is connected between the power supply voltage VDD and the output terminal of the inverter 222 a .

[0067] The inverter 222 a includes transistors Mp2 and Mn11 connected in series between a power supply voltage VDD and a first terminal of the transistor Mn10 , and control terminals of the transistors Mp2 and Mn11 receive a pulse width modulation signal PWM.

[0068] After the main switch MH is turned on, the voltage of the switch node SW starts to rise. When the voltage of the switch node SW rises to VDD-Vth_h1 (Vth_h1 represents the threshold voltage of the high-voltage transistor MH1), that is, the second threshold voltage, the high-voltage transistor MH1 is turned off, and the transistor Mn10 is turned on, so that the path between the low-voltage power supply terminal of the inverter 222a and the ground terminal VSS is turned on, so that the inverter 222a works normally, and the high-level pulse width modulation signal PWM is inverted and output to the input terminal of the non-gate 222c, and then the non-gate 222c outputs a high-level signal to control the trigger 222d to output a valid second detection signal SW_high. When the pulse width modulation signal PWM is at a low level, it outputs a low-level signal after passing through the inverter 222a and the non-gate 222c to control the trigger 222d to output an invalid second detection signal SW_high.

[0069] Figure 5 FIG. 4 is a timing diagram of a buck converter according to an embodiment of the present invention.

[0070] See also Figure 5When the pulse width modulation signal PWM flips to a high level, the second control signal ls_ctrl flips to a low level, the synchronous switch tube ML is turned off, the voltage of the switch node SW drops to the first threshold voltage, and the first detection signal SW_low flips to a high level. Although in theory the pulse width modulation signal PWM flips to a high level and the first detection signal SW_low flips to a high level synchronously, in practice there will be a certain delay due to various factors.

[0071] After the first detection signal SW_low turns to a high level, after a set time t1, the delay signal SW_low_d of the first detection signal turns to a high level, and at the same time, the clock pulse signal clk turns to a high level, and after a second time t2, the turn-on signal en_hs_on of the main switch tube MH turns to a high level. Although in theory the dead time between the turn-off of the synchronous switch tube ML and the turn-on of the main switch tube MH is t=t1+t2, in reality there is a certain delay from the generation of the turn-on signal en_hs_on of the main switch tube MH to the turn-on of the main switch tube MH, and the delay from the turn-off of the synchronous switch tube ML to the turn-on of the delay signal SW_low_d of the first detection signal is also slightly greater than the first time t1, so the actual dead time is Tdt1 / Tdt2.

[0072] When the pulse width modulation signal PWM flips to a low level, the second detection signal SW_high flips to a low level, the first control signal hs_ctrl flips to a low level, the main switch tube MH is turned off, the voltage of the switch node SW drops to the first threshold voltage, the first detection signal SW_low flips to a high level, and after a preset time delay, the second control signal hs_ctrl flips to a high level, and the synchronous switch tube ML is turned on. The dead time between the turning off of the main switch tube MH and the turning on of the synchronous switch tube ML can be set to a fixed value by the logic control circuit 240, that is, Figure 5 Tdt3 is used in this study.

[0073] Optionally, the transistors Mn1 to Mn11 and the high-voltage transistor MH1 are N-type MOS (Metal-Oxide-Semiconductor) transistors, wherein the first end of the NMOS transistor is a drain end, the second end is a source end, and the control end is a gate end.

[0074] Optionally, the transistors Mp1-Mp2 are PMOS transistors, wherein the first end of the PMOS transistor is a source end, the second end is a drain end, and the control end is a gate end.

[0075] The buck converter and its dead time control circuit provided by the present invention are used to control the dead time between the turn-off of the synchronous switch tube and the turn-on of the main switch tube. The dead time control circuit includes a switch node detection circuit, which is used to detect the voltage of the switch node and generate a valid first detection signal when the voltage of the switch node drops to a first threshold voltage; a dead time adjustment circuit, which is used to generate the effective edge of the clock pulse signal at the effective edge of the first detection signal, and count the number of effective edges of the clock pulse signal in multiple consecutive switching cycles to obtain a count value, and adaptively adjust the size of the dead time according to the count value, so that an ideal dead time can be obtained in a steady state.

[0076] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A dead time control circuit for a buck converter, the buck converter comprising a main switch tube and a synchronous switch tube connected in series between a power supply voltage and a ground terminal, the common node of the main switch tube and the synchronous switch tube being a switch node, the dead time control circuit being used to control the dead time between the turning off of the synchronous switch tube and the turning on of the main switch tube, the dead time control circuit comprising: a switch node detection circuit, configured to detect a voltage of the switch node and generate a valid first detection signal when the voltage of the switch node drops to a first threshold voltage; A dead time adjustment circuit is used to generate an effective edge of a clock pulse signal at the effective edge of the first detection signal, and count the number of effective edges of the clock pulse signal in multiple consecutive switching cycles to obtain a count value, and adaptively adjust the size of the dead time according to the count value.

2. The dead time control circuit according to claim 1, wherein: The effective edge of the clock pulse signal is delayed by a set time relative to the effective edge of the first detection signal.

3. The dead time control circuit according to claim 2, wherein: The switch node detection circuit is further configured to generate a valid second detection signal when the voltage of the switch node rises to a second threshold voltage, and to generate an invalid second detection signal when the pulse width modulation signal flips to a second level, wherein the second threshold voltage is greater than the first threshold voltage. The dead time adjustment circuit is used to generate a count control signal according to the delay signal of the first detection signal and the second detection signal, and to perform addition counting or subtraction counting on the effective edge of the clock pulse signal according to the count control signal.

4. The dead time control circuit according to claim 3, wherein: The dead time adjustment circuit performs addition counting on the effective edges of the clock pulse signal when the count control signal is at a first level, and performs subtraction counting on the effective edges of the clock pulse signal when the count control signal is at a second level.

5. The dead time control circuit according to claim 4, wherein: The dead time adjustment circuit comprises: A clock signal generating module, configured to generate the clock pulse signal according to the delayed signal of the first detection signal, the inverted signal of the pulse width modulation signal and the second detection signal; a counting direction control module, configured to generate the counting control signal according to the delayed signal of the first detection signal and the second detection signal; A counting module, used for counting the effective edges of the clock pulse signal according to the level state of the counting control signal to obtain a counting value; The time adjustment module is used to generate a turn-on signal for controlling the turn-on time of the main switch tube according to the control signal of the synchronous switch tube and the count value.

6. The dead time control circuit according to claim 5, wherein: The clock signal generating module comprises: A first NOR gate, a first input terminal of which receives a delayed signal of the first detection signal; A second NOR gate, having a first input terminal receiving the second detection signal, a second input terminal receiving the inverted signal of the pulse width modulation signal, a third input terminal receiving the output terminal of the first NOR gate, and an output terminal connected to the second input terminal of the first NOR gate; A count value detection unit, used for receiving the count value, determining whether the count value is a minimum value, and outputting a determination result; A first NAND gate, a first input end of which is connected to the output end of the count value detection unit, and a second input end of which is connected to the output end of the second NOR gate; A first NOT gate, whose input end is connected to the output end of the first NAND gate and whose output end provides the clock pulse signal, The counting direction control module comprises a setting end, a clock end and an output end, wherein the setting end receives the second detection signal, the clock end receives a delayed signal of the first detection signal, and the output end provides the counting control signal.

7. The dead time control circuit according to claim 1, wherein: The switch node detection circuit includes a first threshold detection circuit, and the first threshold detection circuit includes: A first pull-up module and a voltage detection module are sequentially connected between the power supply voltage and the switch node, and a common node thereof provides a detection voltage; an output module, configured to output the first detection signal according to the detection voltage, Among them, the first pull-up module is used to pull up the detection voltage to the first level when the voltage of the switch node has not dropped to the first threshold voltage; the voltage detection module is used to generate a pull-down current to pull down the detection voltage to the second level when the voltage of the switch node drops to the first threshold voltage, so that the output module outputs a valid first detection signal.

8. The dead time control circuit according to claim 7, wherein: The voltage detection module comprises: A high-voltage transistor, a control end receiving a power supply voltage and a first end connected to the switch node; A first transistor, a first end of which is connected to the first pull-up module, a second end of which is connected to the second end of the high-voltage transistor, and a control end of which receives a bias voltage, wherein the first threshold voltage can be set by setting the bias voltage; A clamping transistor, a first end of which is connected to the second end of the first transistor, and a second end and a control end are connected to a ground end; The output module comprises: The inverting Schmitt trigger and the second NOT gate are sequentially connected between a common node of the first pull-up module and the voltage detection module and an output end of the first detection signal.

9. The dead time control circuit according to claim 7, wherein: The switch node detection circuit further includes a second threshold detection circuit, wherein the second threshold detection circuit includes: A high-voltage transistor, a control end receiving a power supply voltage and a first end connected to the switch node; An inverter, wherein the high voltage supply terminal is connected to the power supply voltage, the low voltage supply terminal is connected to the ground terminal via the second transistor, and the input terminal receives a pulse width modulation signal; A third NOT gate, an input end of which is connected to the output end of the inverter; a trigger connected to the output end of the third NOT gate, and configured to output a valid second detection signal when the output signal of the third NOT gate is at a first level, and to output an invalid second detection signal when the output signal of the third NOT gate is at a second level; The second pull-up module is used to pull up the output signal of the inverter when the path between the low-voltage power supply terminal and the ground terminal of the inverter is disconnected. Wherein, the control end of the second transistor is connected to the second end of the high-voltage transistor.

10. A buck converter, comprising: The main switch tube and the synchronous switch tube are connected between the input voltage and the ground terminal in sequence, and the common node of the main switch tube and the synchronous switch tube is the switch node; A comparator, used for comparing a feedback voltage of an output voltage with a reference voltage, and generating a pulse width modulation signal according to a comparison result; A logic control circuit, used for outputting a first control signal for controlling the main switch tube to be turned on and off and a second control signal for controlling the synchronous switch tube to be turned on and off; and The dead time control circuit according to any one of claims 1 to 9.

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