Low-voltage charge pump circuit and control method thereof

Abstract

The invention discloses a low-voltage charge pump circuit and a control method thereof, and relates to the technical field of power management. Comprising an inverter INV, a charge pump main body structure and an output capacitor COUT. The closed state of a first N-type MOS tube MN1 and a first parasitic diode D1 thereof, the closed state of a second N-type MOS tube MN2 and a third parasitic diode D3 thereof, the closed state of a first P-type MOS tube MP1 and a second parasitic diode D2 thereof, and the closed state of a second P-type MOS tube MP2 and a fourth parasitic diode D4 thereof are controlled through the input voltage of an input port IN and the output voltage of a phase inverter INV, so that the voltage at an X node and the voltage at a Y node are changed. And the output voltage of the output port OUT is charged through the charges stored in the X node and the Y node. The charge pump is simple in structure, can realize self-starting, and can be widely applied to power supply management circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and in particular to a low-voltage charge pump circuit and a control method thereof. Background Art

[0002] Charge pumps are used to quickly charge mobile devices and can be used to drive LCDs and LEDs. In common power chips, charge pumps are used as MOS tube gate drivers. Capacitive charge pumps achieve voltage boost through switch arrays and oscillators, logic circuits, and comparison controllers, and use capacitors to store energy.

[0003] In the prior art, the voltage doubling charge pump circuit is mainly used, and its principle is: based on the charging and discharging of capacitors and charge migration; through periodic charge transfer, the input voltage is gradually accumulated to the output capacitor, thereby achieving voltage doubling. Specifically, the charge pump usually consists of a switch and two capacitors. When the switch is opened under the action of a clock pulse, the charge in the input capacitor will be transferred to the output capacitor; when the switch is closed, the charge in the output capacitor is locked and saved. The charge in the input capacitor will be transferred to the output capacitor to achieve voltage doubling.

[0004] The defects of the above-mentioned prior art are: in the process of voltage doubling, due to the switching of the switch and the charging and discharging of the capacitor, energy loss will be generated, resulting in a decrease in the overall efficiency of the circuit. Summary of the invention

[0005] Based on this, it is necessary to provide a low-voltage charge pump circuit and a control method thereof to address the above technical problems.

[0006] The embodiment of the present invention provides a low voltage charge pump circuit, comprising: an inverter INV, a charge pump main structure and an output capacitor C OUT ; The charge pump main structure includes: a first N-type MOS transistor MN1 and its first parasitic diode D1, a second N-type MOS transistor MN2 and its third parasitic diode D3, a first P-type MOS transistor MP1 and its second parasitic diode D2, a second P-type MOS transistor MP2 and its fourth parasitic diode D4, a first capacitor C1 and a third capacitor C3; The source end of the first N-type MOS transistor MN1 and the source end of the second N-type MOS transistor MN2 are both connected to the input port IN; the source end of the first P-type MOS transistor MP1 and the source end of the second P-type MOS transistor MP2 are both connected to the output port OUT; The input end of the inverter INV is connected to the lower plate of the first capacitor C1, and the upper plate of the first capacitor C1 is connected to the drain end of the first N-type MOS transistor MN1, the drain end of the first P-type MOS transistor MP1, the gate end of the second N-type MOS transistor MN2, and the gate end of the second P-type MOS transistor MP2 to form an X node; the output end of the inverter INV is connected to the lower plate of the third capacitor C3, and the upper plate of the third capacitor C3 is connected to the drain end of the second P-type MOS transistor MP2, the drain end of the second N-type MOS transistor MN2, the gate end of the first N-type MOS transistor MN1, and the gate end of the first P-type MOS transistor MP1 to form a Y node.

[0007] Optionally, it further includes a second capacitor C2 and a fourth capacitor C4; the input end of the inverter INV is also connected to the upper plate of the second capacitor C2, and the lower plate of the second capacitor C2 is grounded; The output end of the inverter INV is also connected to the upper plate of the fourth capacitor C4, and the lower plate of the fourth capacitor C4 is grounded.

[0008] Optionally, the anode of the first parasitic diode D1 is connected to the source terminal of the first N-type MOS transistor MN1, and the cathode of the first parasitic diode D1 is connected to the drain terminal of the first N-type MOS transistor MN1; The anode of the second parasitic diode D2 is connected to the drain terminal of the first P-type MOS transistor MP1, and the cathode of the second parasitic diode D2 is connected to the source terminal of the first P-type MOS transistor MP1; An anode of the third parasitic diode D3 is connected to the source end of the second N-type MOS transistor MN2, and a cathode of the third parasitic diode D3 is connected to the drain end of the second N-type MOS transistor MN2; An anode of the fourth parasitic diode D4 is connected to the drain terminal of the second P-type MOS transistor MP2 , and a cathode of the fourth parasitic diode D4 is connected to the source terminal of the second P-type MOS transistor MP2 .

[0009] Optionally, the source end of the first P-type MOS transistor MP1 is also connected to an output capacitor C OUT The upper plate, output capacitor C OUT The lower plate is grounded.

[0010] An embodiment of the present invention further provides a control method for a low-voltage charge pump circuit, comprising: In the power-on stage, the input voltage VIN is input through the input port IN, the first N-type MOS transistor MN1, the first P-type MOS transistor MP1, the second N-type MOS transistor MN2, and the second P-type MOS transistor MP2 are closed, and the input voltage VIN charges the output voltage VOUT of the output port OUT through the first parasitic diode D1, the second parasitic diode D2, the third parasitic diode D3, and the fourth parasitic diode D4; The voltage drops of the first parasitic diode D1, the second parasitic diode D2, the third parasitic diode D3 and the fourth parasitic diode D4 are Vdiode. When the inverting signal CLKN is at a low level, the voltage at the X node is VIN-Vdiode. When the inverting signal CLKN is at a high level, the voltage at the X node is raised to 2*VIN-Vdiode. When the clock input signal CLK is at a low level, the voltage at the Y node is 2*VIN-Vdiode. When the clock input signal CLK is at a high level, the voltage at the Y node is raised to 2*VIN-Vdiode. The output voltage VOUT is continuously charged to 2*VIN-2*Vdiode by the charges stored in the X node and the Y node through the second parasitic diode D2 and the fourth parasitic diode D4.

[0011] When the power supply voltage reaches a value of 2*VIN-Vdiode, the first N-type MOS transistor MN1, the first P-type MOS transistor MP1, the second N-type MOS transistor MN2 and the second P-type MOS transistor MP2 are fully turned on; When the inverting signal CLKN is at a low level and the clock input signal CLK is at a high level, the voltage at the Y node in the previous power-on stage is raised through the diode path, so that the first N-type MOS transistor MN1 is fully turned on, and the voltage at the X node is VIN. Since the voltage at the Y node has been raised at this time, the second P-type MOS transistor MP2 is also fully turned on; When the inverting signal CLKN is at a high level and the clock input signal CLK is at a low level, the voltage at the X node is raised to 2*VIN, the second N-type MOS transistor MN2 is fully turned on, the voltage at the Y node is VIN, the first P-type MOS transistor MP1 is also fully turned on, and the charge stored at the X node charges the output terminal OUT; in the next cycle, the inverting signal CLKN is at a low level and the clock input signal CLK is at a high level, the voltage at the Y node is raised to 2*VIN, the first N-type MOS transistor MN2 is fully turned on, the voltage at the X node is VIN, the second P-type MOS transistor MP1 is also fully turned on, and the charge stored at the Y node charges the output terminal OUT; the output voltage VOUT is maintained at 2*VIN.

[0012] Compared with the prior art, the low-voltage charge pump circuit and control method thereof provided by the embodiment of the present invention have the following beneficial effects: In the process of voltage doubling, the present invention controls the closed states of the first N-type MOS transistor MN1 and its first parasitic diode D1, the second N-type MOS transistor MN2 and its third parasitic diode D3, the first P-type MOS transistor MP1 and its second parasitic diode D2, and the second P-type MOS transistor MP2 and its fourth parasitic diode D4 through the input voltage of the input port IN and the output voltage of the inverter INV, and accurately regulates the voltages at the X node and the Y node by utilizing the switching characteristics of the MOS transistors and the rectifying effect of the parasitic diodes; and charges the output voltage of the output port OUT through the charges stored in the X node and the Y node, thereby solving the energy loss problem caused by switch switching and capacitor charging and discharging, and improving the overall efficiency of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the structure of a low-voltage charge pump circuit provided in an embodiment. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0015] In one embodiment, a low voltage charge pump circuit is provided, such as Figure 1 As shown, the circuit includes an inverter INV, a charge pump main structure and an output capacitor C OUT .

[0016] The charge pump main structure includes: a first N-type MOS transistor MN1 and its first parasitic diode D1, a second N-type MOS transistor MN2 and its third parasitic diode D3, a first P-type MOS transistor MP1 and its second parasitic diode D2, a second P-type MOS transistor MP2 and its fourth parasitic diode D4, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4.

[0017] The source end of the first N-type MOS transistor MN1 and the source end of the second N-type MOS transistor MN2 are both connected to the input port IN; the source end of the first P-type MOS transistor MP1 and the source end of the second P-type MOS transistor MP2 are both connected to the output port OUT. The source end of the first P-type MOS transistor MP1 is also connected to the output capacitor C OUT The upper plate, output capacitor C OUT The lower plate is grounded.

[0018] The input end of the inverter INV is connected to the lower plate of the first capacitor C1, and the upper plate of the first capacitor C1 is connected to the drain end of the first N-type MOS transistor MN1, the drain end of the first P-type MOS transistor MP1, the gate end of the second N-type MOS transistor MN2, and the gate end of the second P-type MOS transistor MP2 to form an X node. The input end of the inverter INV is also connected to the upper plate of the second capacitor C2, and the lower plate of the second capacitor C2 is grounded.

[0019] The output end of the inverter INV is connected to the lower plate of the third capacitor C3, and the upper plate of the third capacitor C3 is connected to the drain end of the second P-type MOS transistor MP2, the drain end of the second N-type MOS transistor MN2, the gate end of the first N-type MOS transistor MN1, and the gate end of the first P-type MOS transistor MP1 to form a Y node. The output end of the inverter INV is also connected to the upper plate of the fourth capacitor C4, and the lower plate of the fourth capacitor C4 is grounded.

[0020] The anode of the first parasitic diode D1 is connected to the source terminal of the first N-type MOS transistor MN1, and the cathode of the first parasitic diode D1 is connected to the drain terminal of the first N-type MOS transistor MN1. The anode of the second parasitic diode D2 is connected to the drain terminal of the first P-type MOS transistor MP1, and the cathode of the second parasitic diode D2 is connected to the source terminal of the first P-type MOS transistor MP1. The anode of the third parasitic diode D3 is connected to the source terminal of the second N-type MOS transistor MN2, and the cathode of the third parasitic diode D3 is connected to the drain terminal of the second N-type MOS transistor MN2. The anode of the fourth parasitic diode D4 is connected to the drain terminal of the second P-type MOS transistor MP2, and the cathode of the fourth parasitic diode D4 is connected to the source terminal of the second P-type MOS transistor MP2.

[0021] The basic principles of the above technical solution are as follows: CLK is the clock input signal, CLKN is the inverted signal of the clock input signal CLK, and the high level is consistent with the level of the input port IN. There are two paths from the input port IN to the output port OUT, the first path is composed of the first N-type MOS transistor MN1 and the first P-type MOS transistor MP1, and the second path is composed of the second N-type MOS transistor MN2 and the second P-type MOS transistor MP2.

[0022] When the low-voltage charge pump circuit is started, it is in the power-on stage, and the input voltage VIN is input through the input port IN. The power supply voltage in the power-on stage is relatively low, and the first N-type MOS transistor MN1, the first P-type MOS transistor MP1, the second N-type MOS transistor MN2, and the second P-type MOS transistor MP2 cannot be turned on. The input voltage VIN charges the output voltage VOUT through the first parasitic diode D1, the second parasitic diode D2, the third parasitic diode D3, and the fourth parasitic diode D4.

[0023] The voltage drop of the first parasitic diode D1, the second parasitic diode D2, the third parasitic diode D3 and the fourth parasitic diode D4 is Vdiode. When the inverting signal CLKN is at a low level, the voltage at the X node is VIN-Vdiode, and when the inverting signal CLKN is at a high level, the voltage at the X node is raised to 2*VIN-Vdiode; similarly, when the clock input signal CLK is at a low level, the voltage at the Y node is 2*VIN-Vdiode, and when the clock input signal CLK is at a high level, the voltage at the Y node is raised to 2*VIN-Vdiode. Therefore, the output voltage VOUT is continuously charged to 2*VIN-2*Vdiode by the charges stored in the X node and the Y node through the second parasitic diode D2 and the fourth parasitic diode D4.

[0024] When the power supply voltage reaches a value of 2*VIN-Vdiode, the first N-type MOS transistor MN1, the first P-type MOS transistor MP1, the second N-type MOS transistor MN2 and the second P-type MOS transistor MP2 are fully turned on.

[0025] When the inverting signal CLKN is low and the clock input signal CLK is high, in the previous power-on stage, the voltage at the Y node is raised through the diode path, so that the first N-type MOS transistor MN1 is fully turned on, and the voltage at the X node is VIN. Since the voltage at the Y node has been raised at this time, the second P-type MOS transistor MP2 is also fully turned on; when the inverting signal CLKN is high and the clock input signal CLK is low, the voltage at the X node is raised to 2*VIN, the second N-type MOS transistor MN2 is fully turned on, the voltage at the Y node is VIN, the first P-type MOS transistor MP1 is also fully turned on, and the charge stored in the X node charges the output terminal OUT; in the next cycle, the inverting signal CLKN is low and the clock input signal CLK is high, the voltage at the Y node is raised to 2*VIN, the first N-type MOS transistor MN2 is fully turned on, the voltage at the X node is VIN, the second P-type MOS transistor MP1 is also fully turned on, and the charge stored in the Y node charges the output terminal OUT. This cycle is repeated to maintain the output terminal voltage at 2*VIN.

[0026] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A low voltage charge pump circuit, characterized in that: include: Inverter INV, charge pump main structure and output capacitor C OUT ; The charge pump main structure includes: a first N-type MOS transistor MN1 and its first parasitic diode D1, a second N-type MOS transistor MN2 and its third parasitic diode D3, a first P-type MOS transistor MP1 and its second parasitic diode D2, a second P-type MOS transistor MP2 and its fourth parasitic diode D4, a first capacitor C1 and a third capacitor C3; The source end of the first N-type MOS transistor MN1 and the source end of the second N-type MOS transistor MN2 are both connected to the input port IN; the source end of the first P-type MOS transistor MP1 and the source end of the second P-type MOS transistor MP2 are both connected to the output port OUT; The input end of the inverter INV is connected to the lower plate of the first capacitor C1, and the upper plate of the first capacitor C1 is connected to the drain end of the first N-type MOS transistor MN1, the drain end of the first P-type MOS transistor MP1, the gate end of the second N-type MOS transistor MN2, and the gate end of the second P-type MOS transistor MP2 to form an X node; the output end of the inverter INV is connected to the lower plate of the third capacitor C3, and the upper plate of the third capacitor C3 is connected to the drain end of the second P-type MOS transistor MP2, the drain end of the second N-type MOS transistor MN2, the gate end of the first N-type MOS transistor MN1, and the gate end of the first P-type MOS transistor MP1 to form a Y node.

2. A low voltage charge pump circuit as claimed in claim 1, characterized in that: It also includes a second capacitor C2 and a fourth capacitor C4; the input end of the inverter INV is also connected to the upper plate of the second capacitor C2, and the lower plate of the second capacitor C2 is grounded; The output end of the inverter INV is also connected to the upper plate of the fourth capacitor C4, and the lower plate of the fourth capacitor C4 is grounded.

3. A low voltage charge pump circuit as claimed in claim 1, characterized in that: The anode of the first parasitic diode D1 is connected to the source end of the first N-type MOS transistor MN1, and the cathode of the first parasitic diode D1 is connected to the drain end of the first N-type MOS transistor MN1; The anode of the second parasitic diode D2 is connected to the drain terminal of the first P-type MOS transistor MP1, and the cathode of the second parasitic diode D2 is connected to the source terminal of the first P-type MOS transistor MP1; The anode of the third parasitic diode D3 is connected to the source end of the second N-type MOS transistor MN2, and the cathode of the third parasitic diode D3 is connected to the drain end of the second N-type MOS transistor MN2; An anode of the fourth parasitic diode D4 is connected to the drain end of the second P-type MOS transistor MP2 , and a cathode of the fourth parasitic diode D4 is connected to the source end of the second P-type MOS transistor MP2 .

4. A low voltage charge pump circuit as claimed in claim 1, characterized in that: The source end of the first P-type MOS transistor MP1 is also connected to the output capacitor C OUT The upper plate of the output capacitor C OUT The lower plate is grounded.

5. A control method for a low voltage charge pump circuit according to any one of claims 1 to 4, characterized in that: include: In the power-on stage, the input voltage VIN is input through the input port IN, the first N-type MOS transistor MN1, the first P-type MOS transistor MP1, the second N-type MOS transistor MN2, and the second P-type MOS transistor MP2 are closed, and the input voltage VIN charges the output voltage VOUT of the output port OUT through the first parasitic diode D1, the second parasitic diode D2, the third parasitic diode D3, and the fourth parasitic diode D4; The voltage drops of the first parasitic diode D1, the second parasitic diode D2, the third parasitic diode D3 and the fourth parasitic diode D4 are Vdiode. When the inverting signal CLKN is at a low level, the voltage at the X node is VIN-Vdiode. When the inverting signal CLKN is at a high level, the voltage at the X node is raised to 2*VIN-Vdiode. When the clock input signal CLK is at a low level, the voltage at the Y node is 2*VIN-Vdiode. When the clock input signal CLK is at a high level, the voltage at the Y node is raised to 2*VIN-Vdiode. The output voltage VOUT is continuously charged to 2*VIN-2*Vdiode by the charges stored in the X node and the Y node through the second parasitic diode D2 and the fourth parasitic diode D4. When the power supply voltage reaches a value of 2*VIN-Vdiode, the first N-type MOS transistor MN1, the first P-type MOS transistor MP1, the second N-type MOS transistor MN2 and the second P-type MOS transistor MP2 are fully turned on; When the inverting signal CLKN is at a low level and the clock input signal CLK is at a high level, the voltage at the Y node in the previous power-on stage is raised through the diode path, so that the first N-type MOS transistor MN1 is fully turned on, and the voltage at the X node is VIN. Since the voltage at the Y node has been raised at this time, the second P-type MOS transistor MP2 is also fully turned on; When the inverting signal CLKN is at a high level and the clock input signal CLK is at a low level, the voltage at the X node is raised to 2*VIN, the second N-type MOS transistor MN2 is fully turned on, the voltage at the Y node is VIN, the first P-type MOS transistor MP1 is also fully turned on, and the charge stored at the X node charges the output terminal OUT; in the next cycle, the inverting signal CLKN is at a low level and the clock input signal CLK is at a high level, the voltage at the Y node is raised to 2*VIN, the first N-type MOS transistor MN2 is fully turned on, the voltage at the X node is VIN, the second P-type MOS transistor MP1 is also fully turned on, and the charge stored at the Y node charges the output terminal OUT; the output voltage VOUT is maintained at 2*VIN.

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