An amplifier circuit with common mode rejection

Abstract

The application discloses an amplifier circuit with common-mode rejection, and belongs to the technical field of integrated circuits.The amplifier circuit comprises a first input end, a second input end, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first output end, a second output end and a switch.The first input end and the second input end are used for inputting a differential signal to be processed.The first inverter to the eighth inverter are used for realizing common-mode rejection.The switch is used for realizing dynamic amplification processing of the differential signal.The first output end and the second output end are used for outputting the processing result of the differential signal.The application reduces the power consumption of the amplifier, and improves the common-mode rejection without affecting the performance of the amplifier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an amplifier circuit with common-mode rejection. Background Technology

[0002] High-speed, high-precision analog-to-digital converters (ADCs) have wide applications and demands in high-bandwidth real-time oscilloscopes, 5G and Wi-Fi 6 / 7 wireless communications, and high-resolution radar. Pipeline or time-interleaved pipelined ADCs are currently the mainstream architecture for high-speed, high-precision ADCs. However, pipelined architectures suffer from design complexity, high power consumption, and the need for inter-stage gain calibration. Unlike pipelined architectures, successive approximation (SAR) ADCs have a simpler structure, lower power consumption, and better robustness. However, SAR architectures are primarily suitable for high-speed, low-to-medium precision applications.

[0003] The comparator is a key module that affects the conversion speed and accuracy of SAR ADC. Currently used comparators often suffer from slow speed and high noise. To overcome these problems, a preamplifier module is usually added to the front end of the comparator, which can effectively speed up the comparator's settling speed and suppress the comparator's noise.

[0004] Inverter-based static amplifiers are widely used due to their high current efficiency, but their pseudo-differential structure results in common-mode gain being comparable to differential-mode gain, making them sensitive to common-mode variations in the circuit. Therefore, improving common-mode rejection without affecting amplifier performance, and thus better enabling their use in high-speed, high-signal-to-noise ratio SAR ADCs, is a pressing issue that needs to be addressed. Summary of the Invention

[0005] This invention provides an amplifier circuit with common-mode rejection to solve the technical problem of low common-mode rejection in existing amplifiers.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] An amplifier circuit with common-mode rejection includes: a first input terminal, a second input terminal, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first output terminal, a second output terminal, and a switch; wherein,

[0008] The first input terminal and the second input terminal are used to input the differential signal to be processed;

[0009] The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, and the switch are used to process the input differential signal; wherein, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter implement common-mode rejection, and the switch implements dynamic amplification of the differential signal;

[0010] The first output terminal and the second output terminal are used to output the processing results of the differential signal.

[0011] Furthermore, the output terminal of the first inverter is electrically connected to the input terminal of the third inverter, the output terminal of the fifth inverter, and the input terminal of the sixth inverter; the input terminal of the first inverter is electrically connected to the first input terminal and the input terminal of the seventh inverter; the output terminal of the third inverter is electrically connected to the first output terminal and the output terminal of the eighth inverter; the output terminal of the second inverter is electrically connected to the input terminal of the fourth inverter, the output terminal of the sixth inverter, and the input terminal of the fifth inverter; the input terminal of the second inverter is electrically connected to the second input terminal and the input terminal of the eighth inverter; the output terminal of the fourth inverter is electrically connected to the second output terminal and the output terminal of the seventh inverter; the input terminal of the sixth inverter is electrically connected to the first port of the switch, and the input terminal of the fifth inverter is electrically connected to the second port of the switch.

[0012] Furthermore, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter have the same structure, each including an inverter input terminal, an inverter output terminal, a first transistor, and a second transistor;

[0013] The gates of the first transistor and the second transistor are electrically connected and are also electrically connected to the input terminal of the inverter; the drains of the first transistor and the second transistor are electrically connected and are also electrically connected to the output terminal of the inverter.

[0014] Furthermore, the first transistor is an NMOS transistor; the second transistor is a PMOS transistor.

[0015] Furthermore, the switch includes a third transistor; the gate of the third transistor is connected to an externally input clock signal; the drain of the third transistor serves as the first port of the switch, and the source serves as the second port of the switch.

[0016] Furthermore, the third transistor is an NMOS transistor.

[0017] Furthermore, when the clock signal is high, the third transistor is turned on, and the amplifier circuit with common-mode rejection amplifies the input differential signal; when the clock signal is low, the third transistor is turned off, and the amplifier circuit with common-mode rejection stops working. During the period when the amplifier circuit stops working, it can be used to compare the input differential signal and complete the conversion from analog signal to digital signal.

[0018] The beneficial effects of the technical solution provided by this invention include at least the following:

[0019] The amplifier circuit with common-mode rejection provided by this invention achieves common-mode rejection through the first to eighth inverters; dynamic amplification of the differential signal is achieved through switching, reducing the amplifier's power consumption. It can improve common-mode rejection without affecting amplifier performance, thus making it better suited for high-speed, high signal-to-noise ratio SAR ADCs, and solving the problem of low common-mode rejection in existing amplifiers. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the amplifier circuit with common-mode rejection provided in an embodiment of the present invention;

[0022] Figure 2 It is a comparative circuit with a basic structure similar to that of the present invention;

[0023] Figure 3 These are performance graphs of the amplifier circuit with common-mode rejection provided in the embodiments of the present invention under different temperatures, processes, and voltages;

[0024] Figure 4 This is the trigger timing of the amplifier circuit with common-mode rejection provided in the embodiments of the present invention.

[0025] Component marking instructions:

[0026] 1. First inverter; 2. Second inverter; 3. Third inverter; 4. Fourth inverter;

[0027] 5. Fifth inverter; 6. Sixth inverter; 7. Seventh inverter; 8. Eighth inverter;

[0028] Mn1, first transistor; Mp1, second transistor; Mn2, third transistor; S1, switch;

[0029] CLK, clock signal; Vip, first input terminal; Vin, second input terminal; Vop, first output terminal;

[0030] Von, second output terminal; P1, first port; P2, second port. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0032] First, it should be noted that in the embodiments of the present invention, the words "exemplarily," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplarily" is intended to present the concept in a specific manner. Furthermore, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either one or the other.

[0033] This embodiment provides an amplifier circuit with common-mode rejection, including a pseudo-differential Class AB structure with dual-ended input and dual-ended output, used to amplify the input differential signal to obtain a differential signal while suppressing common-mode gain. Figure 1 As shown, the amplifier circuit with common-mode rejection includes: a first input terminal Vip, a second input terminal Vin, a first inverter 1, a second inverter 2, a third inverter 3, a fourth inverter 4, a fifth inverter 5, a sixth inverter 6, a seventh inverter 7, an eighth inverter 8, a first output terminal Vop, a second output terminal Von, and a switch S1; wherein, the first input terminal Vip and the second input terminal Vin are used to input the differential signal to be processed; the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4, the fifth inverter 5, the sixth inverter 6, the seventh inverter 7, the eighth inverter 8, the first output terminal Vop, the ... The fifth inverter 5, the sixth inverter 6, the seventh inverter 7, the eighth inverter 8, and the switch S1 are used to process the input differential signal; wherein, the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4, the fifth inverter 5, the sixth inverter 6, the seventh inverter 7, and the eighth inverter 8 are used to achieve common-mode rejection, and the switch S1 is used to achieve dynamic amplification of the differential signal; the first output terminal Vop and the second output terminal Von are used to output the processing result of the differential signal.

[0034] Specifically, the output terminal of the first inverter 1 is electrically connected to the input terminal of the third inverter 3, the output terminal of the fifth inverter 5, and the input terminal of the sixth inverter 6; the input terminal of the first inverter 1 is electrically connected to the first input terminal Vip and the input terminal of the seventh inverter 7; the output terminal of the third inverter 3 is electrically connected to the first output terminal Vop and is also electrically connected to the output terminal of the eighth inverter 8; the output terminal of the second inverter 2 is electrically connected to the input terminal of the fourth inverter 4, the output terminal of the sixth inverter 6, and the input terminal of the fifth inverter 5; the input terminal of the second inverter 2 is electrically connected to the second input terminal Vin and the input terminal of the eighth inverter 8; the output terminal of the fourth inverter 4 is electrically connected to the second output terminal Von and is also electrically connected to the output terminal of the seventh inverter 7; the input terminal of the sixth inverter 6 is electrically connected to the first port P1 of the switch S1, and the input terminal of the fifth inverter 5 is electrically connected to the second port P2 of the switch S1.

[0035] Furthermore, the first inverter 1, the second inverter 2, the third inverter 3, the fourth inverter 4, the fifth inverter 5, the sixth inverter 6, the seventh inverter 7, and the eighth inverter 8 have the same structure, each including an inverter input terminal, an inverter output terminal, a first transistor Mn1, and a second transistor Mp1; wherein the gates of the first transistor Mn1 and the second transistor Mp1 are electrically connected and electrically connected to the inverter input terminal; the drains of the first transistor Mn1 and the second transistor Mp1 are electrically connected and electrically connected to the inverter output terminal. Specifically, in this embodiment, the first transistor Mn1 is an NMOS transistor; the second transistor Mp1 is a PMOS transistor.

[0036] Further, the switch S1 includes a third transistor Mn2; the gate of the third transistor Mn2 is connected to an externally input clock signal CLK; the drain of the third transistor Mn2 serves as the first port P1 of the switch S1, and the source of the third transistor Mn2 serves as the second port P2 of the switch S1. Specifically, in this embodiment, the third transistor Mn2 is an NMOS transistor.

[0037] Assuming that the MOS transistors in inverters 1 through 8 are all of the same size, then the differential-mode gain of this amplifier is: The common-mode gain is ; where g m g represents the transconductance of the first inverter 1 to the eighth inverter 8. ds The conductance is the electrical conductance of the first inverter 1 to the eighth inverter 8.

[0038] Please see Figure 2It shows a comparative circuit with a basic structure similar to that of the present invention. For example... Figure 2 As shown, this similar structure includes a differential amplifier based on an inverter structure and a differential amplifier based on a dual inverter structure. It uses the same MOS transistor size as the first inverter 1 in this invention, and the differential-mode gain of the inverter structure is... The common-mode gain is The differential-mode gain of the dual inverter structure is The common-mode gain is The performance results obtained under the same process library and the same power supply voltage are shown in Table 1.

[0039] Table 1. Performance Comparison of Various Fully Differential Amplifiers Based on Inverter Structures

[0040]

[0041] As can be seen from Table 1, the amplifier circuit with common-mode rejection of the present invention has a lower common-mode gain under similar differential-mode gain conditions, that is, it has better common-mode rejection.

[0042] Please see Figure 3 The diagram illustrates the performance of the amplifier circuit with common-mode rejection of the present invention under different temperatures, processes, and voltages. Figure 3 As shown, the amplifier circuit with common-mode rejection of the present invention has a certain common-mode rejection capability under various processes.

[0043] Please see Figure 4 This illustrates the trigger timing of the amplifier circuit with common-mode rejection according to the present invention. For example... Figure 4 As shown, when the clock signal CLK is high, the third transistor Mn2 is turned on, and the amplifier amplifies the input differential signal. When the clock signal CLK is low, the third transistor Mn2 is turned off, and the amplifier stops working. In this embodiment, the phase when the amplifier stops working can be used for comparing the differential amplified signals, completing the conversion from analog to digital signals.

[0044] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0045] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention. It should be pointed out that although preferred embodiments of the present invention have been described, those skilled in the art, once they understand the basic inventive concept of the present invention, can make several improvements and modifications without departing from the principles described herein. These improvements and modifications should also be considered within the scope of protection of the present invention. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

Claims

1. An amplifier circuit with common-mode rejection, characterized in that, include: The circuit includes a first input terminal, a second input terminal, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a first output terminal, a second output terminal, and a switch; wherein, The first input terminal and the second input terminal are used to input the differential signal to be processed; The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, and the switch are used to process the input differential signal; wherein, the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter implement common-mode rejection, and the switch implements dynamic amplification of the differential signal; The first output terminal and the second output terminal are used to output the processing results of the differential signal; The output terminal of the first inverter is electrically connected to the input terminal of the third inverter, the output terminal of the fifth inverter, and the input terminal of the sixth inverter; the input terminal of the first inverter is electrically connected to the first input terminal and the input terminal of the seventh inverter; the output terminal of the third inverter is electrically connected to the first output terminal and the output terminal of the eighth inverter; the output terminal of the second inverter is electrically connected to the input terminal of the fourth inverter, the output terminal of the sixth inverter, and the input terminal of the fifth inverter; the input terminal of the second inverter is electrically connected to the second input terminal and the input terminal of the eighth inverter; the output terminal of the fourth inverter is electrically connected to the second output terminal and the output terminal of the seventh inverter. The input terminal of the sixth inverter is electrically connected to the first port of the switch, and the input terminal of the fifth inverter is electrically connected to the second port of the switch.

2. The amplifier circuit with common-mode rejection as described in claim 1, characterized in that, The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, and the eighth inverter have the same structure, each including: an inverter input terminal, an inverter output terminal, a first transistor, and a second transistor; The gates of the first transistor and the second transistor are electrically connected and are also electrically connected to the input terminal of the inverter; the drains of the first transistor and the second transistor are electrically connected and are also electrically connected to the output terminal of the inverter.

3. The amplifier circuit with common-mode rejection as described in claim 2, characterized in that, The first transistor is an NMOS transistor; the second transistor is a PMOS transistor.

4. The amplifier circuit with common-mode rejection as described in claim 1, characterized in that, The switch includes a third transistor; the gate of the third transistor is connected to an externally input clock signal; the drain of the third transistor serves as the first port of the switch, and the source serves as the second port of the switch.

5. The amplifier circuit with common-mode rejection as described in claim 4, characterized in that, The third transistor is an NMOS transistor.

6. The amplifier circuit with common-mode rejection as described in claim 4, characterized in that, When the clock signal is high, the third transistor is turned on, and the amplifier circuit with common-mode rejection amplifies the input differential signal. When the clock signal is low, the third transistor is turned off, and the amplifier circuit with common-mode rejection stops working. During the period when the amplifier circuit stops working, it can be used to compare the input differential signal and complete the conversion from analog signal to digital signal.

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