Clock synchronization keeping method and system for wireless measuring and recording system
By using the combination of GNSS module, FPGA module, DAC module and voltage-controlled crystal oscillator circuit in the wireless recording system, the monitoring of GNSS signals and the synchronization phase-locking loop control of the clock are solved, and the problem of clock out of synchronization caused by GNSS signal interruption is solved. , improves the stability and reliability of the system.
Patent Information
- Application Number
- CN202411522216.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-07
AI Technical Summary
In a strong electromagnetic environment, the GNSS satellite signal may be interrupted, causing the clock of the wireless synchronous recording system to be unable to remain synchronized.
A wireless measuring and recording system clock synchronization holding system is adopted, including GNSS module, FPGA module, DAC module and voltage-controlled crystal oscillator circuit. The FPGA module contains GNSS monitoring module, synchronous phase lock loop, time update module and synchronous state monitoring module. Through these modules, the monitoring of GNSS signals and the synchronous phase lock loop control of the clock are realized, ensuring that the clock enters punctuality when the GNSS state is abnormal. state.
It effectively maintains the synchronization of the wireless recording system clock, ensuring that the clock can be maintained when the GNSS signal is temporarily lost, improving the stability and reliability of the system.
Smart Images
Figure CN119402003A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and in particular to a method and system for maintaining clock synchronization in a wireless recording system. Background Art
[0002] The wireless synchronous measurement and recording system is a distributed voltage and current acquisition, wireless transmission, centralized storage and analysis system based on satellite timing synchronization. The system is widely used in substation startup and commissioning tests and electrical equipment performance tests after maintenance. It can quickly build a field test platform and efficiently complete the test task.
[0003] However, since GNSS satellite signals are affected by many factors when propagating in space, especially in strong electromagnetic environments, GNSS signals may be interrupted. Losing a satellite will make it impossible for the wireless synchronous recording system clock to remain synchronized.
[0004] Application Contents
[0005] The present application aims to solve at least one of the technical problems existing in the prior art, and proposes a method and system for maintaining clock synchronization in a wireless recording system.
[0006] In order to achieve the above-mentioned purpose, the present application adopts the following technical scheme: a clock synchronization maintenance system for a wireless measurement and recording system, comprising a GNSS module, an FPGA module, a DAC module and a voltage-controlled crystal oscillator circuit, wherein the FPGA module is connected to the GNSS module, the input end of the DAC module is connected to the FPGA module, and the output end of the DAC module is connected to the voltage-controlled crystal oscillator circuit;
[0007] The FPGA module includes a GNSS monitoring module, a synchronous phase-locked loop, a time update module and a synchronization status monitoring module;
[0008] The GNSS monitoring module is used to monitor the PPS pulse, time information and GNSS status information of the GNSS module, and provide the PPS pulse as a reference PPS pulse to the synchronous phase-locked loop, provide the time information to the time update module so that the time update module outputs the initial time information according to the time information, and provide the GNSS status information to the synchronous status monitoring module; the synchronous status monitoring module sends the GNSS status information to the synchronous phase-locked loop;
[0009] The synchronous phase-locked loop includes a phase comparator, a frequency comparator, a filter, a DAC controller, a frequency multiplier and a PPS pulse generator;
[0010] The phase comparator is used to output a phase error E(p) according to the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator;
[0011] The frequency comparator is used to output a frequency error E(f) according to the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator;
[0012] The filter is used to obtain an error adjustment value according to the phase error E(p) and the frequency error E(f);
[0013] The DAC controller is used to obtain a voltage output control value of a current cycle according to the error adjustment value and the voltage output control value of a previous cycle;
[0014] The DAC module is used to receive the voltage output control value of the current cycle, and output a control signal to the voltage-controlled crystal oscillator circuit according to the voltage output control value of the current cycle;
[0015] The voltage-controlled crystal oscillator circuit is used to output a first reference clock according to the control signal;
[0016] The frequency multiplier is used to multiply the first reference clock to obtain a second reference clock, and provide the second reference clock to the PPS pulse generator;
[0017] The PPS pulse generator is used to output a standard PPS pulse according to the second reference clock, and provide the standard PPS pulse to the phase comparator, the frequency comparator and the time update module respectively;
[0018] The time update module is used to update the time according to the standard PPS pulse and provide time information output.
[0019] Furthermore, it also includes a synchronizer clock, which is connected to the FPGA module.
[0020] Furthermore, the voltage-controlled crystal oscillator circuit includes a voltage-controlled crystal oscillator and a clock conversion and buffer circuit; the input end of the clock conversion and buffer circuit is connected to the output end of the voltage-controlled crystal oscillator, and each output end of the clock conversion and buffer circuit outputs the first reference clock.
[0021] In addition, the present application also provides a method for maintaining clock synchronization of a wireless recording system using the above-mentioned wireless recording system clock synchronization maintaining system, comprising:
[0022] The GNSS monitoring module monitors the PPS pulse, time information and GNSS status information of the GNSS module, and provides the PPS pulse as a reference PPS pulse to the synchronous phase-locked loop, provides the time information to the time update module so that the time update module outputs initial time information according to the time information, and provides the GNSS status information to the synchronization status monitoring module;
[0023] The synchronization status monitoring module sends the GNSS status information to the synchronous phase-locked loop;
[0024] When the GNSS status information is normal, the phase comparator of the synchronous phase-locked loop compares the phase of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and outputs a phase error E(p);
[0025] The frequency comparator of the synchronous phase-locked loop compares the frequency of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and outputs a frequency error E(f);
[0026] The filter of the synchronous phase-locked loop obtains an error adjustment value according to the phase error E(p) and the frequency error E(f);
[0027] The DAC controller of the synchronous phase-locked loop obtains the voltage output control value of the current cycle according to the error adjustment value and the voltage output control value of the previous cycle;
[0028] The DAC module receives the voltage output control value of the current cycle, and outputs a control signal to the voltage-controlled crystal oscillator circuit according to the voltage output control value of the current cycle;
[0029] The voltage-controlled crystal oscillator circuit outputs a first reference clock according to the control signal;
[0030] The frequency multiplier performs frequency multiplication processing on the first reference clock to obtain a second reference clock, and provides the second reference clock to the PPS pulse generator;
[0031] The PPS pulse generator outputs a standard PPS pulse according to the second reference clock, and provides the standard PPS pulse to the phase comparator, the frequency comparator and the time update module respectively;
[0032] The time update module provides time information output according to the standard PPS pulse update time;
[0033] When the GNSS status information is abnormal, the synchronous phase-locked loop enters the punctual state, the phase comparator and frequency comparator of the synchronous phase-locked loop no longer output the error adjustment value, the voltage output control value of the DAC controller is locked, and the output pulse period and width of the PPS pulse generator are locked.
[0034] Furthermore, the system further includes a synchronizer clock, which is connected to the FPGA module; the FPGA module further includes a synchronizer clock monitoring module; and the method further includes:
[0035] The synchronizer clock receives the standard PPS pulse output by the PPS pulse generator and the first reference clock, and outputs a sampling control clock for sampling control;
[0036] The synchronizer clock monitoring module receives the standard PPS pulse output by the PPS pulse generator and the third clock output by the synchronizer clock, and determines whether the third clock output by the synchronizer clock is abnormal. If an abnormality occurs, a reset signal is output to the synchronizer clock for resetting the synchronizer clock.
[0037] Further, the phase comparison of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator and outputting the phase error E(p) comprises:
[0038] The time difference between the rising edge of the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator is measured using the second reference clock, which is the phase error E(p).
[0039] Further, the frequency comparison of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator and outputting the frequency error E(f) includes:
[0040] Measure the reference PPS pulse and the standard PPS pulse period value output by the PPS pulse generator, compare the period count value of the reference PPS pulse with the period count value of the standard PPS pulse output by the PPS pulse generator, and obtain the difference between the two pulse period count values, which is the frequency error E(f).
[0041] Furthermore, the reference PPS pulse and the standard PPS pulse period value output by the PPS pulse generator are measured using the second reference clock.
[0042] Further, it is determined whether the interval between the rising edge of the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator is less than 5 second reference clock cycles, and if 5 consecutive comparisons satisfy that the interval is less than 5 second reference clock cycles, the phase comparator outputs a phase lock flag;
[0043] When the difference between the cycle count value of the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator is less than or equal to one second reference clock cycle for five consecutive times, the frequency comparator outputs a frequency lock flag.
[0044] Furthermore, the error adjustment value O(s)=K p ×E(p)+K f×E(f);
[0045] Among them, Kp is the proportional coefficient of phase error, and Kf is the proportional coefficient of frequency error;
[0046] The voltage output control value of the current cycle is Vo(N)=Vo(N-1)+0(s), where Vo(N-1) is the voltage output control value of the previous cycle.
[0047] Compared with the prior art, this application has the following beneficial effects:
[0048] The present application synchronizes the standard PPS second pulse generated by the PPS pulse generator with the reference PPS second pulse output by the GNSS through a synchronous phase-locked loop. When the GNSS status information is abnormal, the synchronous phase-locked loop enters a punctual state, the phase comparator and frequency comparator of the synchronous phase-locked loop no longer output error adjustment values, the voltage output control value of the DAC controller is locked, the output pulse length of the PPS pulse generator is locked, and the system enters a punctual state to ensure that clock synchronization is maintained even after a brief loss of the satellite signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] Figure 1 A schematic diagram of the principle of a clock synchronization maintenance system for a wireless recording system provided by an embodiment of the present application;
[0050] Figure 2 A schematic diagram of a synchronous phase-locked loop adjustment principle provided by an embodiment of the present application;
[0051] Figure 3 A circuit diagram of the DAC module provided for this application;
[0052] Figure 4 A circuit diagram of a voltage-controlled crystal oscillator provided for this application;
[0053] Figure 5 A circuit diagram of a clock conversion and buffer circuit provided for the present application;
[0054] Figure 6 A circuit diagram of the synchronizer clock provided in this application. DETAILED DESCRIPTION
[0055] In order to enable those skilled in the art to better understand the technical solution of the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0056] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Multiple means two or more. Similarly, "one", "one" or "the" and other similar words do not indicate quantity restrictions, but indicate that there is at least one. "Including" or "including" and other similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described target changes, the relative positional relationship may also change accordingly.
[0057] In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not all drawn to scale. In addition, some well-known parts may not be shown in the drawings.
[0058] Many specific details of the present application are described below, such as component structures, materials, dimensions, processing techniques, and technologies, in order to more clearly understand the present application. However, as those skilled in the art will appreciate, the present application may be implemented without following these specific details.
[0059] In some embodiments, see Figure 1 and Figure 2 The embodiment of the present application discloses a method for maintaining clock synchronization of a wireless recording system. The method is based on a clock synchronization maintaining system. The system comprises: a GNSS module, an FPGA module, a DAC module and a voltage-controlled crystal oscillator circuit. The GNSS module and the DAC module are connected to the FPGA module, and the DAC module is connected to the voltage-controlled crystal oscillator circuit;
[0060] The internal functional modules of FPGA include: GNSS monitoring module, synchronous phase-locked loop, time update module, and synchronization status monitoring module;
[0061] The method comprises the following steps:
[0062] The GNSS monitoring module monitors the PPS second pulse and serial port message time information of the GNSS module, and provides the PPS second pulse as a reference PPS pulse to the synchronous phase-locked loop; the GNSS monitoring module also provides time information to the time update module, so that the time update module outputs initial time information according to the time information; the GNSS monitoring module also provides GNSS status information to the synchronization status monitoring module, and the synchronization status monitoring module sends the GNSS status information to the synchronous phase-locked loop;
[0063] When the GNSS status information is normal, the phase comparator of the synchronous phase-locked loop compares the phase of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and outputs a phase error E(p);
[0064] The frequency comparator of the synchronous phase-locked loop compares the frequency of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and outputs a frequency error E(f);
[0065] The filter of the synchronous phase-locked loop obtains an error adjustment value according to the phase error E(p) and the frequency error E(f);
[0066] The DAC controller of the synchronous phase-locked loop obtains the voltage output control value of the current cycle according to the error adjustment value and the voltage output control value of the previous cycle;
[0067] The DAC module receives the voltage output control value and outputs a control signal to the voltage-controlled crystal oscillator circuit, so that the voltage-controlled crystal oscillator circuit outputs a first reference clock (such as a 10M reference clock);
[0068] The frequency multiplier of the synchronous phase-locked loop multiplies the first reference clock (such as 10M reference clock) output by the voltage-controlled crystal oscillator circuit to obtain a second reference clock (such as 200M clock) and provides it to the PPS pulse generator;
[0069] The PPS pulse generator outputs a standard PPS pulse according to a second reference clock (such as a 200M clock), and provides the pulses to a phase comparator, a frequency comparator and a time update module respectively;
[0070] The time update module updates the time according to the standard PPS pulse signal output by the PPS pulse generator and provides time information output;
[0071] When the GNSS status information is abnormal, the reference PPS cannot be obtained or the reference PPS pulse period count value is abnormal, the synchronous phase-locked loop enters the punctual state, the phase comparator and frequency comparator of the synchronous phase-locked loop no longer output the error adjustment value, the voltage output control value of the DAC controller is locked, and the output pulse period and width of the PPS pulse generator are locked.
[0072] When the monitored GNSS status information is abnormal, a first reset signal is output to the GNSS module to reset the GNSS module.
[0073] The synchronization status monitoring module also provides synchronization status output.
[0074] In some embodiments, the system further includes a synchronizer clock, the synchronizer clock is connected to the FPGA module, the synchronizer clock receives the standard PPS pulse output by the PPS pulse generator and the first reference clock (such as a 10M reference clock), and outputs a sampling control clock (such as an 8M sampling control clock) for sampling control, such as for;
[0075] The FPGA module also includes a synchronizer clock monitoring module, which receives a standard PPS pulse output by a PPS pulse generator and a third clock (such as an 8M clock) output by the synchronizer clock, and determines whether the third clock (such as an 8M clock) output by the synchronizer clock is abnormal. If an abnormality occurs, a second reset signal is output to the synchronizer clock for resetting the synchronizer clock.
[0076] The reference PPS is P(r), and the PPS output by the PPS pulse generator is P(o). Then: when P(r) rises and P(o)=1, the leading flag outputs 1; when P(r) rises and P(o)=0, the lagging flag outputs 1. The phase comparator outputs the phase error E(p). When the phase is ahead, E(p)>0; when the phase is behind, E(p)<0.
[0077] In some embodiments, a reference PPS pulse is compared with a standard PPS pulse output by a PPS pulse generator in phase, and a phase error E(p) is output, which specifically includes: measuring the edge time difference between the reference PPS and the PPS pulse output by the PPS pulse generator, which is the phase error E(p).
[0078] In some embodiments, the phase error E(p) is a rising edge time difference or a falling edge time difference between a reference PPS and a PPS pulse output by a PPS pulse generator.
[0079] In some embodiments, a reference PPS pulse is compared in phase with a standard PPS pulse output by a PPS pulse generator to output a phase error E(p), specifically including: measuring the time difference between the rising edge and the falling edge of the reference PPS and the PPS pulse output by the PPS pulse generator, and taking the average of the rising edge time difference and the falling edge time difference to obtain the phase error E(p).
[0080] In some embodiments, a second reference clock (eg, a 200M clock) is used to measure the time difference between a reference PPS and a rising edge or / and a falling edge of a PPS pulse output by a PPS pulse generator.
[0081] In some embodiments, a reference PPS pulse is compared in frequency with a standard PPS pulse output by a PPS pulse generator, and a frequency error E(f) is output, which specifically includes: detecting the cycle length of the reference PPS and the cycle length of the PPS output by the PPS pulse generator, and comparing the cycle length of the reference PPS with the cycle length of the PPS output by the PPS pulse generator, and obtaining the difference between the two pulse cycle count values as the frequency error E(f).
[0082] In some embodiments, the present application uses a second reference clock (such as a 200M clock) to measure a reference PPS and a PPS pulse period value output by a PPS pulse generator.
[0083] In some embodiments, since the PPS pulse output by the PPS pulse generator adopts a fixed frequency division ratio, it is only necessary to detect the period length of the reference PPS pulse. If it is greater than the preset period value of the fixed frequency division ratio, the frequency too fast flag outputs 1; if it is less than the preset period value of the fixed frequency division ratio, the frequency too slow flag outputs 1. The frequency comparator outputs a frequency error E(f). When the output frequency is too large, E(f)>0; when the output frequency is too small, E(f)<0.
[0084] In some embodiments, the PPS output by the PPS pulse generator uses a fixed frequency division ratio, and the frequency error E(f) is a preset period value of the fixed frequency division ratio minus a period length of the reference PPS.
[0085] In some embodiments, it is determined whether the interval between the reference PPS pulse and the rising edge of the standard PPS pulse output by the PPS pulse generator is less than 5 second reference clock cycles, and if 5 consecutive comparisons satisfy that the interval is less than 5 second reference clock cycles, the phase comparator outputs a phase lock flag;
[0086] When the difference between the cycle count value of the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator is less than or equal to one second reference clock cycle for five consecutive times, the frequency comparator outputs a frequency lock flag.
[0087] Furthermore, the error adjustment value is O(s)=K p ×E(p)+K f ×E(f), where K p is the proportional coefficient of phase error, Kf is the proportional coefficient of frequency error;
[0088] The voltage output control value of the current cycle is Vo(N)=Vo(N-1)+0(s), and Vo(N-1) is the voltage output control value of the previous cycle. The internal control of the synchronous phase-locked loop is actually a PI control adjustment, using K p and K fThe speed adjustment and the stability of the adjustment module are achieved; the frequency error plays a leading role in the error adjustment value of the low-pass filter. When the frequency difference is large, the frequency error is used as the calibration source; when the frequency is similar, the phase error is used as the calibration source.
[0089] In some embodiments, the pulse generator generates the PPS output by the PPS pulse generator from the 200M clock, and during the generation process, the output of the phase comparator is also used to perform further fine phase adjustment.
[0090] The principles of this application are:
[0091] At startup: the initial value of the pulse width counter is the theoretical length of 1s (assuming the crystal oscillator has no deviation), and the pulse generator generates PPS with the rising edge of GNSS_PPS as the initial value;
[0092] Synchronization: After GNSS_PPS is synchronized and the phase comparator and frequency comparator are locked, the synchronization control logic controls LMK05318 to enter the synchronization state, the system enters the synchronization state, and outputs the synchronization flag to the outside.
[0093] Punctuality: When GNSS is detected to have lost synchronization, the phase comparator and frequency comparator no longer output error adjustment values, the output value of the DAC controller is locked, the output pulse period and width of the PPS pulse generator are locked, and the system enters the punctual state.
[0094] In some embodiments, the embodiments of the present application also disclose a clock synchronization maintenance system for a wireless measurement and recording system, including a GNSS module, an FPGA module, a DAC module, and a voltage-controlled crystal oscillator circuit, wherein the FPGA module is connected to the GNSS module, the input end of the DAC module is connected to the FPGA module, and the output end of the DAC module is connected to the voltage-controlled crystal oscillator circuit.
[0095] In some embodiments, the internal functional modules of the FPGA include: a GNSS monitoring module, a synchronous phase-locked loop, a time update module, and a synchronization status monitoring module;
[0096] The GNSS monitoring module is used to monitor the PPS pulse per second and serial port message time information of the GNSS module, and provide the PPS pulse per second as a reference PPS to the synchronous phase-locked loop; the GNSS monitoring module is also used to provide time information to the time update module, so that the time update module outputs initial time information according to the time information; the GNSS monitoring module is also used to provide GNSS status information to the synchronization status monitoring module, and the synchronization status monitoring module sends the GNSS status information to the synchronous phase-locked loop;
[0097] The phase comparator of the synchronous phase-locked loop is used to compare the phase of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and output a phase error E(p);
[0098] The frequency comparator of the synchronous phase-locked loop is used to compare the frequency of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and output a frequency error E(f);
[0099] The filter of the synchronous phase-locked loop is used to obtain an error adjustment value according to the phase error E(p) and the frequency error E(f);
[0100] The DAC controller of the synchronous phase-locked loop is used to obtain the voltage output control value of the current cycle according to the error adjustment value and the voltage output control value of the previous cycle;
[0101] The DAC module is used to receive the voltage output control value and output a control signal to the voltage-controlled crystal oscillator circuit so that the voltage-controlled crystal oscillator circuit outputs a first reference clock (such as a 10M reference clock);
[0102] The frequency multiplier of the synchronous phase-locked loop is used to multiply the first reference clock (such as 10M reference clock) output by the voltage-controlled crystal oscillator circuit to obtain a second reference clock (such as 200M clock) to provide to the PPS pulse generator;
[0103] The PPS pulse generator is used to output a standard PPS pulse, i.e., an internal PPS pulse, according to a second reference clock (such as a 200M clock), and provide the pulses to a phase comparator, a frequency comparator, and a time update module respectively;
[0104] The time update module is used to update the time according to the standard PPS pulse signal output by the PPS pulse generator and provide time information output.
[0105] The FPGA module also provides an internal PPS pulse output.
[0106] The FPGA module also provides synchronization status outputs.
[0107] In some embodiments, the clock synchronization maintenance system of the wireless measurement and recording system of the present application also includes a synchronizer clock, which is connected to the FPGA module. The synchronizer clock is used to receive the standard PPS pulse output by the PPS pulse generator and the first reference clock (such as a 10M reference clock), and output a sampling control clock (such as an 8M sampling control clock) for sampling control, such as synchronous sampling control of the voltage acquisition terminal and the current acquisition terminal of the wireless measurement and recording system;
[0108] The FPGA module also includes a synchronizer clock monitoring module, which is used to receive the standard PPS pulse output by the PPS pulse generator and the third clock (such as an 8M clock) output by the synchronizer clock, and determine whether the third clock (such as an 8M clock) output by the synchronizer clock is abnormal. If an abnormality occurs, a second reset signal is output to the synchronizer clock for resetting the synchronizer clock.
[0109] In some embodiments, see Figure 6 The synchronizer clock uses the chip model LMK05318.
[0110] In some embodiments, the voltage-controlled crystal oscillator circuit includes a voltage-controlled crystal oscillator and a clock conversion and buffer circuit, the input end of the clock conversion and buffer circuit is connected to the output end of the voltage-controlled crystal oscillator, and each output end of the clock conversion and buffer circuit outputs a first reference clock (such as a 10M reference clock).
[0111] Figure 3 A specific circuit diagram of the DAC module is disclosed.
[0112] Figure 4 The circuit diagrams of voltage-controlled crystal oscillators of two embodiments are disclosed. DSA535SGA is a preferred crystal oscillator, and DSA321SDN is a backup crystal oscillator. Only one of the two is welded at the same time. Figure 5 A circuit diagram of a clock conversion and buffering circuit is disclosed.
[0113] In some embodiments, the embodiments of the present application also disclose a wireless measurement and recording system, including a voltage acquisition terminal, a current acquisition terminal, a host (i.e., a host computer or a computer) and a wireless acquisition collaborative control device. The wireless acquisition collaborative control device wirelessly communicates with the voltage acquisition terminal and the current acquisition terminal to achieve synchronous control of the voltage acquisition terminal and the current acquisition terminal. The voltage acquisition terminal and the current acquisition terminal wirelessly communicate with the host through the wireless acquisition collaborative control device to upload waveform data to the analysis host.
[0114] The wireless acquisition collaborative control device can also communicate wirelessly with the host to realize the configuration of the on-site working mode.
[0115] Under the coordination of wireless collaborative control, the voltage acquisition terminal and the current acquisition terminal realize synchronous and high-speed sampling of multiple (e.g., 6) analog signals (each acquisition terminal), record the waveform data of the first 2S (configurable) and the last 3S (configurable) when the start condition occurs, and upload the waveform data to the analysis host. The wireless collaborative control device provides wireless network access and completes the functions of synchronous control of voltage and current acquisition terminals, task issuance and trigger control, etc.
[0116] The wireless acquisition collaborative control device includes a collaborative control mainboard, a switch, a wireless bridge module, a WIFI wireless network module and a LORA wireless module, as well as a plurality of antennas corresponding to the wireless bridge module, the WIFI wireless network module and the LORA wireless module. The wireless bridge module is connected to the wireless bridge antenna, the WIFI wireless network module is connected to the router antenna, the LORA wireless module is connected to the LORA antenna, and the collaborative control mainboard, the wireless bridge module, the WIFI wireless network module and the LORA wireless module are respectively connected to the switch.
[0117] The WIFI wireless network module uses a wireless router.
[0118] The wireless bridge module is used to provide a 5.8G wireless network; the WIFI wireless network module is used to provide a 2.4G WIFI wireless network, and the LORA wireless module is used to provide a 470M LORA wireless control network.
[0119] The wireless acquisition collaborative control device of this embodiment provides three wireless networks: ①5.8G wireless network, implemented by wireless bridge equipment, provides long-distance communication links such as data interaction, synchronous control, and working mode configuration between acquisition terminals, solving the problem of long-distance data transmission in field tests. ②2.4GWIFI wireless network, implemented by wireless router, provides acquisition terminal data access analysis host communication link, solving the problem of acquisition data transmission. ③470M LORA wireless control network, implemented by LORA wireless module, provides remote power on / off control wireless channel, solves the problem of remote power on / off control of acquisition terminals, ensures that the acquisition terminal is in low power consumption mode in standby state, and prolongs working time.
[0120] The number of wireless bridge antennas, LORA antennas, router antennas, and GPS antennas can be set as needed.
[0121] In some embodiments, the wireless acquisition collaborative control device of the present application also includes a GPS antenna, which is connected to the collaborative control mainboard.
[0122] The collaborative control mainboard is the core of the wireless acquisition collaborative control device. The system working mode configuration, terminal data acquisition synchronous collaborative control, and terminal remote power on / off control are all completed by the main control board. The functional modules in the shell are interconnected by a wired network (LAN).
[0123] The collaborative control mainboard is provided with an FPGA and an ARM. The collaborative control mainboard is provided with an Ethernet module, and the FPGA is connected to the switch through the Ethernet module. The collaborative control mainboard is provided with a GNSS module, the GPS antenna is connected to the GNSS module, and the GNSS module is connected to the FPGA.
[0124] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0125] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A wireless recording system clock synchronization maintenance system, characterized in that: It includes a GNSS module, an FPGA module, a DAC module and a voltage-controlled crystal oscillator circuit, wherein the FPGA module is connected to the GNSS module, the input end of the DAC module is connected to the FPGA module, and the output end of the DAC module is connected to the voltage-controlled crystal oscillator circuit; The FPGA module includes a GNSS monitoring module, a synchronous phase-locked loop, a time update module and a synchronization status monitoring module; The GNSS monitoring module is used to monitor the PPS pulse, time information and GNSS status information of the GNSS module, and provide the PPS pulse as a reference PPS pulse to the synchronous phase-locked loop, provide the time information to the time update module so that the time update module outputs the initial time information according to the time information, and provide the GNSS status information to the synchronous status monitoring module; the synchronous status monitoring module sends the GNSS status information to the synchronous phase-locked loop; The synchronous phase-locked loop includes a phase comparator, a frequency comparator, a filter, a DAC controller, a frequency multiplier and a PPS pulse generator; The phase comparator is used to output a phase error E(p) according to the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator; The frequency comparator is used to output a frequency error E(f) according to the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator; The filter is used to obtain an error adjustment value according to the phase error E(p) and the frequency error E(f); The DAC controller is used to obtain a voltage output control value of a current cycle according to the error adjustment value and the voltage output control value of a previous cycle; The DAC module is used to receive the voltage output control value of the current cycle, and output a control signal to the voltage-controlled crystal oscillator circuit according to the voltage output control value of the current cycle; The voltage-controlled crystal oscillator circuit is used to output a first reference clock according to the control signal; The frequency multiplier is used to multiply the first reference clock to obtain a second reference clock, and provide the second reference clock to the PPS pulse generator; The PPS pulse generator is used to output a standard PPS pulse according to the second reference clock, and provide the standard PPS pulse to the phase comparator, the frequency comparator and the time update module respectively; The time update module is used to update the time according to the standard PPS pulse and provide time information output.
2. The clock synchronization maintenance system for a wireless recording system as claimed in claim 1, characterized in that: It also includes a synchronizer clock, which is connected to the FPGA module.
3. The clock synchronization maintenance system of the wireless recording system as claimed in claim 2, characterized in that: The voltage-controlled crystal oscillator circuit includes a voltage-controlled crystal oscillator and a clock conversion and buffer circuit; the input end of the clock conversion and buffer circuit is connected to the output end of the voltage-controlled crystal oscillator, and each output end of the clock conversion and buffer circuit outputs the first reference clock.
4. A method for maintaining clock synchronization of a wireless recording system using the wireless recording system clock synchronization maintaining system as claimed in any one of claims 1 to 3, characterized in that: include: The GNSS monitoring module monitors the PPS pulse, time information and GNSS status information of the GNSS module, and provides the PPS pulse as a reference PPS pulse to the synchronous phase-locked loop, provides the time information to the time update module so that the time update module outputs initial time information according to the time information, and provides the GNSS status information to the synchronization status monitoring module; The synchronization status monitoring module sends the GNSS status information to the synchronous phase-locked loop; When the GNSS status information is normal, the phase comparator of the synchronous phase-locked loop compares the phase of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and outputs a phase error E(p); The frequency comparator of the synchronous phase-locked loop compares the frequency of the reference PPS pulse with the standard PPS pulse output by the PPS pulse generator, and outputs a frequency error E(f); The filter of the synchronous phase-locked loop obtains an error adjustment value according to the phase error E(p) and the frequency error E(f); The DAC controller of the synchronous phase-locked loop obtains the voltage output control value of the current cycle according to the error adjustment value and the voltage output control value of the previous cycle; The DAC module receives the voltage output control value of the current cycle, and outputs a control signal to the voltage-controlled crystal oscillator circuit according to the voltage output control value of the current cycle; The voltage-controlled crystal oscillator circuit outputs a first reference clock according to the control signal; The frequency multiplier performs frequency multiplication processing on the first reference clock to obtain a second reference clock, and provides the second reference clock to the PPS pulse generator; The PPS pulse generator outputs a standard PPS pulse according to the second reference clock, and provides the standard PPS pulse to the phase comparator, the frequency comparator and the time update module respectively; The time update module provides time information output according to the standard PPS pulse update time; When the GNSS status information is abnormal, the synchronous phase-locked loop enters the punctual state, the phase comparator and frequency comparator of the synchronous phase-locked loop no longer output the error adjustment value, the voltage output control value of the DAC controller is locked, and the output pulse period and width of the PPS pulse generator are locked.
5. The method for maintaining clock synchronization of a wireless recording system as claimed in claim 4, characterized in that: The system further includes a synchronizer clock, which is connected to the FPGA module; the FPGA module further includes a synchronizer clock monitoring module; and the method further includes: The synchronizer clock receives the standard PPS pulse output by the PPS pulse generator and the first reference clock, and outputs a sampling control clock for sampling control; The synchronizer clock monitoring module receives the standard PPS pulse output by the PPS pulse generator and the third clock output by the synchronizer clock, and determines whether the third clock output by the synchronizer clock is abnormal. If an abnormality occurs, a reset signal is output to the synchronizer clock for resetting the synchronizer clock.
6. The method for maintaining clock synchronization of a wireless recording system as claimed in claim 5, characterized in that: The phase comparison between the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator and outputting a phase error E(p) comprises: The time difference between the rising edge of the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator is measured using the second reference clock, which is the phase error E(p).
7. The method for maintaining clock synchronization of a wireless recording system as claimed in claim 6, characterized in that: The frequency comparison of the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator to output a frequency error E(f) includes: Measure the reference PPS pulse and the standard PPS pulse period value output by the PPS pulse generator, compare the period count value of the reference PPS pulse with the period count value of the standard PPS pulse output by the PPS pulse generator, and obtain the difference between the two pulse period count values, which is the frequency error E(f).
8. The method for maintaining clock synchronization of a wireless recording system as claimed in claim 7, characterized in that: The reference PPS pulse and the standard PPS pulse period value output by the PPS pulse generator are measured using the second reference clock.
9. The method for maintaining clock synchronization of a wireless recording system as claimed in claim 8, characterized in that: Determine whether the interval between the reference PPS pulse and the rising edge of the standard PPS pulse output by the PPS pulse generator is less than 5 second reference clock cycles. If 5 consecutive comparisons satisfy that the interval is less than 5 second reference clock cycles, the phase comparator outputs a phase lock flag. When the difference between the cycle count value of the reference PPS pulse and the standard PPS pulse output by the PPS pulse generator is less than or equal to one second reference clock cycle for five consecutive times, the frequency comparator outputs a frequency lock flag.
10. The method for maintaining clock synchronization of a wireless recording system as claimed in claim 9, characterized in that: Error adjustment value O(s) = K p ×E(p)+K f ×E(f); Among them, K p is the proportional coefficient of phase error, K f is the frequency error proportional coefficient; The voltage output control value of the current cycle is Vo(N)=Vo(N-1)+0(s), where Vo(N-1) is the voltage output control value of the previous cycle.