Hardware cryptographic module based on domestic commercial cryptographic algorithm and implementation method thereof

Abstract

The invention discloses a hardware cryptographic module based on a domestic commercial cryptographic algorithm and an implementation method thereof, and belongs to the field of information security passwords, the hardware cryptographic module comprises a hardware module and a software module, the hardware module comprises a central control unit, a bus interface bidirectionally connected with the central control unit, a physical security unit and a power supply, and the password security chip is bidirectionally connected with the bus interface and comprises a main control processor CPU, an encryption engine, an APB and AHB bus system, a TIMER timer module, an integrated storage unit and a Flash chip. According to the hardware cryptographic module based on the domestic commercial cryptographic algorithm and the implementation method of the hardware cryptographic module, a cryptographic engine can be efficiently integrated into a cryptographic security chip, and writing of a subsequent software driver is facilitated; and the method also has great significance for researching a secure operating system and secure communication and authentication protocols based on a security chip.

Description

Technical Field

[0001] The present invention relates to the field of information security cryptographic technology, and in particular to a hardware cryptographic module based on a domestic commercial cryptographic algorithm and an implementation method thereof. Background Art

[0002] The two basic requirements for computer network information security are confidentiality and integrity. Cryptography technology is the basis of network security communication. By encrypting the communication content, unauthorized persons cannot understand its true meaning, thereby preventing passive attacks such as eavesdropping and ensuring the confidentiality of information; the authentication mechanism of the cryptographic system can prevent active attacks on the transmitted information such as tampering and accidental destruction to maintain the integrity of the data.

[0003] Confidentiality and authentication are two important aspects of information system security, but authentication cannot automatically provide confidentiality, and confidentiality cannot provide an authentication mechanism. The basic idea of ​​​​cryptographic design is to disguise information so that unauthorized persons cannot understand its true meaning. The information that is not hidden is called plaintext, and the disguised information is called ciphertext. The two basic elements that constitute a cryptographic system are cryptographic algorithms and keys. When designing a cryptographic system, it is always assumed that the cryptographic algorithm is public, and what really needs to be kept confidential is the key.

[0004] In the existing technology, encrypting private information is an important way to effectively solve the problem of private information leakage. It ensures that data is not tampered with, stolen or destroyed. The encryption and decryption operations only occur between the data sender and the data receiver. During the entire transmission process, the data exists in the form of ciphertext, which greatly improves the security of the data. Integrating encryption technology into the information security protection system can effectively help the security protection of data information.

[0005] Solidifying the cryptographic algorithm into the chip can, on the one hand, increase the speed of cryptographic operations. The speed of cryptographic operations in security chips is much faster than that of software, which is more in line with the application requirements of current IoT devices. On the other hand, it can improve security. For example, key data can be securely stored in the chip, and cryptographic operations are performed inside the chip without leaking data. Summary of the invention

[0006] The purpose of the present invention is to provide a hardware cryptographic module based on a domestic commercial cryptographic algorithm and an implementation method thereof to solve the problems mentioned in the above background technology.

[0007] To achieve the above-mentioned purpose, the present invention provides a hardware cryptographic module based on a domestic commercial cryptographic algorithm, including a hardware module and a software module. The hardware module includes a central control unit, a bus interface bidirectionally connected to the central control unit, a physical security unit and a power supply, and a cryptographic security chip bidirectionally connected to the bus interface. The cryptographic security chip includes a main control processor CPU, an encryption engine, APB and AHB bus systems, a TIMER timer module, an integrated storage unit and a Flash chip.

[0008] Preferably, the software module includes:

[0009] SM2 software module, used to complete signature verification, encryption and decryption, mode control, and data reading;

[0010] SM3 software module, used to complete message grouping, filling, mode control, and data reading;

[0011] SM4 software module is used to complete mode control and data reading.

[0012] Preferably, the APB bus system integrates GPIO ports, SPI, I2C and UART communication interfaces, and the AHB bus system is mounted with a storage unit and a cryptographic engine unit.

[0013] Preferably, the APB bus system data exchanges data with the main control processor via the AHB bus system and is connected via an apb_bridge module.

[0014] Preferably, the encryption engine integrates a random number generator, a PUF module, an SM2 / 3 / 4 hardware cryptographic module, a read-only memory ROM and a random access memory SRAM.

[0015] A method for implementing a hardware cryptographic module based on a domestic commercial cryptographic algorithm, and a storage control method for a cryptographic security chip are as follows:

[0016] After the program is compiled, the main control processor calls SPI to write the user program into the Flash chip. The data address and data type protocol in the Flash are defined according to the BootLoad design;

[0017] After the user program writing operation is completed, the next time the password security chip is started, the user program in the Flash chip will be executed;

[0018] When the password security chip is powered on, the CPU will first run the ROM startup code. The startup code BootLoad will use the SPI interface to load the user program in the Flash chip into the SRAM. BootLoad controls the loading address and the amount of the loaded program. After waiting for the loading to be completed, the CPU starts to execute the user program from the SRAM startup address 0x60002000 defined in BootLoad.

[0019] Therefore, the present invention adopts the above-mentioned hardware cryptographic module based on the domestic commercial cryptographic algorithm and its implementation method, which has the following beneficial effects:

[0020] (1) The cryptographic engine can be efficiently integrated into the cryptographic security chip, which is conducive to the writing of subsequent software drivers;

[0021] (2) As the hardware foundation, the security chip can only play its security value when the upper-level software is effectively used. Therefore, it is also of great significance to study secure operating systems and secure communications and authentication protocols based on security chips.

[0022] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a cryptographic security chip according to an embodiment of the present invention;

[0024] Figure 2 This is a block diagram of a cryptographic security chip storage control according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Example

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Reference Figure 1-Figure 2 The present invention discloses a hardware cryptographic module based on a domestic commercial cryptographic algorithm and an implementation method thereof, including a hardware module and a software module. The hardware module includes a central control unit, a bus interface bidirectionally connected to the central control unit, a physical security unit and a power supply, and a cryptographic security chip bidirectionally connected to the bus interface. The cryptographic security chip includes a main control processor CPU, an encryption engine, an APB and AHB bus system, a TIMER timer module, an integrated storage unit and a Flash chip. The main control processor CPU selects a CK802 processor.

[0028] Software modules include:

[0029] SM2 software module, used to complete signature verification, encryption and decryption, mode control, and data reading;

[0030] SM3 software module, used to complete message grouping, filling, mode control, and data reading;

[0031] SM4 software module is used to complete mode control and data reading.

[0032] The APB bus system integrates GPIO, SPI, I2C and UART communication interfaces, and the AHB bus system is equipped with storage units and cryptographic engine units.

[0033] The APB bus system data exchanges data with the main control processor through the AHB bus system and is connected through the apb_bridge module.

[0034] The encryption engine integrates a random number generator, a PUF module, an SM2 / 3 / 4 hardware password module, a read-only memory ROM and a random access memory SRAM.

[0035] SM2 hardware cryptographic module, used to perform point calculation and modulus calculation functions.

[0036] SM3 hardware cryptographic module, with expansion, iterative compression, and hash generation functions.

[0037] SM4 hardware cryptographic module, used to complete round key generation and encryption and decryption functions.

[0038] For the implementation of the SM2 hardware cryptographic module, since the maximum operating frequency of the processor CK802 is 50Mz, a 128-bit multiplier is used in conjunction with a 512-bit adder, as well as a fast modular reduction algorithm under a special domain to complete a modular multiplication operation in 4 cycles. In addition, coordinate transformation and non-adjacent encoding method HAF are used, and the doubling and point addition scheduling schemes are optimized to successfully accelerate the core operation of point multiplication in SM2.

[0039] A method for implementing a hardware cryptographic module based on a domestic commercial cryptographic algorithm, and a storage control method for a cryptographic security chip are as follows:

[0040] After the program is compiled, the main control processor calls SPI to write the user program into the Flash chip. The data address and data type protocol in the Flash are defined according to the BootLoad design;

[0041] After the user program writing operation is completed, the next time the password security chip is started, the user program in the Flash chip will be executed;

[0042] When the password security chip is powered on, the CPU will first run the ROM startup code. The startup code BootLoad will use the SPI interface to load the user program in the Flash chip into the SRAM. BootLoad controls the loading address and the amount of the loaded program. After waiting for the loading to be completed, the CPU starts to execute the user program from the SRAM startup address 0x60002000 defined in BootLoad.

[0043] Each cryptographic engine module needs to exchange data with the CPU through the AHB bus. Therefore, this paper provides a slave interface IP solution for the integration of the cryptographic engine module based on the AHB-Lite bus transmission protocol and the idea of ​​hardware-software co-design. This IP interface solution can convert the cryptographic operation engine into an AHB slave device, making it easier to integrate the cryptographic engine into the cryptographic security chip system. The AHB master module corresponds to the CPU in the chip, the AHB slave module corresponds to the cryptographic engine module, and the data path between the CPU and the cryptographic engine module is established through the slave interface IP.

[0044] The Slave interface control IP mainly consists of the following parts: address decoder, read / write controller, data storage module, data selection module. Four types of registers are defined in the Slave interface IP, namely input register, data output register, module status register, and control register. The interface design is mainly based on the AHB bus read / write timing design. When the CPU wants to interact with the cryptographic engine, the CPU issues the address, read / write control signal, and data signal to the AHB bus through instructions. The data flow direction between the CPU and the cryptographic engine is determined according to the read / write control. Specifically, it includes the following two aspects:

[0045] When the CPU performs a write operation on a cryptographic engine, the Slave interface of the cryptographic engine receives the chip select signal, address signal, and read / write control signal, finds the register that needs to be written according to the address decoder, and writes the data on the HWDATA bus to the register under the corresponding address. The register data will be directly passed to the module input interface of the encryption engine, thereby completing the writing of the cryptographic engine module data.

[0046] When the CPU performs a read operation on a cryptographic engine, the Slave interface of the cryptographic engine receives the chip select signal, address signal, and read / write control signal, and finds the register that needs to be read according to the address decoder. The readable register is connected to the output signal of the cryptographic engine, so the output result of the cryptographic engine will be transmitted to HRDATA on the AHB bus through the output register, thereby completing the CPU's read operation on the output result of the cryptographic engine.

[0047] Therefore, the present invention adopts the above-mentioned hardware cryptographic module based on the domestic commercial cryptographic algorithm and its implementation method, which can efficiently integrate the cryptographic engine into the cryptographic security chip, which is conducive to the subsequent software driver writing; the security chip is the hardware foundation, and the effective use of the upper-level software can give full play to the security value of the chip. Therefore, it is also of great significance to study secure operating systems and secure communications and authentication protocols based on security chips.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A hardware cryptographic module based on a domestic commercial cryptographic algorithm, characterized in that: It includes hardware modules and software modules. The hardware module includes a central control unit, a bus interface bidirectionally connected to the central control unit, a physical security unit and a power supply, and a cryptographic security chip bidirectionally connected to the bus interface. The cryptographic security chip includes a main control processor CPU, an encryption engine, APB and AHB bus systems, a TIMER timer module, an integrated storage unit and a Flash chip.

2. A hardware cryptographic module based on a domestically produced commercial cryptographic algorithm according to claim 1, characterized in that: Software modules include: SM2 software module, used to complete signature verification, encryption and decryption, mode control, and data reading; SM3 software module, used to complete message grouping, filling, mode control, and data reading; SM4 software module is used to complete mode control and data reading.

3. A hardware cryptographic module based on a domestically produced commercial cryptographic algorithm according to claim 2, characterized in that: The APB bus system integrates GPIO, SPI, I2C and UART communication interfaces, and the AHB bus system is equipped with storage units and cryptographic engine units.

4. The method for implementing a hardware cryptographic module based on a domestic commercial cryptographic algorithm as claimed in claim 3 is characterized in that: The APB bus system data exchanges data with the main control processor through the AHB bus system and is connected through the apb_bridge module.

5. According to claim 1, a hardware cryptographic module based on a domestic commercial cryptographic algorithm and its implementation method, characterized in that: The encryption engine integrates a random number generator, a PUF module, an SM2 / 3 / 4 hardware password module, a read-only memory ROM and a random access memory SRAM.

6. A method for implementing a hardware cryptographic module based on a domestic commercial cryptographic algorithm according to any one of claims 1 to 5, characterized in that: The storage control method of the password security chip is as follows: After the program is compiled, the main control processor calls SPI to write the user program into the Flash chip. The data address and data type protocol in the Flash are defined according to the BootLoad design; After the user program writing operation is completed, the next time the password security chip is started, the user program in the Flash chip will be executed; When the password security chip is powered on, the CPU will first run the ROM startup code. The startup code BootLoad will use the SPI interface to load the user program in the Flash chip into the SRAM. BootLoad controls the loading address and the amount of the loaded program. After waiting for the loading to be completed, the CPU starts to execute the user program from the SRAM startup address 0x60002000 defined in BootLoad.

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