Waveform symmetry optimization circuit and optimization method in CAN bus

Abstract

The present application provides a waveform symmetry optimization circuit in a CAN bus, which is applied to the technical field of integrated circuits, wherein a resistor is connected in series between an N-type buried layer and a drain of a first LDMOS tube, and in the optimization circuit, if a current flows through a diode from a back gate to an N-type buried layer of the first LDMOS tube, the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate to the drain of the first LDMOS tube, so as to reduce the parasitic PNP leakage of the diode from the back gate to the N-type buried layer of the first LDMOS tube to the P-type substrate, suppress the parasitic PNP leakage of the diode from the back gate to the N-type buried layer of the first LDMOS tube to the P-type substrate, reduce the probability of closed-eye pitting, optimize the waveform symmetry in the CAN bus, reduce radiation, and improve communication reliability.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a waveform symmetry optimization circuit and optimization method in a CAN bus. Background Art

[0002] In the prior art, a BCD (Bipolar CMOS and DMOS) process is used. The BCD process is a monolithic integration process technology that can manufacture bipolar transistors (Bipolar), complementary metal oxide semiconductors (CMOS) and metal oxide semiconductor field effect transistors (DMOS) devices on the same chip.

[0003] When the current CAN bus (Controller Area Network) is working normally, the parasitic PNP (parasitic PNP transistor) leakage to the substrate in the current high-voltage BCD process can easily lead to the problem of frequent closed-eye pitting and depression, which in turn causes the waveform symmetry of the CAN bus to be poor.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, the present application provides a waveform symmetry optimization circuit and optimization method in a CAN bus.

[0006] This application provides the following technical solutions:

[0007] A waveform symmetry optimization circuit in a CAN bus provided by the present application includes multiple LDMOS tubes; the multiple LDMOS tubes include a first LDMOS tube and a second LDMOS tube; the CAN bus includes a high-level signal line CANH and a low-level signal line CANL; the first LDMOS tube is connected to the high-level signal line CANH; the second LDMOS tube is connected to the low-level signal line CANL; wherein a resistor is connected in series between an N-type buried layer and a drain of the first LDMOS tube to suppress parasitic PNP leakage to a P-type substrate when a diode from a back gate of the first LDMOS tube to an N-type buried layer is turned on, thereby optimizing the waveform symmetry in the CAN bus.

[0008] Preferably, the first LDMOS transistor includes a first N-channel LDMOS transistor NLD1, and the second LDMOS transistor includes a second N-channel LDMOS transistor NLD2; the plurality of LDMOS transistors further include a first P-channel LDMOS transistor PLD1 and a second P-channel LDMOS transistor PLD2;

[0009] The first N-channel LDMOS transistor NLD1 is connected to the high-level signal line CANH through the first P-channel LDMOS transistor PLD1; the second N-channel LDMOS transistor NLD2 is connected to the low-level signal line CANL through the second P-channel LDMOS transistor PLD2, so that the optimized circuit forms a symmetrical circuit structure.

[0010] Preferably, the gate of the first N-channel LDMOS transistor NLD1 is connected to the power supply voltage terminal VCC, and the drain of the first N-channel LDMOS transistor NLD1 is also connected to the source of the first P-channel LDMOS transistor PLD1;

[0011] The gate of the first P-channel LDMOS transistor PLD1 is grounded, and the drain of the first P-channel LDMOS transistor PLD1 is connected to the high-level signal line CANH;

[0012] The gate of the second N-channel LDMOS transistor NLD2 is connected to the power supply voltage terminal VCC, and the drain of the second N-channel LDMOS transistor NLD2 is connected to the source of the second P-channel LDMOS transistor PLD2;

[0013] A gate of the second P-channel LDMOS transistor PLD2 is grounded, and a drain of the second P-channel LDMOS transistor PLD2 is connected to a low-level signal line CANL.

[0014] Preferably, the optimization circuit further includes a P-channel field effect transistor and an N-channel field effect transistor;

[0015] The P-channel field effect transistor is connected to the source of the first N-channel LDMOS transistor NLD1 , and the N-channel field effect transistor is connected to the source of the second N-channel LDMOS transistor NLD2 .

[0016] Preferably, the P-channel field effect transistors are provided in plurality, including a first P-channel field effect transistor PM1 and a second P-channel field effect transistor PM2; the N-channel field effect transistors are provided in plurality, including a first N-channel field effect transistor NM1 and a second N-channel field effect transistor NM2;

[0017] The drain of the first P-channel field effect transistor PM1 is connected to the gate of the first P-channel field effect transistor PM1 and the gate of the second P-channel field effect transistor PM2 respectively;

[0018] The source of the first P-channel field effect transistor PM1 is connected to the source of the second P-channel field effect transistor PM2;

[0019] The drain of the first N-channel field effect transistor NM1 is connected to the gate of the first N-channel field effect transistor NM1 and the gate of the second N-channel field effect transistor NM2 respectively;

[0020] The source of the second N-channel field effect transistor NM1 is connected to the source of the second N-channel field effect transistor NM2.

[0021] Preferably, the optimization circuit further includes a data transmission terminal TXD, an inverter, a first current source and a second current source;

[0022] The data transmission terminal TXD is connected to the switch control terminal of the first current source and the switch control terminal of the second current source through the inverter output; the first current source is connected to the drain of the first P-channel field effect transistor PM1; the second current source is connected to the drain of the first N-channel field effect transistor NM1.

[0023] Preferably, the data transmission terminal TXD inputs high and low level signals, and controls the on or off of the second P-channel field effect transistor PM2 and the second N-channel field effect transistor NM2 to perform dominant level and recessive level between the high level signal line CANH and the low level signal line CANL.

[0024] Preferably, the optimization circuit has current flowing through the diode from the back gate of the first LDMOS tube to the N-type buried layer, and the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate of the first LDMOS tube to the drain, so as to reduce the parasitic PNP leakage of the diode from the back gate of the first LDMOS tube to the N-type buried layer to the P-type substrate.

[0025] According to an optimization method also provided by the present application, the waveform symmetry optimization circuit in the CAN bus described above is applied, including: connecting a resistor in series between the N-type buried layer and the drain of the first LDMOS tube, and in the optimization circuit, a current flows through the diode from the back gate to the N-type buried layer of the first LDMOS tube, then the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate to the drain of the first LDMOS tube, so as to reduce the parasitic PNP leakage of the diode from the back gate to the N-type buried layer of the first LDMOS tube to the P-type substrate, thereby optimizing the waveform symmetry in the CAN bus.

[0026] Preferably, the optimization method further includes: the first LDMOS tube is set as a first N-channel LDMOS tube NLD1, and the second LDMOS tube is set as a second N-channel LDMOS tube NLD2;

[0027] The first N-channel LDMOS transistor NLD1 is connected to the high-level signal line CANH through the first P-channel LDMOS transistor PLD1; the second N-channel LDMOS transistor NLD2 is connected to the low-level signal line CANL through the second P-channel LDMOS transistor PLD2, so that the optimized circuit forms a symmetrical circuit structure; the input high and low level signals control the dominant level and recessive level between the high-level signal line CANH and the low-level signal line CANL.

[0028] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the present application include at least:

[0029] In the present application, a high-level signal line CANH connected to the CAN bus is connected through a first LDMOS tube, and a low-level signal line CANL connected to the CAN bus is connected through a second LDMOS tube. A resistor is connected in series between the N-type buried layer and the drain of the first LDMOS tube. In the optimization circuit, if a current flows through the diode from the back gate to the N-type buried layer of the first LDMOS tube, the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate to the drain of the first LDMOS tube, so as to reduce the parasitic PNP leakage from the diode from the back gate to the N-type buried layer of the first LDMOS tube to the P-type substrate, suppress the parasitic PNP leakage from the diode from the back gate to the N-type buried layer of the first LDMOS tube to the P-type substrate, reduce the probability of closed-eye pitting, optimize the waveform symmetry in the CAN bus, reduce radiation, and improve communication reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 It is the schematic diagram of CAN output architecture;

[0032] Figure 2 This is a schematic diagram of the optimized connection circuit of the NLD1 tube;

[0033] Figure 3 is a schematic diagram of a cross section of a high voltage LDMOS;

[0034] Figure 4 It is a schematic diagram of the high voltage LDMOS parasitic PNP;

[0035] Figure 5 This is a schematic diagram of a normal CAN bus waveform;

[0036] Figure 6 This is a schematic diagram of the CAN bus waveform when the NLD1 parasitic PNP leakage is large. DETAILED DESCRIPTION

[0037] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0038] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0039] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0040] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0041] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0042] In view of this, the applicant conducted in-depth research and improvement exploration on the CAN bus and found that: the SOI (Silicon-On-Insulator) process is generally used, that is, silicon on an insulating substrate. The SOI process is a semiconductor manufacturing technology that achieves dielectric isolation of components in integrated circuits by introducing a buried oxide layer between the top silicon and the back substrate. This technology can effectively reduce parasitic capacitance and leakage current, improve operating speed and energy efficiency, and is particularly suitable for low-voltage and low-power circuits. This process uses dielectric isolation and has no leakage, but the disadvantage is that the cost is very high, which is not conducive to industrial competition.

[0043] Based on this, the technical solutions provided by the embodiments of the present application are described below in conjunction with the accompanying drawings.

[0044] The embodiment of this specification proposes a waveform symmetry optimization circuit in a CAN bus, such as Figure 1 and Figure 2 As shown, it includes multiple LDMOS tubes; the multiple LDMOS tubes include a first LDMOS tube and a second LDMOS tube; the CAN bus includes a high-level signal line CANH and a low-level signal line CANL; the first LDMOS tube is connected to the high-level signal line CANH; the second LDMOS tube is connected to the low-level signal line CANL; wherein a resistor is connected in series between the N-type buried layer and the drain of the first LDMOS tube to suppress the parasitic PNP leakage to the P-type substrate when the diode from the back gate to the N-type buried layer of the first LDMOS tube is turned on, thereby optimizing the waveform symmetry in the CAN bus. The full name of the LDMOS tube in English is Laterally Diffused Metal Oxide Semiconductor, and its Chinese translation is Laterally Diffused Metal Oxide Semiconductor.

[0045] In one embodiment, the first LDMOS transistor includes a first N-channel LDMOS transistor NLD1, and the second LDMOS transistor includes a second N-channel LDMOS transistor NLD2; the plurality of LDMOS transistors further include a first P-channel LDMOS transistor PLD1 and a second P-channel LDMOS transistor PLD2; the first N-channel LDMOS transistor NLD1 is connected to a high-level signal line CANH through the first P-channel LDMOS transistor PLD1; the second N-channel LDMOS transistor NLD2 is connected to a low-level signal line CANL through the second P-channel LDMOS transistor PLD2, so that the optimized circuit forms a symmetrical circuit structure.

[0046] In one embodiment, the gate of the first N-channel LDMOS transistor NLD1 is connected to the power supply voltage terminal VCC, and the drain of the first N-channel LDMOS transistor NLD1 is also connected to the source of the first P-channel LDMOS transistor PLD1; the gate of the first P-channel LDMOS transistor PLD1 is grounded, and the drain of the first P-channel LDMOS transistor PLD1 is connected to the high-level signal line CANH.

[0047] The gate of the second N-channel LDMOS transistor NLD2 is connected to the power supply voltage terminal VCC, and the drain of the second N-channel LDMOS transistor NLD2 is connected to the source of the second P-channel LDMOS transistor PLD2; the gate of the second P-channel LDMOS transistor PLD2 is grounded, and the drain of the second P-channel LDMOS transistor PLD2 is connected to the low-level signal line CANL.

[0048] In one embodiment, the optimization circuit further includes a P-channel field effect transistor and an N-channel field effect transistor; the P-channel field effect transistor is connected to the source of the first N-channel LDMOS transistor NLD1, and the N-channel field effect transistor is connected to the source of the second N-channel LDMOS transistor NLD2.

[0049] In one embodiment, a plurality of P-channel field effect transistors are provided, including a first P-channel field effect transistor PM1 and a second P-channel field effect transistor PM2; a plurality of N-channel field effect transistors are provided, including a first N-channel field effect transistor NM1 and a second N-channel field effect transistor NM2.

[0050] The drain of the first P-channel field effect transistor PM1 is connected to the gate of the first P-channel field effect transistor PM1 and the gate of the second P-channel field effect transistor PM2 respectively; the source of the first P-channel field effect transistor PM1 is connected to the source of the second P-channel field effect transistor PM2.

[0051] The drain of the first N-channel field effect transistor NM1 is connected to the gate of the first N-channel field effect transistor NM1 and the gate of the second N-channel field effect transistor NM2 respectively; the source of the second N-channel field effect transistor NM1 is connected to the source of the second N-channel field effect transistor NM2.

[0052] In one embodiment, the optimization circuit further includes a data transmission terminal TXD, an inverter, a first current source, and a second current source. The data transmission terminal TXD is connected to a switch control terminal of the first current source after being output by the inverter to control the on or off of the first current; wherein the switch tube may be a gate of a P-channel field effect tube; the data transmission terminal TXD is connected to a switch control terminal of the second current source after being output by the inverter to control the on or off of the second current, wherein the switch tube may be a gate of an N-channel field effect tube.

[0053] In one embodiment, the data transmission terminal TXD inputs high and low level signals, and controls the on or off of the second P-channel field effect transistor PM2 and the second N-channel field effect transistor NM2 to perform dominant level and recessive level between the high level signal line CANH and the low level signal line CANL.

[0054] In one embodiment, the optimization circuit has current flowing through the diode from the back gate of the first LDMOS tube to the N-type buried layer, and the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate to the drain of the first LDMOS tube to reduce the parasitic PNP leakage from the diode from the back gate of the first LDMOS tube to the N-type buried layer to the P-type substrate.

[0055] The embodiments of the present specification also disclose an optimization method, which uses the waveform symmetry optimization circuit in the CAN bus of any of the above embodiments, including: connecting a resistor in series between the N-type buried layer and the drain of the first LDMOS tube, and in the optimization circuit, if current flows through the diode from the back gate to the N-type buried layer of the first LDMOS tube, the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate to the drain of the first LDMOS tube to reduce the parasitic PNP leakage from the diode from the back gate to the N-type buried layer of the first LDMOS tube to the P-type substrate, thereby optimizing the waveform symmetry in the CAN bus.

[0056] In one embodiment, the optimization method further includes: the first LDMOS transistor is set as a first N-channel LDMOS transistor NLD1, and the second LDMOS transistor is set as a second N-channel LDMOS transistor NLD2.

[0057] The first N-channel LDMOS transistor NLD1 is connected to the high-level signal line CANH through the first P-channel LDMOS transistor PLD1; the second N-channel LDMOS transistor NLD2 is connected to the low-level signal line CANL through the second P-channel LDMOS transistor PLD2, so that the optimized circuit forms a symmetrical circuit structure; the input high and low level signals control the dominant level and recessive level between the high-level signal line CANH and the low-level signal line CANL.

[0058] The present application is a method for optimizing waveform symmetry in a CAN bus, which has the characteristics of good transient symmetry, low radiation and high communication reliability, and the present application has low EME (Electro Magnetic Emission), high integration, simple circuit structure and high reliability. The present application suppresses the parasitic PNP leakage to the substrate when the high-voltage LDMOS body diode is turned on by connecting a resistor in series at the NBL end and the DRAIN end of the high-voltage LDMOS tube, thereby optimizing the pitting problem when the CAN bus is closed, and then optimizing the waveform symmetry in the CAN bus, thereby minimizing EME.

[0059] like Figure 1As shown in the figure, the principle of CAN output architecture is shown. In which, due to the voltage resistance requirements of positive and negative high voltage, the output port of CANH and CANL voltage adopts a symmetrical circuit structure, that is, PLD1 and PLD2 with gate grounded, and NLD1 and NLD2 with gate connected to VCC power supply. The TXD input high and low level signals finally realize the dominant level and recessive level of CANH and CANL buses by controlling the conduction or disconnection of PM2 and NM2 tubes. Among them, VCC is the power supply voltage terminal; GND is grounding; TXD is the data transmission terminal; PM1 and PM2 are P-channel field effect tubes; NM1 and NM2 are N-channel field effect tubes; NLD1 and NLD2 are N-channel LDMOS tubes; PLD1 and PLD2 are P-channel LDMOS tubes; CANH is a high level signal line; CANL is a low level signal line.

[0060] like Figure 2 As shown, the optimized connection structure of the NLD1 tube is shown, wherein the PSUB is grounded, and the NBL is short-connected to the drain end of the LDMOS tube through a resistor. The purpose of the resistor is to suppress the parasitic PNP leakage to the substrate PSUB when the body diode of the high-voltage tube is turned on, thereby optimizing the transient waveform symmetry of the CAN bus and ultimately achieving the reduction of EME. In this application, only the NBL end of the NLD1 tube can be connected to the D end through a resistor, and the other LDMOS tubes are connected normally. Among them, the NBL end is an N-type buried layer, the D end (i.e., the DRAIN end) is the drain; the G end is the gate; the S end is the source; the B end is the back gate; and the PSUB end is a P-type substrate. In addition, the PSUB ends of the LDMOS tubes in this application are all grounded.

[0061] The specific principles are as follows: Figure 3 and Figure 4 As shown in the figure, the cross section of the high-voltage LDMOS and the high-voltage LDMOS parasitic PNP are shown. When the NLD1 tube body diode is turned on, if there is no such resistor, the diode from the B end to the D end and the diode from the B end to the NBL end will form a parallel relationship, and the diode from the B end to the NBL end will form a parasitic PNP leakage to the substrate PSUB, that is, the B end → NBL end → PSUB end. This will increase the extra power consumption of the chip and cause the CAN bus waveform to produce a closed-eye pit, such as Figure 6 After the application adds the resistance from NBL to D, it will have a significant inhibitory effect on the diode current path from B to NBL, because once the current flows through the diode, it will flow through the resistor, thereby raising the NBL potential, making the diode conduction not smooth, and most of the current goes from the body diode from B to D, so the parasitic PNP leakage from B → NBL → PSUB is greatly reduced, thereby optimizing the closed-eye waveform of the CAN bus. The closed-eye waveform is as follows: Figure 5As shown, the EME is finally reduced and the reliability and robustness of signal transmission are improved.

[0062] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0063] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A waveform symmetry optimization circuit in a CAN bus, characterized in that: It includes a plurality of LDMOS tubes; the plurality of LDMOS tubes include a first LDMOS tube and a second LDMOS tube; the CAN bus includes a high level signal line CANH and a low level signal line CANL; The first LDMOS tube is connected to the high level signal line CANH; The second LDMOS tube is connected to the low-level signal line CANL; wherein a resistor is connected in series between the N-type buried layer and the drain of the first LDMOS tube to suppress the parasitic PNP leakage to the P-type substrate when the diode from the back gate to the N-type buried layer of the first LDMOS tube is turned on, thereby optimizing the waveform symmetry in the CAN bus; The first LDMOS transistor includes a first N-channel LDMOS transistor NLD1, and the second LDMOS transistor includes a second N-channel LDMOS transistor NLD2; the plurality of LDMOS transistors further include a first P-channel LDMOS transistor PLD1 and a second P-channel LDMOS transistor PLD2; The first N-channel LDMOS transistor NLD1 is connected to the high-level signal line CANH through the first P-channel LDMOS transistor PLD1; the second N-channel LDMOS transistor NLD2 is connected to the low-level signal line CANL through the second P-channel LDMOS transistor PLD2, so that the optimized circuit forms a symmetrical circuit structure; The gate of the first N-channel LDMOS transistor NLD1 is connected to the power supply voltage terminal VCC, and the drain of the first N-channel LDMOS transistor NLD1 is also connected to the source of the first P-channel LDMOS transistor PLD1; The gate of the first P-channel LDMOS transistor PLD1 is grounded, and the drain of the first P-channel LDMOS transistor PLD1 is connected to the high-level signal line CANH; The gate of the second N-channel LDMOS transistor NLD2 is connected to the power supply voltage terminal VCC, and the drain of the second N-channel LDMOS transistor NLD2 is connected to the source of the second P-channel LDMOS transistor PLD2; A gate of the second P-channel LDMOS transistor PLD2 is grounded, and a drain of the second P-channel LDMOS transistor PLD2 is connected to a low-level signal line CANL.

2. The waveform symmetry optimization circuit in the CAN bus according to claim 1, characterized in that: The optimization circuit also includes a P-channel field effect transistor and an N-channel field effect transistor; The P-channel field effect transistor is connected to the source of the first N-channel LDMOS transistor NLD1 , and the N-channel field effect transistor is connected to the source of the second N-channel LDMOS transistor NLD2 .

3. The waveform symmetry optimization circuit in the CAN bus according to claim 2, characterized in that: The P-channel field effect transistors are provided in plurality, including a first P-channel field effect transistor PM1 and a second P-channel field effect transistor PM2; the N-channel field effect transistors are provided in plurality, including a first N-channel field effect transistor NM1 and a second N-channel field effect transistor NM2; The drain of the first P-channel field effect transistor PM1 is connected to the gate of the first P-channel field effect transistor PM1 and the gate of the second P-channel field effect transistor PM2 respectively; The source of the first P-channel field effect transistor PM1 is connected to the source of the second P-channel field effect transistor PM2; The drain of the first N-channel field effect transistor NM1 is connected to the gate of the first N-channel field effect transistor NM1 and the gate of the second N-channel field effect transistor NM2 respectively; The source of the second N-channel field effect transistor NM1 is connected to the source of the second N-channel field effect transistor NM2.

4. The waveform symmetry optimization circuit in the CAN bus according to claim 3, characterized in that: The optimization circuit also includes a first current source and a second current source; The data transmission terminal TXD is connected to the switch control terminal of the first current source and the switch control terminal of the second current source through the inverter output; the first current source is connected to the drain of the first P-channel field effect transistor PM1; the second current source is connected to the drain of the first N-channel field effect transistor NM1.

5. The waveform symmetry optimization circuit in the CAN bus according to claim 4, characterized in that: The data transmission terminal TXD inputs high and low level signals, and controls the dominant level and recessive level between the high level signal line CANH and the low level signal line CANL by controlling the conduction or disconnection of the second P-channel field effect transistor PM2 and the second N-channel field effect transistor NM2.

6. The waveform symmetry optimization circuit in the CAN bus according to any one of claims 1 to 5, characterized in that: In the optimization circuit, when current flows through the diode from the back gate of the first LDMOS tube to the N-type buried layer, the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate of the first LDMOS tube to the drain, so as to reduce the parasitic PNP leakage of the diode from the back gate of the first LDMOS tube to the N-type buried layer to the P-type substrate.

7. An optimization method, characterized in that: A waveform symmetry optimization circuit in a CAN bus according to any one of claims 1 to 6 is applied, comprising: a resistor is connected in series between the N-type buried layer and the drain of a first LDMOS tube, and when a current flows through the diode from the back gate to the N-type buried layer of the first LDMOS tube in the optimization circuit, the current flows through the series resistor to raise the potential of the N-type buried layer of the first LDMOS tube, so that the current passes through the diode from the back gate to the drain of the first LDMOS tube to reduce the parasitic PNP leakage from the diode from the back gate to the N-type buried layer of the first LDMOS tube to the P-type substrate, thereby optimizing the waveform symmetry in the CAN bus.

8. The optimization method according to claim 7, characterized in that: The optimization method further includes: the first LDMOS tube is set as a first N-channel LDMOS tube NLD1, and the second LDMOS tube is set as a second N-channel LDMOS tube NLD2; The first N-channel LDMOS transistor NLD1 is connected to the high-level signal line CANH through the first P-channel LDMOS transistor PLD1; the second N-channel LDMOS transistor NLD2 is connected to the low-level signal line CANL through the second P-channel LDMOS transistor PLD2, so that the optimized circuit forms a symmetrical circuit structure; the input high and low level signals control the dominant level and recessive level between the high-level signal line CANH and the low-level signal line CANL.

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