Semiconductor structure, memory structure and semiconductor device

Abstract

A semiconductor structure according to the present disclosure includes: a first memory cell including a first pull-down transistor and a first pull-up transistor sharing a first gate structure extending along a first direction; a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the first direction; a first transfer gate transistor having a third gate structure spaced apart from but aligned with the second gate structure along the first direction; and a second transfer gate transistor having a fourth gate structure spaced apart from but aligned with the first gate structure along the first direction; a front interconnect structure disposed over the first memory device; and a backside interconnect structure disposed under the first memory device. A source of the second pull-down transistor is electrically connected to the backside interconnect structure through the first backside contact via. The embodiment of the invention also discloses a memory structure and a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures, memory structures, and semiconductor devices. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can support more and more complex and advanced functions at the same time. Accordingly, there is a continuous trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved to a large extent by reducing the size of semiconductor ICs (e.g., minimum feature size), thereby improving production efficiency and reducing related costs. However, this scaling has also led to increased complexity in semiconductor manufacturing processes. Therefore, the continued progress of semiconductor ICs and devices requires similar progress in semiconductor manufacturing processes and technology.

[0003] Static random access memory ("SRAM") generally refers to any memory or storage device that can retain stored data only when powered on. As integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate structures such as fin field effect transistors (FinFETs) or gate-all-around (GAA) transistors are integrated into SRAM cells to improve performance. As the size of SRAM cells continues to shrink, the contact structures that functionally interconnect the transistors in the SRAM cells present additional challenges in terms of reducing resistance (R) and capacitance (C). Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a first memory cell, comprising: a first pull-down transistor and a first pull-up transistor, sharing a first gate structure extending along a first direction; a second pull-down transistor and a second pull-up transistor, sharing a second gate structure extending along the first direction; a first transmission gate transistor, having a third gate structure spaced apart from the second gate structure but aligned with the second gate structure along the first direction; and a second transmission gate transistor, having a fourth gate structure spaced apart from the first gate structure but aligned with the first gate structure along the first direction. The semiconductor structure also includes: a front interconnect structure, disposed above the first memory cell; and a back interconnect structure, disposed below the first memory cell; wherein the source of the second pull-down transistor is electrically connected to the front interconnect structure through a first source / drain contact; wherein the source of the second pull-down transistor is electrically connected to the back interconnect structure through a first back contact via.

[0005] According to another aspect of the embodiment of the present application, a memory structure is provided, comprising: a first memory cell, comprising: a first active region, a second active region, a third active region, and a fourth active region, extending in parallel along a first direction; a first gate structure, extending longitudinally along a second direction perpendicular to the first direction, the first gate structure is joined with the first active region and the second active region to form a first pull-down transistor and a first pull-up transistor, respectively; and a second gate structure, extending longitudinally along the second direction, the second gate structure is joined with the third active region and the fourth active region to form a second pull-up transistor and a second pull-down transistor, respectively. The memory structure also includes: a front interconnect structure, arranged above the first memory cell; and a back interconnect structure, arranged below the first memory cell; wherein the source of the second pull-down transistor is electrically connected to the front interconnect structure through a first source / drain contact; wherein the source of the second pull-down transistor is electrically connected to the back interconnect structure through a first back contact via.

[0006] According to another aspect of the embodiments of the present application, a semiconductor device is provided, including: a first pull-down transistor and a first pull-up transistor, which share a first gate structure extending along a first direction; a second pull-down transistor and a second pull-up transistor, which share a second gate structure extending along the direction; a first transmission gate transistor, having a third gate structure spaced apart from the second gate structure along the direction but aligned with the second gate structure; a second transmission gate transistor, having a fourth gate structure spaced apart from the first gate structure along the direction but aligned with the first gate structure; a first back-side docking contact, which physically contacts a bottom surface of the first gate structure and a bottom surface of a source of the second pull-up transistor; and a second back-side docking contact, which physically contacts the second gate structure and the source of the first pull-up transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a circuit diagram of an SRAM cell according to various aspects of the present disclosure

[0009] Figure 2 is a top view of an SRAM cell according to various aspects of the present disclosure;

[0010] Figure 3 is a partial top view of a front-side interconnect structure of a SRAM quad-cell according to various aspects of the present disclosure;

[0011] Figure 4 According to various aspects of the present disclosure Figure 3 A partial cross-sectional view of section AA' in FIG.

[0012] Figure 5 is a partial top view of a backside interconnect structure of a SRAM quad-cell according to various aspects of the present disclosure;

[0013] Figure 6 According to various aspects of the present disclosure Figure 5 A partial cross-sectional view of the section BB' in FIG.

[0014] Figure 7 According to various aspects of the present disclosure Figure 5 A partial cross-sectional view of the section C-C' in FIG.

[0015] Figure 8 is a partial top view of a front-side interconnect structure of a SRAM quad-cell according to various aspects of the present disclosure;

[0016] Fig. 9 According to various aspects of the present disclosure Figure 8 A partial cross-sectional view of the section BB' in FIG.

[0017] Fig.10 According to various aspects of the present disclosure Figure 8 A partial cross-sectional view of the section BB' in FIG.

[0018] Fig.11 is a partial top view of a front-side interconnect structure of a SRAM quad-cell according to various aspects of the present disclosure;

[0019] Fig.12 is a partial top view of a backside interconnect structure of a SRAM quad-cell according to various aspects of the present disclosure;

[0020] Fig.13 According to various aspects of the present disclosure Fig.12 A partial cross-sectional view of the section D-D' in FIG.

[0021] Fig.14 According to various aspects of the present disclosure Fig.12 A partial cross-sectional view of the section EE' in FIG.

[0022] Fig.15 is a partial top view of a backside interconnect structure of a SRAM quad-cell according to various aspects of the present disclosure;

[0023] Fig.16 is a partial top view of a backside interconnect structure of a SRAM quad-cell according to various aspects of the present disclosure;

[0024] Fig.17is a block diagram of an SRAM array according to various aspects of the present disclosure;

[0025] Figure 18-Figure 21 According to various aspects of the present disclosure Fig.17 The top layout diagram of the SRAM array in;

[0026] Fig. 22 is a block diagram of an SRAM array including a power tap edge cell according to various aspects of the present disclosure;

[0027] Figure 23-Figure 27 is a top layout diagram of an SRAM array including power tap edge cells according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0029] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0030] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range that take into account variations inherently caused during manufacturing as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having features associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, for example, within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may encompass a range of sizes from 4.25 nm to 5.75 nm, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with depositing material layers is + / - 15%. When describing aspects of transistors, the source / drain regions may refer to the source or drain individually or collectively, depending on the context.

[0031] Static random access memory (SRAM) is a semiconductor memory that retains data in a static form as long as the memory has power. Compared with dynamic RAM (DRAM), SRAM is faster, more reliable, and does not require refreshing. SRAM is widely used in many applications, such as cache memory in computers and as part of the random access memory of digital-to-analog converters on video cards. As integrated circuit (IC) technology moves towards smaller technology nodes, multi-gate structures such as fin field effect transistors (FinFETs) or full-all-around gate (GAA) transistors are integrated into SRAM cells to improve performance. The reduction in size creates stress on electrical wiring. When only the front-side interconnect structure exists, the contact vias and metal lines are closely spaced, and the front-side connections to various transistor nodes in the SRAM cell may exhibit high resistance. The tight spacing and high contact resistance may result in high resistance and capacitance, which may result in low drive current and low speed.

[0032] The present disclosure provides an SRAM device, which includes not only a front interconnection but also a back interconnection to improve the performance of the SRAM device. In one embodiment, the source of the pull-down transistor is connected to the back ground rail through a back contact to increase the pull-down current, while the source region of the transmission gate transistor is not connected to the back ground rail. This arrangement improves the beta ratio and alpha ratio of the SRAM device. In another embodiment, the back contacts to the source of the pull-down transistor of the adjacent SRAM cell can be merged to reduce the contact resistance. In another embodiment, the front docking contact is replaced by a back docking contact to provide a cross-locking. This provides space saving by removing the front docking contact. In another embodiment, a filled through via (FTV) is placed in a power tapping area along the edge of the SRAM array. In addition to the back contact, or as a substitute for the back contact, the FTV also provides additional front-to-back electrical lines.

[0033] Figure 1 An exemplary type of memory device is shown in which transistors such as planar transistors, FinFET transistors, or gate-all-around (GAA) transistors may be implemented. In this regard, Figure 1 A circuit schematic diagram of an exemplary SRAM device (e.g., as a single-port SRAM cell (e.g., 1-bit SRAM cell) 10) is shown. The single-port SRAM cell 10 includes a first transmission gate transistor PG1 and a second transmission gate transistor PG2, a first pull-up transistor PU1 and a second pull-up transistor PU2, and a first pull-down transistor PD1 and a second pull-down transistor PD2. The gates of the first transmission gate transistor PG1 and the second transmission gate transistor PG2 are electrically connected to a word line (WL) that determines whether the SRAM cell 10 is selected. In the SRAM cell 10, a memory bit (e.g., a latch or a flip-flop) is formed by a first pull-up transistor PU1 and a second pull-up transistor PU2, and a first pull-down transistor PD1 and a second pull-down transistor PD2 to store a data bit. The complementary value of the bit is stored in a first storage node SN1 and a first complementary storage node SNB1. The stored bit can be written into the SRAM cell 10 or read from the SRAM cell 10 via a bit line (BL) and a bit line bar (BLB). In this arrangement, BL and BLB can carry complementary bit line signals. The SRAM cell 10 is powered by a positive power supply voltage Vdd and is also connected to a ground potential Vss.

[0034] The SRAM cell 10 includes a first inverter 12 formed by a first pull-up transistor PU1 and a first pull-down transistor PD1, and a second inverter 14 formed by a second pull-up transistor PU2 and a second pull-down transistor PD2. Figure 1 As shown in FIG. 1 , the drains of the first pull-up transistor PU1 and the first pull-down transistor PD1 are connected together, and the drains of the second pull-up transistor PU2 and the second pull-down transistor PD2 are connected together. The first inverter 12 and the second inverter 14 are connected between the positive power supply voltage Vdd and the ground potential Vss. Figure 1As shown in , the first inverter 12 and the second inverter 14 are cross-connected. That is, the first inverter 12 has an input terminal connected to the output terminal of the second inverter 14. Similarly, the second inverter 14 has an input terminal connected to the output terminal of the first inverter 12. The output terminal of the first inverter 12 is called the first storage node SN1. Similarly, the output terminal of the second inverter 14 is called the first complementary storage node SNB1. In the normal operation mode, the first storage node SN1 is in a logic state (logic high or logic low) opposite to the first complementary storage node SNB1. By adopting two cross-connected inverters, the SRAM cell 10 can use a latch structure to hold data, so that as long as the power is supplied by Vdd, the stored data will not be lost without applying a refresh cycle.

[0035] Reference now Figure 2 , which shows Figure 1 An exemplary layout of the SRAM cell 10 is shown in FIG. Figure 1 Like the SRAM cell 10 in Figure 2 The layout in includes six (6) transistors used as a first pass gate transistor PG1, a second pass gate transistor PG2, a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2. Figure 2 In some embodiments represented in FIG. 1 , the SRAM cell 10 may be formed over an n-type well 32 (or N-well 32), which is sandwiched between two p-type wells 30 and 34 (or P-wells 30 and 34). The N-well 32 and the P-wells 30 and 34 are formed over a substrate. In some embodiments, as Figure 2 As shown in FIG. 1 , the first transfer gate transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second transfer gate transistor PG2 may be formed over P-wells 30 and 34; and the first pull-up transistor PU1 and the second pull-up transistor PU2 are formed in the N-well 32. In these embodiments, the first transfer gate transistor PG1, the first pull-down transistor PD1, the second pull-down transistor PD2, and the second transfer gate transistor PG2 are n-type GAA transistors; the first pull-up transistor PU1 and the second pull-up transistor PU2 are p-type GAA transistors.

[0036] In some embodiments, the SRAM cell 10 includes four fin-shaped vertical stacks—a first fin-shaped vertical stack 40, a second fin-shaped vertical stack 42, a third fin-shaped vertical stack 44, and a fourth fin-shaped vertical stack 46. The first fin-shaped vertical stack 40 is formed above the P-well 30 and forms a channel region of a first transfer gate transistor PG1 and a first pull-down transistor PD1. The second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 are formed above the N-well 32 and form a channel region of a first pull-up transistor PU1 and a second pull-up transistor PU2, respectively. The fourth fin-shaped vertical stack 46 is formed above the P-well 34 and forms a channel region of a second pull-down transistor PD2 and a second transfer gate transistor PG2. Each of the first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 may include about two (2) to about ten (10) channel components. In some embodiments, each of the first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 includes four channel members. Each of the first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 may be referred to as an active region.

[0037] In some cases, a fin-shaped vertical stack can be formed by depositing or epitaxially growing alternating layers of two different semiconductor materials, patterning the alternating layers to form a fin-shaped structure, and selectively removing a layer formed by one of the two semiconductor materials. For example, an alternating layer of epitaxially grown silicon (Si) and silicon germanium (SiGe) can be formed on a substrate. The substrate can be a silicon (Si) substrate. Then, the alternating layers can be patterned to form a fin-shaped structure of a stack including staggered Si strips and SiGe strips. In a process for forming a transistor channel region in an SRAM cell, the channel region of the fin-shaped structure can undergo different etching processes to selectively remove the SiGe strips and release the silicon layer as a suspended silicon channel member. The channel member can be of different shapes and sizes and can be referred to as a nanostructure, nanowire, or nanosheet. These fin-shaped structures are separated by isolation components such as shallow trench isolation (STI) components. In some embodiments, each fin-shaped vertical stack can include a top formed by alternating layers, and a base formed by a substrate. The base of the fin-shaped vertical stack has a fin shape and can be referred to as a fin structure. The base of the fin-shaped vertical stack can be substantially buried in the isolation component, and the top of the base of the fin-shaped vertical stack can be flush with the top surface of the isolation component. The top of the fin-shaped vertical stack extends from the isolation component and rises above the isolation component.

[0038] Still reference Figure 2. The channel components in the first fin-shaped vertical stack 40 form the channel regions of the first transfer gate transistor PG1 and the first pull-down transistor PD1. The channel components in the second fin-shaped vertical stack 42 form the channel region of the first pull-up transistor PU1. The channel components in the third fin-shaped vertical stack 44 form the channel region of the second pull-up transistor PU2. The channel components in the fourth fin-shaped vertical stack 46 form the channel regions of the second pull-down transistor PD2 and the second transfer gate transistor PG2. In the depicted embodiment, the first fin-shaped vertical stack 40 and the fourth fin-shaped vertical stack 46 are used to form an n-type GAA transistor, and the second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 are used to form a p-type GAA transistor. Figure 2 In the embodiment shown in , the first transmission gate transistor PG1, the first pull-down transistor PD1, the second transmission gate transistor PG2, and the second pull-down transistor PD2 are n-type GAA transistors, and the first pull-up transistor PU1 and the second pull-up transistor PU-2 are p-type GAA transistors. Figure 2 , each of the first fin-shaped vertical stack 40 and the fourth fin-shaped vertical stack 46 has a first width W1 along the X direction, and each of the second fin-shaped vertical stack 42 and the third fin-shaped vertical stack 44 has a second width W2 along the X direction. In some embodiments, in order to achieve better read / write performance, the n-type GAA transistor has a larger channel width than the p-type GAA transistor. That is, the first width W1 can be greater than the second width W2. In some cases, the ratio (W1 / W2) of the first width W1 to the second width W2 is between about 1 and about 5, including between about 1.1 and about 3.0.

[0039] like Figure 2 As shown in , the channel of the first transfer gate transistor PG1 is controlled by the gate structure 20, the channels of the first pull-down transistor PD1 and the first pull-up transistor PU1 are controlled by the gate structure 24, the channels of the second pull-down transistor PD2 and the second pull-up transistor PU2 are controlled by the gate structure 22, and the channel of the second transfer gate transistor PG2 is controlled by the gate structure 26. When the gate structures 20 and 22 are segmented out of a single gate structure, they are longitudinally aligned along the X direction. When the gate structures 24 and 26 are segmented out of a single gate structure, they are longitudinally aligned along the X direction. The first fin-shaped vertical stack 40, the second fin-shaped vertical stack 42, the third fin-shaped vertical stack 44, and the fourth fin-shaped vertical stack 46 extend longitudinally along the Y direction perpendicular to the X direction. In circuit and physical design, Figure 2 The SRAM cell 10 shown in FIG. 1 may be used as a repeating cell in an SRAM array. To facilitate signal routing, adjacent SRAM cells 10 in an SRAM array may be mirror images of each other along their boundaries.

[0040] Figure 3-Figure 7 Various aspects of an exemplary embodiment are shown, wherein the sources of the first pull-down transistor PD1 and the second pull-down transistor PD2 are electrically connected to the back ground rail through a back contact. With respect to this exemplary embodiment, Figure 3 The front-side interconnect layer 140 of a quad-cell 100 including four SRAM cells 10 is shown. Figure 3 For illustration purposes, Figure 3 It also includes a first mirror axis MA1 extending along the Y direction, and a second mirror axis MA2 extending along the X direction. It can be seen that the SRAM cell separated from the SRAM cell 10 by the first mirror axis MA1 is a mirror image of the SRAM cell 10. Similarly, the SRAM cell separated from the SRAM cell by the second mirror axis MA2 is a mirror image of the SRAM cell 10. The mirror image configuration allows the merging of pull-up transistors, pull-down transistors, and transfer gate transistors for efficient wiring and electrical connection. Figure 3 The front interconnect layer 140 in the SRAM cell 10 includes docking contacts, such as a first front docking contact 102F, a second front docking contact 104F, and a third front docking contact 106F. The first front docking contact 102F connects the gate structure 24 of the first pull-up transistor PU1 to the source of the second pull-up transistor PU2. In the SRAM cell above the SRAM cell 10, the front docking contact 104F also connects the gate structure of the first pull-up transistor PU1 to the source of the second pull-up transistor PU2. The third front docking contact 106F connects the gate structure 22 of the second pull-up transistor PU2 to the source of the first pull-up transistor PU1. Figure 3 Also shown are a first common contact 130 connecting the drains of the second pull-up transistor PU2 and the second pull-down transistor PD2 together, a second common contact 132 connecting the sources of two adjacent pull-down transistors together, a third common contact 134 connecting the drains of the pull-up transistor and the pull-down transistor together, and a fourth common contact 136 connecting the sources of the pull-up transistor and the pull-down transistor together.

[0041] Figure 4 Shown along Figure 3 A partial cross-sectional view of the section A-A' in FIG. Figure 4As shown in the figure, section AA' cuts through the gate structure 24, the gate structure 22, the gate structure that is a mirror image of the gate structure 22 (relative to the second mirror axis MA2), and the gate structure that is a mirror image of the gate structure 24 (relative to the second mirror axis MA2), the first common contact 130, the second common contact 132, and the third common contact 134, the first front-side docking contact 102F, the second front-side docking contact 104F, the source 120 of the second pull-up transistor PU2, the drain 122 of the second pull-up transistor PU2, and the source 124 of the pull-up transistor in the SRAM cell above the SRAM cell 10. Figure 4 It is also shown that a front-side interconnect layer 140 is disposed above the transistor and a back-side interconnect layer 170 is disposed below the transistor.

[0042] Figure 5 A backside interconnect layer 170 beneath the quad cell 100 is shown. Figure 5 A first back source contact 172B and a second back source contact 174B are shown. The first back source contact 172B and the second back source contact 174B connect the sources of the pull-down transistors (including the second pull-down transistor PD2) to the back ground rail 180B. Figure 5 As shown in FIG. 1 , the first back source contact 172B and the second back source contact 174B land directly on the back ground rail 180B. It is worth noting that the sources of the first pull-up transistor PU1, the second pull-up transistor PU2, the first pass-gate transistor PG1, and the second pass-gate transistor PG2 are not connected to any conductive feature in the back interconnect layer 170 through any counterpart of the first back source contact 172B or the second back source contact 174B. Figure 6 Shown along Figure 5 A partial cross-sectional view of the quad-cell 100 at section BB' in FIG. The mirror image placement of the SRAM cells in the quad-cell 100 allows the source 137 of the second pull-down transistor PD2 to be placed next to the source 138 of the pull-down transistor in the SRAM cell above the SRAM cell 10. Figure 6In some embodiments represented in , sources 137 and 138 are connected to the Vss via not only through the second common contact 132, but also through the first back source contact 172B and the second back source contact 174B. The additional electrical grounding provided by the first back source contact 172B and the second back source contact 174B enables a higher saturation current to be obtained for the second pull-down transistor PD2. Since the source of the transfer gate transistor is not connected to the additional back contact, the saturation current of the transfer gate transistor remains low. The larger saturation current of the pull-down transistor helps to keep the beta (β) ratio of the SRAM cell 10 greater than 1, which enables the SRAM cell 10 to have good read stability. The lower saturation current of the transfer gate transistor helps to keep the alpha (α) ratio of the SRAM cell relatively high, which enables the SRAM cell 10 to have good writability. Figure 6 The partial cross-sectional view in FIG. 1 also shows a first gate cut feature 188, a second gate cut feature 190, and a third gate cut feature 192. Figure 5 and Figure 6 , the first gate cut component 188 isolates the gate structures 20 and 22. The second gate cut component 190 isolates the gate structure 22 and the gate structure in the SRAM cell mirror image across the first mirror axis MA1. The third gate cut component 192 is a mirror image of the first gate cut component 188 and serves a similar function. The first gate cut component 188, the second gate cut component 190, and the third gate cut component 192 may include silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbon nitride, silicon oxycarbon, silicon carbon nitride, or a combination thereof. The first back source contact 172B and the second back source contact 174B may include tungsten (W).

[0043] Figure 7 Shown along Figure 5 A partial cross-sectional view of the four-unit 100 at the cross section CC' in FIG. Figure 5 As shown in FIG. 1 , the cross section CC′ cuts through the SRAM cell 10 and the SRAM cell mirror image separated by the second mirror axis MA2. Figure 7 , the cross section CC′ cuts through the gate structures 26 and 22 in the SRAM cell 10 and the corresponding gate structures in the mirror image of the SRAM cell separated by the second mirror axis MA2. Figure 7 As shown, a first back source contact 172B extends from a top surface of the back ground rail 180B to electrically connect to the source 137 of the second pull-down transistor PD2. The source 137 of the second pull-down transistor PD2 is also electrically connected to the second common contact 132. As previously described, this arrangement provides an additional current path between the source of the second pull-down transistor PD2 and the ground rail.

[0044] Figure 8-Figure 10 Various aspects of exemplary embodiments are shown in which two adjacent back contact vias can be merged to form a back trench contact, thereby reducing contact resistance. Figure 5 Same, Figure 8 Also shown is the backside interconnect layer 170 beneath the quad cell 100. Figure 5 different, Figure 8 A back side trench contact 175 is shown. The back side trench contact 175 is similar in structure to the partially merged first back side source contact 172B and the second back side source contact 174B. Figure 8 As shown in FIG. 1 , a portion of the back side trench contact 175 spans across the sources 137 and 138 of two adjacent pull-down transistors of two adjacent SRAM cells. Fig. 9 Shown along Figure 8 A partial cross-sectional view of the four-unit 100 at the section BB' in FIG. Fig. 9 In some embodiments represented in , the back side trench contact 175 not only completely spans under the sources 137 and 138 of two adjacent pull-down transistors, but also extends through a portion of the second gate cut feature 190. Fig. 9 As shown in , the back slot contact 175 has an enlarged interface with the underlying back ground rail 180B. Since the cross-sectional area of ​​the conductive path is inversely proportional to the resistance, the enlarged interface provided by the back slot contact 175 can effectively reduce the contact resistance with the back ground rail 180B. Fig.10 In some embodiments represented in , since the etching process used to form the back trench contact opening can etch the second gate cut feature 190 at a greater rate, a wraparound back trench contact 1750 can be formed. The wraparound back trench contact 1750 includes an extension 175E extending between the source 137 and the source 138. Fig. 9 Compared with the back side trench contact 175 in FIG. 1 , the wrap-around back side trench contact 1750 may have a larger contact area with the sources 137 and 138. The back side trench contact 175 and the wrap-around back side trench contact 1750 may include tungsten (W).

[0045] Figure 11-Figure 14 Various aspects of exemplary embodiments are shown in which back-side docking contacts are substituted for those such as Figure 3 and Figure 4 The first front-facing docking contact 102F, the second front-facing docking contact 104F, and the third front-facing docking contact 106F shown in FIG. Functionally, the above combination Figure 3 and Figure 4 The front-facing contacts described adequately implement the intended electrical connections to allow the quad unit 100 to function properly. Figure 4As shown in FIG. 1 , the first front-side docking contact 102F, the second front-side docking contact 104F, and the third front-side docking contact 106F may inevitably occupy valuable wiring space in the first metal layer (M0) above the front-end process (FEOL) structure. In some embodiments, as Fig.11 As shown in FIG. 1 , the front side docking contacts are removed from the front side interconnect layer 140. To replace the front side docking contacts, Fig.12 1 , a back-side interconnect layer 170 is formed with back-side butt contacts, such as a first back-side butt contact 202, a second back-side butt contact 204, and a third back-side butt contact 206. In some embodiments, the vertical projection area of ​​the back-side butt contact may substantially overlap the vertical projection area of ​​the front-side butt contact it replaces. For example, the vertical projection area of ​​the second front-side butt contact 104F may substantially overlap the vertical projection area of ​​the second back-side butt contact 204. In some embodiments, the first back-side butt contact 202, the second back-side butt contact 204, and the third back-side butt contact 206 may include tungsten (W).

[0046] Fig.12 The partial cross-sectional views along section DD′ and section EE′ in FIG. 1 show how the first back side butt contact 202 , the second back side butt contact 204 , and the third back side butt contact 206 are positioned to connect to different components. Fig.13 is a partial cross-sectional view along section D-D', Fig.14 It is a partial cross-sectional view along the section E-E'. First refer to Fig.13 , section DD' cuts through the third common contact 134, the fourth common contact 136, the first back-side docking contact 202, and the second back-side docking contact 204. Fig.13 As shown in FIG. 1 , each of the first back side docking contact 202 and the second back side docking contact 204 is coupled to the source of the pull-up transistor (eg, source 124 ). Referring now to FIG. Fig.14 , section EE' cuts through the source 120 of the second pull-up transistor PU2, the drain 122 of the second pull-up transistor PU2, the source 124 of the pull-up transistor in the SRAM cell adjacent to the SRAM cell 10, the gate structures 22 and 24, the gate structures 22' and 24' in the SRAM cell adjacent to the SRAM cell 10, the second back side docking contact 204, and the third back side docking contact 206. Fig.14 As shown in FIG. 1 , the third back side contact 206 is electrically connected to the gate structure 24 and the source 120, while the second back side contact 204 is electrically connected to the gate structure 24′ and the source 124. It can be seen that along the Y direction, each of the second back side contact 204 and the third back side contact 206 has a contact with the gate structure ( Fig.14 24 or 24') and the adjacent source ( Fig.14 In some embodiments, the second back side contact 204 interfaces with the source 124 through the first silicide layer 220, and the third back side contact 206 interfaces with the source 120 through the second silicide layer 222. In some embodiments, the first silicide layer 220 and the second silicide layer 222 may include metal silicides, such as titanium silicide (TiSi), tungsten silicide (WSi), nickel silicide (NiSi), or cobalt silicide (CoSi).

[0047] exist Fig.15 In some embodiments represented by Fig. 9 The back slot contact 175 (or Fig.10 The wraparound back slot contact 1750 shown in FIG. 1 may be used with Figure 12-14 The back-side docking contacts shown in FIG. 1 are implemented together in a quad unit 100 . Fig.15 is a partial top view of the backside interconnect layer 170 of the quad unit 100 . Fig.15 The back side interconnect layer 170 in FIG. 1 includes a back side trench contact 175 , a first back side docking contact 202 , a second back side docking contact 204 , and a third back side docking contact 206 .

[0048] exist Fig.16 In some embodiments represented in , in addition to the first back source contact 172B and the second back source contact 174B, the quad cell 100 also includes a first back drain contact 310 and a second back drain contact 320. With respect to the SRAM cell 10, the first back drain contact 310 is electrically connected to the bottom surface of the drain of the first pull-up transistor PU1, and the second back drain contact 320 is electrically connected to the bottom surface of the drain of the second pull-up transistor PU2. The first back drain contact 310 and the second back drain contact 320 are both connected to the back power rail 182B instead of the back ground rail 180B. When the back ground rail 180B is connected to the ground potential Vss, the back power rail 182B is connected to the positive power supply voltage Vdd. It can be seen that a back trench contact (or a back wrap-around trench contact) or a back butt contact can also be implemented together with the back drain contact.

[0049] Fig.174 is a block diagram of a first SRAM array 408 in a first memory device 400. The first SRAM array 408 may include a plurality of SRAM cells 10 described above, each SRAM cell 10 being arranged as a mirror image of an adjacent SRAM cell 10. In the first SRAM array 408, the gate structure extends longitudinally along the X direction, and the fin-shaped vertical stack (or active area) extends longitudinally along the Y direction. In some embodiments, the first SRAM array 408 is disposed between two input / output (I / O) cells 420 along the Y direction. Two word line drivers 440 are disposed along the edge of the first SRAM array 408. The first memory device 400 also includes two controllers 430. Each of the two controllers 430 engages one I / O cell 420 and one word line driver 440. Due to the implementation of back source contacts (e.g., first back source contact 172B and second back source contact 174B), back trench contacts (e.g., back trench contact 175 or wrap-around back trench contact 1750), back docking contacts (e.g., first back docking contact 202, second back docking contact 204, or third back docking contact 206), or a combination thereof, the first SRAM array 408 does not include any well tap unit that provides a ground potential (Vss) or a positive power supply potential (Vdd) to the well region.

[0050] exist Fig.18 In some embodiments represented in , the first SRAM array 408 includes back source contacts (e.g., first back source contact 172B and second back source contact 174B) to connect the source of the pull-down transistor to the back ground rail (e.g., back ground rail 180B). Fig.19 In some embodiments represented in , the first SRAM array 408 includes a back trench contact (e.g., back trench contact 175 or wrap-around back trench contact 1750) to connect the source of the pull-down transistor to the back ground rail (e.g., back ground rail 180B). Fig. 20 In some embodiments represented in , the first SRAM array 408 includes back source contacts (e.g., first back source contacts 172B and second back source contacts 174B) and back docking contacts (e.g., first back docking contacts 202, second back docking contacts 204, or third back docking contacts 206). Fig.21 In some embodiments represented in , the first SRAM array 408 includes back-side docking contacts (e.g., the first back-side docking contact 202, the second back-side docking contact 204, or the third back-side docking contact 206) and back-side trench contacts (e.g., the back-side trench contact 175 or the wrap-around back-side trench contact 1750).

[0051] Fig. 22 is a block diagram of a second SRAM array 508 in a second memory device 500. The second SRAM array 508 may include a plurality of SRAM cells 10 described above, each SRAM cell 10 being arranged as a mirror image of an adjacent SRAM cell 10. In the second SRAM array 508, the gate structure extends longitudinally along the X direction, and the fin-shaped vertical stack (or active area) extends longitudinally along the Y direction. In some embodiments, the second SRAM array 508 is disposed between two input / output (I / O) cells 520 along the Y direction. Two word line drivers 540 are disposed along the edge of the second SRAM array 508. The second memory device 500 also includes two controllers 530. Each of the two controllers 530 engages one I / O cell 520 and one word line driver 540. Unlike the first memory device 400, the second memory device 500 also includes two power tap edge cells 512 disposed along the interface with the I / O cell 520. In some embodiments, each of the two power tap edge cells 512 is separated from the second SRAM array 508 by a non-tapped buffer edge 510. In some embodiments, each power tap edge cell 512 includes an array of feedthrough vias (FTVs) 514. Connected to the front contact 516, each FTV 514 provides electrical routing between the front interconnect layer 140 and the back interconnect layer 170. The FTV 514 provides additional front-to-back electrical routing to replace or supplement the back source contact, back drain contact, back trench contact, or back docking contact. In some embodiments, the FTV 514 includes tungsten (W) and the front contact 516 includes aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), or tungsten (W).

[0052] exist Fig.23 In some embodiments represented in , the second SRAM array 508 does not have any back source contacts, back drain contacts, back trench contacts, or back butt contacts. FTV 514 can be used to connect the front positive power potential or the front ground potential to the back positive power rail or the back ground rail. Fig.24 In some embodiments represented in , the second SRAM array 508 includes back source contacts (e.g., first back source contact 172B and second back source contact 174B) to connect the source of the pull-down transistor to the back ground rail (e.g., back ground rail 180B). FTV 514 can be used to connect the front wiring to the back positive power rail or the back ground rail. Fig.25 In some embodiments represented in , the second SRAM array 508 includes a back side trench contact (eg, the back side trench contact 175 or the wrap-around back side trench contact 1750). Fig.26In some embodiments represented in , the second SRAM array 508 includes a back source contact (e.g., a first back source contact 172B and a second back source contact 174B) and a back docking contact (e.g., a first back docking contact 202, a second back docking contact 204, or a third back docking contact 206). Fig. 27 In some embodiments represented in , the second SRAM array 508 includes back source contacts (e.g., first back source contact 172B and second back source contact 174B) for connecting the source of the pull-down transistor to the back ground rail (e.g., back ground rail 180B), and back trench contacts (e.g., back trench contact 175 or wrap-around back trench contact 1750) for connecting the source of the pull-down transistor to the back ground rail (e.g., back ground rail 180B).

[0053] In one exemplary aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first memory cell, which includes a first pull-down transistor and a first pull-up transistor, sharing a first gate structure extending along a first direction; a second pull-down transistor and a second pull-up transistor, sharing a second gate structure extending along the first direction; a first transmission gate transistor, having a third gate structure spaced apart from the second gate structure along the first direction but aligned with the second gate structure; and a second transmission gate transistor, having a fourth gate structure spaced apart from the first gate structure along the first direction but aligned with the first gate structure; a front interconnect structure, disposed above the first memory cell; and a back interconnect structure, disposed below the first memory cell. The source of the second pull-down transistor is electrically connected to the front interconnect structure through a first source / drain contact, and the source of the second pull-down transistor is electrically connected to the back interconnect structure through a first back contact via.

[0054] In some embodiments, the active area of ​​the first pull-down transistor and the active area of ​​the first transfer gate transistor are aligned along a second direction perpendicular to the first direction, and the active area of ​​the second pull-down transistor and the active area of ​​the second transfer gate transistor are aligned along the second direction. In some embodiments, each of the active areas of the first pull-down transistor, the first transfer gate transistor, the second pull-down transistor, and the second transfer gate transistor includes four nanostructures stacked one above the other. In some embodiments, the first pull-down transistor has a first channel width and the first pull-up transistor has a second channel width less than the first channel width. In some embodiments, the semiconductor structure further includes: a first back-side docking contact that physically contacts the first gate structure and the source of the second pull-up transistor. In some embodiments, the semiconductor structure further includes: a second back-side docking contact that physically contacts the second gate structure and the source of the first pull-up transistor. In some embodiments, the semiconductor structure further includes: a second memory cell including a third pull-down transistor and a third pull-up transistor, sharing a third gate structure extending along the first direction; a fourth pull-down transistor and a fourth pull-up transistor, sharing a fourth gate structure extending along the first direction; a third transmission gate transistor, having a fifth gate structure spaced apart from the fourth gate structure but aligned with the fourth gate structure along the first direction; and a fourth transmission gate transistor, having a sixth gate structure spaced apart from the third gate structure but aligned with the third gate structure along the first direction. The second memory cell is a mirror image of the first memory cell with respect to the second direction, such that the second gate structure is aligned with the third gate structure along the first direction, and the first gate structure is aligned with the fifth gate structure. The front interconnect structure is disposed above the second memory cell. The back interconnect structure is disposed below the second memory cell. The source of the third pull-down transistor is electrically connected to the back interconnect structure through a second back contact via. In some embodiments, the first back contact via and the second back contact via land directly on a back power rail in the back interconnect structure. In some embodiments, the first back contact via and the second back contact via merge before directly landing on the back power rail.

[0055] Another aspect of the present disclosure relates to a memory structure. The memory structure includes: a first memory cell, which includes a first active area, a second active area, a third active area, and a fourth active area, extending in parallel along a first direction; a first gate structure, extending longitudinally along a second direction perpendicular to the first direction, the first gate structure is joined with the first active area and the second active area to form a first pull-down transistor and a first pull-up transistor, respectively; a second gate structure, extending longitudinally along the second direction, the second gate structure is joined with the third active area and the fourth active area to form a second pull-up transistor and a second pull-down transistor, respectively; a front interconnect structure, arranged above the first memory cell; and a back interconnect structure, arranged below the first memory cell. The source of the second pull-down transistor is electrically connected to the front interconnect structure through a first source / drain contact. The source of the second pull-down transistor is electrically connected to the back interconnect structure through a first back contact via.

[0056] In some embodiments, the first memory cell further includes: a third gate structure extending longitudinally along the second direction and joined to the first active region to form a first transmission gate transistor; and a fourth gate structure extending longitudinally along the second direction and joined to the fourth active region to form a second transmission gate transistor. In some embodiments, the third gate structure is aligned with the second gate structure along the second direction and is spaced apart from the second gate structure; the fourth gate structure is aligned with the first gate structure along the second direction and is spaced apart from the first gate structure. In some cases, the first active region and the fourth active region include a first width along the second direction, the second active region and the third active region include a second width along the second direction, and the second width is less than the first width. In some embodiments, the memory structure further includes: a second memory cell including a fifth active region, a sixth active region, a seventh active region, and an eighth active region extending in parallel along the first direction; a third gate structure extending longitudinally along the second direction to join the fifth active region and the sixth active region to form a third pull-down transistor and a third pull-up transistor, respectively; and a fourth gate structure extending longitudinally along the second direction to join the seventh active region and the eighth active region to form a fourth pull-up transistor and a fourth pull-down transistor, respectively; a front interconnect structure disposed above the second memory cell; and a back interconnect structure disposed below the second memory cell. The source of the third pull-down transistor is electrically connected to the back interconnect structure through a second back contact via. In some cases, the fourth active region and the fifth active region are separated by an isolation component. In some cases, the first back contact via and the second back contact via are merged below the isolation component.

[0057] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes: a first pull-down transistor and a first pull-up transistor, sharing a first gate structure extending along a first direction; a second pull-down transistor and a second pull-up transistor, sharing a second gate structure extending along the direction; a first transmission gate transistor, having a third gate structure spaced apart from the second gate structure but aligned with the second gate structure along the direction; and a second transmission gate transistor, having a fourth gate structure spaced apart from the first gate structure but aligned with the first gate structure along the direction; a first back-butt contact, physically contacting a bottom surface of the first gate structure and a bottom surface of a source of the second pull-up transistor; and a second back-butt contact, physically contacting the second gate structure and the source of the first pull-up transistor.

[0058] In some embodiments, the first pull-down transistor includes a plurality of first nanostructures, the first gate structure surrounds each of the plurality of first nanostructures; the first transfer gate transistor includes a plurality of second nanostructures, the third gate structure surrounds each of the plurality of second nanostructures; the plurality of first nanostructures include a first width along the direction, the plurality of second nanostructures include a second width along the direction, and the first width is greater than the second width. In some embodiments, the plurality of first nanostructures include four (4) first nanostructures stacked one above another. In some cases, the semiconductor device further includes: a front interconnect structure disposed above the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, the second pull-up transistor, the first transfer gate transistor, and the second transfer gate transistor; and a back interconnect structure disposed below the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, the second pull-up transistor, the first transfer gate transistor, and the second transfer gate transistor. The source of the second pull-down transistor is electrically connected to the front interconnect structure through a front source / drain contact, and the source of the second pull-down transistor is electrically connected to the back interconnect structure through a back contact via.

[0059] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A first memory unit comprises: A first pull-down transistor and a first pull-up transistor share a first gate structure extending along a first direction; a second pull-down transistor and a second pull-up transistor, sharing a second gate structure extending along the first direction; a first pass-gate transistor having a third gate structure spaced apart from but aligned with the second gate structure along the first direction; and a second transfer-gate transistor having a fourth gate structure spaced apart from but aligned with the first gate structure along the first direction; a front-side interconnect structure disposed above the first memory cell; and a backside interconnect structure disposed below the first memory cell; wherein the source of the second pull-down transistor is electrically connected to the front-side interconnect structure via a first source / drain contact; Wherein, the source of the second pull-down transistor is electrically connected to the backside interconnect structure through a first backside contact via.

2. The semiconductor structure according to claim 1, in, An active area of ​​the first pull-down transistor and an active area of ​​the first pass-gate transistor are aligned along a second direction perpendicular to the first direction; Wherein, an active area of ​​the second pull-down transistor and an active area of ​​the second transfer gate transistor are aligned along the second direction.

3. The semiconductor structure according to claim 2, wherein: Each of the active regions of the first pull-down transistor, the first pass-gate transistor, the second pull-down transistor, and the second pass-gate transistor includes four nanostructures stacked one above another.

4. The semiconductor structure according to claim 1, in, The first pull-down transistor has a first channel width; The first pull-up transistor has a second channel width that is smaller than the first channel width.

5. The semiconductor structure according to claim 1, further comprising: A second memory unit comprises: a third pull-down transistor and a third pull-up transistor sharing a third gate structure extending along the first direction; a fourth pull-down transistor and a fourth pull-up transistor sharing a fourth gate structure extending along the first direction; a third transfer-gate transistor having a fifth gate structure spaced apart from but aligned with the fourth gate structure along the first direction; and a fourth pass-gate transistor having a sixth gate structure spaced apart from but aligned with the third gate structure along the first direction; wherein the second memory cell is a mirror image of the first memory cell with respect to a second direction, such that along the first direction the second gate structure is aligned with the third gate structure, and the first gate structure is aligned with the fifth gate structure; wherein the front-side interconnect structure is disposed above the second memory cell; wherein the backside interconnect structure is disposed below the second memory unit; Wherein, the source of the third pull-down transistor is electrically connected to the back-side interconnection structure through a second back-side contact via.

6. A memory structure comprising: A first memory unit comprises: The first active region, the second active region, the third active region, and the fourth active region extend in parallel along a first direction; a first gate structure extending longitudinally along a second direction perpendicular to the first direction, the first gate structure being coupled to the first active region and the second active region to form a first pull-down transistor and a first pull-up transistor, respectively; and a second gate structure extending longitudinally along the second direction, the second gate structure being coupled to the third active region and the fourth active region to form a second pull-up transistor and a second pull-down transistor, respectively; a front-side interconnect structure disposed above the first memory cell; and a backside interconnect structure disposed below the first memory cell; wherein the source of the second pull-down transistor is electrically connected to the front-side interconnect structure via a first source / drain contact; Wherein, the source of the second pull-down transistor is electrically connected to the backside interconnect structure through a first backside contact via.

7. The memory structure according to claim 6, wherein: The first memory unit further comprises: a third gate structure extending longitudinally along the second direction and joined to the first active region to form a first transfer gate transistor; and A fourth gate structure extends longitudinally along the second direction and is joined to the fourth active region to form a second transfer gate transistor.

8. The memory structure according to claim 6, further comprising: A second memory unit comprises: The fifth active region, the sixth active region, the seventh active region, and the eighth active region extend in parallel along the first direction; a third gate structure extending longitudinally along the second direction to join the fifth active region and the sixth active region to form a third pull-down transistor and a third pull-up transistor, respectively; and a fourth gate structure extending longitudinally along the second direction to join the seventh active region and the eighth active region to form a fourth pull-up transistor and a fourth pull-down transistor, respectively; The front side interconnect structure is disposed over the second memory cell; and The backside interconnect structure is disposed below the second memory cell; Wherein, the source of the third pull-down transistor is electrically connected to the back-side interconnection structure through a second back-side contact via.

9. A semiconductor device comprising: A first pull-down transistor and a first pull-up transistor share a first gate structure extending along a first direction; a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the direction; a first pass-gate transistor having a third gate structure spaced apart from but aligned with the second gate structure along the direction; a second transfer-gate transistor having a fourth gate structure spaced apart from but aligned with the first gate structure along the direction; a first backside docking contact physically contacting a bottom surface of the first gate structure and a bottom surface of the source of the second pull-up transistor; as well as A second back side butt contact physically contacts the second gate structure and the source of the first pull-up transistor.

10. The semiconductor device according to claim 9, further comprising: a front-side interconnect structure disposed over the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, the second pull-up transistor, the first transfer gate transistor, and the second transfer gate transistor; and a backside interconnect structure disposed below the first pull-down transistor, the first pull-up transistor, the second pull-down transistor, the second pull-up transistor, the first transfer gate transistor, and the second transfer gate transistor; wherein the source of the second pull-down transistor is electrically connected to the front-side interconnect structure via a front-side source / drain contact; Wherein, the source of the second pull-down transistor is electrically connected to the backside interconnect structure through a backside contact via.

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