Semiconductor device and dual dynamic random access memory cell

Abstract

A semiconductor device and a dual dynamic random access memory cell are provided. The semiconductor device includes: a substrate having a pair of second conductive lines thereon; and a first conductive line extending between the pair of second conductive lines and the substrate. A contact plug extends between the pair of second conductive lines and is electrically connected to the first conductive line. A gate electrode extends on the contact plug. A first semiconductor pattern and a second semiconductor pattern extend on a first conductive line and a second conductive line of the pair of second conductive lines, respectively. A gate insulating pattern extends between each of the first and second semiconductor patterns and the gate electrode. The first conductive line may be configured as a word line, and the pair of second conductive lines may be configured as a pair of bit lines. The gate electrode may be configured as a gate electrode of a first access transistor within the first DRAM cell and a gate electrode of a second access transistor within the second DRAM cell.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0096621 filed on Jul. 25, 2023, the contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to an integrated circuit device and a method for manufacturing the same, and in particular to a semiconductor memory device including a vertical channel transistor and a method for manufacturing the same. Background Art

[0003] The semiconductor device may include an integrated circuit composed of a metal oxide semiconductor field effect transistor (MOS-FET). In order to meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOS-FETs are being actively scaled down. The scaling down of MOS-FETs may result in degradation of the operating properties of the semiconductor device. Various studies have been conducted to overcome the technical limitations associated with the scaling down of semiconductor devices and to provide high-performance semiconductor devices. Summary of the invention

[0004] Embodiments of the inventive concept provide a highly integrated semiconductor device configured to easily control operations of a vertical channel transistor and a method of manufacturing the same.

[0005] Embodiments of the inventive concept provide a semiconductor device including a vertical channel transistor having improved electrical characteristics and a method of manufacturing the same.

[0006] According to an embodiment of the inventive concept, a semiconductor device may include: a first conductive line extending in a first direction parallel to a top surface of the substrate on a substrate; and a second conductive line extending on the first conductive line, spaced apart from each other in the first direction, and extending in a second direction parallel to the top surface of the substrate but not parallel to the first direction. A contact plug is provided, the contact plug is disposed between the second conductive lines and connected to the first conductive line. A gate electrode extends on the contact plug, and semiconductor patterns are respectively disposed on the second conductive lines. A gate insulating pattern extends between each of the semiconductor patterns and the gate electrode. Conductive patterns are respectively disposed on the semiconductor patterns.

[0007] According to another embodiment of the inventive concept, a semiconductor device may include: a first conductive line disposed on a substrate and extending in a first direction parallel to a top surface of the substrate; a lower insulating layer on the first conductive line; a second conductive line disposed on the first conductive line and in the lower insulating layer and spaced apart from each other in the first direction; a contact plug disposed to penetrate the lower insulating layer between the second conductive lines and connected to the first conductive line; a gate electrode on the contact plug; semiconductor patterns respectively disposed on the second conductive lines and spaced apart from each other in the first direction; and a gate insulating pattern extending between each of the semiconductor patterns and the gate electrode. A bottom surface of the gate insulating pattern may contact a top surface of the lower insulating layer.

[0008] According to another embodiment of the inventive concept, a dual DRAM cell (i.e., a dynamic random access memory cell) is provided, the dual DRAM cell comprising: a first access transistor of a first DRAM cell having a cylindrical gate electrode extending vertically relative to the surface of an underlying substrate; and a second access transistor of a second DRAM cell sharing the cylindrical gate electrode. The first access transistor may include a first semiconductor active region that is C-shaped when viewed from a perspective of a planar layout, and the second access transistor may also include a second semiconductor active region that is C-shaped when viewed from a perspective of a planar layout. When viewed from a perspective of a planar layout, the first semiconductor active region and the second semiconductor active region may also be constructed as mirror images of each other. A first bit line electrically connected to a source / drain region within the first semiconductor active region is provided, and a second bit line electrically connected to a source / drain region within the second semiconductor active region is provided. The cylindrical gate electrode may extend between the first bit line and the second bit line. A word line extending between the first bit line and the second bit line and the substrate surface and electrically connected to the cylindrical gate electrode is provided. A first cylindrical capacitor electrode electrically connected to the source / drain region within the first semiconductor active region is provided. Likewise, a second cylindrical capacitor electrode electrically connected to the source / drain region within the second semiconductor active region is provided.In some embodiments, the longitudinal axis of the first cylindrical capacitor electrode, the longitudinal axis of the second cylindrical capacitor electrode, and the longitudinal axis of the cylindrical gate electrode extend parallel to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a plan layout diagram illustrating a semiconductor device according to an embodiment of the inventive concept.

[0010] Figure 2 It is schematically shown Figure 1 A perspective view of a semiconductor device.

[0011] Figure 3 is a plan layout diagram illustrating a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 4 It is along Figure 3 A cross-sectional view taken along line II'.

[0013] Figure 5 It is shown Figure 4 An enlarged view of portion “P1”.

[0014] Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 and Fig.16 is a plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0015] Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 and Fig.17 are respectively along Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 and Fig.16 A cross-sectional view taken along line II'.

[0016] Fig.18 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0017] Fig.19 It is schematically shown Fig.18 A perspective view of a semiconductor device.

[0018] Fig. 20 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0019] Fig.21 It is along Fig. 20 A cross-sectional view taken along line II'.

[0020] Fig. 22 It is shown Fig.21 An enlarged view of portion “P2”.

[0021] Fig.23 , Fig.25 and Fig. 27 is a plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0022] Fig.24 , Fig.26 and Fig.28 are respectively along Fig.23 , Fig.25 and Fig. 27A cross-sectional view taken along line II'.

[0023] Fig.29 is a perspective view schematically illustrating a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0025] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the inventive concept (eg, from a perspective of a planar layout), Figure 2 It is schematically shown Figure 1 A perspective view of a semiconductor device. Figure 1 and Figure 2 , the first conductive line (e.g., word line) 120 may extend in a first direction D1, and the second conductive line (e.g., bit line) 140 may be disposed on the first conductive line 120. The second conductive lines 140 may be spaced apart from each other in the first direction D1 and may extend in a second direction D2 that is not parallel (e.g., orthogonal) to the first direction D1. The second conductive lines 140 may be disposed to cross the first conductive lines 120. A vertical contact plug 150 may be disposed between the second conductive lines 140 and may extend in a third direction D3 that is perpendicular to the first direction D1 and the second direction D2. The contact plug 150 may be electrically connected to the first conductive line 120.

[0026] The gate electrode GE may be disposed on the contact plug 150 and electrically connected to the contact plug 150. The semiconductor patterns VSP1 and VSP2 may be disposed on the second conductive line 140, respectively, and may be spaced apart from each other in the first direction D1. The semiconductor patterns VSP1 and VSP2 may be electrically connected to the second conductive line 140, respectively. The gate insulating pattern GI may extend between each of the semiconductor patterns VSP1 and VSP2 and the gate electrode GE.

[0027] When viewed in a plan view, the gate insulation pattern GI may be a curved or bent pattern extending in the side surface GE_S of the gate electrode GE. When viewed in a plan view, the gate insulation pattern GI may have a ring shape surrounding the side surface GE_S of the gate electrode GE. The inner side surface GI_IS of the gate insulation pattern GI may be in contact with the side surface GE_S of the gate electrode GE. When viewed in a plan view, the inner side surface GI_IS of the gate insulation pattern GI may be a curved or bent surface extending in the side surface GE_S of the gate electrode GE.

[0028] When viewed in a plan view, each of the semiconductor patterns VSP1 and VSP2 may have a curved or bent shape extending in the side surface GE_S of the gate electrode GE. An inner side surface VSP_IS of each of the semiconductor patterns VSP1 and VSP2 may face the side surface GE_S of the gate electrode GE and may be in contact with the gate insulating pattern GI. When viewed in a plan view, an inner side surface VSP_IS of each of the semiconductor patterns VSP1 and VSP2 may be a curved or bent surface extending in the side surface GE_S of the gate electrode GE.

[0029] The separation pattern SPC may extend between the semiconductor patterns VSP1 and VSP2. Between the semiconductor patterns VSP1 and VSP2, the separation patterns SPC may be spaced apart from each other in the second direction D2. The gate electrode GE and the gate insulating pattern GI may extend between the separation patterns SPC. When viewed in a plan view, the semiconductor patterns VSP1 and VSP2 and the separation pattern SPC may surround the gate electrode GE and the gate insulating pattern GI. The semiconductor patterns VSP1 and VSP2 may be electrically separated from each other by the separation pattern SPC.

[0030] Conductive patterns 165 may be respectively disposed on the semiconductor patterns VSP1 and VSP2 and may be spaced apart from each other in the first direction D1. Conductive patterns 165 may be respectively electrically connected to the semiconductor patterns VSP1 and VSP2. Capacitors CAP (e.g., capacitor electrodes of capacitors CAP) may be respectively disposed on the conductive patterns 165 and electrically connected to the conductive patterns 165.

[0031] In an embodiment, the gate electrode GE may be electrically connected to the first conductive line 120 through the contact plug 150, and the first conductive line 120 may be used as a word line. The gate electrode GE, the gate insulation pattern GI, and the semiconductor patterns VSP1 and VSP2 may constitute a pair of vertical channel transistors. The paired vertical channel transistors may share the gate electrode GE and the gate insulation pattern GI, and may include semiconductor patterns VSP1 and VSP2, respectively. Each of the semiconductor patterns VSP1 and VSP2 may be used as a vertical channel of each of the paired vertical channel transistors. The second conductive line 140 may be electrically connected to the semiconductor patterns VSP1 and VSP2, respectively, and may be used as a bit line. The capacitor CAP may be electrically connected to the semiconductor patterns VSP1 and VSP2, respectively, through the conductive pattern 165. Each of the second conductive lines 140 and each of the capacitors CAP may be electrically connected to the source / drain terminals of each of the paired vertical channel transistors. Each of the paired vertical channel transistors and the capacitor CAP connected thereto may constitute a dynamic random access memory (DRAM) cell.

[0032] Figure 3is a plan layout diagram showing a semiconductor device according to an embodiment of the inventive concept; Figure 4 It is along Figure 3 A cross-sectional view taken along line II' of FIG. Figure 5 It is shown Figure 4 An enlarged view of part "P1". Figure 3 and Figure 4 , a device isolation pattern 102 may be provided in the substrate 100 to define an active area ACT in the substrate 100. The substrate 100 may be a semiconductor substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (Si-Ge) substrate, or a semiconductor on insulator (SOI) substrate). The device isolation pattern 102 may be formed of or include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0033] The peripheral transistors PTR may be disposed on the active region ACT of the substrate 100. Each of the peripheral transistors PTR may include a peripheral gate electrode PGE on a corresponding one of the active regions ACT, a peripheral gate insulating pattern PGI between the corresponding active region ACT and the peripheral gate electrode PGE, a peripheral capping pattern PCAP on the peripheral gate electrode PGE, a peripheral gate spacer PGSP on the side surface of the peripheral gate electrode PGE, and a peripheral source / drain region PSD formed in a corresponding portion of the active region ACT at both sides of the peripheral gate electrode PGE. The peripheral gate electrode PGE may be formed of or include at least one of a doped semiconductor material, a conductive metal nitride material, and a metal material. The peripheral gate insulating pattern PGI may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material. The high-k dielectric material may include a material having a higher dielectric constant than that of silicon oxide (e.g., hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO)). The peripheral capping pattern PCAP and the peripheral gate spacer PGSP may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The peripheral transistor PTR may constitute a peripheral circuit for operating a DRAM cell according to an embodiment of the inventive concept.

[0034] The peripheral contact 103 and the peripheral interconnection line 104 may be disposed on the substrate 100. The peripheral contact 103 may be electrically connected to the peripheral source / drain region PSD of the peripheral transistor PTR, and the peripheral interconnection line 104 may be electrically connected to the peripheral contact 103. The peripheral contact 103 and the peripheral interconnection line 104 may be formed of or include at least one of a conductive material (e.g., a metal material). A peripheral insulating layer 110 may be disposed on the substrate 100 to cover the peripheral transistor PTR, the peripheral contact 103, and the peripheral interconnection line 104. The peripheral insulating layer 110 may be formed of or include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0035] The first conductive lines 120 may be disposed on the peripheral insulating layer 110 and may extend in a first direction D1 parallel to the top surface 100U of the substrate 100. The first conductive lines 120 may be spaced apart from each other in a second direction D2 parallel to the top surface 100U of the substrate 100 and not parallel to the first direction D1. Each of the first conductive lines 120 may be electrically connected to a corresponding one of the peripheral interconnection lines 104 through a lower contact 115. The first conductive lines 120 and the lower contact 115 may be formed of or include at least one of a conductive material (e.g., a metal material).

[0036] The first lower insulating layer 130 may be disposed on the peripheral insulating layer 110 to cover the first conductive line 120. The first lower insulating layer 130 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second lower insulating layer 132 may be disposed on the first lower insulating layer 130. The second lower insulating layer 132 may be formed of, for example, a material different from that of the first lower insulating layer 130 or include a material different from that of the first lower insulating layer 130. As an example, the second lower insulating layer 132 may include silicon nitride. The first lower insulating layer 130 and the second lower insulating layer 132 may be referred to as lower insulating layers 130 / 132.

[0037] The second conductive line 140 may be disposed in the lower insulating layer 130 / 132 and on the first conductive line 120. The second conductive line 140 may be vertically spaced apart from the first conductive line 120 in a third direction D3, which is perpendicular to the top surface 100U of the substrate 100. The second conductive lines 140 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The second conductive lines 140 may be disposed to cross the first conductive lines 120. Each of the second conductive lines 140 may be disposed to penetrate an upper portion of the lower insulating layer 130 / 132. As an example, each of the second conductive lines 140 may be disposed to penetrate the second lower insulating layer 132 and may extend into an upper portion of the first lower insulating layer 130. The top surface 140U of the second conductive line 140 may be coplanar with the top surface 132U of the lower insulating layer 130 / 132. The top surface 140U of the second conductive line 140 and the top surface 132U of the lower insulating layer 130 / 132 may be located at the same height from the substrate 100. In this specification, the term "height" will be used to represent a vertical length measured from the top surface 100U of the substrate 100 in the third direction D3. The top surface 132U of the lower insulating layer 130 / 132 may correspond to the top surface 132U of the second lower insulating layer 132. The second conductive line 140 may be formed of or include at least one of a conductive material (e.g., a metal material).

[0038] The contact plugs 150 may be disposed in the lower insulating layer 130 / 132 between the second conductive lines 140. In the lower insulating layer 130 / 132, the contact plugs 150 may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the contact plugs 150 may be positioned between a pair of second conductive lines 140 selected from the second conductive lines 140 closest to each other in the first direction D1. Between the paired second conductive lines 140, each of the contact plugs 150 may be disposed to penetrate the lower insulating layer 130 / 132 and may be electrically connected to a corresponding one of the first conductive lines 120. The contact plugs 150 spaced apart from each other in the first direction D1 among the contact plugs 150 may be electrically connected in common to one of the first conductive lines 120 and may be disposed between the second conductive lines 140, respectively. The contact plugs 150 spaced apart from each other in the second direction D2 among the contact plugs 150 may be electrically connected to different first conductive lines 120 among the first conductive lines 120, respectively, and may be disposed between a pair of second conductive lines 140 selected from among the second conductive lines 140. A top surface 150U of the contact plug 150 may be coplanar with a top surface 132U of the lower insulating layer 130 / 132. The top surface 150U of the contact plug 150 and the top surface 132U of the lower insulating layer 130 / 132 may be located at the same height from the substrate 100. The top surface 150U of the contact plug 150, the top surface 140U of the second conductive line 140, and the top surface 132U of the lower insulating layer 130 / 132 may be coplanar with each other and may be located at the same height from the substrate 100. The contact plug 150 may be formed of or include at least one of conductive materials (e.g., metal materials).

[0039] The gate electrodes GE may be respectively disposed on the contact plugs 150 and electrically connected to the contact plugs 150. Bottom surfaces of the gate electrodes GE may be in contact with top surfaces 150U of the contact plugs 150, respectively. The gate electrodes GE may be spaced apart from each other in the first direction D1 and the second direction D2. The gate electrodes GE spaced apart from each other in the first direction D1 among the gate electrodes GE may be electrically connected in common to one of the first conductive lines 120 through the corresponding contact plugs 150. The gate electrodes GE spaced apart from each other in the second direction D2 among the gate electrodes GE may be electrically connected to different first conductive lines 120 among the first conductive lines 120, respectively, through the corresponding contact plugs 150.

[0040] The gate electrode GE may include at least one of doped polysilicon, a metal material, a conductive metal nitride material, a conductive metal silicide material, a conductive metal oxide material, and a combination thereof. For example, the gate electrode GE may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and combinations thereof or include at least one of them. In an embodiment, the gate electrode GE may include a two-dimensional semiconductor material, and here, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0041] The semiconductor patterns VSP may be disposed at both sides of each of the gate electrodes GE. The semiconductor patterns VSP may be spaced apart from each other in the first direction D1, wherein each of the gate electrodes GE extends between the semiconductor patterns VSP. The semiconductor patterns VSP may be respectively disposed on a pair of second conductive lines 140 selected from the second conductive lines 140 that are closest to each other in the first direction D1, and may be respectively electrically connected to the pair of second conductive lines 140. The bottom surfaces of the semiconductor patterns VSP may be in contact with the top surfaces 140U of the pair of second conductive lines 140, respectively.

[0042] The semiconductor pattern VSP may include at least one of the oxide semiconductor materials. For example, the semiconductor pattern VSP may be made of In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zny Sn z O, Yb x Ga y Zn z O、In x Ga y O and at least one of their combinations form or include In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O and combinations thereof. In an embodiment, the semiconductor pattern VSP may be formed of or include indium gallium zinc oxide (IGZO). The semiconductor pattern VSP may have a single-layer structure or a multi-layer structure including an oxide semiconductor material, and may be formed of or include at least one of an amorphous oxide semiconductor material, a crystalline oxide semiconductor material, and a polycrystalline oxide semiconductor material. The semiconductor pattern VSP may have an energy band gap larger than that of silicon. For example, the semiconductor pattern VSP may have an energy band gap of about 1.5 eV to about 5.6 eV, or may have an energy band gap of about 2.0 eV to about 4.0 eV.

[0043] The gate insulating pattern GI may extend between each gate electrode GE and each semiconductor pattern VSP. The bottom surface of the gate insulating pattern GI may be in contact with the top surface 132U of the lower insulating layer 130 / 132. The semiconductor pattern VSP may be spaced apart from each of the gate electrodes GE, and the gate insulating pattern GI extends between the semiconductor pattern VSP and each of the gate electrodes GE. The gate insulating pattern GI may be formed of or include at least one of silicon oxide, silicon oxynitride, a high-k dielectric material having a higher dielectric constant than silicon oxide, and a combination thereof. The high-k dielectric material may include a metal oxide material or a metal oxynitride material. For example, the high-k dielectric material may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO 2 、ZrO 2 、Al 2 O 3 or a combination thereof.

[0044] The gate insulating pattern GI may be a curved pattern or a bent pattern extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. For example, the gate insulating pattern GI may be a ring pattern disposed to surround the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. The inner side surface GI_IS of the gate insulating pattern GI may be in contact with the side surface GE_S of each of the gate electrodes GE. The inner side surface GI_IS of the gate insulating pattern GI may be a curved surface or a bent surface extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0045] Each of the semiconductor patterns VSP may be a curved pattern or a bent pattern extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. An inner side surface VSP_IS of each of the semiconductor patterns VSP may face the side surface GE_S of each of the gate electrodes GE and may be in contact with the gate insulating pattern GI. An inner side surface VSP_IS of each of the semiconductor patterns VSP may be a curved surface or a bent surface extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0046] The separation pattern SPC may extend between the semiconductor patterns VSP. The separation patterns SPC between the semiconductor patterns VSP may be spaced apart from each other in the second direction D2. Each of the gate electrode GE and the gate insulation pattern GI may extend between the separation patterns SPC. The semiconductor pattern VSP and the separation pattern SPC may surround each of the gate electrode GE and the gate insulation pattern GI in a direction parallel to the top surface 100U of the substrate 100. The semiconductor patterns VSP may be electrically separated from each other by the separation pattern SPC. The separation pattern SPC may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0047] Each of the gate electrode GE, the gate insulating pattern GI, and the semiconductor pattern VSP may form a pair of vertical channel transistors. Each of the semiconductor patterns VSP may serve as a vertical channel of each of the pair of vertical channel transistors. The pair of vertical channel transistors may share each of the gate electrodes GE.

[0048] The gap-filling insulating layer 160 may be disposed on the second lower insulating layer 132 and may fill the space between the pair of vertical channel transistors and another pair of vertical channel transistors adjacent thereto. Each of the semiconductor patterns VSP may have an outer side surface VSP_OS opposite to the inner side surface VSP_IS of each of the semiconductor patterns VSP, and the gap-filling insulating layer 160 may cover the outer side surface VSP_OS of each of the semiconductor patterns VSP. The gap-filling insulating layer 160 may fill the space between the outer side surfaces VSP_OS of the semiconductor patterns VSP. The top surface VSP_U of the semiconductor pattern VSP, the top surface GI_U of the gate insulating pattern GI, and the top surface GE_U of each of the gate electrodes GE may be coplanar with the top surface 160U of the gap-filling insulating layer 160. The top surface VSP_U of the semiconductor pattern VSP, the top surface GI_U of the gate insulating pattern GI, the top surface GE_U of each of the gate electrodes GE, and the top surface 160U of the gap-filling insulating layer 160 may be located at the same height from the substrate 100. The gap-filling insulating layer 160 may be formed of or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0049] The conductive patterns 165 may be respectively disposed on the semiconductor patterns VSP and electrically connected to the semiconductor patterns VSP. Bottom surfaces of the conductive patterns 165 may make contact with top surfaces VSP_U of the semiconductor patterns VSP, respectively.

[0050] Reference Figure 4 and Figure 5, each of the semiconductor patterns VSP may include a first source / drain region SD1 adjacent to each of the second conductive lines 140, a second source / drain region SD2 adjacent to each of the conductive patterns 165, and a channel region CH between the first source / drain region SD1 and the second source / drain region SD2. The first source / drain region SD1 and the second source / drain region SD2 may be spaced apart from each other in the third direction D3, and the channel region CH may be a vertical channel region extending in the third direction D3. Each of the gate electrodes GE, the gate insulating pattern GI, and the semiconductor patterns VSP may constitute a vertical channel transistor, and each of the semiconductor patterns VSP may serve as a vertical channel region of the vertical channel transistor.

[0051] Return to reference Figure 3 and Figure 4 , a first upper insulating layer 170 may be disposed on the gap-filling insulating layer 160 to fill the space between the conductive patterns 165. The first upper insulating layer 170 may cover the top surface GI_U of the gate insulating pattern GI, the top surface GE_U of each of the gate electrodes GE, and the top surface 160U of the gap-filling insulating layer 160. The first upper insulating layer 170 may be formed of or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0052] In an embodiment, the capacitors CAP may be disposed on the conductive patterns 165, respectively. Each of the capacitors CAP may include a bottom electrode BE disposed on each of the conductive patterns 165, a top electrode TE placed on the bottom electrode BE, and a dielectric layer 185 between the bottom electrode BE and the top electrode TE. The bottom electrode BE may have, for example, a hollow cylindrical shape or a cup shape with one closed end. The bottom surface of the bottom electrode BE may contact each of the conductive patterns 165. The top electrode TE may fill a space defined by an inner surface of the bottom electrode BE, and the dielectric layer 185 may extend between the inner surface of the bottom electrode BE and the top electrode TE. The bottom electrode BE may include at least one of doped polysilicon, a metal nitride material (e.g., titanium nitride), and a metal material (e.g., tungsten, aluminum, and copper). The top electrode TE may be formed of or include at least one of doped polysilicon, doped silicon germanium, metal nitride materials (e.g., titanium nitride), and metal materials (e.g., tungsten, aluminum, and copper). The dielectric layer 185 may be formed of or include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and high-k dielectric materials (e.g., hafnium oxide).

[0053] The second upper insulating layer 180 may be disposed on the first upper insulating layer 170 to cover the space between the capacitors CAP. The second upper insulating layer 180 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. A capping insulating layer 190 may be disposed on the second upper insulating layer 180 to cover the top surface of the capacitor CAP. The capping insulating layer 190 may be formed of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride or include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0054] According to an embodiment of the inventive concept, a pair of vertical transistors may share a gate electrode GE controlled by one of the first conductive lines 120, and may include a semiconductor pattern VSP electrically connected to a corresponding second conductive line 140 of the second conductive lines 140. Therefore, it is possible to easily control the operation of the pair of vertical transistors independently. In addition, each of the semiconductor patterns VSP may have a vertical channel structure including a first source / drain region SD1 and a second source / drain region SD2 spaced apart from each other in a third direction D3 and a channel region CH placed between the first source / drain region SD1 and the second source / drain region SD2. Therefore, it is possible to easily increase the integration of a semiconductor device having a vertical channel transistor. Therefore, it is possible to realize a semiconductor device in which the operation of the vertical channel transistor can be easily controlled and the integration can be easily increased.

[0055] In addition, each of the semiconductor patterns VSP may have a curved shape or a bent shape extending along the side surface GE_S of the gate electrode GE in a direction parallel to the top surface 100U of the substrate 100. The inner side surface VSP_IS of each of the semiconductor patterns VSP may be a curved surface or a bent surface disposed to face the side surface GE_S of the gate electrode GE and extending along the side surface GE_S of the gate electrode GE in a direction parallel to the top surface 100U of the substrate 100. Therefore, the effective channel width of the vertical channel transistor including the semiconductor pattern VSP may be easily increased. In this case, the electrical characteristics of the vertical channel transistor in the semiconductor device may be improved.

[0056] Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 and Fig.16 is a plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 and Fig.17 Along the Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 and Fig.16 For simplicity, the previous reference Figures 1 to 5 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0057] Reference Figure 6 and Figure 7 , a device isolation pattern 102 may be formed in the substrate 100 to define an active area ACT. In an embodiment, the formation of the device isolation pattern 102 may include forming a trench 102T in the substrate 100 to define the active area ACT, forming a device isolation layer on the substrate 100 to fill the trench 102T, and planarizing the device isolation layer to expose a top surface of the substrate 100.

[0058] The peripheral transistors PTR may be formed on the active region ACT of the substrate 100. Each of the peripheral transistors PTR may include a peripheral gate electrode PGE on a corresponding one of the active regions ACT, a peripheral gate insulating pattern PGI between the corresponding active region ACT and the peripheral gate electrode PGE, a peripheral capping pattern PCAP on the peripheral gate electrode PGE, a peripheral gate spacer PGSP on a side surface of the peripheral gate electrode PGE, and a peripheral source / drain region PSD formed in a portion of the corresponding active region ACT at both sides of the peripheral gate electrode PGE.

[0059] A peripheral contact 103 and a peripheral interconnection line 104 may be formed on the substrate 100. The peripheral contact 103 may be electrically connected to the peripheral source / drain region PSD of the peripheral transistor PTR, and the peripheral interconnection line 104 may be electrically connected to the peripheral contact 103. A peripheral insulating layer 110 may be formed on the substrate 100 to cover the peripheral transistor PTR, the peripheral contact 103, and the peripheral interconnection line 104.

[0060] The first conductive line 120 may be formed on the peripheral insulating layer 110. The first conductive lines 120 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. In an embodiment, forming the first conductive line 120 may include: forming a first conductive layer on the peripheral insulating layer 110; forming a first mask pattern on the first conductive layer to define a region in which the first conductive line 120 is to be formed; and etching the first conductive layer using the first mask pattern as an etching mask.

[0061] Reference Figure 8 and Fig. 9, a first lower insulating layer 130 may be formed on the peripheral insulating layer 110 to cover the first conductive line 120. A second lower insulating layer 132 may be formed on the first lower insulating layer 130. The second lower insulating layer 132 may be formed of a different material from the first lower insulating layer 130. The first lower insulating layer 130 and the second lower insulating layer 132 may be referred to as lower insulating layers 130 / 132.

[0062] A second conductive line 140 may be formed in the lower insulating layer 130 / 132. The second conductive lines 140 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. Each of the second conductive lines 140 may be disposed to penetrate the second lower insulating layer 132 and may extend into an upper portion of the first lower insulating layer 130. In an embodiment, forming the second conductive line 140 may include: forming a linear groove 140T extending in the second direction D2 and spaced apart from each other in the first direction D1 in the lower insulating layer 130 / 132; forming a second conductive layer on the lower insulating layer 130 / 132 to fill the linear groove 140T; and planarizing the second conductive layer to expose a top surface 132U of the lower insulating layer 130 / 132. Each of the linear grooves 140T may be formed to penetrate the second lower insulating layer 132 and extend in an upper portion of the first lower insulating layer 130. A top surface 132U of the lower insulation layer 130 / 132 may correspond to a top surface 132U of the second lower insulation layer 132 .

[0063] Contact plugs 150 may be formed in the lower insulating layer 130 / 132 between the second conductive lines 140. The contact plugs 150 in the lower insulating layer 130 / 132 may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the contact plugs 150 may be formed to penetrate the lower insulating layer 130 / 132 and may be electrically connected to a corresponding one of the first conductive lines 120. In an embodiment, forming the contact plugs 150 may include: forming a contact hole 150H in the lower insulating layer 130 / 132 between the second conductive lines 140; forming a contact conductive layer on the lower insulating layer 130 / 132 to fill the contact hole 150H; and planarizing the contact conductive layer to expose a top surface 132U of the lower insulating layer 130 / 132. The contact holes 150H in the lower insulating layer 130 / 132 may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the contact holes 150H may be formed to penetrate the lower insulating layer 130 / 132 and expose a top surface of a corresponding one of the first conductive lines 120 .

[0064] Reference Fig.10 and Fig.11, gate electrodes GE may be formed on the contact plugs 150, respectively. The gate electrodes GE may be spaced apart from each other in the first direction D1 and the second direction D2. In an embodiment, forming the gate electrode GE may include: forming a gate electrode layer on the second lower insulating layer 132; forming a second mask pattern on the gate electrode layer to define a region in which the gate electrode GE is to be formed; and etching the gate electrode layer using the second mask pattern as an etching mask.

[0065] A gate insulating layer GIL may be formed on the second lower insulating layer 132 to cover the gate electrode GE. The gate insulating layer GIL may conformally cover the top surface GE_U and the side surface GE_S of each of the gate electrodes GE, and may extend to the top surface 132U of the second lower insulating layer 132 and the top surface 140U of the second conductive line 140. In an embodiment, the gate insulating layer GIL may be formed using a chemical vapor deposition method or a physical vapor deposition method.

[0066] Reference Fig.12 and Fig.13 , a first anisotropic etching process may be performed on the gate insulating layer GIL to locally form a gate insulating pattern GI on the side surface GE_S of each of the gate electrodes GE. As a result of the first anisotropic etching process, the top surface GE_U of each of the gate electrodes GE, the top surface 132U of the second lower insulating layer 132, and the top surface 140U of the second conductive line 140 may be exposed. The gate insulating pattern GI may be a ring-shaped pattern disposed to surround the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0067] A semiconductor layer VSL may be formed on the second lower insulating layer 132 to cover the gate electrode GE and the gate insulating pattern GI. The semiconductor layer VSL may cover the top surface GE_U of each of the gate electrodes GE, and may cover the gate insulating pattern GI on the side surface GE_S of each of the gate electrodes GE. The semiconductor layer VSL may extend to a region on the top surface 132U of the second lower insulating layer 132 and the top surface 140U of the second conductive line 140. In an embodiment, the semiconductor layer VSL may be formed using a chemical vapor deposition method or a physical vapor deposition method.

[0068] Reference Fig.14 and Fig.15, a second anisotropic etching process may be performed on the semiconductor layer VSL to locally form a semiconductor pattern VSP on the side surface GE_S of each of the gate electrodes GE. As a result of the second anisotropic etching process, the top surface GE_U of each of the gate electrodes GE and the top surface 132U of the second lower insulating layer 132 may be exposed. The semiconductor pattern VSP may be in contact with the top surface 140U of a pair of second conductive lines 140 selected from the second conductive lines 140 closest to each other in the first direction D1. The semiconductor pattern VSP may be a ring-shaped pattern disposed to surround the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0069] The gate insulating pattern GI may extend between the side surface GE_S of each of the gate electrodes GE and the semiconductor pattern VSP. The semiconductor pattern VSP may have an inner side surface VSP_IS facing the side surface GE_S of each of the gate electrodes GE and an outer side surface VSP_OS opposite to the inner side surface VSP_IS. The inner side surface VSP_IS of the semiconductor pattern VSP may contact the gate insulating pattern GI.

[0070] According to an embodiment of the inventive concept, since the semiconductor layer VSL is formed on the gate insulating pattern GI using a deposition method, the inner side surface VSP_IS of the semiconductor pattern VSP adjacent to the gate insulating pattern GI may not be exposed to the second anisotropic etching process. Therefore, defects caused by the etching process may not occur on the inner side surface VSP_IS of the semiconductor pattern VSP, and as a result, defects may be prevented from being generated in the effective channel region of the semiconductor pattern VSP. Therefore, a vertical channel transistor including the semiconductor pattern VSP may be formed to have improved electrical characteristics. A gap-filling insulating layer 160 may be formed on the second lower insulating layer 132 to fill the space between adjacent semiconductor patterns VSP in the semiconductor pattern VSP. The gap-filling insulating layer 160 may cover the outer side surface VSP_OS of the semiconductor pattern VSP.

[0071] Reference Fig.16 and Fig.17 , a separation pattern SPC may be formed to penetrate the semiconductor pattern VSP. In the semiconductor pattern VSP, the separation patterns SPC may be spaced apart from each other along the second direction D2, and the semiconductor pattern VSP may be divided into a pair of semiconductor patterns VSP spaced apart from each other in the first direction D1 by the separation patterns SPC. The paired semiconductor patterns VSP may be electrically connected to the paired second conductive lines 140, respectively. The paired semiconductor patterns VSP may have a C-shape, respectively.

[0072] Return to reference Figure 3 and Figure 4, conductive patterns 165 may be formed on the semiconductor patterns VSP, respectively. In an embodiment, forming the conductive patterns 165 may include: forming a conductive layer on the gap-filling insulating layer 160 to cover the semiconductor pattern VSP; forming a third mask pattern on the conductive layer to define a region in which the conductive pattern 165 is to be formed; and etching the conductive layer using the third mask pattern as an etching mask. The conductive patterns 165 may be in contact with the top surfaces VSP_U of the semiconductor patterns VSP, respectively.

[0073] A first upper insulating layer 170 may be formed on the gap-filling insulating layer 160 to fill the space between the conductive patterns 165. A second upper insulating layer 180 may be formed on the first upper insulating layer 170, and capacitors CAP may be formed in the second upper insulating layer 180. The capacitors CAP may be electrically connected to the conductive patterns 165, respectively. Each of the capacitors CAP may include a bottom electrode BE disposed on each of the conductive patterns 165, a top electrode TE placed on the bottom electrode BE, and a dielectric layer 185 between the bottom electrode BE and the top electrode TE.

[0074] In an embodiment, forming the capacitor CAP may include: forming a capacitor hole in the second upper insulating layer 180 to expose each of the conductive patterns 165; forming a bottom electrode BE to fill a portion of the capacitor hole and conformally cover the inner surface of the capacitor hole; forming a dielectric layer 185 to fill a portion of the capacitor hole and conformally cover the inner surface of the bottom electrode BE; and forming a top electrode TE to fill the remaining portion of the capacitor hole. Thereafter, a capping insulating layer 190 may be formed on the second upper insulating layer 180 to cover the top surface of the capacitor CAP.

[0075] Fig.18 is a plan view showing a semiconductor device according to an embodiment of the inventive concept, Fig.19 It is schematically shown Fig.18 For the sake of brevity, the following description will mainly focus on the semiconductor device described in conjunction with the reference Figure 1 and Figure 2 Various features of the semiconductor device are described.

[0076] Reference Fig.18 and Fig.19, the ferroelectric pattern FP may extend between each of the semiconductor patterns VSP1 and VSP2 and the gate insulation pattern GI. When viewed in a plan view, the ferroelectric pattern FP may be a curved pattern or a bent pattern extending along the side surface GE_S of the gate electrode GE. When viewed in a plan view, the ferroelectric pattern FP may have a ring-shaped pattern arranged to surround the side surface GE_S of the gate electrode GE. The inner side surface FP_IS of the ferroelectric pattern FP may face the side surface GE_S of the gate electrode GE and may be spaced apart from the side surface GE_S of the gate electrode GE, and the gate insulation pattern GI extends between the inner side surface FP_IS of the ferroelectric pattern FP and the side surface GE_S of the gate electrode GE. The inner side surface FP_IS of the ferroelectric pattern FP may contact the gate insulation pattern GI. When viewed in a plan view, the inner side surface FP_IS of the ferroelectric pattern FP may be a curved surface or a bent surface extending along the side surface GE_S of the gate electrode GE.

[0077] The separation pattern SPC may extend between the semiconductor patterns VSP1 and VSP2 and may be spaced apart from each other in the second direction D2. The gate electrode GE, the gate insulation pattern GI, and the ferroelectric pattern FP may extend between the separation pattern SPC. When viewed in a plan view, the semiconductor patterns VSP1 and VSP2 and the separation pattern SPC may surround the gate electrode GE, the gate insulation pattern GI, and the ferroelectric pattern FP.

[0078] Conductive patterns 165 may be disposed on the semiconductor patterns VSP1 and VSP2, respectively. The conductive patterns 165 may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. The conductive patterns 165 may extend to be parallel to the second conductive line 140. The conductive patterns 165 may be electrically connected to the semiconductor patterns VSP1 and VSP2, respectively.

[0079] In an embodiment, the gate electrode GE may be electrically connected to the first conductive line 120 through the contact plug 150, and the first conductive line 120 may be used as a word line. The gate electrode GE, the gate insulation pattern GI, the ferroelectric pattern FP, and the semiconductor patterns VSP1 and VSP2 may constitute a pair of vertical channel transistors. The paired vertical channel transistors may share the gate electrode GE, the gate insulation pattern GI, and the ferroelectric pattern FP, and may include semiconductor patterns VSP1 and VSP2, respectively. Each of the semiconductor patterns VSP1 and VSP2 may be used as a vertical channel of each of the paired vertical channel transistors. The second conductive line 140 may be electrically connected to the semiconductor patterns VSP1 and VSP2, respectively, and may be used as a bit line (or source line). The conductive pattern 165 may be electrically connected to the semiconductor patterns VSP1 and VSP2, respectively, and may be used as a source line (or bit line). Each of the second conductive lines 140 and each of the conductive patterns 165 may be electrically connected to the source / drain terminal of each of the paired vertical channel transistors. Each of the pair of vertical channel transistors may constitute a ferroelectric random access memory (FeRAM) cell.

[0080] Fig. 20 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept, and Fig.21 It is along Fig. 20 A cross-sectional view taken along line II'. Fig. 22 It is shown Fig.21 For the sake of brevity, the following description will focus on the reference Figures 3 to 5 Various features of the semiconductor device are described.

[0081] Reference Fig. 20 and Fig.21 , the peripheral transistor PTR may constitute a peripheral circuit for operating or driving the FeRAM cell according to an embodiment of the inventive concept. The first conductive line 120 may be disposed on the peripheral insulating layer 110. The first conductive lines 120 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. Each of the first conductive lines 120 may be electrically connected to a corresponding one of the peripheral interconnection lines 104 through the lower contact 115.

[0082] The first lower insulating layer 130 may be disposed on the peripheral insulating layer 110 to cover the first conductive line 120. The second lower insulating layer 132 may be disposed on the first lower insulating layer 130. The first lower insulating layer 130 and the second lower insulating layer 132 may be referred to as lower insulating layers 130 / 132. The second conductive line 140 may be disposed in the lower insulating layer 130 / 132 and on the first conductive line 120. The second conductive line 140 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The second conductive line 140 may be disposed to cross the first conductive line 120.

[0083] The contact plugs 150 may be disposed in the lower insulating layer 130 / 132 between the second conductive lines 140. In the lower insulating layer 130 / 132, the contact plugs 150 may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the contact plugs 150 may be positioned between a pair of second conductive lines 140 selected from the second conductive lines 140 that are closest to each other in the first direction D1. Between the paired second conductive lines 140, each of the contact plugs 150 may be disposed to penetrate the lower insulating layer 130 / 132 and may be electrically connected to a corresponding one of the first conductive lines 120. The gate electrodes GE may be respectively disposed on the contact plugs 150 and electrically connected to the contact plugs 150. The gate electrodes GE may be spaced apart from each other in the first direction D1 and the second direction D2.

[0084] The semiconductor patterns VSP may be disposed at both sides of each of the gate electrodes GE. The semiconductor patterns VSP may be spaced apart from each other in the first direction D1, with each of the gate electrodes GE extending therebetween. The semiconductor patterns VSP may be respectively disposed on a pair of second conductive lines 140 selected from the second conductive lines 140 that are closest to each other in the first direction D1, and may be respectively electrically connected to the paired second conductive lines 140.

[0085] The gate insulating pattern GI may extend between each of the gate electrodes GE and each of the semiconductor patterns VSP. The gate insulating pattern GI may be a curved pattern or a meandering pattern extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. The gate insulating pattern GI may be a ring-shaped pattern disposed to surround the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0086] In an embodiment, the ferroelectric pattern FP may be arranged to extend between each of the semiconductor patterns VSP and the gate insulation pattern GI. The ferroelectric pattern FP may be a curved pattern or a bent pattern extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. The ferroelectric pattern FP may be an annular pattern arranged to surround the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. The inner side surface FP_IS of the ferroelectric pattern FP may face the side surface GE_S of each of the gate electrodes GE and may contact the gate insulation pattern GI. The inner side surface FP_IS of the ferroelectric pattern FP may be a curved surface or a bent surface extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0087] The ferroelectric pattern FP may include hafnium oxide having ferroelectric properties. The ferroelectric pattern FP may also include a dopant, and in an embodiment, the dopant may be at least one of Zr, Si, Al, Y, Gd, La, Sc, and Sr. The ferroelectric pattern FP may be composed of, for example, HfO 2 , HfZnO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or a combination thereof or including, for example, HfO 2 , HfZnO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or a combination thereof. The ferroelectric pattern FP may have an orthorhombic phase. The ferroelectric pattern FP may have a laminated structure in which at least two different kinds of ferroelectric layers are stacked, or a laminated structure in which at least one ferroelectric layer and at least one insulating layer are stacked.

[0088] Each of the semiconductor patterns VSP may be a curved pattern or a bent pattern extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. An inner side surface VSP_IS of each of the semiconductor patterns VSP may face the side surface GE_S of each of the gate electrodes GE and may be in contact with the ferroelectric pattern FP. An inner side surface VSP_IS of each of the semiconductor patterns VSP may be a curved surface or a bent surface extending along the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0089] The separation pattern SPC may extend between the semiconductor patterns VSP. Between the semiconductor patterns VSP, the separation patterns SPC may be spaced apart from each other in the second direction D2. Each of the gate electrodes GE, the gate insulation pattern GI, and the ferroelectric pattern FP may extend between the separation patterns SPC. The semiconductor pattern VSP and the separation pattern SPC may surround each of the gate electrodes GE, the gate insulation pattern GI, and the ferroelectric pattern FP in a direction parallel to the top surface 100U of the substrate 100.

[0090] Each of the gate electrodes GE, the gate insulating pattern GI, the ferroelectric pattern FP and the semiconductor pattern VSP may constitute a pair of vertical channel transistors. Each of the semiconductor patterns VSP may be used as a vertical channel of each of the paired vertical channel transistors. The paired vertical channel transistors may share each of the gate electrodes GE.

[0091] The gap-filling insulating layer 160 may be disposed on the second lower insulating layer 132 and may fill a space between a pair of vertical channel transistors and another pair of vertical channel transistors adjacent thereto. The gap-filling insulating layer 160 may cover an outer side surface VSP_OS of each of the semiconductor patterns VSP. The gap-filling insulating layer 160 may fill a space between the outer side surfaces VSP_OS of the semiconductor patterns VSP.

[0092] The conductive patterns 165 may be respectively disposed on the semiconductor patterns VSP and electrically connected to the semiconductor patterns VSP. In an embodiment, the conductive patterns 165 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The conductive patterns 165 may extend to be parallel to the second conductive lines 140. Each of the conductive patterns 165 may be electrically connected in common to the semiconductor patterns VSP arranged in the second direction D2.

[0093] Reference Fig.21 and Fig. 22 , each of the semiconductor patterns VSP may include a first source / drain region SD1 adjacent to each of the second conductive lines 140, a second source / drain region SD2 adjacent to each of the conductive patterns 165, and a channel region CH between the first source / drain region SD1 and the second source / drain region SD2. The first source / drain region SD1 and the second source / drain region SD2 may be spaced apart from each other in the third direction D3, and the channel region CH may be a vertical channel region extending in the third direction D3. Each of the gate electrodes GE, the gate insulating pattern GI, the ferroelectric pattern FP, and the semiconductor pattern VSP may form a vertical channel transistor, and each of the semiconductor patterns VSP may serve as a vertical channel region of the vertical channel transistor.

[0094] Reference Fig. 20 and Fig.21 , the first upper insulating layer 170 may be disposed on the gap-filling insulating layer 160 to fill the space between the conductive patterns 165. In an embodiment, the reference Figure 3 and Figure 4 Capacitor CAP described.

[0095] Fig.23 , Fig.25 and Fig. 27 is a plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Fig.24 , Fig.26 and Fig.28 Along the Fig.23 , Fig.25 and Fig. 27 For the sake of brevity, the following will mainly describe the cross-sectional view taken along the line II'. Figures 6 to 17 The described manufacturing methods have different features.

[0096] Reference Fig.23 and Fig.24 , a device isolation pattern 102 may be formed in the substrate 100 to define an active area ACT. A peripheral transistor PTR may be formed on the active area ACT of the substrate 100, and a peripheral contact 103 and a peripheral interconnection line 104 may be formed on the substrate 100. A peripheral insulating layer 110 may be formed on the substrate 100 to cover the peripheral transistor PTR, the peripheral contact 103, and the peripheral interconnection line 104.

[0097] A first conductive line 120 may be formed on the peripheral insulating layer 110. The first conductive lines 120 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. A first lower insulating layer 130 may be formed on the peripheral insulating layer 110 to cover the first conductive line 120. A second lower insulating layer 132 may be formed on the first lower insulating layer 130.

[0098] Second conductive lines 140 may be formed in the lower insulating layer 130 / 132. The second conductive lines 140 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. Contact plugs 150 may be formed in the lower insulating layer 130 / 132 between the second conductive lines 140. In the lower insulating layer 130 / 132, the contact plugs 150 may be spaced apart from each other in the first direction D1 and the second direction D2. Gate electrodes GE may be formed on the contact plugs 150, respectively. The gate electrodes GE may be spaced apart from each other in the first direction D1 and the second direction D2.

[0099] A gate insulating layer GIL may be formed on the second lower insulating layer 132 to cover the gate electrode GE. The gate insulating layer GIL may conformally cover the top surface GE_U and the side surface GE_S of each of the gate electrodes GE, and may extend to the top surface 132U of the second lower insulating layer 132 and the top surface 140U of the second conductive line 140. In an embodiment, the gate insulating layer GIL may be formed using a chemical vapor deposition method or a physical vapor deposition method.

[0100] Reference Fig.25 and Fig.26 , a first anisotropic etching process may be performed on the gate insulating layer GIL to locally form a gate insulating pattern GI on the side surface GE_S of each of the gate electrodes GE. As a result of the first anisotropic etching process, the top surface GE_U of each of the gate electrodes GE, the top surface 132U of the second lower insulating layer 132, and the top surface 140U of the second conductive line 140 may be exposed. The gate insulating pattern GI may be a ring-shaped pattern disposed to surround the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100.

[0101] A ferroelectric layer FPL may be formed on the second lower insulating layer 132 to cover the gate electrode GE and the gate insulating pattern GI. The ferroelectric layer FPL may cover the top surface GE_U of each of the gate electrodes GE, and may cover the gate insulating pattern GI on the side surface GE_S of each of the gate electrodes GE. The ferroelectric layer FPL may extend to an area on the top surface 132U of the second lower insulating layer 132 and the top surface 140U of the second conductive line 140. In an embodiment, the ferroelectric layer FPL may be formed using a chemical vapor deposition method or a physical vapor deposition method.

[0102] Reference Fig. 27 and Fig.28 , a third anisotropic etching process may be performed on the ferroelectric layer FPL to locally form a ferroelectric pattern FP on the side surface GE_S of each of the gate electrodes GE. As a result of the third anisotropic etching process, the top surface GE_U of each of the gate electrodes GE, the top surface 132U of the second lower insulating layer 132, and the top surface 140U of the second conductive line 140 may be exposed. The ferroelectric pattern FP may be a ring-shaped pattern disposed to surround the side surface GE_S of each of the gate electrodes GE in a direction parallel to the top surface 100U of the substrate 100. In addition to the above-mentioned features, the manufacturing method according to the present embodiment may be similar to the method of reference 1 to 3. Figures 6 to 17 The manufacturing method is basically the same.

[0103] Fig.29 Schematically shows a perspective view of a semiconductor device according to an embodiment of the inventive concept. Fig.18and Fig.19 The semiconductor device described has different characteristics. Fig.29 , an additional gate electrode GE-1 may be disposed on the gate electrode GE and may be electrically connected to the gate electrode GE through an additional contact plug (not shown). The additional semiconductor patterns VSP1-1 and VSP2-1 may be respectively disposed on the conductive pattern 165 and may be spaced apart from each other in the first direction D1. The additional semiconductor patterns VSP1-1 and VSP2-1 may be respectively electrically connected to the conductive pattern 165. The additional gate insulating pattern GI-1 may extend between each of the additional semiconductor patterns VSP1-1 and VSP2-1 and the additional gate electrode GE-1. The additional ferroelectric pattern FP-1 may extend between each of the additional semiconductor patterns VSP1-1 and VSP2-1 and the additional gate insulating pattern GI-1.

[0104] The additional second conductive lines 140-1 may be disposed on the additional semiconductor patterns VSP1-1 and VSP2-1, respectively. The additional second conductive lines 140-1 may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. The additional second conductive lines 140-1 may extend to be parallel to the conductive pattern 165. The additional second conductive lines 140-1 may be electrically connected to the additional semiconductor patterns VSP1-1 and VSP2-1, respectively.

[0105] In an embodiment, the gate electrode GE and the additional gate electrode GE-1 may be electrically connected to the first conductive line 120 through the contact plug 150 and the additional contact plug, and the first conductive line 120 may be used as a word line. The gate electrode GE, the gate insulation pattern GI, the ferroelectric pattern FP, and the semiconductor patterns VSP1 and VSP2 may form a first pair of vertical channel transistors, and the additional gate electrode GE-1, the additional gate insulation pattern GI-1, the additional ferroelectric pattern FP-1, and the additional semiconductor patterns VSP1-1 and VSP2-1 may form a second pair of vertical channel transistors. The second pair of vertical channel transistors may be vertically stacked (e.g., in the third direction D3) on the first pair of vertical channel transistors.

[0106] The second conductive line 140 may be electrically connected to the semiconductor patterns VSP1 and VSP2, respectively, and may be used as a bit line. The conductive pattern 165 may be electrically connected to the semiconductor patterns VSP1 and VSP2, respectively, and may be used as a source line. The conductive pattern 165 may be electrically connected to the additional semiconductor patterns VSP1-1 and VSP2-1, respectively. The semiconductor patterns VSP1 and VSP2 and the additional semiconductor patterns VSP1-1 and VSP2-1 may share the conductive pattern 165, and the conductive pattern 165 may be used as a common source line. The additional second conductive line 140-1 may be electrically connected to the additional semiconductor patterns VSP1-1 and VSP2-1, respectively, and may be used as an additional bit line.

[0107] According to an embodiment of the inventive concept, a pair of vertical transistors may share a gate electrode controlled by a first conductive line and may respectively include a semiconductor pattern electrically connected to a corresponding second conductive line semiconductor pattern in a second conductive line semiconductor pattern. Therefore, the operation of the paired vertical transistors can be easily and independently controlled. In addition, each of the semiconductor patterns may have a vertical channel structure and a channel region, the vertical channel structure including a first source / drain region and a second source / drain region spaced apart from each other in a vertical direction, the channel region being disposed between the first source / drain region and the second source / drain region. Therefore, the integration of a semiconductor device having a vertical channel transistor can be easily increased. Therefore, a semiconductor device and a method for manufacturing the same in which the operation of the vertical channel transistor can be easily controlled and the integration can be easily increased can be realized.

[0108] In addition, each of the semiconductor patterns may be a curved pattern or a bent pattern extending along the side surface of the gate electrode in the horizontal direction. Each of the semiconductor patterns may have an inner side surface, which is arranged to face the side surface of the gate electrode and is a curved surface or a bent surface extending along the side surface of the gate electrode in the horizontal direction. Therefore, the effective channel width of the vertical channel transistor including the semiconductor pattern can be easily increased. The inner side surface of each of the semiconductor patterns may not be exposed to the etching process performed to form the semiconductor pattern, and therefore, defects caused by the etching process can be prevented from being generated in the effective channel region of each of the semiconductor patterns. As a result, a semiconductor device including a vertical channel transistor with improved electrical characteristics and a method for manufacturing the same can be realized.

[0109] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate having a pair of second conductive lines thereon; a first conductive line extending between the pair of second conductive lines and the substrate; a contact plug extending between the pair of second conductive lines and electrically connected to the first conductive line; a gate electrode on the contact plug; A first semiconductor pattern and a second semiconductor pattern extending on a first second conductive line and a second second conductive line of the pair of second conductive lines, respectively; a gate insulating pattern extending between each of the first semiconductor pattern and the second semiconductor pattern and the gate electrode; as well as The first conductive pattern and the second conductive pattern extend on the first semiconductor pattern and the second semiconductor pattern, respectively.

2. The semiconductor device according to claim 1, wherein The first conductive pattern and the second conductive pattern are electrically connected to a capacitor electrode of the first capacitor and a capacitor electrode of the second capacitor, respectively; Wherein, the first conductive line is configured as a word line; wherein the pair of second conductive lines is configured as a pair of bit lines; and The gate electrode is configured as a gate electrode of a first access transistor in the first dynamic random access memory cell and a gate electrode of a second access transistor in the second dynamic random access memory cell.

3. The semiconductor device according to claim 2, wherein: When viewed from a planar layout perspective, each of the first semiconductor pattern and the second semiconductor pattern has a C-shape; and Wherein, when viewed from the perspective of planar layout, the gate insulating pattern has a circular ring shape.

4. The semiconductor device according to claim 1, wherein The first conductive line is configured as a word line; wherein the pair of second conductive lines is configured as a pair of bit lines; and The gate electrode is configured as a gate electrode of a first access transistor in the first dynamic random access memory cell and a gate electrode of a second access transistor in the second dynamic random access memory cell.

5. The semiconductor device according to claim 4, wherein: A first conductive line extends across the surface of the substrate in a first direction; wherein the pair of second conductive lines extend across the surface of the substrate in a second direction; and The first direction is perpendicular to the second direction.

6. The semiconductor device according to claim 2, wherein: The capacitor electrode of the first capacitor has a cylindrical shape and the capacitor electrode of the second capacitor has a cylindrical shape; wherein the gate electrode has a cylindrical shape; and Therein, a longitudinal axis of the gate electrode is parallel to a longitudinal axis of the capacitor electrode of the first capacitor and parallel to a longitudinal axis of the capacitor electrode of the second capacitor.

7. The semiconductor device according to claim 3, further comprising: The ferroelectric pattern extends between the first semiconductor pattern, the second semiconductor pattern and the gate insulating pattern.

8. The semiconductor device according to claim 7, wherein: When viewed from a planar layout perspective, the ferroelectric pattern has a donut shape.

9. The semiconductor device according to claim 3, wherein: The first semiconductor pattern includes: a first source / drain region electrically connected to the first conductive pattern; and The second source / drain region is electrically connected to a first second conductive line of the pair of second conductive lines.

10. The semiconductor device according to claim 9, wherein The first semiconductor pattern has a first surface thereon in contact with the first conductive pattern and a second surface thereon in contact with a first second conductive line of the pair of second conductive lines.

11. A semiconductor device, comprising: a first conductive line disposed on the substrate and extending in a first direction parallel to a top surface of the substrate; a lower insulating layer on the first conductive line; second conductive lines disposed on the first conductive lines and in the lower insulating layer and spaced apart from each other in the first direction; a contact plug penetrating the lower insulating layer between the second conductive lines and connected to the first conductive line; a gate electrode on the contact plug; semiconductor patterns extending on the second conductive lines, respectively, and spaced apart from each other in the first direction; as well as a gate insulating pattern extending between each of the semiconductor patterns and the gate electrode; Wherein, a bottom surface of the gate insulating pattern contacts a top surface of the lower insulating layer.

12. The semiconductor device according to claim 11, wherein Bottom surfaces of the semiconductor patterns contact top surfaces of the second conductive lines, respectively.

13. The semiconductor device according to claim 12, wherein: A bottom surface of the gate electrode contacts a top surface of the contact plug.

14. The semiconductor device according to claim 13, wherein: A top surface of the lower insulating layer, a top surface of the second conductive line, and a top surface of the contact plug are located at the same height from a top surface of the substrate in a direction perpendicular to the top surface of the substrate.

15. The semiconductor device according to claim 13, wherein: Each of the semiconductor pattern and the gate insulating pattern is a bent pattern or a zigzag pattern extending along a side surface of the gate electrode in a direction parallel to a top surface of the substrate.

16. A dual dynamic random access memory cell, the dual dynamic random access memory cell comprising: a first access transistor of the first DRAM cell including a cylindrical gate electrode extending vertically relative to a surface of an underlying substrate; as well as The second access transistor of the second dynamic random access memory cell shares the cylindrical gate electrode.

17. The dual dynamic random access memory cell according to claim 16, wherein: The first access transistor includes a first semiconductor active region having a C-shape when viewed from a planar layout perspective; wherein the second access transistor includes a second semiconductor active region that is C-shaped when viewed from a planar layout perspective; and Therein, when viewed from the perspective of a planar layout, the first semiconductor active region and the second semiconductor active region are configured as mirror images of each other.

18. The dual dynamic random access memory cell according to claim 17, further comprising: a first bit line electrically connected to a source / drain region within the first semiconductor active region; as well as a second bit line electrically connected to the source / drain region within the second semiconductor active region; and The cylindrical gate electrode extends between the first bit line and the second bit line.

19. The dual dynamic random access memory cell according to claim 18, further comprising: A word line extends between the first bit line and the second bit line and the surface of the substrate and is electrically connected to the cylindrical gate electrode.

20. The dual dynamic random access memory cell according to claim 17, further comprising: a first cylindrical capacitor electrode electrically connected to the source / drain region within the first semiconductor active region; as well as A second cylindrical capacitor electrode is electrically connected to the source / drain region within the second semiconductor active region.

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