Semiconductor structure, method for preparing same, and chip

Abstract

The present application provides a semiconductor structure, a preparation method thereof, and a chip, relating to the field of semiconductor technology, aiming to reduce the process difficulty. The preparation method of the semiconductor structure includes: forming a first electrode on a substrate by using a sputtering process; forming a dielectric layer on a side of the first electrode away from the substrate; forming a second electrode on a side of the dielectric layer away from the substrate; wherein, during the process of forming the first electrode, the substrate is heated, and a DC bias voltage or an RF bias power is applied to the substrate; the heating temperature range of the substrate is 50°C to 400°C, the DC bias voltage varies within the range of -500V to +150V, or the RF bias power varies within the range of 50w to 400w. The above semiconductor structure can be applied to a memory chip or a sensor chip. The memory chip can be a non-volatile memory, and the sensor chip can be a MEMS pressure sensor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure, a preparation method thereof, and a chip. Background Art

[0002] Currently, ultra-small sensors using Micro-Electro-Mechanical System (MEMS) technology are becoming mainstream. In MEMS pressure sensors, a film can be formed by Chemical Solution Deposition (CSD) process. The cost of the CSD process is relatively low. However, its process temperature is relatively high (600°C - 750°C), which limits the freedom of material use and process selection, and increases the process difficulty. Summary of the Invention

[0003] This application provides a semiconductor structure, a preparation method thereof, and a chip, aiming to reduce the process difficulty.

[0004] To achieve the above object, the embodiments of this application provide the following technical solutions:

[0005] On the one hand, a preparation method of a semiconductor structure is provided. The preparation method includes: forming a first electrode on a substrate by sputtering process; forming a dielectric layer on a side of the first electrode away from the substrate; forming a second electrode on a side of the dielectric layer away from the substrate; wherein, during the process of forming the first electrode, the substrate is heated, and a DC bias voltage or RF bias power is applied to the substrate; the heating temperature range of the substrate is 50°C - 400°C, the DC bias voltage varies within the range of -500V to +150V, or the RF bias power varies within the range of 50w to 400w.

[0006] In the preparation method provided by the embodiments of this application, the first electrode is formed by sputtering process. During sputtering, by applying a DC bias voltage to the substrate, and the DC bias voltage varies within the range of -500V to +150V. It can be understood that when the DC bias voltage is a negative voltage, argon ions in the vacuum chamber can be attracted to bombard the substrate, and when the DC bias voltage is a positive voltage, electrons in the vacuum chamber can be attracted to bombard the substrate, generating plasma heat on the surface of the substrate, which can increase the surface temperature of the substrate and promote the crystallization growth of subsequent dielectric materials. Therefore, even if the heating temperature of the substrate is reduced to the range of 50°C - 400°C, the film quality and characteristics of the subsequent formed dielectric layer can be ensured.

[0007] Alternatively, during sputtering, by applying a radio frequency (RF) bias power to the substrate, with the RF bias power varying within the range of 50 W to 400 W, it can be understood that when the RF bias power is negative, argon ions in the vacuum chamber can be attracted to bombard the substrate, and when the RF bias power is positive, electrons in the vacuum chamber can be attracted to bombard the substrate. This can also increase the surface temperature of the substrate and promote the crystallization growth of the subsequent dielectric material. Therefore, even if the heating temperature of the substrate is reduced to the range of 50°C to 400°C, the film quality and characteristics of the subsequent formed dielectric layer can be ensured.

[0008] Moreover, compared with heating the substrate using a heater or the plasma heat generated by the detachment of target atoms bombarding the substrate, by controlling the change of the DC bias voltage or RF bias power, the plasma heat generated by the bombardment of argon ions and electrons on the substrate can be controlled. This method is easy to control and has a good heating effect on the substrate.

[0009] In some embodiments, the heating temperature range of the substrate is 100°C to 250°C.

[0010] In some embodiments, during the process of forming a dielectric layer by sputtering, the substrate is heated, and the heating temperature range of the substrate is 100°C to 300°C.

[0011] In some embodiments, during the process of forming a dielectric layer by sputtering, a DC bias voltage or an RF bias power is applied to the substrate, with the DC bias voltage varying within the range of -500 V to +150 V or the RF bias power varying within the range of 50 W to 400 W.

[0012] In some embodiments, before forming the first electrode, an adhesion layer is formed on the substrate, and the adhesion layer is in contact with the substrate. Forming the first electrode includes: forming the first electrode on the side of the adhesion layer away from the substrate.

[0013] In some embodiments, forming the dielectric layer includes: forming a dielectric thin film on the side of the first electrode away from the substrate; using a lithography process to pattern the dielectric thin film to form the dielectric layer.

[0014] In some embodiments, during the process of forming the first electrode, the heating temperature of the substrate is 200°C, the DC bias voltage is -300 V, or the RF bias power is 250 W.

[0015] In some embodiments, the material of the dielectric layer includes a piezoelectric material. During the process of forming the dielectric layer, the heating temperature of the substrate is 200°C, the DC bias voltage is -250 V, or the RF bias power is 250 W.

[0016] In some embodiments, the substrate includes opposite first and second surfaces, and a first electrode is formed on the first surface of the substrate; before forming the first electrode, the preparation method further includes: disposing a bias voltage electrode on the second surface of the substrate, and the bias voltage electrode is used to apply a DC bias voltage or RF bias power to the substrate.

[0017] In some embodiments, before forming the first electrode, the preparation method further includes: disposing a magnet on the second surface of the substrate.

[0018] On the other hand, a semiconductor structure is provided, which is prepared by the preparation method described in any one of the above embodiments. The semiconductor structure includes a substrate, and a first electrode, a dielectric layer, and a second electrode stacked on the substrate.

[0019] In yet another aspect, a chip is provided, and the chip includes the semiconductor structure described in the above embodiments.

[0020] The above semiconductor structure and chip have the same structure and beneficial technical effects as the preparation method provided in some of the above embodiments, and will not be elaborated here. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not represent the actual sizes of the products or the actual processes of the methods involved in the embodiments of the present application.

[0022] Figure 1 It is the architecture diagram of the memory chip provided by the embodiment of the present application;

[0023] Figure 2 It is the structural diagram of the sensor chip provided by the embodiment of the present application;

[0024] Figure 3 It is the structural diagram of the semiconductor structure provided by the embodiment of the present application;

[0025] Figure 4 It is the step diagram of setting the substrate of the semiconductor structure provided by the embodiment of the present application;

[0026] Figure 5 It is a step diagram of preparing a first electrode provided by the embodiment of the present application;

[0027] Figure 6 It is the parameter diagram of the working voltage of the magnetron sputtering equipment provided by the embodiment of the present application;

[0028] Figure 7 Another process diagram for preparing the first electrode provided by the embodiment of the present application;

[0029] Figure 8 A process diagram for preparing the dielectric layer provided by the embodiment of the present application;

[0030] Figure 9 Another process diagram for preparing the dielectric layer provided by the embodiment of the present application;

[0031] Figure 10 A process diagram for preparing the second electrode provided by the embodiment of the present application. Detailed implementation manners

[0032] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0033] Unless otherwise required by the context, in the entire specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to".

[0034] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0035] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0036] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond the stated ones.

[0037] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0038] The exemplary embodiments are described with reference to cross-sectional views as idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0039] Embodiments of the present application provide a chip, which can be a memory chip or a sensor chip. Figure 1 It is a block diagram of the memory chip provided by the embodiments of the present application.

[0040] See Figure 1 , when the chip 1 is a memory chip, the memory chip can be a non-volatile memory, and the non-volatile memory includes a plurality of memory cells arranged in an array, and each memory cell includes a ferroelectric capacitor.

[0041] Figure 2 It is a structural diagram of the sensor chip provided by the embodiments of the present application.

[0042] See Figure 2 , when the chip 1 is a sensor chip, the sensor chip can be a Micro-Electro-Mechanical System (MEMS) pressure sensor, and the MEMS pressure sensor includes at least one sensor unit, and each sensor unit includes a piezoelectric device.

[0043] Both the above-mentioned ferroelectric capacitor and piezoelectric device have a semiconductor structure as shown in Figure 3 . See Figure 3 , the semiconductor structure 10 includes a substrate 11, and a first electrode 12, a dielectric layer 13 and a second electrode 14 stacked on the substrate 11. When the semiconductor structure 10 is a ferroelectric capacitor, the material of the dielectric layer 13 includes a ferroelectric material. Alternatively, when the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material.

[0044] Exemplarily, the semiconductor structure 10 further includes an isolation layer 19, and the isolation layer 19 is disposed between the substrate 11 and the first electrode 12. The isolation layer 19 is used to isolate the first electrode 12 from the substrate 11 to prevent alloying between the two and affect the conductivity of the first electrode 12.

[0045] Exemplarily, the semiconductor structure 10 further includes a first adhesion layer 15 disposed between the substrate 11 and the first electrode 12, and the first adhesion layer 15 is used to improve the adhesion between the first electrode 12 and the substrate 11. When the semiconductor structure 10 further includes an isolation layer 19, the first adhesion layer 15 is disposed between the isolation layer 19 and the first electrode 12.

[0046] Exemplarily, the semiconductor structure 10 further includes a second adhesion layer 18 disposed between the dielectric layer 13 and the second electrode 14, and the second adhesion layer 18 is used to improve the adhesion between the second electrode 14 and the dielectric layer 13.

[0047] In the process of fabricating the above semiconductor structure 10, the first electrode 12 is first formed on the substrate 11, and then the dielectric layer 13 is formed on the first electrode 12. In order to promote the crystallization growth of the dielectric material, the substrate 11 usually needs to be heated to a high temperature of 500 °C to 600 °C. Due to the high heating temperature of the substrate 11, the material selection of the substrate 11 and the freedom of process selection are restricted, which increases the process difficulty of fabricating the semiconductor structure 10.

[0048] To solve the above problems, an embodiment of the present application further provides a method for fabricating a semiconductor structure. Figures 4 - 10 These are the process diagrams of the steps for fabricating the semiconductor structure provided by the embodiments of the present application.

[0049] See Figure 4 , place the substrate 11 in the vacuum chamber 2 of a magnetron sputtering device.

[0050] Exemplarily, the substrate 11 is a silicon substrate. In this case, first perform a standard cleaning 1 (SC-1) on the substrate 11. The composition of the cleaning solution used includes ammonium hydroxide (chemical formula: NH4OH), hydrogen peroxide (chemical formula: H2O2), and water (chemical formula: H2O). Then, perform a standard cleaning 2 (SC-2) on the substrate 11. The composition of the cleaning solution used includes hydrogen chloride (chemical formula: HCl), hydrogen peroxide (chemical formula: H2O2), and water (chemical formula: H2O). Finally, place the substrate 11 in the vacuum chamber 2 of the magnetron sputtering device. For example, the substrate 11 is placed on the stage 3 in the vacuum chamber 2.

[0051] Exemplarily, the substrate 11 is a quartz substrate. In this case, the substrate 11 is first cleaned with a cleaning solution of alkoxy, and then cleaned with a cleaning solution containing sulfuric acid (chemical formula: H2SO4) and hydrogen peroxide (chemical formula: H2O2). After the substrate 11 is dried, it is placed in the vacuum chamber 2 of the magnetron sputtering device. For example, the substrate 11 is placed on the stage 3 in the vacuum chamber 2.

[0052] Refer to Figure 5 , and a first electrode 12 is formed on the substrate 11 by a sputtering process. During the formation of the first electrode 12, the substrate 11 is heated, and the heating temperature range of the substrate 11 is 50°C to 400°C, and a DC bias voltage is applied to the substrate 11 through the anode, and the DC bias voltage varies within the range of -500V to +150V.

[0053] Exemplarily, as Figure 5 shown, the electrode target 16 is placed at the cathode of the magnetron sputtering device, and argon gas, or argon gas and oxygen, or argon gas and nitrogen is introduced into the vacuum chamber 2 through the gas inlet. A magnetic field is provided near the electrode target 16, and electrons are subjected to the Lorentz force in the magnetic field and perform spiral motion, which can increase the number of collisions between electrons and argon molecules, increase the number of argon ions generated by the ionization of argon molecules, and thus increase the density of the plasma in the vacuum chamber 2. The argon ions are accelerated under the action of the electric field and bombard the surface of the electrode target 16, causing the target atoms to fall off and deposit on the substrate 11 to form the first electrode 12.

[0054] Moreover, during the magnetron sputtering to form the first electrode 12, the stage 3 can be rotated to drive the substrate 11 to rotate, which is beneficial to improving the thickness uniformity of the first electrode 12.

[0055] Exemplarily, refer to Figure 6 , the cathode of the magnetron sputtering device receives the target reference voltage, and the anode receives the DC bias voltage, and the DC bias voltage varies within the range of -500V to +150V, ensuring that the DC bias voltage is always greater than the target reference voltage, so that the argon ions are accelerated under the action of the electric field and bombard the target, that is, the value of the target reference voltage should be less than the minimum value -500V of the DC bias voltage.

[0056] Exemplarily, during the formation of the first electrode 12, the heating temperature of the substrate 11 is 50°C, 100°C, 200°C, 225°C, 250°C, 300°C or 400°C. Exemplarily, during the formation of the first electrode 12, the DC bias voltage applied to the substrate 11 is -500V, -300V, -250V, -175V, +100V or +150V.

[0057] For example, during the formation of the first electrode 12, the heating temperature of the substrate 11 is 200°C, and the DC bias voltage applied to the substrate 11 is -300V.

[0058] Alternatively, referring to Figure 7 , a sputtering process is adopted to form the first electrode 12 on the substrate 11. During the formation of the first electrode 12, the substrate 11 is heated, and the heating temperature range of the substrate 11 is 50°C to 400°C, and an RF bias power is applied to the substrate 11 through the anode, and the RF bias power varies within the range of 50w to 400w.

[0059] Exemplarily, during the formation of the first electrode 12, the heating temperature of the substrate 11 is 50°C, 100°C, 225°C, 250°C, 300°C or 400°C. Exemplarily, during the formation of the first electrode 12, the RF bias power applied to the substrate 11 is 50w, 100w, 225w, 250w or 400w.

[0060] For example, during the formation of the first electrode 12, the heating temperature of the substrate 11 is 200°C, and the RF bias power applied to the substrate 11 is 250w.

[0061] In the above embodiments of the present application, the first electrode 12 is formed by a sputtering process. During sputtering, a DC bias voltage is applied to the substrate 11 through the anode, and the DC bias voltage varies within the range of -500V to +150V. It can be understood that when the DC bias voltage is a negative voltage, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11. When the DC bias voltage is a positive voltage, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, generating plasma heat on the surface of the substrate 11, which can increase the surface temperature of the substrate 11 and promote the crystallization growth of the subsequent dielectric material. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 50°C to 400°C, the film quality and characteristics of the subsequent formed dielectric layer can be ensured.

[0062] Alternatively, during sputtering, an RF bias power is applied to the substrate 11 through the anode, and the RF bias power varies within the range of 50w to 400w. It can be understood that when the RF bias power is negative, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11. When the RF bias power is positive, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, which can also increase the surface temperature of the substrate 11 and promote the crystallization growth of the subsequent dielectric material. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 50°C to 400°C, the film quality and characteristics of the subsequent formed dielectric layer can be ensured.

[0063] Moreover, compared with heating the substrate 11 using a heater or the plasma heat generated by the detachment of target atoms bombarding the substrate 11, by controlling the change of the DC bias voltage or RF bias power, the plasma heat generated by argon ions and electrons bombarding the substrate 11 can be controlled. This method is easy to control and has a good heating effect on the substrate 11.

[0064] Exemplarily, during the formation of the first electrode 12, the substrate 11 is heated, and the heating temperature range of the substrate 11 is 100°C to 250°C. Even when the heating temperature of the substrate 11 decreases, the film quality and characteristics of the dielectric layer 13 can be ensured.

[0065] Exemplarily, before forming the first electrode 12 on the substrate 11, an isolation layer 19 can be first formed on the substrate 11. The material of the isolation layer 19 can include at least one of silicon dioxide (chemical formula: SiO2), zirconium dioxide (chemical formula: ZrO2), silicon carbide (chemical formula: SiC), strontium ruthenate (chemical formula: SrRuO3), or strontium titanate (chemical formula: SrTiO3) or aluminum oxide (chemical formula: Al2O3). The film thickness range of the isolation layer 19 is 0.003 μm to 1 μm. The isolation layer 19 is used to isolate the first electrode 12 from the substrate 11 to prevent alloying between the two and affect the conductivity of the first electrode 12.

[0066] For example, when the material of the isolation layer 19 includes silicon dioxide, tetraethyl orthosilicate (TEOS) can be used to prepare a silicon dioxide film layer under a low-temperature process.

[0067] Exemplarily, referring to Figure 5 and Figure 7 , before forming the first electrode 12 on the substrate 11, a first adhesion layer 15 is formed on the substrate 11. The first adhesion layer 15 is used to improve the adhesion between the first electrode 12 and the substrate 11. The material of the first adhesion layer 15 can include at least one of titanium (chemical formula: Ti), iridium dioxide (chemical formula: IrO2), zirconium dioxide, or chromium (chemical formula: Cr). The film thickness range of the first adhesion layer 15 is 3 nm to 200 nm. Finally, the first electrode 12 is formed on the side of the first adhesion layer 15 away from the substrate 11.

[0068] In some other embodiments, since the heating temperature of the substrate 11 decreases during the formation of the first electrode 12, the first electrode 12 is not easily alloyed with the substrate 11. Therefore, before forming the first adhesion layer 15, there is no need to form the isolation layer 19 on the substrate 11, and no isolation layer 19 is provided between the first adhesion layer 15 and the substrate 11, that is, the first adhesion layer 15 can be in direct contact with the substrate 11, which can simplify the process and reduce the process cost.

[0069] Exemplarily, the material of the first electrode 12 may include at least one of platinum (chemical formula: Pt), iridium (chemical formula: Ir), rhenium (chemical formula: Re), ruthenium (chemical formula: Ru), or titanium nitride (chemical formula: TiN), and the film thickness range of the first electrode 12 is 10 nm to 1500 nm.

[0070] In some embodiments, referring to Figure 5 and Figure 7 , the substrate 11 includes opposite first and second surfaces 11a and 11b, and the first electrode 12 is formed on the first surface 11a of the substrate 11. Before forming the first electrode 12, a bias voltage electrode 4 is further provided on the second surface 11b of the substrate 11. For example, the bias voltage electrode 4 may be formed on the surface of the stage 3, and the bias voltage electrode 4 is used to apply a DC bias voltage or RF bias power to the substrate 11.

[0071] In some embodiments, referring to Figure 5 and Figure 7 , before forming the first electrode 12, a magnet may also be provided on the second surface 11b of the substrate 11. By setting a magnetic field near the substrate 11, the number of collisions between electrons and argon molecules near the substrate 11 can be increased, and the number of argon ions can be increased, thereby increasing the density of the plasma near the substrate 11.

[0072] Based on this, during the formation of the first electrode 12, by applying a DC bias voltage or RF bias power to the substrate 11, the number of argon ions and electrons bombarding the substrate 11 can be increased, further increasing the surface temperature of the substrate 11, promoting the crystallization growth of the subsequent dielectric material, being beneficial to reducing the heating temperature of the substrate 11, and ensuring the film quality and characteristics of the dielectric layer 13.

[0073] Referring to Figure 8 , a dielectric layer 13 is formed on the side of the first electrode 12 away from the substrate 11.

[0074] Exemplarily, as Figure 8 shown, the dielectric target 17 is placed at the cathode of the magnetron sputtering device, and argon gas, or argon gas and oxygen, or argon gas and nitrogen is introduced into the vacuum chamber 2 through the gas inlet. The composition of the introduced gas depends on the use of the dielectric layer 13 to be formed. The electrons are subjected to the Lorentz force in the magnetic field and move in a spiral motion, which can increase the number of collisions between electrons and argon molecules, increase the number of argon ions generated by the ionization of argon molecules, and thus increase the density of the plasma in the vacuum chamber 2. The argon ions are accelerated under the action of the electric field and bombard the surface of the dielectric target 17, causing the target atoms to fall off and deposit on the substrate 11 to form a whole-surface dielectric thin film. Then, a photolithography process is used to pattern the dielectric thin film to form the dielectric layer 13.

[0075] During the formation of the dielectric film, the substrate 11 is heated, and the heating temperature range of the substrate 11 is 100°C to 300°C. For example, the heating temperature of the substrate 11 is 100°C, 150°C, 200°C, 250°C, or 300°C.

[0076] It can be understood that during the formation of the first electrode 12, a DC bias voltage or RF bias power is applied to the substrate 11, and the DC bias voltage or RF bias power undergoes dynamic switching of positive and negative values, which can attract argon ions and electrons in the vacuum chamber 2 to bombard the substrate 11, increasing the surface temperature of the substrate 11. Therefore, during the formation of the dielectric film, the heating temperature of the substrate 11 can be reduced to 100°C to 300°C, and it can also promote the crystallization growth of the dielectric material, ensuring the film quality and characteristics of the dielectric layer 13.

[0077] Moreover, after film formation, there is no need to perform high-temperature treatment on the substrate 11, enabling the temperature of the substrate 11 to be adapted to the temperature of the lithography process. Therefore, after the formation of the dielectric film, a lithography process can be used to pattern the dielectric film to form the dielectric layer 13.

[0078] Exemplarily, as Figure 8 shown, during the formation of the dielectric layer 13, a DC bias voltage is applied to the substrate 11, and the DC bias voltage varies within the range of -500V to +150V.

[0079] For example, during the formation of the dielectric layer 13, the DC bias voltage applied to the substrate 11 is -500V, -250V, -175V, +100V, or +150V.

[0080] When the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material. During the formation of the dielectric layer 13, the heating temperature of the substrate 11 is 200°C, and the DC bias voltage applied to the substrate 11 is -250V.

[0081] Or, as Figure 9 shown, during the formation of the dielectric layer 13, an RF bias power is applied to the substrate 11, and the RF bias power varies within the range of 50w to 400w.

[0082] For example, during the formation of the dielectric layer 13, the RF bias power applied to the substrate 11 is 50w, 100w, 225w, 250w, or 400w.

[0083] When the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material. During the formation of the dielectric layer 13, the heating temperature of the substrate 11 is 200°C, and the RF bias power applied to the substrate 11 is 250w.

[0084] In the above embodiments of the present application, the dielectric layer 13 is formed by a sputtering process. During the sputtering process, a DC bias voltage is applied to the substrate 11 through the anode. The DC bias voltage varies within the range of -500V to +150V. It can be understood that when the DC bias voltage is a negative voltage, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11. When the DC bias voltage is a positive voltage, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, generating plasma heat on the surface of the substrate 11, which can increase the surface temperature of the substrate 11 and promote the crystallization growth of the dielectric material. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 100°C to 300°C, the film quality and characteristics of the dielectric layer 13 can be ensured.

[0085] Alternatively, during the sputtering process, an RF bias power is applied to the substrate 11 through the anode. The RF bias power varies within the range of 50w to 400w. It can be understood that when the RF bias power is negative, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11. When the RF bias power is positive, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, which can also increase the surface temperature of the substrate 11 and promote the crystallization growth of the dielectric material. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 100°C to 300°C, the film quality and characteristics of the dielectric layer 13 can be ensured.

[0086] Moreover, compared with heating the substrate 11 using a heater or the plasma heat generated by the detachment of target atoms bombarding the substrate 11, by controlling the change of the DC bias voltage or the RF bias power, the plasma heat generated by argon ions and electrons bombarding the substrate 11 can be controlled. This method is easy to control and has a good heating effect on the substrate 11.

[0087] In addition, since the heating temperature of the substrate 11 is reduced during the formation of the dielectric layer 13, the first electrode 12 is not easily alloyed with the substrate 11. Therefore, it is not necessary to form an isolation layer 19 on the substrate 11 before forming the first adhesion layer 15, and no isolation layer 19 is provided between the first adhesion layer 15 and the substrate 11, that is, the first adhesion layer 15 can be in direct contact with the substrate 11, which can simplify the process and reduce the process cost.

[0088] Exemplarily, depending on the use, the film thickness of the dielectric layer 13 is different. When the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material. For example, the piezoelectric material may include at least one of lead zirconate titanate (PZT: PbTiO3 / PbZrO3) or lead niobate zirconate titanate (PNZT: PbTiO3 / PbZrO3 / PbNbO3), and the film thickness range of the dielectric layer 13 is 0.001μm to 400μm.

[0089] See Figure 10 A second electrode 14 is formed on the side of the dielectric layer 13 away from the substrate 11, and thus the preparation of the semiconductor structure 10 is completed.

[0090] Exemplarily, before forming the second electrode 14 on the substrate 11, a second adhesion layer 18 is formed on the substrate 11. The second adhesion layer 18 is used to improve the adhesion between the second electrode 14 and the dielectric layer 13. The material of the second adhesion layer 18 may include at least one of titanium, iridium dioxide, zirconium dioxide, or chromium. The film thickness range of the second adhesion layer 18 is 3 nm to 200 nm.

[0091] Exemplarily, a magnetron sputtering process can be used to form the second electrode 14. For example, as Figure 10 shown, the electrode target 16 is placed at the cathode of the magnetron sputtering device, and argon gas, or argon gas and oxygen, or argon gas and nitrogen is introduced into the vacuum chamber 2 through the gas inlet. A magnetic field is provided near the electrode target 16. The electrons are affected by the Lorentz force in the magnetic field and move in a spiral motion, which can increase the number of collisions between the electrons and argon molecules, increase the number of argon ions generated by the ionization of argon molecules, and thus increase the density of the plasma in the vacuum chamber 2. The argon ions are accelerated under the action of the electric field and bombard the surface of the electrode target 16, causing the target atoms to fall off and deposit on the substrate 11 to form the second electrode 14.

[0092] Moreover, during the formation of the second electrode 14 by magnetron sputtering, the stage 3 can be rotated to drive the substrate 11 to rotate, which is beneficial to improving the thickness uniformity of the second electrode 14.

[0093] Exemplarily, the material of the second electrode 14 may include at least one of platinum, iridium, rhenium, or ruthenium. The film thickness range of the second electrode 14 is 10 nm to 1500 nm.

[0094] To verify the above embodiments, the inventors of the present application also conducted the following comparative experiments:

[0095] Comparative example: During the formation of the first electrode and the dielectric layer, the substrate was heated, the heating temperature of the substrate was 600 °C, and no DC bias voltage was applied to the substrate.

[0096] Example 1: During the formation of the first electrode 12, the substrate 11 was heated, the heating temperature of the substrate 11 was 250 °C, and no DC bias voltage was applied to the substrate; during the formation of the dielectric layer 13, the substrate 11 was heated, the heating temperature of the substrate 11 was 250 °C, and a DC bias voltage of -250 V was applied to the substrate 11.

[0097] Example 2: During the formation of the first electrode 12, the substrate 11 is heated to a temperature of 200 °C, and a DC bias voltage of -300 V is applied to the substrate 11; during the formation of the dielectric layer 13, the substrate 11 is heated to a temperature of 200 °C, and a DC bias voltage of -250 V is applied to the substrate 11.

[0098] The comparison between the comparative example and the examples is realized by obtaining the polarization-electric field hysteresis loop (P-E loop) of the dielectric layer 13, or observing the cross-section of the dielectric layer 13 using a Scanning Electron Microscope (SEM), or obtaining the XRD curve of the dielectric layer 13 by an X-ray diffractometer.

[0099] It is found that the film quality of the dielectric layer 13 in the comparative example, Example 1 and Example 2 is close. By comparing the comparative example and Example 1, it can be seen that during the formation of the dielectric layer 13, by applying a DC bias voltage of -250 V to the substrate 11, even if the substrate 11 is not heated to 600 °C and the heating temperature of the substrate 11 is reduced to 250 °C, the same crystal growth quality can be obtained.

[0100] Moreover, by comparing Example 1 and Example 2, it can be seen that during the formation of the first electrode 12, by applying a DC bias voltage of -300 V to the substrate 11, even if the substrate 11 is not heated to 250 °C and the heating temperature of the substrate 11 is reduced to 200 °C, the same crystal growth quality can be obtained.

[0101] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, thinking of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Comprising: Forming a first electrode on a substrate by a sputtering process; Forming a dielectric layer on a side of the first electrode away from the substrate; Forming a second electrode on a side of the dielectric layer away from the substrate; Wherein, during the process of forming the first electrode, heating the substrate and applying a DC bias voltage or RF bias power to the substrate; The heating temperature range of the substrate is 50°C to 400°C, and the DC bias voltage dynamically switches between positive and negative values within the range of -500V to +150V or the RF bias power dynamically changes within the range of 50w to 400w.

2. The preparation method according to claim 1, characterized in that, The heating temperature range of the substrate is 100°C to 250°C.

3. The preparation method according to claim 1, characterized in that, During the process of forming the dielectric layer by a sputtering process, heating the substrate, and the heating temperature range of the substrate is 100°C to 300°C.

4. The preparation method according to claim 1, wherein During the process of forming the dielectric layer by a sputtering process, applying a DC bias voltage or RF bias power to the substrate, and the DC bias voltage changes within the range of -500V to +150V or the RF bias power changes within the range of 50w to 400w.

5. The preparation method according to claim 1, characterized in that, Before forming the first electrode, the preparation method further includes: Forming an adhesion layer on the substrate, and the adhesion layer is in contact with the substrate; Forming the first electrode includes: Forming the first electrode on a side of the adhesion layer away from the substrate.

6. The preparation method according to claim 1, characterized in that, Forming the dielectric layer includes: Forming a dielectric thin film on a side of the first electrode away from the substrate; Using a photolithography process to pattern the dielectric thin film to form the dielectric layer.

7. The preparation method according to claim 1, characterized in that, The material of the dielectric layer includes a piezoelectric material; During the process of forming the dielectric layer, the heating temperature of the substrate is 200°C, the DC bias voltage is -250V or the RF bias power is 250w.

8. The preparation method according to claim 1, wherein, The substrate includes opposite first and second surfaces, and the first electrode is formed on the first surface of the substrate; Before forming the first electrode, the preparation method further includes: Providing a bias voltage electrode on the second surface of the substrate, and the bias voltage electrode is used to apply a DC bias voltage to the substrate.

9. The preparation method according to claim 8, wherein Before forming the first electrode, the preparation method further includes: Providing a magnet on the second surface of the substrate.

10. A semiconductor structure, characterized in that, Comprising a substrate, and a first electrode, a dielectric layer, and a second electrode stacked on the substrate; The semiconductor structure is prepared by the preparation method according to any one of claims 1 to 9.

11. A chip, characterized in that, Comprising the semiconductor structure according to claim 10.

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