Method for manufacturing a semiconductor device and semiconductor device

Abstract

The application belongs to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor device manufacturing method and a semiconductor device, which comprises the following steps: manufacturing a first wafer, the first wafer comprising a base layer and a target structure layer, the first side of the base layer being provided with a receiving groove, and the target structure layer being partially or wholly located in the receiving groove; dividing the target structure layer into a normal region and a deviation region according to the height of the upper surface of the target structure layer relative to the first side; designing the volume of the receiving groove corresponding to the deviation region on the second wafer according to the deviation of the height of the deviation region on the first wafer relative to the height of the normal region; and manufacturing a second wafer, at least part of the target structure layer of the second wafer and part of the target structure layer of the first wafer being manufactured by using the same process condition. By increasing or decreasing the volume of the receiving groove on the second wafer, the height of the upper surface of the target structure layer can be controlled, the film thickness consistency of the target structure layer is improved, and the yield of the semiconductor device is improved.

Description

[0001] This application is a divisional application of application number 202311535788.1, filed on November 16, 2023, entitled "Method for manufacturing a semiconductor device and semiconductor device". Technical Field

[0002] This application belongs to the field of semiconductor manufacturing technology, specifically relating to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0003] In the fabrication of semiconductor devices, it is often necessary to form a target structural layer on a substrate or one or more structural layers on the substrate. A groove is formed on the substrate or one or more structural layers on the substrate, and the target structural layer is partially or entirely formed in the groove.

[0004] Limited by the groove structure of the substrate or one or more structural layers on the substrate, and the fabrication process of the target structural layer, the film height uniformity of the target structural layer is poor, which leads to a decrease in the yield of semiconductor devices. Summary of the Invention

[0005] The purpose of this application is to provide a method for manufacturing a semiconductor device and a semiconductor device in order to improve the yield of semiconductor devices.

[0006] To achieve the above objectives, this application provides a method for fabricating a semiconductor device, comprising:

[0007] A first wafer is fabricated, which is a wafer sample. The first wafer includes a transistor. The transistor includes a base layer and a target structure layer formed on one side of the base layer. A receiving trench is provided on a first side of the base layer. The target structure layer is partially or entirely located within the receiving trench. The target structure layer includes a silicon-germanium body. The transistor includes a gate located on the first side. A gap is formed between adjacent gates. An overflow portion of the silicon-germanium body is located in the gap between adjacent gates. The silicon-germanium body includes a seed layer and an epitaxial layer. The seed layer is formed on the inner sidewall of the receiving trench. The epitaxial layer is formed within the seed layer and outside the receiving trench. The epitaxial layer is formed using an epitaxial growth process. The epitaxial layer of the second wafer and the epitaxial layer of the first wafer are fabricated using the same process conditions.

[0008] Based on the height of the upper surface of the target structure layer relative to the first side, the target structure layer is divided into a normal area and an off-center area, wherein the height of the off-center area is greater than or less than the height of the normal area;

[0009] Based on the deviation of the height of the offset region on the first wafer from the height of the normal region, the volume of the accommodating groove on the second wafer corresponding to the offset region is designed accordingly, and the second wafer is a positive wafer.

[0010] The second wafer is fabricated using the same process conditions as the target structure layer portion of the first wafer.

[0011] Optionally, the target structural layer is partially located within the receiving groove, which is a rectangular groove or a convex hexagonal groove. The target structural layer includes a buried portion and an overflow portion. The buried portion is embedded within the base layer, and the overflow portion is exposed on the first side. The height of the target structural layer relative to the first side is equal to the thickness of the overflow portion.

[0012] Optionally, the volume of the accommodating groove on the second wafer corresponding to the offset region includes:

[0013] When fabricating the second wafer, the thickness H_bulk1 of the overflow portion corresponding to the deviation region is set;

[0014] Calculate the cross-sectional area S_bulk1 of the overflow portion in the direction of the gap between adjacent gates based on the thickness H_bulk1 of the overflow portion;

[0015] Based on the cross-sectional area S_SiGe of the silicon-germanium body in the direction of the gap between adjacent gates and the cross-sectional area S_bulk1 of the overflow portion, the cross-sectional area S_Trench1 of the accommodating trench on the second wafer in the direction of the gap between adjacent gates is calculated.

[0016] Optionally, the receiving groove is a convex hexagonal groove, and the cross-sectional area S_bulk1 of the overflow portion is:

[0017]

[0018] Wherein, OP is the width of the gap between adjacent gates, and α is the apex angle of the overflow portion.

[0019] Optionally, the cross-sectional area S_Trench1 of the receiving groove is:

[0020] S_Trench1 = S_SiGe - S_bulk1.

[0021] Optionally, the cross-sectional areas S_Trench1 and L_Trench1 of the receiving groove conform to the following formula:

[0022]

[0023] Wherein, L_Trench0 is the cross-sectional perimeter of the accommodating groove corresponding to the offset region of the first wafer in the direction of the gap between adjacent gates, and L_Trench1 is the cross-sectional perimeter of the accommodating groove corresponding to the offset region of the second wafer in the direction of the gap between adjacent gates.

[0024] Optionally, the gate includes a gate electrode and a sidewall located between the gate electrode and the receiving groove, the receiving groove being a convex hexagonal groove, and the perimeter L_Trench of the receiving groove in the direction of extension of the gap between adjacent gates is calculated by the following perimeter calculation formula:

[0025]

[0026] Wherein, BCD is the lower side length of the cross-section of the receiving groove, S2G is the width of the sidewall, T2G is the distance between the receiving groove and the gate electrode in the gap width direction between adjacent gates, RCD is the depth of the receiving groove, the receiving groove includes an upper isosceles trapezoidal region away from the base layer and a lower isosceles trapezoidal region close to the base layer, and SMD is the height of the upper isosceles trapezoidal region;

[0027] Both the cross-sectional perimeter L_Trench0 and the cross-sectional perimeter L_Trench1 are calculated using the perimeter calculation formula.

[0028] Optionally, the volume of the accommodating groove on the second wafer corresponding to the offset region includes:

[0029] Calculate the cross-sectional perimeter L_Trench1 of the receiving groove based on its cross-sectional area S_Trench1, and calculate the cross-sectional perimeter L_Trench0 of the receiving groove of the first wafer.

[0030] Substitute the cross-sectional perimeter L_Trench1 and the cross-sectional perimeter L_Trench0 into the calculation formula for the cross-sectional area S_Trench1 of the receiving groove to calculate the expected cross-sectional area S_bulk1 of the overflow portion.

[0031] When the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements, the receiving groove is formed according to the cross-sectional area S_Trench1 of the receiving groove. When the expected cross-sectional area S_bulk1 of the overflow portion does not meet the design requirements, the thickness H_bulk1 of the overflow portion and the corresponding cross-sectional area S_bulk1 of the overflow portion are redesigned until the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements.

[0032] Optionally, the deviation region includes a thinner region, and the volume of the receiving groove on the second wafer corresponding to the deviation region includes: reducing the volume of the receiving groove on the second wafer corresponding to the thinner region;

[0033] Alternatively, the deviation region may include a thicker region, and the volume of the accommodating groove on the second wafer corresponding to the deviation region may include: increasing the volume of the accommodating groove on the second wafer corresponding to the thicker region.

[0034] Optionally, the deviation region includes a thicker region and a thinner region, and the formation process of the target structural layer includes chemical vapor deposition or physical vapor deposition; before the volume of the accommodating trench corresponding to the deviation region on the corresponding second wafer, the following steps are included:

[0035] When the thinnest region of the target structural layer of at least the first wafer is 0, the method for fabricating the semiconductor device includes:

[0036] Reduce the thickness of the target structure layer formed during the fabrication of the second wafer, and then divide the normal region and the deviation region according to the target structure layer to be formed;

[0037] When the thickness region of the target structural layer of at least the first wafer is 0, the method of fabricating the semiconductor device includes:

[0038] Increase the thickness of the target structure layer formed during the fabrication of the second wafer, and then divide the normal region and the deviation region according to the target structure layer to be formed;

[0039] The method for adjusting the thickness of the target structure layer formed during the fabrication of the second wafer includes adjusting the time for forming the target structure layer, the reaction temperature for forming the target structure layer, and the flow rate of the reaction gas.

[0040] This application also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0041] The semiconductor device fabrication method and semiconductor device disclosed in this application have the following beneficial effects:

[0042] The method for fabricating a semiconductor device in this application includes: fabricating a first wafer, the first wafer including a base layer and a target structure layer, a receiving trench provided on a first side of the base layer, and the target structure layer partially or entirely located within the receiving trench; dividing the target structure layer into a normal region and an off-center region according to the height of the upper surface of the target structure layer relative to the first side; designing the volume of the receiving trench corresponding to the off-center region on a second wafer according to the height of the off-center region of the target structure layer on the first wafer; and then fabricating the second wafer using the same process conditions. Since the target structure layers of the first and second wafers are fabricated using the same process conditions, their volume distributions are approximately equal. By increasing or decreasing the volume of the receiving trench on the second wafer, the height of the upper surface of the target structure layer can be controlled, ensuring that almost all areas of the target structure layer are within the range of the normal region, thereby improving the film thickness uniformity of the target structure layer and thus improving the yield of the semiconductor device.

[0043] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0046] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application.

[0047] Figure 2 This is a schematic diagram of the structure of the semiconductor device in the embodiments of this application.

[0048] Figure 3 This is a schematic diagram of the target structural layer partitioning of the first wafer in an embodiment of this application.

[0049] Figure 4 This is a schematic diagram of the structure of a semiconductor device with a P-type transistor in an embodiment of this application.

[0050] Figure 5 This is a schematic diagram of the formation of a silicon-germanium body in an embodiment of this application.

[0051] Explanation of reference numerals in the attached figures:

[0052] 100, Substrate; 101, First side; 110, Receiving groove;

[0053] 200. Target structural layer; 201. Normal region; 202. Thinner region; 203. Thicker region; 210. Seed layer; 220. Epitaxial layer; 221. Buried part; 222. Overflow part;

[0054] 300, Gate insulation layer; 400, Gate electrode; 500, Sidewall; 600, Cap; 700, Metal layer;

[0055] 10. Wafer; 20. Reaction chamber. Detailed Implementation

[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0057] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0058] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0059] See Figure 1 and Figure 2 As shown, the method for fabricating the semiconductor device in this embodiment includes:

[0060] S100: Fabricate a first wafer, the first wafer including a transistor, the transistor including a base layer and a target structure layer 200 formed on a first side of the base layer, the first side 101 of the base layer is provided with a receiving trench 110, and the target structure layer 200 is partially or entirely located in the receiving trench 110.

[0061] The base layer may include a substrate 100, meaning the target structure layer 200 can be directly formed on the substrate 100. The base layer may also include the substrate 100 and one or more functional layers formed on the substrate 100, with the target structure layer 200 formed on the functional layers away from the substrate 100. The target structure layer 200 can be formed using processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), with CVD including epitaxial growth. In this embodiment, the specific formation process of the target structure layer 200 is not limited.

[0062] S200: Based on the height of the upper surface of the target structure layer 200 relative to the first side 101, the target structure layer 200 is divided into a normal area 201 and an off-center area, the height of the off-center area being greater than or less than the height of the normal area 201.

[0063] It should be noted that in this embodiment, the height of the target structural layer 200 and the heights of its normal region 201 and deviation region all refer to the height relative to the first side 101. The upper surface of the target structural layer 200 may be higher or lower than the first side 101. When the upper surface of the target structural layer 200 is higher than the first side 101, the height of the upper surface of the target structural layer 200 relative to the first side 101 is a positive value; when the upper surface of the target structural layer 200 is lower than the first side 101, the height of the upper surface of the target structural layer 200 relative to the first side 101 is a negative value. The range of values ​​for the height of the upper surface of the target structural layer 200 relative to the first side 101 when the normal region 201 is a qualified semiconductor device. On the first wafer, the area of ​​the target structural layer 200 located in the normal region 201 is greater than or equal to 0.

[0064] S300: Based on the deviation of the height of the offset region on the first wafer from the height of the normal region 201, design the volume of the accommodating groove 110 corresponding to the offset region on the second wafer.

[0065] The first wafer is a wafer sample or a wafer produced in the previous batch, and the second wafer is a wafer die or a wafer produced in the subsequent batch. The height of the upper surface of the target structural layer 200 may be higher than the upper limit of the value range or lower than the lower limit of the value range. The volume of the corresponding offset region receiving groove 110 on the second wafer is designed accordingly, that is, the volume of the corresponding offset region receiving groove 110 on the second wafer is increased or decreased.

[0066] S400: Fabricate a second wafer, wherein at least a portion of the target structure layer 200 of the second wafer is fabricated using the same process conditions as a portion of the target structure layer 200 of the first wafer.

[0067] The same process conditions include the same film-forming equipment, the same process method, and the same process parameters, but are not limited to these, as long as the target structural layer 200 can be formed with the same morphology.

[0068] It should be noted that the target structural layer 200 can be a single structural layer formed by one process, or it can be two or more structural layers formed by two or more processes. At least the portion of the target structural layer 200 on the second wafer and the portion of the target structural layer 200 on the first wafer are fabricated using the same process conditions. That is, when the target structural layer 200 includes two or more structural layers, at least one of the structural layers is fabricated using the same process conditions.

[0069] In the fabrication of existing semiconductor devices, the substrate 100 or one or more functional layers on the substrate 100 are limited by the groove structure of the receiving groove, and the fabrication process of the target structural layer 200. The film thickness of the target structural layer 200 is inconsistent, which leads to a decrease in the yield of semiconductor devices.

[0070] The semiconductor device fabrication method in this embodiment includes: fabricating a first wafer, the first wafer including a base layer and a target structure layer 200, a receiving groove 110 provided on a first side 101 of the base layer, and the target structure layer 200 partially or entirely located within the receiving groove 110; dividing the target structure layer 200 into a normal region 201 and an off-center region according to the height of the upper surface of the target structure layer 200 relative to the first side 101; designing the volume of the receiving groove 110 corresponding to the off-center region on a second wafer according to the height of the off-center region of the target structure layer 200 on the first wafer; and then fabricating the second wafer using the same process conditions. Since the target structure layer 200 of the first wafer and the second wafer are fabricated using the same process conditions, their volume distributions are approximately equal. By increasing or decreasing the volume of the receiving groove 110 corresponding to the off-center region on the second wafer, the height of the upper surface of the target structure layer 200 can be controlled, so that almost all areas of the target structure layer 200 are within the value range of the normal region 201, thereby improving the film thickness uniformity of the target structure layer 200 and thus improving the yield of the semiconductor device.

[0071] In some embodiments, the target structural layer 200 is partially located within the receiving groove 110. The target structural layer 200 includes a buried portion 221 and an overflow portion 222. The buried portion 221 is embedded in the base layer, and the overflow portion 222 is exposed on a first side 101 of the base layer. The height of the target structural layer 200 relative to the first side 101 is equal to the thickness of the overflow portion 222.

[0072] The target structural layer 200 includes a buried portion 221 and an overflow portion 222. The buried portion 221 fills the receiving groove 110. At this time, by increasing or decreasing the volume of the receiving groove 110 on the second wafer, the thickness of the overflow portion 222 can be controlled more precisely.

[0073] In some embodiments, the offset region includes a thinner region 202, and the volume of the accommodating groove 110 corresponding to the offset region on the second wafer includes:

[0074] Reduce the volume of the accommodating groove 110 corresponding to the thinner region 202 on the second wafer.

[0075] In addition, the offset region also includes an overly thick region 203, and the volume of the corresponding accommodating groove 110 on the second wafer for the offset region includes:

[0076] Increase the volume of the accommodating groove 110 on the second wafer corresponding to the thicker region 203.

[0077] Since the target structural layer 200 of the first wafer and the second wafer are fabricated using the same process conditions, their volume distributions are approximately equal. For the thinner region 202 of the target structural layer 200, reducing the volume of the receiving groove 110 corresponding to the thinner region 202 when fabricating the second wafer can reduce the volume of the buried portion 221 of the corresponding thinner region 202 of the target structural layer 200, thereby increasing the thickness of the overflow portion 222 of the corresponding thinner region 202 of the target structural layer 200; for the thinner region 202 of the target structural layer 200... In the thick region 203, by increasing the volume of the accommodating trench 110 corresponding to the thin region 202 during the fabrication of the second wafer, the volume of the buried portion 221 of the corresponding thin region 202 of the target structural layer 200 can be increased, thereby reducing the thickness of the overflow portion 222 of the corresponding thick region 203 of the target structural layer 200. This improves the uniformity of the thickness of the overflow portion 222, ensuring that almost all areas of the target structural layer 200 of the second wafer are within the value range of the normal region 201, thereby improving the yield of the semiconductor device.

[0078] In some embodiments, when at least the thinner region 202 of the target structural layer 200 is 0 and the thicker region 203 is not 0, before the volume of the accommodating trench 110 corresponding to the deviation region on the corresponding second wafer, the method of fabricating a semiconductor device includes: reducing the thickness of the target structural layer 200 formed when fabricating the second wafer, and then dividing the normal region 201 and the deviation region according to the target structural layer 200 to be formed.

[0079] At least the thinner region 202 of the target structural layer 200 of the first wafer is 0, that is, the target structural layer 200 has a normal region 201 and a thicker region 203, or the target structural layer 200 is thick overall. In this case, the time to form the target structural layer 200 when making the second wafer can be reduced, so as to reduce the thickness of the target structural layer 200. Then, according to the target structural layer 200 to be formed, the normal region 201 and the deviation region are divided, and the thickness of the overflow portion 222 is adjusted by adjusting the volume of the receiving groove 110, so as to reduce the thickness of the overflow portion 222 of the corresponding thicker region 203 of the target structural layer 200, so that almost all areas of the target structural layer 200 are within the value range of the normal region 201.

[0080] Accordingly, when the thicker region 203 of the target structure layer 200 of the first wafer is 0 and the thinner region 202 is not 0, before the volume of the accommodating trench 110 corresponding to the offset region on the corresponding second wafer, the method of fabricating the semiconductor device includes: increasing the thickness of the target structure layer 200 formed when fabricating the second wafer.

[0081] At least the thicker region 203 of the target structural layer 200 is 0, that is, the target structural layer 200 has a normal region 201 and a thinner region 202, or the target structural layer 200 is thin overall. In this case, the time for forming the target structural layer 200 when making the second wafer can be increased to increase the thickness of the target structural layer 200. Then, the normal region 201 and the deviation region are divided according to the target structural layer 200 to be formed. The thickness of the overflow portion 222 is adjusted by adjusting the volume of the receiving groove 110 to increase the thickness of the overflow portion 222 corresponding to the thinner region 202 of the target structural layer 200, so that almost all areas of the target structural layer 200 are within the value range of the normal region 201.

[0082] It should be noted that the thickness of the target structure layer 200 is mainly affected by the formation time of the target structure layer 200. The thickness of the target structure layer 200 can be adjusted by increasing or decreasing the formation time of the target structure layer 200, but it is not limited to this. The thickness of the target structure layer 200 can also be adjusted by adjusting the temperature, the flow rate of the reaction gas, etc., depending on the specific situation.

[0083] By employing the aforementioned methods, the adjustment ratio of the receiving groove 110 in the thicker region 203 and the thinner region 202 is reduced, thereby lowering the technological difficulty of adjusting the size of the receiving groove 110. For example, when the size change of the receiving groove 110 is small, the difficulty of controlling the etching process for forming the receiving groove 110 is reduced.

[0084] For example, to achieve higher performance, semiconductor devices are evolving towards smaller feature sizes and higher device densities. Consequently, the gates of metal-oxide-semiconductor (MOS) transistors are becoming increasingly thinner and shorter than ever before, impacting the electrical performance of semiconductor devices. Simultaneously, due to the inherent properties of silicon, the speed of silicon-based devices is approaching its physical limits.

[0085] Using embedded silicon germanium (Embedded SiGe) technology to fabricate P-type metal-oxide-semiconductor transistors (PMOS, hereinafter referred to as P-type transistors) can enhance the carrier mobility of P-type transistors, thereby greatly improving the performance of P-type transistors and P-type transistor semiconductor devices.

[0086] See Figure 4In the illustrated embodiment, the P-type transistor semiconductor device is fabricated using embedded silicon-germanium technology. The P-type transistor semiconductor device includes a channel located in a substrate 100, a silicon-germanium body (SiGe) serving as the source and drain, and a gate. The substrate 100 is a single-crystal material. The gate includes a gate insulating layer 300 and a gate electrode 400. Optionally, the gate also includes sidewalls 500. Optionally, the PMOS also includes a cap 600 and a metal layer 700. The gate electrode 400 is formed on a first side 101 of the substrate 100, the gate insulating layer 300 is formed between the gate electrode 400 and the substrate 100, and the sidewalls 500 are formed on both sides of the gate electrode 400. Receiving trenches 110 serving as source-drain trenches are formed on the substrate 100 on both sides of the gate, i.e., on both sides of the gate electrode 400 and its sidewalls 500.

[0087] For example, the accommodating trench 110 is created by anisotropic wet etching. Since the substrate 100 or the functional material layer on the substrate 100, i.e., the base layer, is a single-crystal material, and different crystal orientations have different etching rates under the same etchant, polygonal source / drain trenches are created. Figure 4 In the illustrated embodiment, the source / drain trench is a convex hexagonal trench, commonly referred to as a Sigma trench, and the silicon-germanium body is at least partially formed within the convex hexagonal trench. In other embodiments, depending on the crystal orientation of the substrate 100, the source / drain trench may also be formed as a rectangular trench, i.e., the sidewalls of the source / drain trench are perpendicular to the bottom surface.

[0088] A cap 600 is formed on the side of the silicon-germanium body away from the substrate 100, and a metal layer 700 is formed on the side of the cap 600 and the gate electrode 400 away from the substrate 100. The cap 600 is, for example, a highly doped single-crystal silicon layer, with dopants including, for example, boron. The metal layer 700 is made of, for example, at least one of refractory metals such as nickel (Ni), tungsten (W), and titanium (Ti). Optionally, the metal layer 700 undergoes a silicide reaction with the cap 600 and the gate electrode 400, which is made of polycrystalline silicon, to form a metal silicide, thereby improving the contact between the metal and the source / drain regions and the gate electrode. In other embodiments, the metal layer 700 is in direct contact with the target structure layer 200 and undergoes a silicide reaction to form a metal silicide.

[0089] In fabricating a P-type transistor semiconductor device, a gate insulating layer 300, a gate electrode 400, and a sidewall 500 can be formed on a substrate 100 first, then a convex hexagonal trench and a silicon-germanium body can be formed, and finally a cap 600 and a metal layer 700 can be formed. The silicon-germanium body can be formed using an epitaxial growth process.

[0090] See Figure 5As shown, wafer 10 is placed in the reaction chamber 20 of the epitaxial growth equipment. Reaction gas is introduced from one side of the first direction and flows out from the other side. Due to the influence of various conditions such as reaction temperature, temperature field, gas flow rate, and gas flow field, the silicon-germanium bulk film thickness uniformity is poor. This variation is particularly pronounced at the edge region of wafer 10. Some epitaxial growth equipment allows the introduction of a small amount of reaction gas along a second direction, perpendicular to the first direction. However, introducing reaction gas along the second direction can only improve the silicon-germanium bulk film thickness uniformity at the edge region of wafer 10 to a certain extent.

[0091] The applicant discovered that when the height of the upper surface of the silicon-germanium body is too low—for example, when its epitaxial height is lower than the first side 101 of the substrate 100; or when the silicide reaction between the metal layer 700 and the target structure layer 200 consumes a significant amount of the target structure layer 200 thickness, resulting in the upper surface of the target structure layer 200 being lower than the first side 101 of the substrate 100 after the silicide reaction; or when the silicide reaction between the metal layer 700 and the cap 600 consumes all of the cap 600 and further consumes excessive amounts of the target structure layer 200 thickness, resulting in the upper surface of the target structure layer 200 being lower than the first side 101 of the substrate 100 after the silicide reaction—metal ions in the metal layer 700 easily diffuse into the channel between adjacent silicon-germanium bodies, leading to a decrease in the yield of the P-type transistor semiconductor device. Besides the aforementioned situation where the upper surface of the target structure layer 200 is lower than the first side 101 of the substrate 100, insufficient thickness of the overflow portion 222 also causes metal ions in the metal layer 700 to easily diffuse into the channel between adjacent silicon-germanium bodies.

[0092] In this embodiment, the semiconductor device fabrication method is used to fabricate a P-type transistor semiconductor device. The receiving trench 110 is a convex hexagonal trench, and the target structure layer 200 includes a silicon-germanium body. The transistor includes a gate located on the first side 101 of the substrate 100, with gaps formed between adjacent gates. The overflow portion 222 of the silicon-germanium body is located within the gap between adjacent gates. The target structure layer 200 includes a silicon-germanium body, and the lower limit of the value range of the normal region 201 of the target structure layer 200 is greater than 0, meaning the thickness of the overflow portion 222 is greater than 0. It can be understood that when the height of the upper surface of the target structure layer 200 relative to the first side 101 is outside the value range of the normal region 201, it is considered an offset region.

[0093] The silicon-germanium body of the P-type transistor semiconductor device is fabricated using the semiconductor device fabrication method in this embodiment. This ensures that the upper surface of the silicon-germanium body is uniformly higher than the first side 101 of the substrate 100, avoids the overflow portion 222 being too thin, and allows metal ions in the metal layer 700 to diffuse into the channel between adjacent silicon-germanium bodies, thereby improving the yield of the P-type transistor semiconductor device.

[0094] See Figure 2 and Figure 4As shown, the silicon-germanium body includes a seed layer 210 and an epitaxial layer 220. The seed layer 210 is formed on the inner sidewall of the receiving trench 110, and the epitaxial layer 220 is formed inside the seed layer 210 and outside the receiving trench 110. The epitaxial layer 220 is formed using an epitaxial growth process, and at least the epitaxial layer 220 of the second wafer and the epitaxial layer 220 of the first wafer are fabricated using the same process conditions. The overflow portion 222 is the portion of the epitaxial layer 220 located outside the receiving trench 110, and the buried portion 221 includes the portion of the epitaxial layer 220 located inside the receiving trench 110 and the seed layer 210.

[0095] Since the volume of the epitaxial layer 220 in the silicon-germanium body is larger than the volume of the seed layer 210, the epitaxial layer 220 of the second wafer and the epitaxial layer 220 of the first wafer are fabricated using the same process conditions, which can ensure that the volume distribution of the silicon-germanium body remains approximately unchanged.

[0096] See Figure 1 and Figure 2 As shown, the volume of the accommodating trench 110 corresponding to the offset region on the second wafer includes:

[0097] When fabricating the second wafer, set the thickness H_bulk1 of the overflow portion 222 corresponding to the deviation region;

[0098] Calculate the cross-sectional area S_bulk1 of the overflow portion 222 in the direction of the gap extension between adjacent gates based on the thickness H_bulk1 of the overflow portion 222.

[0099] Based on the cross-sectional area S_SiGe of the silicon-germanium body in the direction of the gap between adjacent gates and the cross-sectional area S_bulk1 of the overflow portion 222, the cross-sectional area S_Trench1 of the accommodating trench 110 on the second wafer in the direction of the gap between adjacent gates is calculated.

[0100] The silicon-germanium bodies on the first wafer and the second wafer are fabricated using the same process conditions, and their volume distributions are approximately equal. By adjusting the volume of the accommodating trench 110 corresponding to the deviation region, the thickness H_bulk1 of the overflow portion 222 can be adjusted to fall within the value range of the normal region 201. The cross-sectional area S_Trench1 of the accommodating trench 110 is equal to the cross-sectional area of ​​the buried portion 221, and the cross-sectional area S_Trench1 of the accommodating trench 110 can be calculated based on the cross-sectional area S_bulk1 of the overflow portion 222. The length of the accommodating trench 110 along the direction of the gap between adjacent gates is almost constant; therefore, the volume of the accommodating trench 110 is determined by its cross-sectional area.

[0101] In this embodiment, the receiving groove 110 is a convex hexagonal groove, comprising an upper isosceles trapezoidal region away from the substrate 100 and a lower isosceles trapezoidal region close to the substrate 100. The formula for calculating the cross-sectional area S_Trench of the receiving groove 110 is:

[0102]

[0103] Wherein, OP is the width of the gap between gates, that is, the upper side length of the cross-section of the accommodating trench 110, BCD is the lower side length of the cross-section of the accommodating trench 110, S2G is the width of the sidewall 500, T2G is the distance between the accommodating trench 110 and the gate electrode 400 in the direction of the gap width between adjacent gates, RCD is the depth of the accommodating trench 110, and SMD is the height of the upper isosceles trapezoidal region.

[0104] Based on the above formula for calculating the cross-sectional area of ​​the accommodating groove 110, the cross-sectional area S_Trench0 of the accommodating groove 110 of the first wafer can be calculated. Similarly, the dimensions such as the depth RCD of the accommodating groove 110 can be calculated based on the cross-sectional area S_Trench1 of the accommodating groove 110 of the second wafer, for the following reasons:

[0105] Since the sidewalls 500 are almost not etched during the etching process of the accommodating trench 110, the width OP of the gap between adjacent gates remains almost unchanged before and after the etching of the accommodating trench 110. The accommodating trench 110 is formed by etching the upper surface of the substrate 100 exposed by adjacent gates. The etching method is, for example, anisotropic wet etching. Since the substrate 100 or the functional material layer on the substrate 100, i.e., the base layer, is a single crystal material, when using anisotropic wet etchants, such as TMAH, the etching rates of substrates 100 with different crystal orientations differ greatly under the same etchant, thus producing a polygonal structure accommodating trench 110. Figure 2 In the illustrated embodiment, the accommodating trench 110 is a convex hexagon, and the tilt angle of each side of the convex hexagon is related to the crystal orientation, that is, it has a fixed tilt angle relative to the surface of the substrate 100. According to the above geometric relationship, the lower side length BCD of the cross-section of the accommodating trench 110, the width S2G of the sidewall 500, the distance T2G between the accommodating trench 110 and the gate electrode 400 in the gap width direction between adjacent gates, the depth RCD of the accommodating trench 110, and the height SMD of the upper isosceles trapezoidal region are all relevant dimensions. The etching depth RCD of the accommodating trench 110 can be calculated based on the cross-sectional area S_Trench1 of the accommodating trench 110 of the second wafer.

[0106] In summary, by setting the thickness H_bulk1 of the overflow portion 222 during the fabrication of the second wafer, and calculating the cross-sectional area S_Trench1 of the accommodating trench 110 based on the thickness H_bulk1 of the overflow portion 222, the etching depth RCD of the accommodating trench 110 can be further calculated. The accommodating trench 110 is then etched based on the etching depth RCD. For example, by controlling the etching time, etchant concentration distribution, and regional etching, the etching depth can be controlled, thereby increasing the distribution range of silicon germanium in the normal region 201 and thus improving the yield of P-type transistor semiconductor devices.

[0107] In some embodiments, the cross-sectional area S_bulk1 of the overflow portion 222 is:

[0108]

[0109] For the first wafer, OP is the width of the gap between adjacent gates, and α is the apex angle of the overflow portion 222. When at least the epitaxial layer 220 in the target structure layer 200 is fabricated using an epitaxial process, the crystal orientation of the epitaxial layer 220 can be related to the crystal orientation of the substrate 100. Therefore, the apex angle α of the formed epitaxial layer 220 is a fixed value related to the crystal orientation of the substrate 100. In other embodiments, the apex angle α of the epitaxial layer 220 can vary due to the deposition process or other adjustment means. This invention does not specifically limit this, but it is understood that the same apex angle α should be produced under the same process conditions.

[0110] The silicon-germanium body of the first wafer and the silicon-germanium body of the second wafer are fabricated using the same process conditions. The apex angles of the overflow portion 222 of the two wafers are approximately equal. Therefore, the cross-sectional area S_bulk1 of the overflow portion 222 can be calculated based on the thickness H_bulk1 of the overflow portion 222 set when fabricating the second wafer.

[0111] For example, the cross-sectional area S_Trench1 of the receiving slot 110 is:

[0112] S_Trench1 = S_SiGe - S_bulk1.

[0113] The cross-sectional area S_Trench1 of the receiving groove 110 is calculated by subtracting the cross-sectional area S_bulk1 of the overflow part 222 from the cross-sectional area S_SiGe of the silicon-germanium bulk, which is a simpler calculation method.

[0114] In some embodiments, the cross-sectional areas S_Trench1 and L_Trench1 of the receiving groove 110 of the second wafer conform to the following formula:

[0115]

[0116] Wherein, L_Trench0 is the cross-sectional perimeter of the accommodating trench corresponding to the offset region of the first wafer in the direction of the gap between adjacent gates, and L_Trench1 is the cross-sectional perimeter of the accommodating trench corresponding to the offset region of the second wafer in the direction of the gap between adjacent gates.

[0117] By substituting the formulas relating the cross-sectional perimeters L_Trench and S_Trench to the side lengths, as well as the values ​​of S_SiGe, S_bulk1, and L_Trench0, into the formula for calculating the cross-sectional area S_Trench1 of the second wafer's accommodating trench 110, the etching depth RCD of the accommodating trench 110 can be calculated. Etching the accommodating trench 110 according to the etching depth RCD can improve the distribution range of silicon-germanium bodies within the value range of the normal region 201, thereby improving the yield of P-type transistor semiconductor devices.

[0118] Since the perimeter of the receiving groove 110 changes with its cross-sectional area, and the perimeter of the receiving groove 110 affects the overall epitaxial growth rate—that is, the longer the perimeter of the receiving groove 110, the larger the epitaxial area of ​​the target structural layer 200 in the receiving groove 110 during the epitaxial process, and the larger the volume of the generated target structural layer 200 under the same epitaxial process time—it is necessary to consider the impact of the change in the perimeter of the receiving groove 110 when calculating its cross-sectional area S_Trench1. Obtaining a corrected S_Trench1 can further improve the accuracy of the calculation of the cross-sectional area of ​​the receiving groove 110.

[0119] In some embodiments, the perimeter L_Trench of the accommodating trench 110 in the direction of the gap between adjacent gates is calculated using the following perimeter calculation formula:

[0120]

[0121] Both the cross-sectional perimeter L_Trench0 and the cross-sectional perimeter L_Trench1 are calculated using the above perimeter calculation formula.

[0122] Although the receiving groove 110 is a convex hexagonal groove, the seed layer 210 is formed on the inner wall of the receiving groove 110. When the epitaxial layer 220 grows, it grows from the inside of the seed layer 210 to the outside of the receiving groove 110. Since the seed layer 210 does not exist at the opening of the receiving groove 110, that is, at the top of the cross-section, only the bottom and sides of the receiving groove 110 affect the volume change rate of the epitaxial growth of the epitaxial layer 220. Therefore, when calculating the perimeter of the cross-section of the receiving groove 110, its top side is not included, which can further improve the accuracy of the calculation of the cross-sectional area of ​​the receiving groove 110.

[0123] In some embodiments, the volume of the accommodating groove 110 corresponding to the offset region on the second wafer includes:

[0124] Calculate the cross-sectional perimeter L_Trench1 of the accommodating groove 110 based on its cross-sectional area S_Trench1, and calculate the cross-sectional perimeter L_Trench0 of the accommodating groove 110 of the first wafer.

[0125] Substitute the cross-sectional perimeter L_Trench1 and cross-sectional perimeter L_Trench0 into the calculation formula for the cross-sectional area S_Trench1 of the receiving groove 110 to calculate the expected cross-sectional area S_bulk1 of the overflow part.

[0126] When the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements, the receiving groove 110 is formed according to the cross-sectional area S_Trench1 of the receiving groove 110. When the expected cross-sectional area S_bulk1 of the overflow portion does not meet the design requirements, the thickness H_bulk1 of the overflow portion and the corresponding cross-sectional area S_bulk1 of the overflow portion are redesigned until the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements.

[0127] In this embodiment, the cross-sectional perimeter L_Trench1 and cross-sectional perimeter L_Trench0 are substituted into the calculation formula of the cross-sectional area S_Trench1 of the receiving groove to calculate the expected cross-sectional area S_bulk1 of the overflow part, and then it is simpler to verify whether the expected cross-sectional area S_bulk1 of the overflow part meets the design requirements, thus obtaining the cross-sectional area S_Trench1 of the receiving groove 110 and the corresponding etching depth RCD.

[0128] In some embodiments, when adjusting the cross-sectional area of ​​the receiving groove 110 according to the above method, a small adjustment of the cross-sectional area of ​​the receiving groove 110 can improve the height uniformity of the overflow portion.

[0129] In other embodiments, the receiving groove 110 is rectangular in shape, and the present invention still applies, only the geometric formulas for calculating the area and perimeter are different. In this embodiment, the depth of the groove and the width of the lateral opening need to be changed according to the etching principle. It can be understood that a large difference in etching rate between different crystal orientations can lead to negligible etching on the surfaces of the receiving groove 110 corresponding to some crystal orientations.

[0130] This application also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method disclosed above.

[0131] In this embodiment, during semiconductor device fabrication, a first wafer is first fabricated. The first wafer includes a base layer and a target structure layer 200. A receiving groove 110 is provided on the first side 101 of the base layer. The target structure layer 200 is partially or entirely located within the receiving groove 110. Based on the height of the upper surface of the target structure layer 200 relative to the first side 101, the target structure layer 200 is divided into a normal region 201 and an off-center region. The volume of the receiving groove 110 on the second wafer corresponding to the off-center region is designed according to the height of the off-center region of the target structure layer 200 on the first wafer. The second wafer is then fabricated using the same process conditions. Since the target structure layer 200 of the first and second wafers is fabricated using the same process conditions, their volume distributions are approximately equal. By increasing or decreasing the volume of the receiving groove 110 on the second wafer, the height of the upper surface of the target structure layer 200 can be controlled, ensuring that almost all areas of the target structure layer 200 are within the value range of the normal region 201. This improves the film thickness uniformity of the target structure layer 200, thereby increasing the yield of the semiconductor device.

[0132] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0133] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0134] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0135] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Fabricating a first wafer, the first wafer being a wafer sample, the first wafer including a transistor, the transistor including a base layer and a target structure layer formed on one side of the base layer, a receiving trench provided on a first side of the base layer, the target structure layer being partially or entirely located within the receiving trench, the target structure layer including a silicon-germanium body, the transistor including a gate located on the first side, a gap being formed between adjacent gates, an overflow portion of the silicon-germanium body located in the gap between adjacent gates, the silicon-germanium body including a seed layer and an epitaxial layer, the seed layer being formed on the inner sidewall of the receiving trench, the epitaxial layer being formed within the seed layer and outside the receiving trench, the epitaxial layer being formed using an epitaxial growth process; Based on the height of the upper surface of the target structure layer relative to the first side, the target structure layer is divided into a normal area and an off-center area, wherein the height of the off-center area is greater than or less than the height of the normal area; Based on the deviation of the height of the offset region on the first wafer from the height of the normal region, the volume of the accommodating groove on the second wafer corresponding to the offset region is designed accordingly, and the second wafer is a positive wafer. The second wafer is fabricated using the same process conditions as the epitaxial layer of the first wafer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The target structural layer is partially located within the receiving groove, which is a rectangular groove or a convex hexagonal groove. The target structural layer includes a buried portion and an overflow portion. The buried portion is embedded within the base layer, and the overflow portion is exposed on the first side. The height of the target structural layer relative to the first side is equal to the thickness of the overflow portion. The overflow portion is the portion of the epitaxial layer located outside the receiving groove. The buried portion includes the portion of the epitaxial layer located inside the receiving groove and the seed layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The volume of the accommodating groove on the second wafer corresponding to the offset region includes: When fabricating the second wafer, the thickness H_bulk1 of the overflow portion corresponding to the deviation region is set; Calculate the cross-sectional area S_bulk1 of the overflow portion in the direction of the gap between adjacent gates based on the thickness H_bulk1 of the overflow portion; Based on the cross-sectional area S_SiGe of the silicon-germanium body in the direction of the gap between adjacent gates and the cross-sectional area S_bulk1 of the overflow portion, the cross-sectional area S_Trench1 of the accommodating trench on the second wafer in the direction of the gap between adjacent gates is calculated.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The receiving groove is a convex hexagonal groove, and the cross-sectional area S_bulk1 of the overflow portion is: ； Wherein, OP is the width of the gap between adjacent gates, and α is the apex angle of the overflow portion.

5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The cross-sectional area S_Trench1 of the receiving groove is: 。 6. The method for fabricating a semiconductor device according to claim 3, characterized in that, The cross-sectional areas S_Trench1 and L_Trench1 of the receiving groove conform to the following formula: ； Wherein, L_Trench0 is the cross-sectional perimeter of the accommodating groove corresponding to the offset region of the first wafer in the direction of the gap between adjacent gates, and L_Trench1 is the cross-sectional perimeter of the accommodating groove corresponding to the offset region of the second wafer in the direction of the gap between adjacent gates.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The gate includes a gate electrode and a sidewall located between the gate electrode and the receiving groove. The receiving groove is a convex hexagonal groove. The perimeter L_Trench of the receiving groove in the direction of extension of the gap between adjacent gates is calculated by the following perimeter calculation formula: ； Wherein, BCD is the lower side length of the cross-section of the receiving groove, S2G is the width of the sidewall, T2G is the distance between the receiving groove and the gate electrode in the gap width direction between adjacent gates, RCD is the depth of the receiving groove, the receiving groove includes an upper isosceles trapezoidal region away from the base layer and a lower isosceles trapezoidal region close to the base layer, and SMD is the height of the upper isosceles trapezoidal region; Both the cross-sectional perimeter L_Trench0 and the cross-sectional perimeter L_Trench1 are calculated using the perimeter calculation formula.

8. The method for fabricating a semiconductor device according to claim 6, characterized in that, The volume of the accommodating groove on the second wafer corresponding to the offset region includes: Calculate the cross-sectional perimeter L_Trench1 of the receiving groove based on its cross-sectional area S_Trench1, and calculate the cross-sectional perimeter L_Trench0 of the receiving groove of the first wafer. Substitute the cross-sectional perimeter L_Trench1 and the cross-sectional perimeter L_Trench0 into the calculation formula for the cross-sectional area S_Trench1 of the receiving groove to calculate the expected cross-sectional area S_bulk1 of the overflow portion. When the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements, the receiving groove is formed according to the cross-sectional area S_Trench1 of the receiving groove. When the expected cross-sectional area S_bulk1 of the overflow portion does not meet the design requirements, the thickness H_bulk1 of the overflow portion and the corresponding cross-sectional area S_bulk1 of the overflow portion are redesigned until the expected cross-sectional area S_bulk1 of the overflow portion meets the design requirements.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The deviation region includes a thinner region, and the volume of the accommodating groove on the second wafer corresponding to the deviation region includes: reducing the volume of the accommodating groove on the second wafer corresponding to the thinner region; Alternatively, the deviation region may include a thicker region, and the volume of the accommodating groove on the second wafer corresponding to the deviation region may include: increasing the volume of the accommodating groove on the second wafer corresponding to the thicker region.

10. The method for fabricating a semiconductor device according to claim 1, characterized in that, The deviation region includes a thicker region and a thinner region, and the formation process of the target structural layer includes chemical vapor deposition or physical vapor deposition; before the volume of the accommodating trench corresponding to the deviation region on the corresponding second wafer, the following steps are performed: When the thinnest region of the target structural layer of at least the first wafer is 0, the method for fabricating the semiconductor device includes: Reduce the thickness of the target structure layer formed during the fabrication of the second wafer, and then divide the normal region and the deviation region according to the target structure layer to be formed; When the thickness region of the target structural layer of at least the first wafer is 0, the method of fabricating the semiconductor device includes: Increase the thickness of the target structure layer formed during the fabrication of the second wafer, and then divide the normal region and the deviation region according to the target structure layer to be formed; The method for adjusting the thickness of the target structure layer formed during the fabrication of the second wafer includes adjusting the time for forming the target structure layer, the reaction temperature for forming the target structure layer, and the flow rate of the reaction gas.

11. A semiconductor device, characterized in that, The semiconductor device is manufactured using the semiconductor device manufacturing method as described in any one of claims 1 to 10.

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