A Gallium Nitride transistor based on a polysilicon field plate and a preparation method thereof

Abstract

The present invention relates to a gallium nitride transistor based on a polysilicon field plate and a preparation method thereof, belonging to the technical field of semiconductor devices. The transistor includes a substrate, a GaN buffer layer, a GaN channel layer, an AlN interlayer, and an AlGaN barrier layer which are sequentially arranged from bottom to top. A P-GaN cap layer and a first passivation layer are arranged on the upper side of the AlGaN barrier layer. A gate metal field plate is arranged on the upper side of the P-GaN cap layer. A second passivation layer is arranged on the upper sides of the gate metal field plate and the first passivation layer. Source metal and drain metal are respectively arranged on both sides of the GaN buffer layer. Grooves are arranged on the first passivation layer and the second passivation layer, and the bottom of the grooves penetrates through to the AlGaN barrier layer. A polysilicon field plate is arranged on the upper side of the source metal, the upper side of the second passivation layer, and in the grooves. By introducing the polysilicon field plate, the present invention suppresses interface charges and significantly improves the electrical performance of the device.

Description

Technical Field

[0001] The present invention relates to a gallium nitride transistor based on a polysilicon field plate and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] As the performance of Si-based materials gradually approaches the theoretical limit, the third-generation semiconductors represented by GaN are gradually coming to the center of the semiconductor world stage. GaN materials have a series of excellent electrical characteristics such as a high bandgap width, a high electron mobility, a high electron saturation velocity, and a high breakdown electric field, showing great application potential in the fields of high-frequency, high-power, and high-temperature electronic devices, being widely used in the fields of power electronics and microwave radio frequency, and also being one of the core key technologies in the 5G field.

[0003] However, existing HEMT devices are prone to be restricted by the breakdown voltage and affected by interface charges in a high-power and high-voltage environment, reducing the mobility, current performance, and breakdown voltage resistance. In device manufacturing, the process of forming a dielectric layer will introduce interface charges, such as PECVD plasma deposition, etc. Traditional HEMT devices usually adopt metal field plates, but this structure cannot remove the interfacial contamination charges, resulting in a significant reduction in the channel mobility and current. In contrast, a polysilicon field plate can deposit positive charges inside itself, thereby affecting and eliminating the interface charges between the oxide and the semiconductor, having a significant advantage in suppressing interface charges, and being able to maintain a high mobility and current performance while increasing the breakdown voltage of the device. Therefore, the application of using a polysilicon field plate to replace the metal field plate in high-power GaN HEMT devices has gradually attracted attention. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the present invention provides a gallium nitride transistor based on a polysilicon field plate, which suppresses interface charges and significantly improves the electrical performance of the device by introducing the polysilicon field plate.

[0005] The present invention also provides a preparation method for the above-mentioned gallium nitride transistor based on a polysilicon field plate.

[0006] The technical solution of the present invention is as follows:

[0007] A gallium nitride transistor based on a polysilicon field plate, comprising a substrate, a GaN buffer layer, a GaN channel layer, an AlN interlayer, and an AlGaN barrier layer arranged in sequence from bottom to top. A P-GaN cap layer and a first passivation layer are arranged on the upper side of the AlGaN barrier layer. A gate metal field plate is arranged on the upper side of the P-GaN cap layer. A second passivation layer is arranged on the upper sides of the gate metal field plate and the first passivation layer. Source metal and drain metal are respectively arranged on both sides of the GaN buffer layer. Grooves are arranged on the first passivation layer and the second passivation layer, and the bottom of the grooves penetrates through to the AlGaN barrier layer. A polysilicon field plate is arranged on the upper side of the source metal, the upper side of the second passivation layer, and in the grooves.

[0008] Preferably according to the present invention, the substrate material is silicon carbide, silicon or sapphire;

[0009] The source metal and the drain metal are made of the same material, which is a metal stack of Ti / Al / Ni / Au, Ti / Al / Ti / Au or Ti / Al / Mo / Au;

[0010] The material of the gate metal field plate is a metal stack of Ni / Au;

[0011] The first passivation layer and the second passivation layer are made of the same material, which is SiN and SiO 2 .

[0012] Further preferably according to the present invention, the substrate material is silicon carbide;

[0013] The source metal and the drain metal are made of a metal stack of Ti / Al / Ni / Au;

[0014] The first passivation layer and the second passivation layer are made of SiO 2 .

[0015] Preferably according to the present invention, the thickness of the GaN buffer layer is 0.8 - 3 μm;

[0016] The thickness of the GaN channel layer is 10 - 300 nm;

[0017] The thickness of the AlN interlayer is 0.2 - 1.2 nm;

[0018] The thickness of the AlGaN barrier layer is 8 - 30 nm, wherein the molar ratio of Al is 10 - 26%;

[0019] The thickness of the p-GaN cap layer is 1 - 1000 nm, and the doping concentration is 1×10 17 -1×10 20 cm -3 , and the doping source is magnesium or boron;

[0020] The thickness of the first passivation layer is 50 - 400 nm;

[0021] The length of the gate metal field plate is 1 - 5 μm;

[0022] The thickness of the second passivation layer is 50 - 300 nm.

[0023] According to a further preference of the present invention, the thickness of the GaN buffer layer is 2 μm;

[0024] The thickness of the GaN channel layer is 200 nm;

[0025] The thickness of the AlN interlayer is 0.5 nm;

[0026] The thickness of the AlGaN barrier layer is 12.5 nm, wherein the molar ratio of Al is 18%;

[0027] The thickness of the p-GaN cap layer is 100 nm, and the doping concentration is 3×10 19 cm -3 ;

[0028] The thickness of the first passivation layer is 260 nm;

[0029] The length of the gate metal field plate is 2 μm;

[0030] The thickness of the second passivation layer is 100 nm.

[0031] According to the preference of the present invention, the gate-source spacing is 5 μm, the gate length is 2 μm, the gate-drain spacing is 13 μm, and the gate width is 100 μm.

[0032] The gate-source spacing is the distance from the gate electrode to the source electrode, the gate length is the length from the left end to the right end of the gate electrode, the gate-drain spacing is the distance from the gate electrode to the drain electrode, and the gate width is the side width of the gate electrode.

[0033] The preparation method of the above-mentioned gallium nitride transistor based on a polysilicon field plate is as follows:

[0034] S1. Grow a GaN buffer layer, a GaN channel layer, an AlN interlayer, an AlGaN barrier layer, and a p-GaN cap layer on the substrate in sequence;

[0035] S2. Dry-etch the p-GaN cap layer except for the position of the gate electrode;

[0036] S3. Remove the GaN channel layer, the AlN interlayer, and the AlGaN barrier layer outside the device by dry etching to form a mesa;

[0037] S4. Evaporate source metal and drain metal at the mesa position respectively;

[0038] S5. Anneal in the drain metal and source metal regions to form an ohmic contact;

[0039] S6. Deposit a first passivation layer over the P-GaN cap layer and the AlGaN barrier layer;

[0040] S7. Open holes in the first passivation layer in the gate electrode region by dry etching;

[0041] S8. Evaporate a gate metal field plate in the open hole region, and the gate metal field plate extends to the first passivation layer on one side;

[0042] S9. Deposit a second passivation layer over the gate metal field plate and the first passivation layer;

[0043] S10. Perform dry etching on the first passivation layer and the second passivation layer on one side of the gate electrode to form a groove;

[0044] S11. Grow a source polysilicon field plate on the upper side of the source metal, the upper side of the second passivation layer, and in the groove to complete the preparation.

[0045] Preferably according to the present invention, in step S1, the growth methods of the GaN buffer layer, the GaN channel layer, the AlN interlayer, the AlGaN barrier layer, and the p-GaN cap layer are high-quality film formation methods such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0046] Preferably according to the present invention, in steps S2, S3, S7, and S10, the dry etching method is inductively coupled plasma etching (ICP) or reactive ion etching (RIE).

[0047] Preferably according to the present invention, in steps S6 and S9, the deposition method is a high-quality film formation method such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD).

[0048] Preferably according to the present invention, in step S5, the annealing treatment method for the source metal and the drain metal is laser selective annealing.

[0049] The beneficial effects of the present invention are as follows:

[0050] 1. The introduction of the polysilicon field plate in the present invention effectively eliminates the interfacial contaminating charges, significantly improves the mobility and current performance of the device. Compared with the metal field plate, the polysilicon field plate device has a higher breakdown voltage, enhancing the stability and reliability of the device in high-voltage applications. Moreover, the polysilicon field plate has excellent interfacial charge handling ability, can maintain the interface stability in a high-power environment, reduce the performance degradation. At the same time, using polysilicon to replace the metal field plate effectively reduces the production defects and the scrap rate, reduces the overall manufacturing cost, reduces the problems of decline and damage of the device during long-term operation, and extends the service life of the device.

[0051] 2. In the present invention, the polysilicon field plate is embedded in the groove, the distance between the polysilicon field plate and the barrier layer is shortened, the polysilicon field plate is closer to the interface charges at these interfaces, and the coverage area is larger, which can more effectively offset the negative effects of the interface charges, reduce the carrier scattering caused by the interface charges, and improve the mobility of the channel electrons; improve the conduction performance, significantly enhance the current driving ability and response speed of the device. Moreover, since the polysilicon field plate is close to the barrier layer, the polysilicon field plate can more directly affect the electric field distribution near the barrier layer and effectively reduce the electric field peak value.

[0052] At the same time, the groove structure makes the coupling effect between the barrier layer and the polysilicon field plate stronger. This can not only neutralize the interface charges, but also reduce the possibility of new interface charges accumulating due to process or thermal stress. The interface charge problem is dynamic, and the embedded field plate design helps to maintain the interface stability in the long term.

[0053] The heat generated by the device during high-power operation needs to be effectively dissipated. The etched groove not only provides a better heat dissipation path for the polysilicon field plate, but also reduces the additional thermal resistance of the field plate, thereby enhancing the thermal stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a schematic structural diagram of the present invention;

[0055] Figure 2 is a comparison diagram of the mobility of the polysilicon field plate device of the present invention;

[0056] Figure 3 is a comparison diagram of the transfer curves (linear curves) of the polysilicon field plate device of the present invention;

[0057] Figure 4 is a comparison diagram of the transfer curves (logarithmic curves) of the polysilicon field plate device of the present invention;

[0058] Figure 5 is a comparison diagram of the output curves of the polysilicon field plate device of the present invention;

[0059] Figure 6 is a comparison diagram of the breakdown voltages of the polysilicon field plate devices of the present invention;

[0060] In the figure: 1. Substrate; 2. GaN buffer layer; 3. GaN channel layer; 4. AlN interlayer; 5. AlGaN barrier layer; 6. P-GaN cap layer; 7. First passivation layer; 8. Source metal; 9. Drain metal; 10. Polysilicon field plate; 11. Gate metal field plate; 12. Second passivation layer. DETAILED DESCRIPTION OF THE INVENTION

[0061] The present invention will be further described below by way of examples in conjunction with the drawings, but is not limited thereto.

[0062] Embodiment 1:

[0063] As shown in Figure 1 , this embodiment provides a gallium nitride transistor based on a polysilicon field plate, which includes a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlN interlayer 4, and an AlGaN barrier layer 5 arranged in sequence from bottom to top. A P-GaN cap layer 6 and a first passivation layer 7 are arranged on the upper side of the AlGaN barrier layer 5. A gate metal field plate 11 is arranged on the upper side of the P-GaN cap layer 6. A second passivation layer 12 is arranged on the upper sides of the gate metal field plate 11 and the first passivation layer 7. Source metal 8 and drain metal 9 are respectively arranged on both sides of the GaN buffer layer 2. Grooves are arranged on the first passivation layer 7 and the second passivation layer 12, and the bottom of the grooves penetrates through the AlGaN barrier layer 5. A polysilicon field plate 10 is arranged on the upper side of the source metal 8, the upper side of the second passivation layer 12, and in the grooves.

[0064] The material of the substrate 1 is silicon carbide; the material of the gate metal field plate 11 is a metal stack Ni / Au; the materials of the source metal 8 and the drain metal 9 are metal stacks Ti / Al / Ni / Au; the materials of the first passivation layer 7 and the second passivation layer 12 are SiO 2 .

[0065] The thickness of the GaN buffer layer 2 is 2 μm; the thickness of the GaN channel layer 3 is 200 nm; the thickness of the AlN interlayer 4 is 0.5 nm; the thickness of the AlGaN barrier layer 5 is 12.5 nm, where the molar ratio of Al is 18%; the thickness of the p-GaN cap layer 6 is 100 nm, and the doping concentration is 3×10 19 cm -3 ; the thickness of the first passivation layer 7 is 260 nm; the length of the gate metal field plate 11 is 2 μm; the thickness of the second passivation layer 12 is 100 nm.

[0066] The gate-source spacing is 5 μm, the gate length is 2 μm, the gate-drain spacing is 13 μm, and the gate width is 100 μm.

[0067] The preparation method of the above-mentioned gallium nitride transistor based on a polysilicon field plate is as follows:

[0068] S1. Grow a GaN buffer layer 2, a GaN channel layer 3, an AlN interlayer 4, an AlGaN barrier layer 5, and a p-GaN cap layer 6 on the substrate 1 in sequence;

[0069] S2. Dry-etch the p-GaN cap layer 6 except for the gate electrode position;

[0070] S3. Remove the GaN channel layer 3, the AlN interlayer 4, and the AlGaN barrier layer 5 outside the device by dry etching to form a mesa;

[0071] S4. Evaporate the source metal 8 and the drain metal 9 at the mesa position respectively;

[0072] S5. Anneal in the drain metal 9 and source metal 8 regions to form an ohmic contact;

[0073] S6. Deposit a first passivation layer 7 over the P-GaN cap layer 6 and the AlGaN barrier layer 5;

[0074] S7. Open a hole in the first passivation layer 7 in the gate electrode region by dry etching;

[0075] S8. Evaporate a gate metal field plate 11 in the opened hole region, and the gate metal field plate 11 extends to the first passivation layer 7 on one side;

[0076] S9. Deposit a second passivation layer 12 over the gate metal field plate 11 and the first passivation layer 7;

[0077] S10. Perform dry etching on the first passivation layer 7 and the second passivation layer 12 on one side of the gate electrode to form a groove;

[0078] S11. Grow a source polysilicon field plate 10 on the upper side of the source metal 8, the upper side of the second passivation layer 12, and in the groove to complete the preparation.

[0079] In step S1, the growth method of the GaN buffer layer 2, the GaN channel layer 3, the AlN interlayer 4, the AlGaN barrier layer 5, and the p-GaN cap layer 6 is metalorganic chemical vapor deposition (MOCVD).

[0080] In steps S2, S3, S7, and S10, the dry etching method is inductively coupled plasma etching (ICP).

[0081] In steps S6 and S9, the deposition method is a high-quality film-forming method such as low-pressure chemical vapor deposition (LPCVD).

[0082] In step S5, the annealing treatment method for the source metal and the drain metal is laser selective annealing.

[0083] In Sentaurus TCAD simulation, the performance of the device prepared in this embodiment is verified, and the steps are as follows:

[0084] (1) Simulation model construction: Construct a two-dimensional structure model in Sentaurus TCAD software;

[0085] (2) Simulation parameter setting: Set boundary conditions and initial conditions, including voltage and current, etc. For the transfer curve, first apply a drain voltage of 10 V, and then apply a varying gate voltage. For the output curve, increase the drain voltage from 0 V to 10 V at different gate voltages. For breakdown, first apply a gate voltage of -6 V to ensure depletion, and then apply a drain voltage until breakdown;

[0086] (3) Simulation process: Conduct simulation and observe the changes in electrical properties of the polysilicon field plate compared with the metal field plate.

[0087] (4) Result analysis: As can be seen from Figure 2 , the channel mobility of this embodiment has exceeded that of the traditional metal field plate by exactly one time, increasing from 1200 cm 2 / V·s to 2500 cm 2 / V·s. From Figure 3 , Figure 4 , Figure 5 , it can be found that the saturation current of this embodiment has increased significantly while the threshold voltage remains unchanged. In the Figure 6 breakdown curve, taking the critical breakdown field strength of 3.3 MV / cm of the GaN material as the discrimination criterion, the breakdown voltage of the polysilicon field plate device in this embodiment reaches 1050 V, which is better than 950 V of the traditional metal field plate. This shows that the polysilicon field plate plays an important role in eliminating interface charges, improving device stability, and optimizing device performance.

[0088] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A gallium nitride transistor based on a polysilicon field plate, characterized in that: It comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer and an AlGaN barrier layer which are sequentially arranged from bottom to top, a P-GaN cap layer and a first passivation layer are arranged on the upper side of the AlGaN barrier layer, a gate metal field plate is arranged on the upper side of the P-GaN cap layer, a second passivation layer is arranged on the upper side of the gate metal field plate and the first passivation layer, a source metal and a drain metal are arranged on both sides of the GaN buffer layer, a groove is arranged on the first passivation layer and the second passivation layer, the bottom of the groove penetrates to the AlGaN barrier layer, and a polysilicon field plate is arranged on the upper side of the source metal, the upper side of the second passivation layer and in the groove; The substrate material is silicon carbide; The source metal and drain metal are made of metal stack Ti / Al / Ni / Au; The materials of the first passivation layer and the second passivation layer are SiO2; The thickness of the GaN buffer layer is 0.8-3μm; The thickness of the GaN channel layer is 10-300nm; The thickness of the AlN intercalation layer is 0.2-1.2nm; The thickness of the AlGaN barrier layer is 8-30 nm, wherein the molar ratio of Al is 10-26%; The thickness of the p-GaN cap layer is 1-1000nm and the doping concentration is 1×10 17 -1×10 20 cm -3 , the doping source is magnesium or boron; The thickness of the first passivation layer is 50-400nm; The length of the gate metal field plate is 1-5μm; The thickness of the second passivation layer is 50-300 nm.

2. The gallium nitride transistor based on polysilicon field plate according to claim 1, characterized in that: The material of the gate metal field plate is a metal stack Ni / Au.

3. The gallium nitride transistor based on polysilicon field plate according to claim 1, characterized in that: The thickness of the GaN buffer layer is 2 μm; The thickness of the GaN channel layer is 200nm; The thickness of the AlN intercalation layer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, wherein the molar ratio of Al is 18%; The thickness of the p-GaN cap layer is 100 nm and the doping concentration is 3×10 19 cm -3 ; The thickness of the first passivation layer is 260nm; The length of the gate metal field plate is 2 μm; The thickness of the second passivation layer is 100 nm.

4. The gallium nitride transistor based on polysilicon field plate according to claim 1, characterized in that: The gate-source spacing is 5μm, the gate length is 2μm, the gate-drain spacing is 13μm, and the gate width is 100μm.

5. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to any one of claims 1 to 4, characterized in that: Here are the steps: S1, sequentially growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer and a p-GaN cap layer on a substrate; S2, dry etching the p-GaN cap layer except for the gate electrode position; S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa; S4, evaporating source metal and drain metal at the mesa position respectively; S5, annealing the drain metal and source metal regions to form ohmic contacts; S6, depositing a first passivation layer on the P-GaN cap layer and the AlGaN barrier layer; S7, opening a hole in the first passivation layer in the gate electrode region by dry etching; S8, evaporating a gate metal field plate in the opening area, wherein the gate metal field plate extends to the first passivation layer on one side; S9, depositing a second passivation layer over the gate metal field plate and the first passivation layer; S10, performing dry etching on the first passivation layer and the second passivation layer on one side of the gate electrode to form a groove; S11, growing a source polysilicon field plate on the upper side of the source metal, the upper side of the second passivation layer and in the groove to complete the preparation.

6. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to claim 5, characterized in that: In step S1 , the growth method of the GaN buffer layer, the GaN channel layer, the AlN intercalation layer, the AlGaN barrier layer and the p-GaN cap layer is metal organic chemical vapor deposition or molecular beam epitaxy.

7. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to claim 5, characterized in that: The dry etching method in step S2, step S3, step S7 and step S10 is inductively coupled plasma etching or reactive ion etching; The deposition method in step S6 and step S9 is plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

8. The method for preparing a gallium nitride transistor based on a polysilicon field plate according to claim 5, characterized in that: In step S5, the annealing method of the source metal and the drain metal is laser selective annealing.

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