Super junction mosfet device

Abstract

The application discloses a super-junction MOSFET device, a first contact hole on the top of a source region is directly composed of a material layer filled in a front metal layer of the first contact hole opening, the material of the front metal layer adopts AlSiCu, and the Si content in the AlSiCu reaches above a saturation value; the AlSiCu of the first contact hole directly forms an ohmic contact with the semiconductor material of the source region and a first epitaxial layer of a second conductive type well, the feature that the Si content in the AlSiCu reaches above the saturation value is utilized to prevent the formation of cusps defects when the AlCu directly contacts the semiconductor material of the first epitaxial layer; the feature that the resistivity of the AlSiCu is greater than that of the AlCu is utilized to increase the forward conduction voltage drop of a body diode and improve the reverse recovery characteristic of the device. The application can reduce the reverse recovery charge and improve the reverse recovery characteristic of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit, and in particular to a super junction MOSFET device. BACKGROUND

[0002] Compared with the traditional VDMOS, the super junction MOSFET has been widely used in various electronic power fields due to its excellent device characteristics. Due to the special mutual compensation of the N column and the P column in the super junction MOSFET structure, the area of the PN built-in electric field is expanded, so that it can achieve high breakdown voltage on a relatively thick NEPI epitaxial substrate. The super junction MOSFET thus has a low on-resistance and a high breakdown voltage beyond the Si limit.

[0003] The super junction MOSFET device mainly has two challenges, one is that the device process is relatively complex, and the other is that the device reverse recovery characteristic is poor. Due to the large PN junction area of the super junction MOSFET, the parasitic diode will inject more minority carrier charge when turned on; the lateral depletion speed of the N column and the P column is fast, which is easy to cause current overshoot. Therefore, the reverse recovery characteristic of the super junction MOSFE is characterized by large reverse recovery charge (large reverse recovery current and long reverse recovery time), hard reverse recovery curve, which ultimately increases the power consumption of the device and reduces the application reliability.

[0004] The main solution to improve the reverse recovery characteristic at present is to add a buffer layer at the bottom of the P column or the N column, so as to slow down the depletion speed of the N column and the P column, and obtain a soft reverse recovery characteristic, but this method often increases the reverse recovery charge. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a super junction MOSFET device which can reduce the reverse recovery charge and improve the reverse recovery characteristic of the device.

[0006] To solve the above technical problems, the super junction MOSFET device provided by the present application comprises:

[0007] A super junction structure formed in a first epitaxial layer doped with a first conductivity type, the super junction structure comprising first conductivity type columns and second conductivity type columns arranged alternately.

[0008] The first epitaxial layer at the bottom of the super junction structure serves as a buffer layer.

[0009] In the active region, a plurality of parallel device unit structures are formed in the top region of the super junction structure.

[0010] The device unit structure comprises a gate structure, a second conductivity type well, and a first conductivity type heavily doped source region.

[0011] The second conductive type well is formed in a top region of the second conductive type column and extends into the first conductive type column. The drift region includes the first conductive type column and the buffer layer located outside or at the bottom of the second conductive type well.

[0012] The surface of the second conductive type well covered by the gate structure is used to form a conductive channel connecting the source region and the drift region.

[0013] The body diode is a parasitic diode formed by the second conductive type well and the drift region.

[0014] The source region and the top of the second conductive type well are connected to the source metal composed of the front metal layer through a first contact hole; the first contact hole passes through the source region and contacts the second conductive type well.

[0015] The first contact hole is directly composed of a material layer of the front metal layer filling the opening of the first contact hole, and the material of the front metal layer is AlSiCu, and the Si content in AlSiCu reaches above the saturation value; the AiSiCu of the first contact hole directly forms an ohmic contact with the semiconductor material of the first epitaxial layer of the source region and the second conductive type well, and utilizes the characteristic that the Si content in AlSiCu reaches above the saturation value to prevent the formation of a sharp convex defect when the AlCu directly contacts the semiconductor material of the first epitaxial layer; utilizes the characteristic that the resistivity of AlSiCu is greater than the resistivity of AlCu to increase the forward conduction voltage drop of the body diode and improve the reverse recovery characteristics of the device.

[0016] A further improvement is that the gate structure includes a gate dielectric layer and a gate conductive material layer; the top of the gate conductive material layer is connected to the gate metal composed of the front metal layer through a second contact hole; and the second contact hole is directly composed of the material layer of the front metal layer filling the opening of the second contact hole.

[0017] A further improvement is that the gate structure is a planar gate or a trench gate.

[0018] A further improvement is that the second conductive type column includes a second conductive type doped second epitaxial layer filled in the super junction trench, and the first conductive type column includes the first epitaxial layer located between the super junction trenches.

[0019] A further improvement is that a transition region surrounds the active region, and a termination region surrounds the transition region.

[0020] The second conductivity type well also extends into the transition region.

[0021] A further improvement is that the first epitaxial layer is formed on the top surface of the semiconductor substrate.

[0022] A drain region heavily doped with the first conductivity type is formed on the back side of the drift region, and the drain region is composed of the thinned semiconductor substrate heavily doped with the first conductivity type or a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate.

[0023] A further improvement is that the material of the semiconductor substrate includes silicon.

[0024] The material of the first epitaxial layer includes silicon.

[0025] A further improvement is that the Si content in the AlSiCu of the front metal layer is greater than or equal to 1%.

[0026] A further improvement is that the thickness of the front metal layer is 4 μm to 5 μm.

[0027] A further improvement is that increasing the Si content in the AlSiCu of the front metal layer increases the threshold voltage of the device.

[0028] An initial design value of the implantation dose of the second conductive type well is determined by the AlCu material, and an actual value of the implantation dose of the second conductive type well is reduced based on the initial design value and is determined according to the increase in the threshold voltage caused by the Si content in the AlSiCu of the front metal layer.

[0029] A further improvement is that the actual value of the implantation dose of the second conductive type well is in the range of 5E12cm -2 ~5E13cm -2 .

[0030] A further improvement is that the active region is defined by a protective epoxy film, and the protective epoxy film covers the top surface of the first epitaxial layer in the transition region and the termination region.

[0031] A further improvement is that a third contact hole is formed in the transition region and the terminal region, and the third contact hole is composed of the front metal layer filling the third contact hole opening.

[0032] The first contact hole passes through the interlayer film and a portion of the thickness of the first epitaxial layer; the first contact hole passes through the thickness of the first epitaxial layer to ensure passing through the source region.

[0033] The third contact hole passes through the interlayer film and the protective epoxy film and contacts the first epitaxial layer, and the thickness of the first epitaxial layer through which the third contact hole passes is smaller than the thickness of the first epitaxial layer through which the first contact hole passes.

[0034] A further improvement is that the thickness of the first contact hole through the first epitaxial layer is The thickness of the third contact hole passing through the first epitaxial layer is less than

[0035] A further improvement is that the super junction MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super junction MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0036] In response to the adverse effects on the reverse recovery characteristics of the device caused by the large PN junction area and fast lateral depletion rate brought about by the superjunction structure in the superjunction MOSFET device, the present invention makes special arrangements for the metal materials of the contact hole and the front metal layer. The filling metal of the contact hole is directly filled with the front metal layer, and the material of the front metal layer is set to AlSiCu, that is, Si is added to the basis of AlCu and the Si content is specially set. The Si content in AlSiCu reaches above the saturation value. In this way, it is possible to directly make AlSiCu contact with the material of the first epitaxial layer without using a barrier layer such as a Ti and TiN stacking layer. The material of the first epitaxial layer usually includes Si. Since the Si in AlSiCu is already saturated, the Si in the first epitaxial layer will no longer diffuse into the AlSiCu, thereby avoiding the resulting convex defects.

[0037] When both the contact hole and the front metal layer are made of AlSiCu, the resistivity of AlSiCu is slightly greater than that of AlCu, compared with the prior art in which the metal material of the contact hole is W and the material of the front metal layer is AlCu. This increases the forward conduction resistance of the body diode of the present invention and reduces the forward conduction current. The reduced forward conduction current reduces the stored charge generated by the body diode during the conduction process, and the corresponding reverse recovery charge is also reduced. This reduces the reverse recovery time and reverse recovery current, thereby improving the reverse recovery characteristics of the device and making the reverse recovery curve softer. Therefore, the present invention can simultaneously obtain softer reverse recovery characteristics while reducing the reverse recovery charge.

[0038] At the same time, compared with directly using AlCu material for the front metal layer, after Si is doped, the AlSiCu material will increase the threshold voltage of the device, such as the threshold voltage of the NMOS device. In order to compensate for the increase in the threshold voltage of the device, the doping concentration of the second conductive type well can be further reduced. After the doping concentration of the second conductive type well is reduced, the amount of second conductive type charge injection into the body diode can be reduced, thereby further improving the reverse recovery characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0040] Figure 1 1 is a schematic structural diagram of a super junction MOSFET device according to an embodiment of the present invention;

[0041] Figure 2A-2E Schematic diagram of the device structure in each step of the method for manufacturing a super junction MOSFET device according to an embodiment of the present invention;

[0042] Figure 3 1 is a reverse recovery characteristic curve of the body diode of the super junction MOSFET device according to the embodiment of the present invention and the existing super junction MOSFET device. DETAILED DESCRIPTION

[0043] In order to overcome the shortcomings of the existing technology, the applicant conducted further analysis of the existing super junction MOSFET device:

[0044] In existing super junction MOSFET devices, the metal electrode is formed by patterning the front metal layer, and the bottom of the metal electrode is connected to the corresponding contact hole. The material of the front metal layer is usually AlCu, and the filling metal of the contact hole is tungsten. Usually, before tungsten fills the contact hole opening, a barrier layer formed by Ti and TiN, that is, a Ti layer and a TiN layer, is formed, and then metal tungsten is filled and the tungsten on the outer surface of the contact hole opening is removed, and then the AlCu layer is formed. Ti and TiN are used to prevent the Si in the bottom epitaxial layer from dissolving in AlCu and thus prevent the spikes formed by the dissolution of Si. The metal electrodes in the prior art have the advantage of low on-resistance. In order to improve the reverse recovery characteristics of the super junction device, the applicant has set his sights on how to improve the materials of the metal electrodes such as the contact holes and the front metal layer to improve the reverse recovery characteristics of the super junction device. Finally, the embodiment of the present invention increases the forward conduction voltage drop of the body diode, reduces the reverse recovery charge, and increases the softness of the reverse recovery characteristic curve by adopting AlSiCu as the metal electrode material of the super junction MOSFET device. The following is combined with Figure 1 The super junction MOSFET device according to the embodiment of the present invention is further described in detail:

[0045] like Figure 1 FIG. 1 is a schematic diagram of the structure of a super junction MOSFET device according to an embodiment of the present invention. The super junction MOSFET device according to an embodiment of the present invention includes:

[0046] The super junction structure is formed in the first epitaxial layer 2 doped with the first conductivity type, and the super junction structure includes first conductivity type pillars and second conductivity type pillars 4 arranged alternately.

[0047] In the embodiment of the present invention, the second conductivity type column 4 includes a second conductivity type doped second epitaxial layer filled in the super junction trench 3 , and the first conductivity type column includes a first epitaxial layer 2 located between the super junction trenches 3 .

[0048] The first epitaxial layer 2 at the bottom of the super junction structure serves as a buffer layer.

[0049] In the active region, a plurality of parallel device unit structures are formed in the top region of the super junction structure. Figure 1 Only the structure in the active region is shown in FIG. , and the active region is surrounded by a transition region (not shown) and a termination region (not shown) on the periphery of the transition region.

[0050] The device unit structure includes a gate structure, a second conductivity type well 8 and a first conductivity type heavily doped source region 9 .

[0051] In the embodiment of the present invention, the second conductivity type well 8 also extends into the transition region.

[0052] In an embodiment of the present invention, the gate structure includes a gate dielectric layer 6 and a gate conductive material layer 7. In some embodiments, the gate dielectric layer 6 is made of silicon dioxide, and the gate conductive material layer 7 is made of polysilicon.

[0053] In this embodiment of the present invention, the gate structure is a trench gate. A gate dielectric layer 6 is formed on the inner surface of a gate trench 5, and a gate conductive material layer 7 is filled in the gate trench 5. The gate trench 5 vertically passes through the second conductivity type well 8. In other embodiments, the gate structure can also be a planar gate.

[0054] The second conductivity type well 8 is formed in the top region of the second conductivity type column 4 and extends into the first conductivity type column. The drift region includes the first conductivity type column and the buffer layer located outside or at the bottom of the second conductivity type well 8. When the gate structure is a trench gate, the second conductivity type well 8 is typically located in the top region of the first conductivity type column and the second conductivity type column 4 between each gate trench 5. In other embodiments, when the gate structure is a planar gate, a gap is formed between the second conductivity type wells 8 on both sides of the first conductivity type column.

[0055] The surface of the second conductivity type well 8 covered by the gate structure is used to form a conductive channel connecting the source region 9 and the drift region.

[0056] The body diode is a parasitic diode formed by the second conductivity type well 8 and the drift region.

[0057] The source region 9 and the top of the second conductive type well 8 are connected to the source metal composed of the front metal layer 12 through the first contact hole 11; the first contact hole 11 passes through the source region 9 and contacts the second conductive type well 8.

[0058] The first contact hole 11 is directly composed of a material layer of the front metal layer 12 filling the opening of the first contact hole 11. The material of the front metal layer 12 is AlSiCu and the Si content in AlSiCu reaches above the saturation value; the AiSiCu in the first contact hole 11 directly forms an ohmic contact with the semiconductor material of the first epitaxial layer 2 of the source region 9 and the second conductive type well 8. The characteristic that the Si content in AlSiCu reaches above the saturation value is utilized to prevent the formation of sharp convex defects when the AiCu directly contacts the semiconductor material of the first epitaxial layer 2; the characteristic that the resistivity of AlSiCu is greater than the resistivity of AlCu is utilized to increase the forward conduction voltage drop of the body diode and improve the reverse recovery characteristics of the device.

[0059] In some embodiments, the Si content in the AlSiCu of the front metal layer 12 is greater than or equal to 1%.

[0060] The thickness of the front metal layer 12 is 4 μm to 5 μm.

[0061] In the embodiment of the present invention, the top of the gate conductive material layer 7 is connected to the gate metal composed of the front metal layer 12 through the second contact hole, and the second contact hole and the gate metal are not located at Figure 1 On the corresponding cross section, Figure 1 The second contact hole and the gate metal are not shown; the second contact hole is directly composed of a material layer of the front metal layer 12 filling the second contact hole opening.

[0062] In the embodiment of the present invention, the first epitaxial layer 2 is formed on the top surface of the semiconductor substrate 1 .

[0063] A drain region heavily doped with the first conductivity type is formed on the back side of the drift region. The drain region is composed of a thinned semiconductor substrate 1 heavily doped with the first conductivity type or a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate 1.

[0064] The material of the semiconductor substrate 1 includes silicon.

[0065] The material of the first epitaxial layer 2 includes silicon.

[0066] In the embodiment of the present invention, an increase in the Si content in the AlSiCu of the front metal layer 12 will increase the threshold voltage of the device.

[0067] The initial design value of the implantation dose of the second conductive type well 8 is determined by the AlCu material. The actual value of the implantation dose of the second conductive type well 8 is reduced based on the initial design value and determined according to the increase in threshold voltage due to the Si content in the AlSiCu of the front metal layer 12. In some embodiments, the actual value of the implantation dose of the second conductive type well 8 is in the range of 5E12cm -2 ~5E13cm-2 .

[0068] In the embodiment of the present invention, the active region is defined by a protective epoxy film (not shown) covering the top surface of the first epitaxial layer 2 in the transition region and the termination region.

[0069] A third contact hole is formed in the transition region and the terminal region. The third contact hole is formed by the front metal layer 12 filling the third contact hole opening. The third contact hole can connect the doped region formed in the transition region or the terminal region to the field plate formed by the front metal layer 12.

[0070] The first contact hole 11 passes through the interlayer film 10 and a portion of the thickness of the first epitaxial layer 2 ; the first contact hole 11 passes through the thickness of the first epitaxial layer 2 to ensure passing through the source region 9 .

[0071] The third contact hole passes through the interlayer film 10 and the protective epoxy film and contacts the first epitaxial layer 2 . The thickness of the first epitaxial layer 2 passed through the third contact hole is smaller than the thickness of the first epitaxial layer 2 passed through the first contact hole 11 .

[0072] In some embodiments, the first contact hole 11 passes through the first epitaxial layer 2 to a thickness of The thickness of the third contact hole through the first epitaxial layer 2 is less than

[0073] In the embodiment of the present invention, the superjunction MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the superjunction MOSFET device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0074] In view of the adverse effects on the reverse recovery characteristics of the device caused by the large PN junction area and the fast lateral depletion rate brought about by the super junction structure in the super junction MOSFET device, the embodiment of the present invention makes special settings for the metal materials of the contact hole and the front metal layer 12. The filling metal of the contact hole is directly filled with the front metal layer 12, and the material of the front metal layer 12 is set to AlSiCu, that is, Si is added to the basis of AlCu and the Si content is specially set. The Si content in AlSiCu reaches above the saturation value. In this way, it is possible to directly make AlSiCu and the material of the first epitaxial layer 2 contact without using a barrier layer such as a superimposed layer of Ti and TiN. The material of the first epitaxial layer 2 usually includes Si. Since the Si in AlSiCu is already saturated, the Si in the first epitaxial layer 2 will no longer diffuse into AlSiCu, so the resulting convex defects can be avoided.

[0075] When both the contact hole and the front metal layer 12 are made of AlSiCu, compared with the prior art in which the metal material of the contact hole is W and the material of the front metal layer 12 is AlCu, the resistivity of AlSiCu is slightly larger than that of AlCu, which will increase the forward conduction resistance of the body diode of the embodiment of the present invention and reduce the forward conduction current. The reduced forward conduction current will reduce the stored charge generated by the body diode during the conduction process, and the corresponding reverse recovery charge will also be reduced, thereby reducing the reverse recovery time and reverse recovery current, thereby improving the reverse recovery characteristics of the device and making the reverse recovery curve softer. Therefore, the embodiment of the present invention can obtain softer reverse recovery characteristics while reducing the reverse recovery charge.

[0076] At the same time, compared with the direct use of AlCu material for the front metal layer 12, after Si is doped, the AlSiCu material will increase the threshold voltage of the device, such as the threshold voltage of the NMOS device. In order to compensate for the increase in the threshold voltage of the device, the doping concentration of the second conductive type well 8 can be further reduced. After the doping concentration of the second conductive type well 8 is reduced, the amount of second conductive type charge injection into the body diode can be reduced, thereby further improving the reverse recovery characteristics of the device.

[0077] The present invention improves the reverse recovery characteristics of the body diode by using an AlSiCu metal process, that is, depositing AlSiCu as the source and gate electrode materials of a superjunction MOSFET, and optimizing the metal electrode composition. To further illustrate the superjunction MOSFET of the present invention, the following is a further description of the manufacturing method and corresponding parameters:

[0078] like Figures 2A to 2E FIG. 1 is a schematic diagram of the device structure in each step of the manufacturing method of a super-junction MOSFET device according to an embodiment of the present invention. Taking a 600V trench-gate N-type super-junction MOSFET as an example, the corresponding wafer manufacturing process includes the following steps:

[0079] 1. Such as Figure 2A As shown, a first N-type epitaxial layer 2 is first grown on a low-resistivity N-type semiconductor substrate 1, i.e., a silicon substrate. This first epitaxial layer 2 is 50 μm thick and uses a double-layer epitaxial growth process. The top layer has a resistivity of 0.85 ohm.cm, while the bottom layer has a resistivity of 1.05 ohm.cm. In actual production, single-layer, double-layer, and multi-layer N-type epitaxial layers with varying resistivities are common.

[0080] 2. Such as Figure 2B As shown, a super junction trench 3 is formed.

[0081] The steps of forming the super junction trench 3 include:

[0082] A dielectric film is then deposited on the first epitaxial layer 2, and several superjunction trenches 3 with a certain aspect ratio are etched into the first epitaxial layer 2 using photolithography. The width of the superjunction trench 3 for a typical 600V superjunction product is 3.2μm, and the distance between each superjunction trench 3 is 3.8μm. The superjunction trench 3 depth is 40-45μm. The trench width, spacing, and width can be adjusted based on the characteristics of the product and the choice of epitaxial substrate. Generally, for the aforementioned superjunction product (N-type epitaxial thickness 50μm), the trench depth will not exceed 47μm. A buffer layer of a certain thickness is required at the bottom of the trench to improve the device's resistance to current surges. After the superjunction trench 3 morphology is etched, a dielectric film, either an oxide film or a SiN film, with a thickness of approximately 0.1-0.2 microns, needs to be left at the bottom of the superjunction trench 3. Some processes also inject P-type ions at the bottom of the superjunction trench 3 to increase BVdss. The commonly used P-type ions are boron, with an injection energy of 90-180keV and an injection dose of 1.0E12cm -2 ~2.0E12cm -2 Then, P-type silicon, namely the second epitaxial layer, is epitaxially filled in the super junction trench 3 , and then chemical mechanical polishing is used for planarization to form a P-type column, namely the second conductive type column 4 , composed of the second epitaxial layer filled in the super junction trench 3 .

[0083] 3. Such as Figure 2C As shown, several gate trenches 5 are then formed on the first epitaxial layer 2 by photolithography and etching. The gate trenches 5 are shallower than the superjunction trenches 3. The depth of the gate trenches 5 is generally 2 to 4 μm. A gate oxide film, i.e., a gate dielectric layer 6, is then deposited. The thickness of the gate oxide film is about Then, a gate conductive material layer 7 of the device is formed by depositing and etching polysilicon.

[0084] 4. Such as Figure 2D As shown, after CVD deposition, a layer of thickness is formed on the surface of the silicon wafer, that is, the silicon substrate. The protective oxide film, also known as the epoxy film, protects the device from high voltage breakdown. Generally, the higher the BVdss of the device, the thicker the oxide film required. This oxide film only covers the transition and terminal regions; the oxide film in the charge flow area needs to be etched away.

[0085] 5. Then, a P-type well, i.e., a second conductive type well 8, is formed in the device cell region, i.e., the active region and the transition region, by photolithography and ion implantation. The implanted impurity is generally boron, with an implantation energy of 60-120 KeV and an implantation dose of 1e13 cm -2 ~1e14cm -2 In daily production, the threshold voltage of the device will be affected by product characteristics, such as irradiation or non-irradiation products, and other process adjustments. This can be achieved by changing the implantation dose or energy of the P-type well.

[0086] 6. Such as Figure 2E As shown, a source region 9 is then formed by photolithography and ion implantation of N-type impurities. Common N-type impurities include phosphorus and arsenic.

[0087] Compared with the prior art, the embodiment of the present invention mainly changes the materials of the contact hole and the front metal layer. The following describes the corresponding formation processes of the contact hole and the front metal layer respectively:

[0088] In the existing method, the subsequent process steps for forming the metal electrode include:

[0089] 7. Return Figure 1 As shown, the current metal electrode process primarily involves depositing an interlayer film 10, etching and filling contact holes 11, and depositing a front metal layer 12 to form a semiconductor-metal ohmic contact. In conventional metal electrode processes, in the device current flow region, the first contact hole 11 etches away silicon in the N-type high-concentration region, with an etching depth of 2000-4000 angstroms. In the transition region, the third contact hole only needs to penetrate the interlayer film 10 and the protective epoxy film, with the etching depth of silicon in this region not exceeding 500 angstroms. Subsequently, a Ti-TiN blocking layer (Ti and TiN) is deposited to prevent Si from dissolving in the AlCu and forming a spike, and annealing is performed. Tungsten (W) is then deposited to fill the contact hole to a thickness of 4000 angstroms. The surface metal is then removed, and 4-5μm of AlCu is deposited, with a Cu content of 0.5%, to form the metal electrode.

[0090] In the embodiment of the present invention, the subsequent process for forming the metal electrode is slightly different, using an AlSiCu process. Step 7 corresponding to the above-mentioned existing method is replaced by the AlSiCu process. The specific process steps of the AlSiCu process include:

[0091] After etching the contact holes, a 4-5μm AlSiCu layer is deposited directly without depositing a Ti-TiN blocking layer. AlSiCu forms an ohmic metal-semiconductor contact with Si, forming the device's metal electrode. The AlSiCu metal is prepared by adding approximately 1% Si to the AlCu metal, which saturates the AlCu with Si. When the AlSiCu metal is deposited on the device surface, it prevents Si on the device's top surface from dissolving into the AlCu metal and effectively prevents the occurrence of cusp bumps.

[0092] The subsequent steps are the same as those in the embodiment of the present invention and the existing method, including:

[0093] 8. Next comes the preparation of the passivation and protective layers. Typically, a high-density silicon oxide layer (the passivation layer) is deposited under plasma, followed by a thicker polyimide film as a protective layer. Photolithography and development are then used to form a protective pattern covering the terminal area, transition region, gate region, and source region openings. The polyimide layer is baked to a thickness of 4 to 10 μm.

[0094] 9. Some devices require electron irradiation. This can be done after the passivation layer process, followed by the polyimide process. However, processes such as polyimide baking may affect the effect of electron irradiation. Alternatively, electron irradiation can be introduced after the polyimide process, followed by setting an appropriate dose and annealing conditions. In some embodiments, the typical electron irradiation dose is 60-300 kGY, and the annealing conditions include a temperature of 300-380°C and a duration of 30-300 minutes. This can further improve the device's body diode reverse recovery characteristics.

[0095] Compared with AlCu, AlSiCu has a slightly larger resistivity, which makes it difficult to turn on the body diode of the superjunction MOSFET, reduces the forward conduction current of the body diode, and reduces the stored charge. According to the test results, the forward conduction voltage drop of the body diode of the AlCu electrode device, that is, the existing superjunction MOSFET device, is 0.9V, while the forward conduction voltage drop of the body diode of the AlSiCu electrode device, that is, the superjunction MOSFET device of the embodiment of the present invention, increases to 0.95V. Correspondingly, the reverse recovery charge of the body diode of the AlCu electrode device is 0.85uc, while the reverse recovery charge of the body diode of the AlSiCu electrode device is reduced to 0.67uc, a reduction of 20%. The reverse recovery time of the AlSiCu electrode device is shorter and the reverse recovery current is smaller. See Table 1 for specific comparison values. Moreover, the reverse recovery curve of the AlSiCu electrode device is softer, with a softness factor of 0.63, while the reverse recovery softness factor of the existing AlCu electrode device is 0.53. The comparison curve of the reverse recovery characteristics of the AlSiCu electrode device and the AlCu electrode device is shown in Figure 3 , Figure 3 The middle curve 101 represents the reverse recovery characteristic curve of the body diode of the existing super junction MOSFET device, namely the reverse recovery characteristic curve of the AlCu electrode device, and the curve 102 represents the reverse recovery characteristic curve of the body diode of the super junction MOSFET device according to the embodiment of the present invention, namely the reverse recovery characteristic curve of the AlSiCu electrode device.

[0096] Table 1

[0097]

[0098]

[0099] In Table 1, Irrm represents the reverse recovery peak current, trr represents the reverse recovery time, and Qrr represents the reverse recovery charge.

[0100] The AlSiCu metal electrode process will affect the threshold voltage (VTH) of the device. The interface between the polysilicon and silicon dioxide of the device will change, causing the threshold voltage to drift. According to experimental data, the VTH of the device with the AlSiCu electrode process increases by 0.5V. In order to achieve the VTH value required by the application, the embodiment of the present invention will reduce the boron dose injected into the P-type well. The boron dose injected into the P-type well of the initial process corresponding to the existing method is as high as 1e13cm -2 ~1e14cm -2 In the process of the embodiment of the present invention, the dose can be reduced to 5e12cm -2 ~5e13cm -2 This also results in a reduction in the number of holes injected into the body diode, improving the reverse recovery characteristics.

[0101] Compared to existing technologies, the embodiments of the present invention improve the reverse recovery characteristics of superjunction MOSFETs by utilizing a metal electrode process compatible with existing superjunction processes without increasing process complexity and cost. Specifically, the use of AlSiCu metal electrodes instead of traditional AlCu metal electrodes reduces the forward conduction current of the superjunction MOSFET body diode, thereby reducing the number of injected minority carriers. This, in turn, reduces the reverse recovery charge and softens the reverse recovery curve, ultimately reducing device power consumption and improving device reliability.

[0102] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A super junction MOSFET device, characterized in that: include: A super junction structure formed in a first epitaxial layer doped with a first conductivity type, the super junction structure comprising alternatingly arranged first conductivity type pillars and second conductivity type pillars; The first epitaxial layer at the bottom of the super junction structure serves as a buffer layer; In the active area, a plurality of parallel device unit structures are formed in the top region of the super junction structure; The device unit structure includes a gate structure, a second conductivity type well and a first conductivity type heavily doped source region; The second conductive type well is formed in a top region of the second conductive type column and extends into the first conductive type column, and the drift region includes the first conductive type column and the buffer layer located outside or at the bottom of the second conductive type well; The surface of the second conductive type well covered by the gate structure is used to form a conductive channel connecting the source region and the drift region; The body diode is a parasitic diode formed by the second conductive type well and the drift region; The source region and the top of the second conductive type well are connected to the source metal composed of the front metal layer through a first contact hole; the first contact hole passes through the source region and contacts the second conductive type well; The first contact hole is directly composed of a material layer of the front metal layer filling the opening of the first contact hole, and the material of the front metal layer is AlSiCu, and the Si content in AlSiCu reaches above the saturation value; the AiSiCu of the first contact hole directly forms an ohmic contact with the semiconductor material of the first epitaxial layer of the source region and the second conductive type well, and utilizes the characteristic that the Si content in AlSiCu reaches above the saturation value to prevent the formation of a sharp convex defect when the AlCu directly contacts the semiconductor material of the first epitaxial layer; utilizes the characteristic that the resistivity of AlSiCu is greater than the resistivity of AlCu to increase the forward conduction voltage drop of the body diode and improve the reverse recovery characteristics of the device.

2. The super junction MOSFET device according to claim 1, wherein: The gate structure includes a gate dielectric layer and a gate conductive material layer; the top of the gate conductive material layer is connected to the gate metal composed of the front metal layer through a second contact hole; the second contact hole is directly composed of the material layer of the front metal layer filling the second contact hole opening.

3. The super junction MOSFET device according to claim 1, wherein: The gate structure is a planar gate or a trench gate.

4. The super junction MOSFET device according to claim 1, wherein: The second conductive type column includes a second conductive type doped second epitaxial layer filled in a super junction trench, and the first conductive type column includes the first epitaxial layer located between the super junction trenches.

5. The super junction MOSFET device according to claim 1, wherein: A transition region surrounds the active region, and a terminal region surrounds the transition region. The second conductivity type well also extends into the transition region.

6. The super junction MOSFET device according to claim 1, wherein: The first epitaxial layer is formed on the top surface of the semiconductor substrate; A drain region heavily doped with the first conductivity type is formed on the back side of the drift region, and the drain region is composed of the thinned semiconductor substrate heavily doped with the first conductivity type or a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate.

7. The super junction MOSFET device according to claim 6, wherein: The material of the semiconductor substrate includes silicon; The material of the first epitaxial layer includes silicon.

8. The super junction MOSFET device according to claim 2, wherein: The Si content in the AlSiCu of the front metal layer is greater than or equal to 1%.

9. The super junction MOSFET device according to claim 2, wherein: The thickness of the front metal layer is 4 μm to 5 μm.

10. The super junction MOSFET device according to claim 2, wherein: Increasing the Si content in the AlSiCu of the front metal layer will increase the threshold voltage of the device; An initial design value of the implantation dose of the second conductive type well is determined by the AlCu material, and an actual value of the implantation dose of the second conductive type well is reduced based on the initial design value and is determined according to the increase in the threshold voltage caused by the Si content in the AlSiCu of the front metal layer.

11. The super junction MOSFET device according to claim 10, wherein: The actual value range of the implantation dose of the second conductive type well is 5E12cm -2 ~5E13cm -2 .

12. The super junction MOSFET device according to claim 5, wherein: The active region is defined by a protective epoxy film covering a top surface of the first epitaxial layer in the transition region and the termination region.

13. The super junction MOSFET device according to claim 12, wherein: A third contact hole is formed in the transition region and the terminal region, and the third contact hole is composed of the front metal layer filling the third contact hole opening; The first contact hole passes through the interlayer film and a portion of the thickness of the first epitaxial layer; the first contact hole passes through the thickness of the first epitaxial layer to ensure that it passes through the source region; The third contact hole passes through the interlayer film and the protective epoxy film and contacts the first epitaxial layer, and the thickness of the first epitaxial layer through which the third contact hole passes is smaller than the thickness of the first epitaxial layer through which the first contact hole passes.

14. The super junction MOSFET device according to claim 13, wherein: The thickness of the first contact hole through the first epitaxial layer is The thickness of the third contact hole passing through the first epitaxial layer is less than 15. The super junction MOSFET device according to any one of claims 1 to 14, wherein: The super junction MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the super junction MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

Images